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tests/test-mmap.c: Check mmap() return value before using it
[qemu/ar7.git] / hw / eepro100.c
blobedf48f61d1000f4cb632358dd24b1605a7d32f4c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include "hw.h"
46 #include "pci.h"
47 #include "net.h"
48 #include "eeprom93xx.h"
49 #include "sysemu.h"
50
51 #define KiB 1024
52
53 /* Debug EEPRO100 card. */
54 #if 0
55 # define DEBUG_EEPRO100
56 #endif
57
58 #ifdef DEBUG_EEPRO100
59 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
60 #else
61 #define logout(fmt, ...) ((void)0)
62 #endif
63
64 /* Set flags to 0 to disable debug output. */
65 #define INT 1 /* interrupt related actions */
66 #define MDI 1 /* mdi related actions */
67 #define OTHER 1
68 #define RXTX 1
69 #define EEPROM 1 /* eeprom related actions */
70
71 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72
73 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
74
75 #define MAX_ETH_FRAME_SIZE 1514
76
77 /* This driver supports several different devices which are declared here. */
78 #define i82550 0x82550
79 #define i82551 0x82551
80 #define i82557A 0x82557a
81 #define i82557B 0x82557b
82 #define i82557C 0x82557c
83 #define i82558A 0x82558a
84 #define i82558B 0x82558b
85 #define i82559A 0x82559a
86 #define i82559B 0x82559b
87 #define i82559C 0x82559c
88 #define i82559ER 0x82559e
89 #define i82562 0x82562
90 #define i82801 0x82801
91
92 /* Use 64 word EEPROM. TODO: could be a runtime option. */
93 #define EEPROM_SIZE 64
94
95 #define PCI_MEM_SIZE (4 * KiB)
96 #define PCI_IO_SIZE 64
97 #define PCI_FLASH_SIZE (128 * KiB)
98
99 #define BIT(n) (1 << (n))
100 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101
102 /* The SCB accepts the following controls for the Tx and Rx units: */
103 #define CU_NOP 0x0000 /* No operation. */
104 #define CU_START 0x0010 /* CU start. */
105 #define CU_RESUME 0x0020 /* CU resume. */
106 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
107 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
108 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
109 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
110 #define CU_SRESUME 0x00a0 /* CU static resume. */
111
112 #define RU_NOP 0x0000
113 #define RX_START 0x0001
114 #define RX_RESUME 0x0002
115 #define RU_ABORT 0x0004
116 #define RX_ADDR_LOAD 0x0006
117 #define RX_RESUMENR 0x0007
118 #define INT_MASK 0x0100
119 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
120
121 typedef struct {
122 PCIDeviceInfo pci;
123 uint32_t device;
124 uint16_t device_id;
125 uint8_t revision;
126 uint8_t stats_size;
127 bool has_extended_tcb_support;
128 bool power_management;
129 } E100PCIDeviceInfo;
130
131 /* Offsets to the various registers.
132 All accesses need not be longword aligned. */
133 enum speedo_offsets {
134 SCBStatus = 0, /* Status Word. */
135 SCBAck = 1,
136 SCBCmd = 2, /* Rx/Command Unit command and status. */
137 SCBIntmask = 3,
138 SCBPointer = 4, /* General purpose pointer. */
139 SCBPort = 8, /* Misc. commands and operands. */
140 SCBflash = 12, /* Flash memory control. */
141 SCBeeprom = 14, /* EEPROM control. */
142 SCBCtrlMDI = 16, /* MDI interface control. */
143 SCBEarlyRx = 20, /* Early receive byte count. */
144 SCBFlow = 24, /* Flow Control. */
145 SCBpmdr = 27, /* Power Management Driver. */
146 SCBgctrl = 28, /* General Control. */
147 SCBgstat = 29, /* General Status. */
148 };
149
150 /* A speedo3 transmit buffer descriptor with two buffers... */
151 typedef struct {
152 uint16_t status;
153 uint16_t command;
154 uint32_t link; /* void * */
155 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
156 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
157 uint8_t tx_threshold; /* transmit threshold */
158 uint8_t tbd_count; /* TBD number */
159 #if 0
160 /* This constitutes two "TBD" entries: hdr and data */
161 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
162 int32_t tx_buf_size0; /* Length of Tx hdr. */
163 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
164 int32_t tx_buf_size1; /* Length of Tx data. */
165 #endif
166 } eepro100_tx_t;
167
168 /* Receive frame descriptor. */
169 typedef struct {
170 int16_t status;
171 uint16_t command;
172 uint32_t link; /* struct RxFD * */
173 uint32_t rx_buf_addr; /* void * */
174 uint16_t count;
175 uint16_t size;
176 char packet[MAX_ETH_FRAME_SIZE + 4];
177 } eepro100_rx_t;
178
179 typedef enum {
180 COMMAND_EL = BIT(15),
181 COMMAND_S = BIT(14),
182 COMMAND_I = BIT(13),
183 COMMAND_NC = BIT(4),
184 COMMAND_SF = BIT(3),
185 COMMAND_CMD = BITS(2, 0),
186 } scb_command_bit;
187
188 typedef enum {
189 STATUS_C = BIT(15),
190 STATUS_OK = BIT(13),
191 } scb_status_bit;
192
193 typedef struct {
194 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
195 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
196 tx_multiple_collisions, tx_total_collisions;
197 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
198 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
199 rx_short_frame_errors;
200 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
201 uint16_t xmt_tco_frames, rcv_tco_frames;
202 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
203 uint32_t reserved[4];
204 } eepro100_stats_t;
205
206 typedef enum {
207 cu_idle = 0,
208 cu_suspended = 1,
209 cu_active = 2,
210 cu_lpq_active = 2,
211 cu_hqp_active = 3
212 } cu_state_t;
213
214 typedef enum {
215 ru_idle = 0,
216 ru_suspended = 1,
217 ru_no_resources = 2,
218 ru_ready = 4
219 } ru_state_t;
220
221 typedef struct {
222 PCIDevice dev;
223 /* Hash register (multicast mask array, multiple individual addresses). */
224 uint8_t mult[8];
225 int mmio_index;
226 NICState *nic;
227 NICConf conf;
228 uint8_t scb_stat; /* SCB stat/ack byte */
229 uint8_t int_stat; /* PCI interrupt status */
230 /* region must not be saved by nic_save. */
231 uint32_t region[3]; /* PCI region addresses */
232 uint16_t mdimem[32];
233 eeprom_t *eeprom;
234 uint32_t device; /* device variant */
235 uint32_t pointer;
236 /* (cu_base + cu_offset) address the next command block in the command block list. */
237 uint32_t cu_base; /* CU base address */
238 uint32_t cu_offset; /* CU address offset */
239 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
240 uint32_t ru_base; /* RU base address */
241 uint32_t ru_offset; /* RU address offset */
242 uint32_t statsaddr; /* pointer to eepro100_stats_t */
243
244 /* Temporary status information (no need to save these values),
245 * used while processing CU commands. */
246 eepro100_tx_t tx; /* transmit buffer descriptor */
247 uint32_t cb_address; /* = cu_base + cu_offset */
248
249 /* Statistical counters. Also used for wake-up packet (i82559). */
250 eepro100_stats_t statistics;
251
252 /* Configuration bytes. */
253 uint8_t configuration[22];
254
255 /* Data in mem is always in the byte order of the controller (le). */
256 uint8_t mem[PCI_MEM_SIZE];
257 /* vmstate for each particular nic */
258 VMStateDescription *vmstate;
259
260 /* Quasi static device properties (no need to save them). */
261 uint16_t stats_size;
262 bool has_extended_tcb_support;
263 } EEPRO100State;
264
265 /* Word indices in EEPROM. */
266 typedef enum {
267 EEPROM_CNFG_MDIX = 0x03,
268 EEPROM_ID = 0x05,
269 EEPROM_PHY_ID = 0x06,
270 EEPROM_VENDOR_ID = 0x0c,
271 EEPROM_CONFIG_ASF = 0x0d,
272 EEPROM_DEVICE_ID = 0x23,
273 EEPROM_SMBUS_ADDR = 0x90,
274 } EEPROMOffset;
275
276 /* Bit values for EEPROM ID word. */
277 typedef enum {
278 EEPROM_ID_MDM = BIT(0), /* Modem */
279 EEPROM_ID_STB = BIT(1), /* Standby Enable */
280 EEPROM_ID_WMR = BIT(2), /* ??? */
281 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
282 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
283 EEPROM_ID_ALT = BIT(7), /* */
284 /* BITS(10, 8) device revision */
285 EEPROM_ID_BD = BIT(11), /* boot disable */
286 EEPROM_ID_ID = BIT(13), /* id bit */
287 /* BITS(15, 14) signature */
288 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
289 } eeprom_id_bit;
290
291 /* Default values for MDI (PHY) registers */
292 static const uint16_t eepro100_mdi_default[] = {
293 /* MDI Registers 0 - 6, 7 */
294 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
295 /* MDI Registers 8 - 15 */
296 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
297 /* MDI Registers 16 - 31 */
298 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
300 };
301
302 /* Readonly mask for MDI (PHY) registers */
303 static const uint16_t eepro100_mdi_mask[] = {
304 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
305 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
306 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
307 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
308 };
309
310 /* XXX: optimize */
311 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
312 {
313 val = cpu_to_le32(val);
314 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
315 }
316
317 #define POLYNOMIAL 0x04c11db6
318
319 /* From FreeBSD */
320 /* XXX: optimize */
321 static unsigned compute_mcast_idx(const uint8_t * ep)
322 {
323 uint32_t crc;
324 int carry, i, j;
325 uint8_t b;
326
327 crc = 0xffffffff;
328 for (i = 0; i < 6; i++) {
329 b = *ep++;
330 for (j = 0; j < 8; j++) {
331 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
332 crc <<= 1;
333 b >>= 1;
334 if (carry) {
335 crc = ((crc ^ POLYNOMIAL) | carry);
336 }
337 }
338 }
339 return (crc & BITS(7, 2)) >> 2;
340 }
341
342 #if defined(DEBUG_EEPRO100)
343 static const char *nic_dump(const uint8_t * buf, unsigned size)
344 {
345 static char dump[3 * 16 + 1];
346 char *p = &dump[0];
347 if (size > 16) {
348 size = 16;
349 }
350 while (size-- > 0) {
351 p += sprintf(p, " %02x", *buf++);
352 }
353 return dump;
354 }
355 #endif /* DEBUG_EEPRO100 */
356
357 enum scb_stat_ack {
358 stat_ack_not_ours = 0x00,
359 stat_ack_sw_gen = 0x04,
360 stat_ack_rnr = 0x10,
361 stat_ack_cu_idle = 0x20,
362 stat_ack_frame_rx = 0x40,
363 stat_ack_cu_cmd_done = 0x80,
364 stat_ack_not_present = 0xFF,
365 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
366 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
367 };
368
369 static void disable_interrupt(EEPRO100State * s)
370 {
371 if (s->int_stat) {
372 TRACE(INT, logout("interrupt disabled\n"));
373 qemu_irq_lower(s->dev.irq[0]);
374 s->int_stat = 0;
375 }
376 }
377
378 static void enable_interrupt(EEPRO100State * s)
379 {
380 if (!s->int_stat) {
381 TRACE(INT, logout("interrupt enabled\n"));
382 qemu_irq_raise(s->dev.irq[0]);
383 s->int_stat = 1;
384 }
385 }
386
387 static void eepro100_acknowledge(EEPRO100State * s)
388 {
389 s->scb_stat &= ~s->mem[SCBAck];
390 s->mem[SCBAck] = s->scb_stat;
391 if (s->scb_stat == 0) {
392 disable_interrupt(s);
393 }
394 }
395
396 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
397 {
398 uint8_t mask = ~s->mem[SCBIntmask];
399 s->mem[SCBAck] |= status;
400 status = s->scb_stat = s->mem[SCBAck];
401 status &= (mask | 0x0f);
402 #if 0
403 status &= (~s->mem[SCBIntmask] | 0x0xf);
404 #endif
405 if (status && (mask & 0x01)) {
406 /* SCB mask and SCB Bit M do not disable interrupt. */
407 enable_interrupt(s);
408 } else if (s->int_stat) {
409 disable_interrupt(s);
410 }
411 }
412
413 static void eepro100_cx_interrupt(EEPRO100State * s)
414 {
415 /* CU completed action command. */
416 /* Transmit not ok (82557 only, not in emulation). */
417 eepro100_interrupt(s, 0x80);
418 }
419
420 static void eepro100_cna_interrupt(EEPRO100State * s)
421 {
422 /* CU left the active state. */
423 eepro100_interrupt(s, 0x20);
424 }
425
426 static void eepro100_fr_interrupt(EEPRO100State * s)
427 {
428 /* RU received a complete frame. */
429 eepro100_interrupt(s, 0x40);
430 }
431
432 static void eepro100_rnr_interrupt(EEPRO100State * s)
433 {
434 /* RU is not ready. */
435 eepro100_interrupt(s, 0x10);
436 }
437
438 static void eepro100_mdi_interrupt(EEPRO100State * s)
439 {
440 /* MDI completed read or write cycle. */
441 eepro100_interrupt(s, 0x08);
442 }
443
444 static void eepro100_swi_interrupt(EEPRO100State * s)
445 {
446 /* Software has requested an interrupt. */
447 eepro100_interrupt(s, 0x04);
448 }
449
450 #if 0
451 static void eepro100_fcp_interrupt(EEPRO100State * s)
452 {
453 /* Flow control pause interrupt (82558 and later). */
454 eepro100_interrupt(s, 0x01);
455 }
456 #endif
457
458 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
459 {
460 uint32_t device = s->device;
461 uint8_t *pci_conf = s->dev.config;
462
463 TRACE(OTHER, logout("%p\n", s));
464
465 /* PCI Vendor ID */
466 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
467 /* PCI Device ID */
468 pci_config_set_device_id(pci_conf, e100_device->device_id);
469 /* PCI Status */
470 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
471 PCI_STATUS_FAST_BACK);
472 /* PCI Revision ID */
473 pci_config_set_revision(pci_conf, e100_device->revision);
474 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
475 /* PCI Latency Timer */
476 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
477 /* Capability Pointer is set by PCI framework. */
478 /* Interrupt Line */
479 /* Interrupt Pin */
480 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
481 /* Minimum Grant */
482 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
483 /* Maximum Latency */
484 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
485
486 s->stats_size = e100_device->stats_size;
487 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
488
489 switch (device) {
490 case i82550:
491 case i82551:
492 case i82557A:
493 case i82557B:
494 case i82557C:
495 case i82558A:
496 case i82558B:
497 case i82559A:
498 case i82559B:
499 case i82559ER:
500 case i82562:
501 case i82801:
502 break;
503 case i82559C:
504 #if EEPROM_SIZE > 0
505 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
506 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
507 #endif
508 break;
509 default:
510 logout("Device %X is undefined!\n", device);
511 }
512
513 /* Standard TxCB. */
514 s->configuration[6] |= BIT(4);
515
516 /* Standard statistical counters. */
517 s->configuration[6] |= BIT(5);
518
519 if (s->stats_size == 80) {
520 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
521 if (s->configuration[6] & BIT(2)) {
522 /* TCO statistical counters. */
523 assert(s->configuration[6] & BIT(5));
524 } else {
525 if (s->configuration[6] & BIT(5)) {
526 /* No extended statistical counters, i82557 compatible. */
527 s->stats_size = 64;
528 } else {
529 /* i82558 compatible. */
530 s->stats_size = 76;
531 }
532 }
533 } else {
534 if (s->configuration[6] & BIT(5)) {
535 /* No extended statistical counters. */
536 s->stats_size = 64;
537 }
538 }
539 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
540
541 if (e100_device->power_management) {
542 /* Power Management Capabilities */
543 int cfg_offset = 0xdc;
544 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
545 cfg_offset, PCI_PM_SIZEOF);
546 assert(r >= 0);
547 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
548 #if 0 /* TODO: replace dummy code for power management emulation. */
549 /* TODO: Power Management Control / Status. */
550 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
551 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
552 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
553 #endif
554 }
555
556 #if EEPROM_SIZE > 0
557 if (device == i82557C || device == i82558B || device == i82559C) {
558 /*
559 TODO: get vendor id from EEPROM for i82557C or later.
560 TODO: get device id from EEPROM for i82557C or later.
561 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
562 TODO: header type is determined by EEPROM for i82559.
563 TODO: get subsystem id from EEPROM for i82557C or later.
564 TODO: get subsystem vendor id from EEPROM for i82557C or later.
565 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
566 TODO: capability pointer depends on EEPROM for i82558.
567 */
568 logout("Get device id and revision from EEPROM!!!\n");
569 }
570 #endif /* EEPROM_SIZE > 0 */
571 }
572
573 static void nic_selective_reset(EEPRO100State * s)
574 {
575 size_t i;
576 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
577 #if 0
578 eeprom93xx_reset(s->eeprom);
579 #endif
580 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
581 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
582 if (s->device == i82557B || s->device == i82557C)
583 eeprom_contents[5] = 0x0100;
584 eeprom_contents[EEPROM_PHY_ID] = 1;
585 uint16_t sum = 0;
586 for (i = 0; i < EEPROM_SIZE - 1; i++) {
587 sum += eeprom_contents[i];
588 }
589 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
590 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
591
592 memset(s->mem, 0, sizeof(s->mem));
593 uint32_t val = BIT(21);
594 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
595
596 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
597 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
598 }
599
600 static void nic_reset(void *opaque)
601 {
602 EEPRO100State *s = opaque;
603 TRACE(OTHER, logout("%p\n", s));
604 /* TODO: Clearing of hash register for selective reset, too? */
605 memset(&s->mult[0], 0, sizeof(s->mult));
606 nic_selective_reset(s);
607 }
608
609 #if defined(DEBUG_EEPRO100)
610 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
611 "Command/Status",
612 "General Pointer",
613 "Port",
614 "EEPROM/Flash Control",
615 "MDI Control",
616 "Receive DMA Byte Count",
617 "Flow Control",
618 "General Status/Control"
619 };
620
621 static char *regname(uint32_t addr)
622 {
623 static char buf[32];
624 if (addr < PCI_IO_SIZE) {
625 const char *r = e100_reg[addr / 4];
626 if (r != 0) {
627 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
628 } else {
629 snprintf(buf, sizeof(buf), "0x%02x", addr);
630 }
631 } else {
632 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
633 }
634 return buf;
635 }
636 #endif /* DEBUG_EEPRO100 */
637
638 /*****************************************************************************
639 *
640 * Command emulation.
641 *
642 ****************************************************************************/
643
644 #if 0
645 static uint16_t eepro100_read_command(EEPRO100State * s)
646 {
647 uint16_t val = 0xffff;
648 TRACE(OTHER, logout("val=0x%04x\n", val));
649 return val;
650 }
651 #endif
652
653 /* Commands that can be put in a command list entry. */
654 enum commands {
655 CmdNOp = 0,
656 CmdIASetup = 1,
657 CmdConfigure = 2,
658 CmdMulticastList = 3,
659 CmdTx = 4,
660 CmdTDR = 5, /* load microcode */
661 CmdDump = 6,
662 CmdDiagnose = 7,
663
664 /* And some extra flags: */
665 CmdSuspend = 0x4000, /* Suspend after completion. */
666 CmdIntr = 0x2000, /* Interrupt after completion. */
667 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
668 };
669
670 static cu_state_t get_cu_state(EEPRO100State * s)
671 {
672 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
673 }
674
675 static void set_cu_state(EEPRO100State * s, cu_state_t state)
676 {
677 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
678 }
679
680 static ru_state_t get_ru_state(EEPRO100State * s)
681 {
682 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
683 }
684
685 static void set_ru_state(EEPRO100State * s, ru_state_t state)
686 {
687 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
688 }
689
690 static void dump_statistics(EEPRO100State * s)
691 {
692 /* Dump statistical data. Most data is never changed by the emulation
693 * and always 0, so we first just copy the whole block and then those
694 * values which really matter.
695 * Number of data should check configuration!!!
696 */
697 cpu_physical_memory_write(s->statsaddr,
698 (uint8_t *) & s->statistics, s->stats_size);
699 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
700 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
701 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
702 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
703 #if 0
704 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
705 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
706 missing("CU dump statistical counters");
707 #endif
708 }
709
710 static void read_cb(EEPRO100State *s)
711 {
712 cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
713 s->tx.status = le16_to_cpu(s->tx.status);
714 s->tx.command = le16_to_cpu(s->tx.command);
715 s->tx.link = le32_to_cpu(s->tx.link);
716 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
717 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
718 }
719
720 static void tx_command(EEPRO100State *s)
721 {
722 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
723 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
724 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
725 uint8_t buf[2600];
726 uint16_t size = 0;
727 uint32_t tbd_address = s->cb_address + 0x10;
728 TRACE(RXTX, logout
729 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
730 tbd_array, tcb_bytes, s->tx.tbd_count));
731
732 if (tcb_bytes > 2600) {
733 logout("TCB byte count too large, using 2600\n");
734 tcb_bytes = 2600;
735 }
736 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
737 logout
738 ("illegal values of TBD array address and TCB byte count!\n");
739 }
740 assert(tcb_bytes <= sizeof(buf));
741 while (size < tcb_bytes) {
742 uint32_t tx_buffer_address = ldl_phys(tbd_address);
743 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
744 #if 0
745 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
746 #endif
747 tbd_address += 8;
748 TRACE(RXTX, logout
749 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
750 tx_buffer_address, tx_buffer_size));
751 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
752 cpu_physical_memory_read(tx_buffer_address, &buf[size],
753 tx_buffer_size);
754 size += tx_buffer_size;
755 }
756 if (tbd_array == 0xffffffff) {
757 /* Simplified mode. Was already handled by code above. */
758 } else {
759 /* Flexible mode. */
760 uint8_t tbd_count = 0;
761 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
762 /* Extended Flexible TCB. */
763 for (; tbd_count < 2; tbd_count++) {
764 uint32_t tx_buffer_address = ldl_phys(tbd_address);
765 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
766 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
767 tbd_address += 8;
768 TRACE(RXTX, logout
769 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
770 tx_buffer_address, tx_buffer_size));
771 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
772 cpu_physical_memory_read(tx_buffer_address, &buf[size],
773 tx_buffer_size);
774 size += tx_buffer_size;
775 if (tx_buffer_el & 1) {
776 break;
777 }
778 }
779 }
780 tbd_address = tbd_array;
781 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
782 uint32_t tx_buffer_address = ldl_phys(tbd_address);
783 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
784 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
785 tbd_address += 8;
786 TRACE(RXTX, logout
787 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
788 tx_buffer_address, tx_buffer_size));
789 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
790 cpu_physical_memory_read(tx_buffer_address, &buf[size],
791 tx_buffer_size);
792 size += tx_buffer_size;
793 if (tx_buffer_el & 1) {
794 break;
795 }
796 }
797 }
798 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
799 qemu_send_packet(&s->nic->nc, buf, size);
800 s->statistics.tx_good_frames++;
801 /* Transmit with bad status would raise an CX/TNO interrupt.
802 * (82557 only). Emulation never has bad status. */
803 #if 0
804 eepro100_cx_interrupt(s);
805 #endif
806 }
807
808 static void set_multicast_list(EEPRO100State *s)
809 {
810 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
811 uint16_t i;
812 memset(&s->mult[0], 0, sizeof(s->mult));
813 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
814 for (i = 0; i < multicast_count; i += 6) {
815 uint8_t multicast_addr[6];
816 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
817 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
818 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
819 assert(mcast_idx < 64);
820 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
821 }
822 }
823
824 static void action_command(EEPRO100State *s)
825 {
826 for (;;) {
827 bool bit_el;
828 bool bit_s;
829 bool bit_i;
830 bool bit_nc;
831 uint16_t ok_status = STATUS_OK;
832 s->cb_address = s->cu_base + s->cu_offset;
833 read_cb(s);
834 bit_el = ((s->tx.command & COMMAND_EL) != 0);
835 bit_s = ((s->tx.command & COMMAND_S) != 0);
836 bit_i = ((s->tx.command & COMMAND_I) != 0);
837 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
838 #if 0
839 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
840 #endif
841 s->cu_offset = s->tx.link;
842 TRACE(OTHER,
843 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
844 s->tx.status, s->tx.command, s->tx.link));
845 switch (s->tx.command & COMMAND_CMD) {
846 case CmdNOp:
847 /* Do nothing. */
848 break;
849 case CmdIASetup:
850 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
851 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
852 break;
853 case CmdConfigure:
854 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
855 sizeof(s->configuration));
856 TRACE(OTHER, logout("configuration: %s\n",
857 nic_dump(&s->configuration[0], 16)));
858 TRACE(OTHER, logout("configuration: %s\n",
859 nic_dump(&s->configuration[16],
860 ARRAY_SIZE(s->configuration) - 16)));
861 if (s->configuration[20] & BIT(6)) {
862 TRACE(OTHER, logout("Multiple IA bit\n"));
863 }
864 break;
865 case CmdMulticastList:
866 set_multicast_list(s);
867 break;
868 case CmdTx:
869 if (bit_nc) {
870 missing("CmdTx: NC = 0");
871 ok_status = 0;
872 break;
873 }
874 tx_command(s);
875 break;
876 case CmdTDR:
877 TRACE(OTHER, logout("load microcode\n"));
878 /* Starting with offset 8, the command contains
879 * 64 dwords microcode which we just ignore here. */
880 break;
881 case CmdDiagnose:
882 TRACE(OTHER, logout("diagnose\n"));
883 /* Make sure error flag is not set. */
884 s->tx.status = 0;
885 break;
886 default:
887 missing("undefined command");
888 ok_status = 0;
889 break;
890 }
891 /* Write new status. */
892 stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
893 if (bit_i) {
894 /* CU completed action. */
895 eepro100_cx_interrupt(s);
896 }
897 if (bit_el) {
898 /* CU becomes idle. Terminate command loop. */
899 set_cu_state(s, cu_idle);
900 eepro100_cna_interrupt(s);
901 break;
902 } else if (bit_s) {
903 /* CU becomes suspended. Terminate command loop. */
904 set_cu_state(s, cu_suspended);
905 eepro100_cna_interrupt(s);
906 break;
907 } else {
908 /* More entries in list. */
909 TRACE(OTHER, logout("CU list with at least one more entry\n"));
910 }
911 }
912 TRACE(OTHER, logout("CU list empty\n"));
913 /* List is empty. Now CU is idle or suspended. */
914 }
915
916 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
917 {
918 cu_state_t cu_state;
919 switch (val) {
920 case CU_NOP:
921 /* No operation. */
922 break;
923 case CU_START:
924 cu_state = get_cu_state(s);
925 if (cu_state != cu_idle && cu_state != cu_suspended) {
926 /* Intel documentation says that CU must be idle or suspended
927 * for the CU start command. */
928 logout("unexpected CU state is %u\n", cu_state);
929 }
930 set_cu_state(s, cu_active);
931 s->cu_offset = s->pointer;
932 action_command(s);
933 break;
934 case CU_RESUME:
935 if (get_cu_state(s) != cu_suspended) {
936 logout("bad CU resume from CU state %u\n", get_cu_state(s));
937 /* Workaround for bad Linux eepro100 driver which resumes
938 * from idle state. */
939 #if 0
940 missing("cu resume");
941 #endif
942 set_cu_state(s, cu_suspended);
943 }
944 if (get_cu_state(s) == cu_suspended) {
945 TRACE(OTHER, logout("CU resuming\n"));
946 set_cu_state(s, cu_active);
947 action_command(s);
948 }
949 break;
950 case CU_STATSADDR:
951 /* Load dump counters address. */
952 s->statsaddr = s->pointer;
953 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
954 break;
955 case CU_SHOWSTATS:
956 /* Dump statistical counters. */
957 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
958 dump_statistics(s);
959 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
960 break;
961 case CU_CMD_BASE:
962 /* Load CU base. */
963 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
964 s->cu_base = s->pointer;
965 break;
966 case CU_DUMPSTATS:
967 /* Dump and reset statistical counters. */
968 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
969 dump_statistics(s);
970 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
971 memset(&s->statistics, 0, sizeof(s->statistics));
972 break;
973 case CU_SRESUME:
974 /* CU static resume. */
975 missing("CU static resume");
976 break;
977 default:
978 missing("Undefined CU command");
979 }
980 }
981
982 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
983 {
984 switch (val) {
985 case RU_NOP:
986 /* No operation. */
987 break;
988 case RX_START:
989 /* RU start. */
990 if (get_ru_state(s) != ru_idle) {
991 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
992 #if 0
993 assert(!"wrong RU state");
994 #endif
995 }
996 set_ru_state(s, ru_ready);
997 s->ru_offset = s->pointer;
998 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
999 break;
1000 case RX_RESUME:
1001 /* Restart RU. */
1002 if (get_ru_state(s) != ru_suspended) {
1003 logout("RU state is %u, should be %u\n", get_ru_state(s),
1004 ru_suspended);
1005 #if 0
1006 assert(!"wrong RU state");
1007 #endif
1008 }
1009 set_ru_state(s, ru_ready);
1010 break;
1011 case RU_ABORT:
1012 /* RU abort. */
1013 if (get_ru_state(s) == ru_ready) {
1014 eepro100_rnr_interrupt(s);
1015 }
1016 set_ru_state(s, ru_idle);
1017 break;
1018 case RX_ADDR_LOAD:
1019 /* Load RU base. */
1020 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1021 s->ru_base = s->pointer;
1022 break;
1023 default:
1024 logout("val=0x%02x (undefined RU command)\n", val);
1025 missing("Undefined SU command");
1026 }
1027 }
1028
1029 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1030 {
1031 eepro100_ru_command(s, val & 0x0f);
1032 eepro100_cu_command(s, val & 0xf0);
1033 if ((val) == 0) {
1034 TRACE(OTHER, logout("val=0x%02x\n", val));
1035 }
1036 /* Clear command byte after command was accepted. */
1037 s->mem[SCBCmd] = 0;
1038 }
1039
1040 /*****************************************************************************
1041 *
1042 * EEPROM emulation.
1043 *
1044 ****************************************************************************/
1045
1046 #define EEPROM_CS 0x02
1047 #define EEPROM_SK 0x01
1048 #define EEPROM_DI 0x04
1049 #define EEPROM_DO 0x08
1050
1051 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1052 {
1053 uint16_t val;
1054 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1055 if (eeprom93xx_read(s->eeprom)) {
1056 val |= EEPROM_DO;
1057 } else {
1058 val &= ~EEPROM_DO;
1059 }
1060 TRACE(EEPROM, logout("val=0x%04x\n", val));
1061 return val;
1062 }
1063
1064 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1065 {
1066 TRACE(EEPROM, logout("val=0x%02x\n", val));
1067
1068 /* mask unwriteable bits */
1069 #if 0
1070 val = SET_MASKED(val, 0x31, eeprom->value);
1071 #endif
1072
1073 int eecs = ((val & EEPROM_CS) != 0);
1074 int eesk = ((val & EEPROM_SK) != 0);
1075 int eedi = ((val & EEPROM_DI) != 0);
1076 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1077 }
1078
1079 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1080 {
1081 s->pointer = le32_to_cpu(val);
1082 TRACE(OTHER, logout("val=0x%08x\n", val));
1083 }
1084
1085 /*****************************************************************************
1086 *
1087 * MDI emulation.
1088 *
1089 ****************************************************************************/
1090
1091 #if defined(DEBUG_EEPRO100)
1092 static const char * const mdi_op_name[] = {
1093 "opcode 0",
1094 "write",
1095 "read",
1096 "opcode 3"
1097 };
1098
1099 static const char * const mdi_reg_name[] = {
1100 "Control",
1101 "Status",
1102 "PHY Identification (Word 1)",
1103 "PHY Identification (Word 2)",
1104 "Auto-Negotiation Advertisement",
1105 "Auto-Negotiation Link Partner Ability",
1106 "Auto-Negotiation Expansion"
1107 };
1108
1109 static const char *reg2name(uint8_t reg)
1110 {
1111 static char buffer[10];
1112 const char *p = buffer;
1113 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1114 p = mdi_reg_name[reg];
1115 } else {
1116 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1117 }
1118 return p;
1119 }
1120 #endif /* DEBUG_EEPRO100 */
1121
1122 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1123 {
1124 uint32_t val;
1125 memcpy(&val, &s->mem[0x10], sizeof(val));
1126
1127 #ifdef DEBUG_EEPRO100
1128 uint8_t raiseint = (val & BIT(29)) >> 29;
1129 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1130 uint8_t phy = (val & BITS(25, 21)) >> 21;
1131 uint8_t reg = (val & BITS(20, 16)) >> 16;
1132 uint16_t data = (val & BITS(15, 0));
1133 #endif
1134 /* Emulation takes no time to finish MDI transaction. */
1135 val |= BIT(28);
1136 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1137 val, raiseint, mdi_op_name[opcode], phy,
1138 reg2name(reg), data));
1139 return val;
1140 }
1141
1142 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1143 {
1144 uint8_t raiseint = (val & BIT(29)) >> 29;
1145 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1146 uint8_t phy = (val & BITS(25, 21)) >> 21;
1147 uint8_t reg = (val & BITS(20, 16)) >> 16;
1148 uint16_t data = (val & BITS(15, 0));
1149 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1150 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1151 if (phy != 1) {
1152 /* Unsupported PHY address. */
1153 #if 0
1154 logout("phy must be 1 but is %u\n", phy);
1155 #endif
1156 data = 0;
1157 } else if (opcode != 1 && opcode != 2) {
1158 /* Unsupported opcode. */
1159 logout("opcode must be 1 or 2 but is %u\n", opcode);
1160 data = 0;
1161 } else if (reg > 6) {
1162 /* Unsupported register. */
1163 logout("register must be 0...6 but is %u\n", reg);
1164 data = 0;
1165 } else {
1166 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1167 val, raiseint, mdi_op_name[opcode], phy,
1168 reg2name(reg), data));
1169 if (opcode == 1) {
1170 /* MDI write */
1171 switch (reg) {
1172 case 0: /* Control Register */
1173 if (data & 0x8000) {
1174 /* Reset status and control registers to default. */
1175 s->mdimem[0] = eepro100_mdi_default[0];
1176 s->mdimem[1] = eepro100_mdi_default[1];
1177 data = s->mdimem[reg];
1178 } else {
1179 /* Restart Auto Configuration = Normal Operation */
1180 data &= ~0x0200;
1181 }
1182 break;
1183 case 1: /* Status Register */
1184 missing("not writable");
1185 data = s->mdimem[reg];
1186 break;
1187 case 2: /* PHY Identification Register (Word 1) */
1188 case 3: /* PHY Identification Register (Word 2) */
1189 missing("not implemented");
1190 break;
1191 case 4: /* Auto-Negotiation Advertisement Register */
1192 case 5: /* Auto-Negotiation Link Partner Ability Register */
1193 break;
1194 case 6: /* Auto-Negotiation Expansion Register */
1195 default:
1196 missing("not implemented");
1197 }
1198 s->mdimem[reg] = data;
1199 } else if (opcode == 2) {
1200 /* MDI read */
1201 switch (reg) {
1202 case 0: /* Control Register */
1203 if (data & 0x8000) {
1204 /* Reset status and control registers to default. */
1205 s->mdimem[0] = eepro100_mdi_default[0];
1206 s->mdimem[1] = eepro100_mdi_default[1];
1207 }
1208 break;
1209 case 1: /* Status Register */
1210 s->mdimem[reg] |= 0x0020;
1211 break;
1212 case 2: /* PHY Identification Register (Word 1) */
1213 case 3: /* PHY Identification Register (Word 2) */
1214 case 4: /* Auto-Negotiation Advertisement Register */
1215 break;
1216 case 5: /* Auto-Negotiation Link Partner Ability Register */
1217 s->mdimem[reg] = 0x41fe;
1218 break;
1219 case 6: /* Auto-Negotiation Expansion Register */
1220 s->mdimem[reg] = 0x0001;
1221 break;
1222 }
1223 data = s->mdimem[reg];
1224 }
1225 /* Emulation takes no time to finish MDI transaction.
1226 * Set MDI bit in SCB status register. */
1227 s->mem[SCBAck] |= 0x08;
1228 val |= BIT(28);
1229 if (raiseint) {
1230 eepro100_mdi_interrupt(s);
1231 }
1232 }
1233 val = (val & 0xffff0000) + data;
1234 memcpy(&s->mem[0x10], &val, sizeof(val));
1235 }
1236
1237 /*****************************************************************************
1238 *
1239 * Port emulation.
1240 *
1241 ****************************************************************************/
1242
1243 #define PORT_SOFTWARE_RESET 0
1244 #define PORT_SELFTEST 1
1245 #define PORT_SELECTIVE_RESET 2
1246 #define PORT_DUMP 3
1247 #define PORT_SELECTION_MASK 3
1248
1249 typedef struct {
1250 uint32_t st_sign; /* Self Test Signature */
1251 uint32_t st_result; /* Self Test Results */
1252 } eepro100_selftest_t;
1253
1254 static uint32_t eepro100_read_port(EEPRO100State * s)
1255 {
1256 return 0;
1257 }
1258
1259 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1260 {
1261 val = le32_to_cpu(val);
1262 uint32_t address = (val & ~PORT_SELECTION_MASK);
1263 uint8_t selection = (val & PORT_SELECTION_MASK);
1264 switch (selection) {
1265 case PORT_SOFTWARE_RESET:
1266 nic_reset(s);
1267 break;
1268 case PORT_SELFTEST:
1269 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1270 eepro100_selftest_t data;
1271 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1272 data.st_sign = 0xffffffff;
1273 data.st_result = 0;
1274 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1275 break;
1276 case PORT_SELECTIVE_RESET:
1277 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1278 nic_selective_reset(s);
1279 break;
1280 default:
1281 logout("val=0x%08x\n", val);
1282 missing("unknown port selection");
1283 }
1284 }
1285
1286 /*****************************************************************************
1287 *
1288 * General hardware emulation.
1289 *
1290 ****************************************************************************/
1291
1292 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1293 {
1294 uint8_t val = 0;
1295 if (addr <= sizeof(s->mem) - sizeof(val)) {
1296 memcpy(&val, &s->mem[addr], sizeof(val));
1297 }
1298
1299 switch (addr) {
1300 case SCBStatus:
1301 case SCBAck:
1302 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1303 break;
1304 case SCBCmd:
1305 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1306 #if 0
1307 val = eepro100_read_command(s);
1308 #endif
1309 break;
1310 case SCBIntmask:
1311 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1312 break;
1313 case SCBPort + 3:
1314 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1315 break;
1316 case SCBeeprom:
1317 val = eepro100_read_eeprom(s);
1318 break;
1319 case SCBpmdr: /* Power Management Driver Register */
1320 val = 0;
1321 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1322 break;
1323 case SCBgstat: /* General Status Register */
1324 /* 100 Mbps full duplex, valid link */
1325 val = 0x07;
1326 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1327 break;
1328 default:
1329 logout("addr=%s val=0x%02x\n", regname(addr), val);
1330 missing("unknown byte read");
1331 }
1332 return val;
1333 }
1334
1335 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1336 {
1337 uint16_t val = 0;
1338 if (addr <= sizeof(s->mem) - sizeof(val)) {
1339 memcpy(&val, &s->mem[addr], sizeof(val));
1340 }
1341
1342 switch (addr) {
1343 case SCBStatus:
1344 case SCBCmd:
1345 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1346 break;
1347 case SCBeeprom:
1348 val = eepro100_read_eeprom(s);
1349 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1350 break;
1351 default:
1352 logout("addr=%s val=0x%04x\n", regname(addr), val);
1353 missing("unknown word read");
1354 }
1355 return val;
1356 }
1357
1358 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1359 {
1360 uint32_t val = 0;
1361 if (addr <= sizeof(s->mem) - sizeof(val)) {
1362 memcpy(&val, &s->mem[addr], sizeof(val));
1363 }
1364
1365 switch (addr) {
1366 case SCBStatus:
1367 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1368 break;
1369 case SCBPointer:
1370 #if 0
1371 val = eepro100_read_pointer(s);
1372 #endif
1373 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1374 break;
1375 case SCBPort:
1376 val = eepro100_read_port(s);
1377 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1378 break;
1379 case SCBCtrlMDI:
1380 val = eepro100_read_mdi(s);
1381 break;
1382 default:
1383 logout("addr=%s val=0x%08x\n", regname(addr), val);
1384 missing("unknown longword read");
1385 }
1386 return val;
1387 }
1388
1389 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1390 {
1391 /* SCBStatus is readonly. */
1392 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1393 memcpy(&s->mem[addr], &val, sizeof(val));
1394 }
1395
1396 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1397
1398 switch (addr) {
1399 case SCBStatus:
1400 break;
1401 case SCBAck:
1402 eepro100_acknowledge(s);
1403 break;
1404 case SCBCmd:
1405 eepro100_write_command(s, val);
1406 break;
1407 case SCBIntmask:
1408 if (val & BIT(1)) {
1409 eepro100_swi_interrupt(s);
1410 }
1411 eepro100_interrupt(s, 0);
1412 break;
1413 case SCBPort + 3:
1414 case SCBFlow: /* does not exist on 82557 */
1415 case SCBFlow + 1:
1416 case SCBFlow + 2:
1417 case SCBpmdr: /* does not exist on 82557 */
1418 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1419 break;
1420 case SCBeeprom:
1421 eepro100_write_eeprom(s->eeprom, val);
1422 break;
1423 default:
1424 logout("addr=%s val=0x%02x\n", regname(addr), val);
1425 missing("unknown byte write");
1426 }
1427 }
1428
1429 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1430 {
1431 /* SCBStatus is readonly. */
1432 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1433 memcpy(&s->mem[addr], &val, sizeof(val));
1434 }
1435
1436 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1437
1438 switch (addr) {
1439 case SCBStatus:
1440 s->mem[SCBAck] = (val >> 8);
1441 eepro100_acknowledge(s);
1442 break;
1443 case SCBCmd:
1444 eepro100_write_command(s, val);
1445 eepro100_write1(s, SCBIntmask, val >> 8);
1446 break;
1447 case SCBeeprom:
1448 eepro100_write_eeprom(s->eeprom, val);
1449 break;
1450 default:
1451 logout("addr=%s val=0x%04x\n", regname(addr), val);
1452 missing("unknown word write");
1453 }
1454 }
1455
1456 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1457 {
1458 if (addr <= sizeof(s->mem) - sizeof(val)) {
1459 memcpy(&s->mem[addr], &val, sizeof(val));
1460 }
1461
1462 switch (addr) {
1463 case SCBPointer:
1464 eepro100_write_pointer(s, val);
1465 break;
1466 case SCBPort:
1467 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1468 eepro100_write_port(s, val);
1469 break;
1470 case SCBCtrlMDI:
1471 eepro100_write_mdi(s, val);
1472 break;
1473 default:
1474 logout("addr=%s val=0x%08x\n", regname(addr), val);
1475 missing("unknown longword write");
1476 }
1477 }
1478
1479 /*****************************************************************************
1480 *
1481 * Port mapped I/O.
1482 *
1483 ****************************************************************************/
1484
1485 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1486 {
1487 EEPRO100State *s = opaque;
1488 #if 0
1489 logout("addr=%s\n", regname(addr));
1490 #endif
1491 return eepro100_read1(s, addr - s->region[1]);
1492 }
1493
1494 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1495 {
1496 EEPRO100State *s = opaque;
1497 return eepro100_read2(s, addr - s->region[1]);
1498 }
1499
1500 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1501 {
1502 EEPRO100State *s = opaque;
1503 return eepro100_read4(s, addr - s->region[1]);
1504 }
1505
1506 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1507 {
1508 EEPRO100State *s = opaque;
1509 #if 0
1510 logout("addr=%s val=0x%02x\n", regname(addr), val);
1511 #endif
1512 eepro100_write1(s, addr - s->region[1], val);
1513 }
1514
1515 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1516 {
1517 EEPRO100State *s = opaque;
1518 eepro100_write2(s, addr - s->region[1], val);
1519 }
1520
1521 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1522 {
1523 EEPRO100State *s = opaque;
1524 eepro100_write4(s, addr - s->region[1], val);
1525 }
1526
1527 /***********************************************************/
1528 /* PCI EEPRO100 definitions */
1529
1530 static void pci_map(PCIDevice * pci_dev, int region_num,
1531 pcibus_t addr, pcibus_t size, int type)
1532 {
1533 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1534
1535 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1536 "size=0x%08"FMT_PCIBUS", type=%d\n",
1537 region_num, addr, size, type));
1538
1539 assert(region_num == 1);
1540 register_ioport_write(addr, size, 1, ioport_write1, s);
1541 register_ioport_read(addr, size, 1, ioport_read1, s);
1542 register_ioport_write(addr, size, 2, ioport_write2, s);
1543 register_ioport_read(addr, size, 2, ioport_read2, s);
1544 register_ioport_write(addr, size, 4, ioport_write4, s);
1545 register_ioport_read(addr, size, 4, ioport_read4, s);
1546
1547 s->region[region_num] = addr;
1548 }
1549
1550 /*****************************************************************************
1551 *
1552 * Memory mapped I/O.
1553 *
1554 ****************************************************************************/
1555
1556 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1557 {
1558 EEPRO100State *s = opaque;
1559 #if 0
1560 logout("addr=%s val=0x%02x\n", regname(addr), val);
1561 #endif
1562 eepro100_write1(s, addr, val);
1563 }
1564
1565 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1566 {
1567 EEPRO100State *s = opaque;
1568 #if 0
1569 logout("addr=%s val=0x%02x\n", regname(addr), val);
1570 #endif
1571 eepro100_write2(s, addr, val);
1572 }
1573
1574 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1575 {
1576 EEPRO100State *s = opaque;
1577 #if 0
1578 logout("addr=%s val=0x%02x\n", regname(addr), val);
1579 #endif
1580 eepro100_write4(s, addr, val);
1581 }
1582
1583 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1584 {
1585 EEPRO100State *s = opaque;
1586 #if 0
1587 logout("addr=%s\n", regname(addr));
1588 #endif
1589 return eepro100_read1(s, addr);
1590 }
1591
1592 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1593 {
1594 EEPRO100State *s = opaque;
1595 #if 0
1596 logout("addr=%s\n", regname(addr));
1597 #endif
1598 return eepro100_read2(s, addr);
1599 }
1600
1601 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1602 {
1603 EEPRO100State *s = opaque;
1604 #if 0
1605 logout("addr=%s\n", regname(addr));
1606 #endif
1607 return eepro100_read4(s, addr);
1608 }
1609
1610 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1611 pci_mmio_writeb,
1612 pci_mmio_writew,
1613 pci_mmio_writel
1614 };
1615
1616 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1617 pci_mmio_readb,
1618 pci_mmio_readw,
1619 pci_mmio_readl
1620 };
1621
1622 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1623 pcibus_t addr, pcibus_t size, int type)
1624 {
1625 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1626
1627 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1628 "size=0x%08"FMT_PCIBUS", type=%d\n",
1629 region_num, addr, size, type));
1630
1631 assert(region_num == 0 || region_num == 2);
1632
1633 /* Map control / status registers and flash. */
1634 cpu_register_physical_memory(addr, size, s->mmio_index);
1635 s->region[region_num] = addr;
1636 }
1637
1638 static int nic_can_receive(VLANClientState *nc)
1639 {
1640 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1641 TRACE(RXTX, logout("%p\n", s));
1642 return get_ru_state(s) == ru_ready;
1643 #if 0
1644 return !eepro100_buffer_full(s);
1645 #endif
1646 }
1647
1648 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1649 {
1650 /* TODO:
1651 * - Magic packets should set bit 30 in power management driver register.
1652 * - Interesting packets should set bit 29 in power management driver register.
1653 */
1654 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1655 uint16_t rfd_status = 0xa000;
1656 static const uint8_t broadcast_macaddr[6] =
1657 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1658
1659 if (s->configuration[8] & 0x80) {
1660 /* CSMA is disabled. */
1661 logout("%p received while CSMA is disabled\n", s);
1662 return -1;
1663 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1664 /* Short frame and configuration byte 7/0 (discard short receive) set:
1665 * Short frame is discarded */
1666 logout("%p received short frame (%zu byte)\n", s, size);
1667 s->statistics.rx_short_frame_errors++;
1668 #if 0
1669 return -1;
1670 #endif
1671 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1672 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1673 * Long frames are discarded. */
1674 logout("%p received long frame (%zu byte), ignored\n", s, size);
1675 return -1;
1676 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1677 /* Frame matches individual address. */
1678 /* TODO: check configuration byte 15/4 (ignore U/L). */
1679 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1680 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1681 /* Broadcast frame. */
1682 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1683 rfd_status |= 0x0002;
1684 } else if (buf[0] & 0x01) {
1685 /* Multicast frame. */
1686 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1687 if (s->configuration[21] & BIT(3)) {
1688 /* Multicast all bit is set, receive all multicast frames. */
1689 } else {
1690 unsigned mcast_idx = compute_mcast_idx(buf);
1691 assert(mcast_idx < 64);
1692 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1693 /* Multicast frame is allowed in hash table. */
1694 } else if (s->configuration[15] & BIT(0)) {
1695 /* Promiscuous: receive all. */
1696 rfd_status |= 0x0004;
1697 } else {
1698 TRACE(RXTX, logout("%p multicast ignored\n", s));
1699 return -1;
1700 }
1701 }
1702 /* TODO: Next not for promiscuous mode? */
1703 rfd_status |= 0x0002;
1704 } else if (s->configuration[15] & BIT(0)) {
1705 /* Promiscuous: receive all. */
1706 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1707 rfd_status |= 0x0004;
1708 } else if (s->configuration[20] & BIT(6)) {
1709 /* Multiple IA bit set. */
1710 unsigned mcast_idx = compute_mcast_idx(buf);
1711 assert(mcast_idx < 64);
1712 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1713 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1714 } else {
1715 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1716 return -1;
1717 }
1718 } else {
1719 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1720 nic_dump(buf, size)));
1721 return size;
1722 }
1723
1724 if (get_ru_state(s) != ru_ready) {
1725 /* No resources available. */
1726 logout("no resources, state=%u\n", get_ru_state(s));
1727 /* TODO: RNR interrupt only at first failed frame? */
1728 eepro100_rnr_interrupt(s);
1729 s->statistics.rx_resource_errors++;
1730 #if 0
1731 assert(!"no resources");
1732 #endif
1733 return -1;
1734 }
1735 /* !!! */
1736 eepro100_rx_t rx;
1737 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1738 offsetof(eepro100_rx_t, packet));
1739 uint16_t rfd_command = le16_to_cpu(rx.command);
1740 uint16_t rfd_size = le16_to_cpu(rx.size);
1741
1742 if (size > rfd_size) {
1743 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1744 "(%zu bytes); data truncated\n", rfd_size, size);
1745 size = rfd_size;
1746 }
1747 if (size < 64) {
1748 rfd_status |= 0x0080;
1749 }
1750 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1751 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1752 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1753 rfd_status);
1754 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1755 /* Early receive interrupt not supported. */
1756 #if 0
1757 eepro100_er_interrupt(s);
1758 #endif
1759 /* Receive CRC Transfer not supported. */
1760 if (s->configuration[18] & BIT(2)) {
1761 missing("Receive CRC Transfer");
1762 return -1;
1763 }
1764 /* TODO: check stripping enable bit. */
1765 #if 0
1766 assert(!(s->configuration[17] & BIT(0)));
1767 #endif
1768 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1769 offsetof(eepro100_rx_t, packet), buf, size);
1770 s->statistics.rx_good_frames++;
1771 eepro100_fr_interrupt(s);
1772 s->ru_offset = le32_to_cpu(rx.link);
1773 if (rfd_command & COMMAND_EL) {
1774 /* EL bit is set, so this was the last frame. */
1775 logout("receive: Running out of frames\n");
1776 set_ru_state(s, ru_suspended);
1777 }
1778 if (rfd_command & COMMAND_S) {
1779 /* S bit is set. */
1780 set_ru_state(s, ru_suspended);
1781 }
1782 return size;
1783 }
1784
1785 static const VMStateDescription vmstate_eepro100 = {
1786 .version_id = 3,
1787 .minimum_version_id = 2,
1788 .minimum_version_id_old = 2,
1789 .fields = (VMStateField []) {
1790 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1791 VMSTATE_UNUSED(32),
1792 VMSTATE_BUFFER(mult, EEPRO100State),
1793 VMSTATE_BUFFER(mem, EEPRO100State),
1794 /* Save all members of struct between scb_stat and mem. */
1795 VMSTATE_UINT8(scb_stat, EEPRO100State),
1796 VMSTATE_UINT8(int_stat, EEPRO100State),
1797 VMSTATE_UNUSED(3*4),
1798 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1799 VMSTATE_UNUSED(19*4),
1800 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1801 /* The eeprom should be saved and restored by its own routines. */
1802 VMSTATE_UINT32(device, EEPRO100State),
1803 /* TODO check device. */
1804 VMSTATE_UINT32(pointer, EEPRO100State),
1805 VMSTATE_UINT32(cu_base, EEPRO100State),
1806 VMSTATE_UINT32(cu_offset, EEPRO100State),
1807 VMSTATE_UINT32(ru_base, EEPRO100State),
1808 VMSTATE_UINT32(ru_offset, EEPRO100State),
1809 VMSTATE_UINT32(statsaddr, EEPRO100State),
1810 /* Save eepro100_stats_t statistics. */
1811 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1812 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1817 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1818 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1819 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1820 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1825 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1826 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1827 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1828 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1829 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1830 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1831 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1832 /* Configuration bytes. */
1833 VMSTATE_BUFFER(configuration, EEPRO100State),
1834 VMSTATE_END_OF_LIST()
1835 }
1836 };
1837
1838 static void nic_cleanup(VLANClientState *nc)
1839 {
1840 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1841
1842 s->nic = NULL;
1843 }
1844
1845 static int pci_nic_uninit(PCIDevice *pci_dev)
1846 {
1847 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1848
1849 cpu_unregister_io_memory(s->mmio_index);
1850 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1851 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1852 qemu_del_vlan_client(&s->nic->nc);
1853 return 0;
1854 }
1855
1856 static NetClientInfo net_eepro100_info = {
1857 .type = NET_CLIENT_TYPE_NIC,
1858 .size = sizeof(NICState),
1859 .can_receive = nic_can_receive,
1860 .receive = nic_receive,
1861 .cleanup = nic_cleanup,
1862 };
1863
1864 static int e100_nic_init(PCIDevice *pci_dev)
1865 {
1866 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1867 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1868 pci_dev->qdev.info);
1869
1870 TRACE(OTHER, logout("\n"));
1871
1872 s->device = e100_device->device;
1873
1874 e100_pci_reset(s, e100_device);
1875
1876 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1877 * i82559 and later support 64 or 256 word EEPROM. */
1878 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1879
1880 /* Handler for memory-mapped I/O */
1881 s->mmio_index =
1882 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
1883 DEVICE_NATIVE_ENDIAN);
1884
1885 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1886 PCI_BASE_ADDRESS_SPACE_MEMORY |
1887 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1888 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1889 pci_map);
1890 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1891 pci_mmio_map);
1892
1893 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1894 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1895 assert(s->region[1] == 0);
1896
1897 nic_reset(s);
1898
1899 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1900 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1901
1902 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1903 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1904
1905 qemu_register_reset(nic_reset, s);
1906
1907 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1908 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1909 s->vmstate->name = s->nic->nc.model;
1910 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1911
1912 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1913
1914 return 0;
1915 }
1916
1917 static E100PCIDeviceInfo e100_devices[] = {
1918 {
1919 .pci.qdev.name = "i82550",
1920 .pci.qdev.desc = "Intel i82550 Ethernet",
1921 .device = i82550,
1922 /* TODO: check device id. */
1923 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1924 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1925 .revision = 0x0e,
1926 /* TODO: check size of statistical counters. */
1927 .stats_size = 80,
1928 /* TODO: check extended tcb support. */
1929 .has_extended_tcb_support = true,
1930 .power_management = true,
1931 },{
1932 .pci.qdev.name = "i82551",
1933 .pci.qdev.desc = "Intel i82551 Ethernet",
1934 .device = i82551,
1935 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1936 /* Revision ID: 0x0f, 0x10. */
1937 .revision = 0x0f,
1938 /* TODO: check size of statistical counters. */
1939 .stats_size = 80,
1940 .has_extended_tcb_support = true,
1941 .power_management = true,
1942 },{
1943 .pci.qdev.name = "i82557a",
1944 .pci.qdev.desc = "Intel i82557A Ethernet",
1945 .device = i82557A,
1946 .device_id = PCI_DEVICE_ID_INTEL_82557,
1947 .revision = 0x01,
1948 .power_management = false,
1949 },{
1950 .pci.qdev.name = "i82557b",
1951 .pci.qdev.desc = "Intel i82557B Ethernet",
1952 .device = i82557B,
1953 .device_id = PCI_DEVICE_ID_INTEL_82557,
1954 .revision = 0x02,
1955 .power_management = false,
1956 },{
1957 .pci.qdev.name = "i82557c",
1958 .pci.qdev.desc = "Intel i82557C Ethernet",
1959 .device = i82557C,
1960 .device_id = PCI_DEVICE_ID_INTEL_82557,
1961 .revision = 0x03,
1962 .power_management = false,
1963 },{
1964 .pci.qdev.name = "i82558a",
1965 .pci.qdev.desc = "Intel i82558A Ethernet",
1966 .device = i82558A,
1967 .device_id = PCI_DEVICE_ID_INTEL_82557,
1968 .revision = 0x04,
1969 .stats_size = 76,
1970 .has_extended_tcb_support = true,
1971 .power_management = true,
1972 },{
1973 .pci.qdev.name = "i82558b",
1974 .pci.qdev.desc = "Intel i82558B Ethernet",
1975 .device = i82558B,
1976 .device_id = PCI_DEVICE_ID_INTEL_82557,
1977 .revision = 0x05,
1978 .stats_size = 76,
1979 .has_extended_tcb_support = true,
1980 .power_management = true,
1981 },{
1982 .pci.qdev.name = "i82559a",
1983 .pci.qdev.desc = "Intel i82559A Ethernet",
1984 .device = i82559A,
1985 .device_id = PCI_DEVICE_ID_INTEL_82557,
1986 .revision = 0x06,
1987 .stats_size = 80,
1988 .has_extended_tcb_support = true,
1989 .power_management = true,
1990 },{
1991 .pci.qdev.name = "i82559b",
1992 .pci.qdev.desc = "Intel i82559B Ethernet",
1993 .device = i82559B,
1994 .device_id = PCI_DEVICE_ID_INTEL_82557,
1995 .revision = 0x07,
1996 .stats_size = 80,
1997 .has_extended_tcb_support = true,
1998 .power_management = true,
1999 },{
2000 .pci.qdev.name = "i82559c",
2001 .pci.qdev.desc = "Intel i82559C Ethernet",
2002 .device = i82559C,
2003 .device_id = PCI_DEVICE_ID_INTEL_82557,
2004 #if 0
2005 .revision = 0x08,
2006 #endif
2007 /* TODO: Windows wants revision id 0x0c. */
2008 .revision = 0x0c,
2009 .stats_size = 80,
2010 .has_extended_tcb_support = true,
2011 .power_management = true,
2012 },{
2013 .pci.qdev.name = "i82559er",
2014 .pci.qdev.desc = "Intel i82559ER Ethernet",
2015 .device = i82559ER,
2016 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2017 .revision = 0x09,
2018 .stats_size = 80,
2019 .has_extended_tcb_support = true,
2020 .power_management = true,
2021 },{
2022 .pci.qdev.name = "i82562",
2023 .pci.qdev.desc = "Intel i82562 Ethernet",
2024 .device = i82562,
2025 /* TODO: check device id. */
2026 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2027 /* TODO: wrong revision id. */
2028 .revision = 0x0e,
2029 .stats_size = 80,
2030 .has_extended_tcb_support = true,
2031 .power_management = true,
2032 },{
2033 /* Toshiba Tecra 8200. */
2034 .pci.qdev.name = "i82801",
2035 .pci.qdev.desc = "Intel i82801 Ethernet",
2036 .device = i82801,
2037 .device_id = 0x2449,
2038 .revision = 0x03,
2039 .stats_size = 80,
2040 .has_extended_tcb_support = true,
2041 .power_management = true,
2042 }
2043 };
2044
2045 static Property e100_properties[] = {
2046 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2047 DEFINE_PROP_END_OF_LIST(),
2048 };
2049
2050 static void eepro100_register_devices(void)
2051 {
2052 size_t i;
2053 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2054 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2055 /* We use the same rom file for all device ids.
2056 QEMU fixes the device id during rom load. */
2057 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2058 pci_dev->init = e100_nic_init;
2059 pci_dev->exit = pci_nic_uninit;
2060 pci_dev->qdev.props = e100_properties;
2061 pci_dev->qdev.size = sizeof(EEPRO100State);
2062 pci_qdev_register(pci_dev);
2063 }
2064 }
2065
2066 device_init(eepro100_register_devices)
AR7 emulation for QEMU