hw/intc/arm_gicv3_common.c

   1 /*
   2  * ARM GICv3 support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Copyright (c) 2015 Huawei.
   6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   7  * Written by Peter Maydell
   8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation, either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qom/cpu.h"
  27 #include "hw/intc/arm_gicv3_common.h"
  28 #include "gicv3_internal.h"
  29 #include "hw/arm/linux-boot-if.h"
  30
  31 static void gicv3_pre_save(void *opaque)
  32 {
  33     GICv3State *s = (GICv3State *)opaque;
  34     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
  35
  36     if (c->pre_save) {
  37         c->pre_save(s);
  38     }
  39 }
  40
  41 static int gicv3_post_load(void *opaque, int version_id)
  42 {
  43     GICv3State *s = (GICv3State *)opaque;
  44     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
  45
  46     if (c->post_load) {
  47         c->post_load(s);
  48     }
  49     return 0;
  50 }
  51
  52 static const VMStateDescription vmstate_gicv3_cpu = {
  53     .name = "arm_gicv3_cpu",
  54     .version_id = 1,
  55     .minimum_version_id = 1,
  56     .fields = (VMStateField[]) {
  57         VMSTATE_UINT32(level, GICv3CPUState),
  58         VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
  59         VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
  60         VMSTATE_UINT32(gicr_waker, GICv3CPUState),
  61         VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
  62         VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
  63         VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
  64         VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
  65         VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
  66         VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
  67         VMSTATE_UINT32(edge_trigger, GICv3CPUState),
  68         VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
  69         VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
  70         VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
  71         VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
  72         VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
  73         VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
  74         VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
  75         VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
  76         VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
  77         VMSTATE_END_OF_LIST()
  78     }
  79 };
  80
  81 static const VMStateDescription vmstate_gicv3 = {
  82     .name = "arm_gicv3",
  83     .version_id = 1,
  84     .minimum_version_id = 1,
  85     .pre_save = gicv3_pre_save,
  86     .post_load = gicv3_post_load,
  87     .fields = (VMStateField[]) {
  88         VMSTATE_UINT32(gicd_ctlr, GICv3State),
  89         VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
  90         VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
  91         VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
  92         VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
  93         VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
  94         VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
  95         VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
  96         VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
  97         VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
  98         VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
  99         VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
 100                              DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
 101         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
 102                                              vmstate_gicv3_cpu, GICv3CPUState),
 103         VMSTATE_END_OF_LIST()
 104     }
 105 };
 106
 107 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 108                               const MemoryRegionOps *ops)
 109 {
 110     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 111     int i;
 112
 113     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 114      * GPIO array layout is thus:
 115      *  [0..N-1] spi
 116      *  [N..N+31] PPIs for CPU 0
 117      *  [N+32..N+63] PPIs for CPU 1
 118      *   ...
 119      */
 120     i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
 121     qdev_init_gpio_in(DEVICE(s), handler, i);
 122
 123     for (i = 0; i < s->num_cpu; i++) {
 124         sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
 125     }
 126     for (i = 0; i < s->num_cpu; i++) {
 127         sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
 128     }
 129
 130     memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
 131                           "gicv3_dist", 0x10000);
 132     memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
 133                           "gicv3_redist", 0x20000 * s->num_cpu);
 134
 135     sysbus_init_mmio(sbd, &s->iomem_dist);
 136     sysbus_init_mmio(sbd, &s->iomem_redist);
 137 }
 138
 139 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
 140 {
 141     GICv3State *s = ARM_GICV3_COMMON(dev);
 142     int i;
 143
 144     /* revision property is actually reserved and currently used only in order
 145      * to keep the interface compatible with GICv2 code, avoiding extra
 146      * conditions. However, in future it could be used, for example, if we
 147      * implement GICv4.
 148      */
 149     if (s->revision != 3) {
 150         error_setg(errp, "unsupported GIC revision %d", s->revision);
 151         return;
 152     }
 153
 154     if (s->num_irq > GICV3_MAXIRQ) {
 155         error_setg(errp,
 156                    "requested %u interrupt lines exceeds GIC maximum %d",
 157                    s->num_irq, GICV3_MAXIRQ);
 158         return;
 159     }
 160     if (s->num_irq < GIC_INTERNAL) {
 161         error_setg(errp,
 162                    "requested %u interrupt lines is below GIC minimum %d",
 163                    s->num_irq, GIC_INTERNAL);
 164         return;
 165     }
 166
 167     /* ITLinesNumber is represented as (N / 32) - 1, so this is an
 168      * implementation imposed restriction, not an architectural one,
 169      * so we don't have to deal with bitfields where only some of the
 170      * bits in a 32-bit word should be valid.
 171      */
 172     if (s->num_irq % 32) {
 173         error_setg(errp,
 174                    "%d interrupt lines unsupported: not divisible by 32",
 175                    s->num_irq);
 176         return;
 177     }
 178
 179     s->cpu = g_new0(GICv3CPUState, s->num_cpu);
 180
 181     for (i = 0; i < s->num_cpu; i++) {
 182         CPUState *cpu = qemu_get_cpu(i);
 183         uint64_t cpu_affid;
 184         int last;
 185
 186         s->cpu[i].cpu = cpu;
 187         s->cpu[i].gic = s;
 188
 189         /* Pre-construct the GICR_TYPER:
 190          * For our implementation:
 191          *  Top 32 bits are the affinity value of the associated CPU
 192          *  CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
 193          *  Processor_Number == CPU index starting from 0
 194          *  DPGS == 0 (GICR_CTLR.DPG* not supported)
 195          *  Last == 1 if this is the last redistributor in a series of
 196          *            contiguous redistributor pages
 197          *  DirectLPI == 0 (direct injection of LPIs not supported)
 198          *  VLPIS == 0 (virtual LPIs not supported)
 199          *  PLPIS == 0 (physical LPIs not supported)
 200          */
 201         cpu_affid = object_property_get_int(OBJECT(cpu), "mp-affinity", NULL);
 202         last = (i == s->num_cpu - 1);
 203
 204         /* The CPU mp-affinity property is in MPIDR register format; squash
 205          * the affinity bytes into 32 bits as the GICR_TYPER has them.
 206          */
 207         cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
 208                      (cpu_affid & 0xFFFFFF);
 209         s->cpu[i].gicr_typer = (cpu_affid << 32) |
 210             (1 << 24) |
 211             (i << 8) |
 212             (last << 4);
 213     }
 214 }
 215
 216 static void arm_gicv3_common_reset(DeviceState *dev)
 217 {
 218     GICv3State *s = ARM_GICV3_COMMON(dev);
 219     int i;
 220
 221     for (i = 0; i < s->num_cpu; i++) {
 222         GICv3CPUState *cs = &s->cpu[i];
 223
 224         cs->level = 0;
 225         cs->gicr_ctlr = 0;
 226         cs->gicr_statusr[GICV3_S] = 0;
 227         cs->gicr_statusr[GICV3_NS] = 0;
 228         cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
 229         cs->gicr_propbaser = 0;
 230         cs->gicr_pendbaser = 0;
 231         /* If we're resetting a TZ-aware GIC as if secure firmware
 232          * had set it up ready to start a kernel in non-secure, we
 233          * need to set interrupts to group 1 so the kernel can use them.
 234          * Otherwise they reset to group 0 like the hardware.
 235          */
 236         if (s->irq_reset_nonsecure) {
 237             cs->gicr_igroupr0 = 0xffffffff;
 238         } else {
 239             cs->gicr_igroupr0 = 0;
 240         }
 241
 242         cs->gicr_ienabler0 = 0;
 243         cs->gicr_ipendr0 = 0;
 244         cs->gicr_iactiver0 = 0;
 245         cs->edge_trigger = 0xffff;
 246         cs->gicr_igrpmodr0 = 0;
 247         cs->gicr_nsacr = 0;
 248         memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
 249
 250         cs->hppi.prio = 0xff;
 251
 252         /* State in the CPU interface must *not* be reset here, because it
 253          * is part of the CPU's reset domain, not the GIC device's.
 254          */
 255     }
 256
 257     /* For our implementation affinity routing is always enabled */
 258     if (s->security_extn) {
 259         s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
 260     } else {
 261         s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
 262     }
 263
 264     s->gicd_statusr[GICV3_S] = 0;
 265     s->gicd_statusr[GICV3_NS] = 0;
 266
 267     memset(s->group, 0, sizeof(s->group));
 268     memset(s->grpmod, 0, sizeof(s->grpmod));
 269     memset(s->enabled, 0, sizeof(s->enabled));
 270     memset(s->pending, 0, sizeof(s->pending));
 271     memset(s->active, 0, sizeof(s->active));
 272     memset(s->level, 0, sizeof(s->level));
 273     memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
 274     memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
 275     memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
 276     memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
 277     /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must
 278      * write these to get sane behaviour and we need not populate the
 279      * pointer cache here; however having the cache be different for
 280      * "happened to be 0 from reset" and "guest wrote 0" would be
 281      * too confusing.
 282      */
 283     gicv3_cache_all_target_cpustates(s);
 284
 285     if (s->irq_reset_nonsecure) {
 286         /* If we're resetting a TZ-aware GIC as if secure firmware
 287          * had set it up ready to start a kernel in non-secure, we
 288          * need to set interrupts to group 1 so the kernel can use them.
 289          * Otherwise they reset to group 0 like the hardware.
 290          */
 291         for (i = GIC_INTERNAL; i < s->num_irq; i++) {
 292             gicv3_gicd_group_set(s, i);
 293         }
 294     }
 295 }
 296
 297 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
 298                                       bool secure_boot)
 299 {
 300     GICv3State *s = ARM_GICV3_COMMON(obj);
 301
 302     if (s->security_extn && !secure_boot) {
 303         /* We're directly booting a kernel into NonSecure. If this GIC
 304          * implements the security extensions then we must configure it
 305          * to have all the interrupts be NonSecure (this is a job that
 306          * is done by the Secure boot firmware in real hardware, and in
 307          * this mode QEMU is acting as a minimalist firmware-and-bootloader
 308          * equivalent).
 309          */
 310         s->irq_reset_nonsecure = true;
 311     }
 312 }
 313
 314 static Property arm_gicv3_common_properties[] = {
 315     DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
 316     DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
 317     DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
 318     DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
 319     DEFINE_PROP_END_OF_LIST(),
 320 };
 321
 322 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
 323 {
 324     DeviceClass *dc = DEVICE_CLASS(klass);
 325     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 326
 327     dc->reset = arm_gicv3_common_reset;
 328     dc->realize = arm_gicv3_common_realize;
 329     dc->props = arm_gicv3_common_properties;
 330     dc->vmsd = &vmstate_gicv3;
 331     albifc->arm_linux_init = arm_gic_common_linux_init;
 332 }
 333
 334 static const TypeInfo arm_gicv3_common_type = {
 335     .name = TYPE_ARM_GICV3_COMMON,
 336     .parent = TYPE_SYS_BUS_DEVICE,
 337     .instance_size = sizeof(GICv3State),
 338     .class_size = sizeof(ARMGICv3CommonClass),
 339     .class_init = arm_gicv3_common_class_init,
 340     .abstract = true,
 341     .interfaces = (InterfaceInfo []) {
 342         { TYPE_ARM_LINUX_BOOT_IF },
 343         { },
 344     },
 345 };
 346
 347 static void register_types(void)
 348 {
 349     type_register_static(&arm_gicv3_common_type);
 350 }
 351
 352 type_init(register_types)