2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "qemu/osdep.h"
32 #include "hw/boards.h"
33 #include "hw/sysbus.h"
34 #include "strongarm.h"
35 #include "qemu/error-report.h"
36 #include "hw/arm/arm.h"
37 #include "sysemu/char.h"
38 #include "sysemu/sysemu.h"
39 #include "hw/ssi/ssi.h"
40 #include "qemu/cutils.h"
47 - Implement cp15, c14 ?
48 - Implement cp15, c15 !!! (idle used in L)
49 - Implement idle mode handling/DIM
50 - Implement sleep mode/Wake sources
51 - Implement reset control
52 - Implement memory control regs
54 - Maybe support MBGNT/MBREQ
59 - Enhance UART with modem signals
63 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
65 # define DPRINTF(format, ...) do { } while (0)
72 { 0x80010000, SA_PIC_UART1
},
73 { 0x80030000, SA_PIC_UART2
},
74 { 0x80050000, SA_PIC_UART3
},
78 /* Interrupt Controller */
80 #define TYPE_STRONGARM_PIC "strongarm_pic"
81 #define STRONGARM_PIC(obj) \
82 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
84 typedef struct StrongARMPICState
{
85 SysBusDevice parent_obj
;
104 #define SA_PIC_SRCS 32
107 static void strongarm_pic_update(void *opaque
)
109 StrongARMPICState
*s
= opaque
;
111 /* FIXME: reflect DIM */
112 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
113 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
116 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
118 StrongARMPICState
*s
= opaque
;
121 s
->pending
|= 1 << irq
;
123 s
->pending
&= ~(1 << irq
);
126 strongarm_pic_update(s
);
129 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
132 StrongARMPICState
*s
= opaque
;
136 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
142 return s
->int_idle
== 0;
144 return s
->pending
& s
->is_fiq
& s
->enabled
;
148 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
154 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
155 uint64_t value
, unsigned size
)
157 StrongARMPICState
*s
= opaque
;
167 s
->int_idle
= (value
& 1) ? 0 : ~0;
170 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
174 strongarm_pic_update(s
);
177 static const MemoryRegionOps strongarm_pic_ops
= {
178 .read
= strongarm_pic_mem_read
,
179 .write
= strongarm_pic_mem_write
,
180 .endianness
= DEVICE_NATIVE_ENDIAN
,
183 static void strongarm_pic_initfn(Object
*obj
)
185 DeviceState
*dev
= DEVICE(obj
);
186 StrongARMPICState
*s
= STRONGARM_PIC(obj
);
187 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
189 qdev_init_gpio_in(dev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
190 memory_region_init_io(&s
->iomem
, obj
, &strongarm_pic_ops
, s
,
192 sysbus_init_mmio(sbd
, &s
->iomem
);
193 sysbus_init_irq(sbd
, &s
->irq
);
194 sysbus_init_irq(sbd
, &s
->fiq
);
197 static int strongarm_pic_post_load(void *opaque
, int version_id
)
199 strongarm_pic_update(opaque
);
203 static VMStateDescription vmstate_strongarm_pic_regs
= {
204 .name
= "strongarm_pic",
206 .minimum_version_id
= 0,
207 .post_load
= strongarm_pic_post_load
,
208 .fields
= (VMStateField
[]) {
209 VMSTATE_UINT32(pending
, StrongARMPICState
),
210 VMSTATE_UINT32(enabled
, StrongARMPICState
),
211 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
212 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
213 VMSTATE_END_OF_LIST(),
217 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
219 DeviceClass
*dc
= DEVICE_CLASS(klass
);
221 dc
->desc
= "StrongARM PIC";
222 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
225 static const TypeInfo strongarm_pic_info
= {
226 .name
= TYPE_STRONGARM_PIC
,
227 .parent
= TYPE_SYS_BUS_DEVICE
,
228 .instance_size
= sizeof(StrongARMPICState
),
229 .instance_init
= strongarm_pic_initfn
,
230 .class_init
= strongarm_pic_class_init
,
233 /* Real-Time Clock */
234 #define RTAR 0x00 /* RTC Alarm register */
235 #define RCNR 0x04 /* RTC Counter register */
236 #define RTTR 0x08 /* RTC Timer Trim register */
237 #define RTSR 0x10 /* RTC Status register */
239 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
240 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
241 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
242 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
244 /* 16 LSB of RTTR are clockdiv for internal trim logic,
245 * trim delete isn't emulated, so
246 * f = 32 768 / (RTTR_trim + 1) */
248 #define TYPE_STRONGARM_RTC "strongarm-rtc"
249 #define STRONGARM_RTC(obj) \
250 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
252 typedef struct StrongARMRTCState
{
253 SysBusDevice parent_obj
;
261 QEMUTimer
*rtc_alarm
;
267 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
269 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
270 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
273 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
275 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
276 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
277 (1000 * ((s
->rttr
& 0xffff) + 1));
281 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
283 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
284 timer_mod(s
->rtc_hz
, s
->last_hz
+ 1000);
286 timer_del(s
->rtc_hz
);
289 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
290 timer_mod(s
->rtc_alarm
, s
->last_hz
+
291 (((s
->rtar
- s
->last_rcnr
) * 1000 *
292 ((s
->rttr
& 0xffff) + 1)) >> 15));
294 timer_del(s
->rtc_alarm
);
298 static inline void strongarm_rtc_alarm_tick(void *opaque
)
300 StrongARMRTCState
*s
= opaque
;
302 strongarm_rtc_timer_update(s
);
303 strongarm_rtc_int_update(s
);
306 static inline void strongarm_rtc_hz_tick(void *opaque
)
308 StrongARMRTCState
*s
= opaque
;
310 strongarm_rtc_timer_update(s
);
311 strongarm_rtc_int_update(s
);
314 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
317 StrongARMRTCState
*s
= opaque
;
327 return s
->last_rcnr
+
328 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
329 (1000 * ((s
->rttr
& 0xffff) + 1));
331 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
336 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
337 uint64_t value
, unsigned size
)
339 StrongARMRTCState
*s
= opaque
;
344 strongarm_rtc_hzupdate(s
);
346 strongarm_rtc_timer_update(s
);
351 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
352 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
354 if (s
->rtsr
!= old_rtsr
) {
355 strongarm_rtc_timer_update(s
);
358 strongarm_rtc_int_update(s
);
363 strongarm_rtc_timer_update(s
);
367 strongarm_rtc_hzupdate(s
);
368 s
->last_rcnr
= value
;
369 strongarm_rtc_timer_update(s
);
373 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
377 static const MemoryRegionOps strongarm_rtc_ops
= {
378 .read
= strongarm_rtc_read
,
379 .write
= strongarm_rtc_write
,
380 .endianness
= DEVICE_NATIVE_ENDIAN
,
383 static void strongarm_rtc_init(Object
*obj
)
385 StrongARMRTCState
*s
= STRONGARM_RTC(obj
);
386 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
392 qemu_get_timedate(&tm
, 0);
394 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
395 s
->last_hz
= qemu_clock_get_ms(rtc_clock
);
397 s
->rtc_alarm
= timer_new_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
398 s
->rtc_hz
= timer_new_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
400 sysbus_init_irq(dev
, &s
->rtc_irq
);
401 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
403 memory_region_init_io(&s
->iomem
, obj
, &strongarm_rtc_ops
, s
,
405 sysbus_init_mmio(dev
, &s
->iomem
);
408 static void strongarm_rtc_pre_save(void *opaque
)
410 StrongARMRTCState
*s
= opaque
;
412 strongarm_rtc_hzupdate(s
);
415 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
417 StrongARMRTCState
*s
= opaque
;
419 strongarm_rtc_timer_update(s
);
420 strongarm_rtc_int_update(s
);
425 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
426 .name
= "strongarm-rtc",
428 .minimum_version_id
= 0,
429 .pre_save
= strongarm_rtc_pre_save
,
430 .post_load
= strongarm_rtc_post_load
,
431 .fields
= (VMStateField
[]) {
432 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
433 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
434 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
435 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
436 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
437 VMSTATE_END_OF_LIST(),
441 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
443 DeviceClass
*dc
= DEVICE_CLASS(klass
);
445 dc
->desc
= "StrongARM RTC Controller";
446 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
449 static const TypeInfo strongarm_rtc_sysbus_info
= {
450 .name
= TYPE_STRONGARM_RTC
,
451 .parent
= TYPE_SYS_BUS_DEVICE
,
452 .instance_size
= sizeof(StrongARMRTCState
),
453 .instance_init
= strongarm_rtc_init
,
454 .class_init
= strongarm_rtc_sysbus_class_init
,
467 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
468 #define STRONGARM_GPIO(obj) \
469 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
471 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
472 struct StrongARMGPIOInfo
{
475 qemu_irq handler
[28];
491 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
494 for (i
= 0; i
< 11; i
++) {
495 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
498 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
501 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
503 StrongARMGPIOInfo
*s
= opaque
;
509 s
->status
|= s
->rising
& mask
&
510 ~s
->ilevel
& ~s
->dir
;
513 s
->status
|= s
->falling
& mask
&
518 if (s
->status
& mask
) {
519 strongarm_gpio_irq_update(s
);
523 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
525 uint32_t level
, diff
;
528 level
= s
->olevel
& s
->dir
;
530 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
532 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
535 s
->prev_level
= level
;
538 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
541 StrongARMGPIOInfo
*s
= opaque
;
544 case GPDR
: /* GPIO Pin-Direction registers */
547 case GPSR
: /* GPIO Pin-Output Set registers */
548 qemu_log_mask(LOG_GUEST_ERROR
,
549 "strongarm GPIO: read from write only register GPSR\n");
552 case GPCR
: /* GPIO Pin-Output Clear registers */
553 qemu_log_mask(LOG_GUEST_ERROR
,
554 "strongarm GPIO: read from write only register GPCR\n");
557 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
560 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
563 case GAFR
: /* GPIO Alternate Function registers */
566 case GPLR
: /* GPIO Pin-Level registers */
567 return (s
->olevel
& s
->dir
) |
568 (s
->ilevel
& ~s
->dir
);
570 case GEDR
: /* GPIO Edge Detect Status registers */
574 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
580 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
581 uint64_t value
, unsigned size
)
583 StrongARMGPIOInfo
*s
= opaque
;
586 case GPDR
: /* GPIO Pin-Direction registers */
588 strongarm_gpio_handler_update(s
);
591 case GPSR
: /* GPIO Pin-Output Set registers */
593 strongarm_gpio_handler_update(s
);
596 case GPCR
: /* GPIO Pin-Output Clear registers */
598 strongarm_gpio_handler_update(s
);
601 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
605 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
609 case GAFR
: /* GPIO Alternate Function registers */
613 case GEDR
: /* GPIO Edge Detect Status registers */
615 strongarm_gpio_irq_update(s
);
619 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
623 static const MemoryRegionOps strongarm_gpio_ops
= {
624 .read
= strongarm_gpio_read
,
625 .write
= strongarm_gpio_write
,
626 .endianness
= DEVICE_NATIVE_ENDIAN
,
629 static DeviceState
*strongarm_gpio_init(hwaddr base
,
635 dev
= qdev_create(NULL
, TYPE_STRONGARM_GPIO
);
636 qdev_init_nofail(dev
);
638 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
639 for (i
= 0; i
< 12; i
++)
640 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
641 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
646 static void strongarm_gpio_initfn(Object
*obj
)
648 DeviceState
*dev
= DEVICE(obj
);
649 StrongARMGPIOInfo
*s
= STRONGARM_GPIO(obj
);
650 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
653 qdev_init_gpio_in(dev
, strongarm_gpio_set
, 28);
654 qdev_init_gpio_out(dev
, s
->handler
, 28);
656 memory_region_init_io(&s
->iomem
, obj
, &strongarm_gpio_ops
, s
,
659 sysbus_init_mmio(sbd
, &s
->iomem
);
660 for (i
= 0; i
< 11; i
++) {
661 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
663 sysbus_init_irq(sbd
, &s
->irqX
);
666 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
667 .name
= "strongarm-gpio",
669 .minimum_version_id
= 0,
670 .fields
= (VMStateField
[]) {
671 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
672 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
673 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
674 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
675 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
676 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
677 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
678 VMSTATE_UINT32(prev_level
, StrongARMGPIOInfo
),
679 VMSTATE_END_OF_LIST(),
683 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
685 DeviceClass
*dc
= DEVICE_CLASS(klass
);
687 dc
->desc
= "StrongARM GPIO controller";
688 dc
->vmsd
= &vmstate_strongarm_gpio_regs
;
691 static const TypeInfo strongarm_gpio_info
= {
692 .name
= TYPE_STRONGARM_GPIO
,
693 .parent
= TYPE_SYS_BUS_DEVICE
,
694 .instance_size
= sizeof(StrongARMGPIOInfo
),
695 .instance_init
= strongarm_gpio_initfn
,
696 .class_init
= strongarm_gpio_class_init
,
699 /* Peripheral Pin Controller */
706 #define TYPE_STRONGARM_PPC "strongarm-ppc"
707 #define STRONGARM_PPC(obj) \
708 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
710 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
711 struct StrongARMPPCInfo
{
712 SysBusDevice parent_obj
;
715 qemu_irq handler
[28];
727 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
729 StrongARMPPCInfo
*s
= opaque
;
732 s
->ilevel
|= 1 << line
;
734 s
->ilevel
&= ~(1 << line
);
738 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
740 uint32_t level
, diff
;
743 level
= s
->olevel
& s
->dir
;
745 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
747 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
750 s
->prev_level
= level
;
753 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
756 StrongARMPPCInfo
*s
= opaque
;
759 case PPDR
: /* PPC Pin Direction registers */
760 return s
->dir
| ~0x3fffff;
762 case PPSR
: /* PPC Pin State registers */
763 return (s
->olevel
& s
->dir
) |
764 (s
->ilevel
& ~s
->dir
) |
768 return s
->ppar
| ~0x41000;
774 return s
->ppfr
| ~0x7f001;
777 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
783 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
784 uint64_t value
, unsigned size
)
786 StrongARMPPCInfo
*s
= opaque
;
789 case PPDR
: /* PPC Pin Direction registers */
790 s
->dir
= value
& 0x3fffff;
791 strongarm_ppc_handler_update(s
);
794 case PPSR
: /* PPC Pin State registers */
795 s
->olevel
= value
& s
->dir
& 0x3fffff;
796 strongarm_ppc_handler_update(s
);
800 s
->ppar
= value
& 0x41000;
804 s
->psdr
= value
& 0x3fffff;
808 s
->ppfr
= value
& 0x7f001;
812 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
816 static const MemoryRegionOps strongarm_ppc_ops
= {
817 .read
= strongarm_ppc_read
,
818 .write
= strongarm_ppc_write
,
819 .endianness
= DEVICE_NATIVE_ENDIAN
,
822 static void strongarm_ppc_init(Object
*obj
)
824 DeviceState
*dev
= DEVICE(obj
);
825 StrongARMPPCInfo
*s
= STRONGARM_PPC(obj
);
826 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
828 qdev_init_gpio_in(dev
, strongarm_ppc_set
, 22);
829 qdev_init_gpio_out(dev
, s
->handler
, 22);
831 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ppc_ops
, s
,
834 sysbus_init_mmio(sbd
, &s
->iomem
);
837 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
838 .name
= "strongarm-ppc",
840 .minimum_version_id
= 0,
841 .fields
= (VMStateField
[]) {
842 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
843 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
844 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
845 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
846 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
847 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
848 VMSTATE_UINT32(prev_level
, StrongARMPPCInfo
),
849 VMSTATE_END_OF_LIST(),
853 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
855 DeviceClass
*dc
= DEVICE_CLASS(klass
);
857 dc
->desc
= "StrongARM PPC controller";
858 dc
->vmsd
= &vmstate_strongarm_ppc_regs
;
861 static const TypeInfo strongarm_ppc_info
= {
862 .name
= TYPE_STRONGARM_PPC
,
863 .parent
= TYPE_SYS_BUS_DEVICE
,
864 .instance_size
= sizeof(StrongARMPPCInfo
),
865 .instance_init
= strongarm_ppc_init
,
866 .class_init
= strongarm_ppc_class_init
,
878 #define UTCR0_PE (1 << 0) /* Parity enable */
879 #define UTCR0_OES (1 << 1) /* Even parity */
880 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
881 #define UTCR0_DSS (1 << 3) /* 8-bit data */
883 #define UTCR3_RXE (1 << 0) /* Rx enable */
884 #define UTCR3_TXE (1 << 1) /* Tx enable */
885 #define UTCR3_BRK (1 << 2) /* Force Break */
886 #define UTCR3_RIE (1 << 3) /* Rx int enable */
887 #define UTCR3_TIE (1 << 4) /* Tx int enable */
888 #define UTCR3_LBM (1 << 5) /* Loopback */
890 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
891 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
892 #define UTSR0_RID (1 << 2) /* Receiver Idle */
893 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
894 #define UTSR0_REB (1 << 4) /* Receiver end break */
895 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
897 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
898 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
899 #define UTSR1_PRE (1 << 3) /* Parity error */
900 #define UTSR1_FRE (1 << 4) /* Frame error */
901 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
903 #define RX_FIFO_PRE (1 << 8)
904 #define RX_FIFO_FRE (1 << 9)
905 #define RX_FIFO_ROR (1 << 10)
907 #define TYPE_STRONGARM_UART "strongarm-uart"
908 #define STRONGARM_UART(obj) \
909 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
911 typedef struct StrongARMUARTState
{
912 SysBusDevice parent_obj
;
927 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
931 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
933 QEMUTimer
*rx_timeout_timer
;
935 } StrongARMUARTState
;
937 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
941 if (s
->tx_len
!= 8) {
945 if (s
->rx_len
!= 0) {
946 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
949 if (ent
& RX_FIFO_PRE
) {
950 s
->utsr1
|= UTSR1_PRE
;
952 if (ent
& RX_FIFO_FRE
) {
953 s
->utsr1
|= UTSR1_FRE
;
955 if (ent
& RX_FIFO_ROR
) {
956 s
->utsr1
|= UTSR1_ROR
;
963 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
965 uint16_t utsr0
= s
->utsr0
&
966 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
969 if ((s
->utcr3
& UTCR3_TXE
) &&
970 (s
->utcr3
& UTCR3_TIE
) &&
975 if ((s
->utcr3
& UTCR3_RXE
) &&
976 (s
->utcr3
& UTCR3_RIE
) &&
981 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
982 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
988 qemu_set_irq(s
->irq
, utsr0
);
991 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
993 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
994 QEMUSerialSetParams ssp
;
998 if (s
->utcr0
& UTCR0_PE
) {
1001 if (s
->utcr0
& UTCR0_OES
) {
1009 if (s
->utcr0
& UTCR0_SBS
) {
1015 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
1016 frame_size
+= data_bits
+ stop_bits
;
1017 speed
= 3686400 / 16 / (s
->brd
+ 1);
1019 ssp
.parity
= parity
;
1020 ssp
.data_bits
= data_bits
;
1021 ssp
.stop_bits
= stop_bits
;
1022 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
1023 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1025 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1026 speed
, parity
, data_bits
, stop_bits
);
1029 static void strongarm_uart_rx_to(void *opaque
)
1031 StrongARMUARTState
*s
= opaque
;
1034 s
->utsr0
|= UTSR0_RID
;
1035 strongarm_uart_update_int_status(s
);
1039 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1041 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1046 if (s
->wait_break_end
) {
1047 s
->utsr0
|= UTSR0_REB
;
1048 s
->wait_break_end
= false;
1051 if (s
->rx_len
< 12) {
1052 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1055 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1058 static int strongarm_uart_can_receive(void *opaque
)
1060 StrongARMUARTState
*s
= opaque
;
1062 if (s
->rx_len
== 12) {
1065 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1066 if (s
->rx_len
< 8) {
1067 return 8 - s
->rx_len
;
1072 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1074 StrongARMUARTState
*s
= opaque
;
1077 for (i
= 0; i
< size
; i
++) {
1078 strongarm_uart_rx_push(s
, buf
[i
]);
1081 /* call the timeout receive callback in 3 char transmit time */
1082 timer_mod(s
->rx_timeout_timer
,
1083 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1085 strongarm_uart_update_status(s
);
1086 strongarm_uart_update_int_status(s
);
1089 static void strongarm_uart_event(void *opaque
, int event
)
1091 StrongARMUARTState
*s
= opaque
;
1092 if (event
== CHR_EVENT_BREAK
) {
1093 s
->utsr0
|= UTSR0_RBB
;
1094 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1095 s
->wait_break_end
= true;
1096 strongarm_uart_update_status(s
);
1097 strongarm_uart_update_int_status(s
);
1101 static void strongarm_uart_tx(void *opaque
)
1103 StrongARMUARTState
*s
= opaque
;
1104 uint64_t new_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1106 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1107 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1108 } else if (qemu_chr_fe_get_driver(&s
->chr
)) {
1109 /* XXX this blocks entire thread. Rewrite to use
1110 * qemu_chr_fe_write and background I/O callbacks */
1111 qemu_chr_fe_write_all(&s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1114 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1117 timer_mod(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1119 strongarm_uart_update_status(s
);
1120 strongarm_uart_update_int_status(s
);
1123 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1126 StrongARMUARTState
*s
= opaque
;
1137 return s
->brd
& 0xff;
1143 if (s
->rx_len
!= 0) {
1144 ret
= s
->rx_fifo
[s
->rx_start
];
1145 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1147 strongarm_uart_update_status(s
);
1148 strongarm_uart_update_int_status(s
);
1160 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1165 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1166 uint64_t value
, unsigned size
)
1168 StrongARMUARTState
*s
= opaque
;
1172 s
->utcr0
= value
& 0x7f;
1173 strongarm_uart_update_parameters(s
);
1177 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1178 strongarm_uart_update_parameters(s
);
1182 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1183 strongarm_uart_update_parameters(s
);
1187 s
->utcr3
= value
& 0x3f;
1188 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1191 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1194 strongarm_uart_update_status(s
);
1195 strongarm_uart_update_int_status(s
);
1199 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1200 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1202 strongarm_uart_update_status(s
);
1203 strongarm_uart_update_int_status(s
);
1204 if (s
->tx_len
== 1) {
1205 strongarm_uart_tx(s
);
1211 s
->utsr0
= s
->utsr0
& ~(value
&
1212 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1213 strongarm_uart_update_int_status(s
);
1217 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1221 static const MemoryRegionOps strongarm_uart_ops
= {
1222 .read
= strongarm_uart_read
,
1223 .write
= strongarm_uart_write
,
1224 .endianness
= DEVICE_NATIVE_ENDIAN
,
1227 static void strongarm_uart_init(Object
*obj
)
1229 StrongARMUARTState
*s
= STRONGARM_UART(obj
);
1230 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1232 memory_region_init_io(&s
->iomem
, obj
, &strongarm_uart_ops
, s
,
1234 sysbus_init_mmio(dev
, &s
->iomem
);
1235 sysbus_init_irq(dev
, &s
->irq
);
1237 s
->rx_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_rx_to
, s
);
1238 s
->tx_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_tx
, s
);
1241 static void strongarm_uart_realize(DeviceState
*dev
, Error
**errp
)
1243 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1245 qemu_chr_fe_set_handlers(&s
->chr
,
1246 strongarm_uart_can_receive
,
1247 strongarm_uart_receive
,
1248 strongarm_uart_event
,
1252 static void strongarm_uart_reset(DeviceState
*dev
)
1254 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1256 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1257 s
->brd
= 23; /* 9600 */
1258 /* enable send & recv - this actually violates spec */
1259 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1261 s
->rx_len
= s
->tx_len
= 0;
1263 strongarm_uart_update_parameters(s
);
1264 strongarm_uart_update_status(s
);
1265 strongarm_uart_update_int_status(s
);
1268 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1270 StrongARMUARTState
*s
= opaque
;
1272 strongarm_uart_update_parameters(s
);
1273 strongarm_uart_update_status(s
);
1274 strongarm_uart_update_int_status(s
);
1276 /* tx and restart timer */
1278 strongarm_uart_tx(s
);
1281 /* restart rx timeout timer */
1283 timer_mod(s
->rx_timeout_timer
,
1284 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1290 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1291 .name
= "strongarm-uart",
1293 .minimum_version_id
= 0,
1294 .post_load
= strongarm_uart_post_load
,
1295 .fields
= (VMStateField
[]) {
1296 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1297 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1298 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1299 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1300 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1301 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1302 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1303 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1304 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1305 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1306 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1307 VMSTATE_END_OF_LIST(),
1311 static Property strongarm_uart_properties
[] = {
1312 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1313 DEFINE_PROP_END_OF_LIST(),
1316 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1318 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1320 dc
->desc
= "StrongARM UART controller";
1321 dc
->reset
= strongarm_uart_reset
;
1322 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1323 dc
->props
= strongarm_uart_properties
;
1324 dc
->realize
= strongarm_uart_realize
;
1327 static const TypeInfo strongarm_uart_info
= {
1328 .name
= TYPE_STRONGARM_UART
,
1329 .parent
= TYPE_SYS_BUS_DEVICE
,
1330 .instance_size
= sizeof(StrongARMUARTState
),
1331 .instance_init
= strongarm_uart_init
,
1332 .class_init
= strongarm_uart_class_init
,
1335 /* Synchronous Serial Ports */
1337 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1338 #define STRONGARM_SSP(obj) \
1339 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1341 typedef struct StrongARMSSPState
{
1342 SysBusDevice parent_obj
;
1351 uint16_t rx_fifo
[8];
1354 } StrongARMSSPState
;
1356 #define SSCR0 0x60 /* SSP Control register 0 */
1357 #define SSCR1 0x64 /* SSP Control register 1 */
1358 #define SSDR 0x6c /* SSP Data register */
1359 #define SSSR 0x74 /* SSP Status register */
1361 /* Bitfields for above registers */
1362 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1363 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1364 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1365 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1366 #define SSCR0_SSE (1 << 7)
1367 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1368 #define SSCR1_RIE (1 << 0)
1369 #define SSCR1_TIE (1 << 1)
1370 #define SSCR1_LBM (1 << 2)
1371 #define SSSR_TNF (1 << 2)
1372 #define SSSR_RNE (1 << 3)
1373 #define SSSR_TFS (1 << 5)
1374 #define SSSR_RFS (1 << 6)
1375 #define SSSR_ROR (1 << 7)
1376 #define SSSR_RW 0x0080
1378 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1382 level
|= (s
->sssr
& SSSR_ROR
);
1383 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1384 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1385 qemu_set_irq(s
->irq
, level
);
1388 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1390 s
->sssr
&= ~SSSR_TFS
;
1391 s
->sssr
&= ~SSSR_TNF
;
1392 if (s
->sscr
[0] & SSCR0_SSE
) {
1393 if (s
->rx_level
>= 4) {
1394 s
->sssr
|= SSSR_RFS
;
1396 s
->sssr
&= ~SSSR_RFS
;
1399 s
->sssr
|= SSSR_RNE
;
1401 s
->sssr
&= ~SSSR_RNE
;
1403 /* TX FIFO is never filled, so it is always in underrun
1404 condition if SSP is enabled */
1405 s
->sssr
|= SSSR_TFS
;
1406 s
->sssr
|= SSSR_TNF
;
1409 strongarm_ssp_int_update(s
);
1412 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1415 StrongARMSSPState
*s
= opaque
;
1426 if (~s
->sscr
[0] & SSCR0_SSE
) {
1429 if (s
->rx_level
< 1) {
1430 printf("%s: SSP Rx Underrun\n", __func__
);
1434 retval
= s
->rx_fifo
[s
->rx_start
++];
1436 strongarm_ssp_fifo_update(s
);
1439 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1445 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1446 uint64_t value
, unsigned size
)
1448 StrongARMSSPState
*s
= opaque
;
1452 s
->sscr
[0] = value
& 0xffbf;
1453 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1454 printf("%s: Wrong data size: %i bits\n", __func__
,
1455 (int)SSCR0_DSS(value
));
1457 if (!(value
& SSCR0_SSE
)) {
1461 strongarm_ssp_fifo_update(s
);
1465 s
->sscr
[1] = value
& 0x2f;
1466 if (value
& SSCR1_LBM
) {
1467 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1469 strongarm_ssp_fifo_update(s
);
1473 s
->sssr
&= ~(value
& SSSR_RW
);
1474 strongarm_ssp_int_update(s
);
1478 if (SSCR0_UWIRE(s
->sscr
[0])) {
1481 /* Note how 32bits overflow does no harm here */
1482 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1484 /* Data goes from here to the Tx FIFO and is shifted out from
1485 * there directly to the slave, no need to buffer it.
1487 if (s
->sscr
[0] & SSCR0_SSE
) {
1489 if (s
->sscr
[1] & SSCR1_LBM
) {
1492 readval
= ssi_transfer(s
->bus
, value
);
1495 if (s
->rx_level
< 0x08) {
1496 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1498 s
->sssr
|= SSSR_ROR
;
1501 strongarm_ssp_fifo_update(s
);
1505 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1510 static const MemoryRegionOps strongarm_ssp_ops
= {
1511 .read
= strongarm_ssp_read
,
1512 .write
= strongarm_ssp_write
,
1513 .endianness
= DEVICE_NATIVE_ENDIAN
,
1516 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1518 StrongARMSSPState
*s
= opaque
;
1520 strongarm_ssp_fifo_update(s
);
1525 static void strongarm_ssp_init(Object
*obj
)
1527 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1528 DeviceState
*dev
= DEVICE(sbd
);
1529 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1531 sysbus_init_irq(sbd
, &s
->irq
);
1533 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ssp_ops
, s
,
1535 sysbus_init_mmio(sbd
, &s
->iomem
);
1537 s
->bus
= ssi_create_bus(dev
, "ssi");
1540 static void strongarm_ssp_reset(DeviceState
*dev
)
1542 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1544 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1549 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1550 .name
= "strongarm-ssp",
1552 .minimum_version_id
= 0,
1553 .post_load
= strongarm_ssp_post_load
,
1554 .fields
= (VMStateField
[]) {
1555 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1556 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1557 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1558 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1559 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1560 VMSTATE_END_OF_LIST(),
1564 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1566 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1568 dc
->desc
= "StrongARM SSP controller";
1569 dc
->reset
= strongarm_ssp_reset
;
1570 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1573 static const TypeInfo strongarm_ssp_info
= {
1574 .name
= TYPE_STRONGARM_SSP
,
1575 .parent
= TYPE_SYS_BUS_DEVICE
,
1576 .instance_size
= sizeof(StrongARMSSPState
),
1577 .instance_init
= strongarm_ssp_init
,
1578 .class_init
= strongarm_ssp_class_init
,
1581 /* Main CPU functions */
1582 StrongARMState
*sa1110_init(MemoryRegion
*sysmem
,
1583 unsigned int sdram_size
, const char *rev
)
1588 s
= g_new0(StrongARMState
, 1);
1594 if (strncmp(rev
, "sa1110", 6)) {
1595 error_report("Machine requires a SA1110 processor.");
1599 s
->cpu
= cpu_arm_init(rev
);
1602 error_report("Unable to find CPU definition");
1606 memory_region_allocate_system_memory(&s
->sdram
, NULL
, "strongarm.sdram",
1608 memory_region_add_subregion(sysmem
, SA_SDCS0
, &s
->sdram
);
1610 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1611 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
),
1612 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
),
1615 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1616 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1617 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1618 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1619 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1622 sysbus_create_simple(TYPE_STRONGARM_RTC
, 0x90010000,
1623 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1625 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1627 s
->ppc
= sysbus_create_varargs(TYPE_STRONGARM_PPC
, 0x90060000, NULL
);
1629 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1630 DeviceState
*dev
= qdev_create(NULL
, TYPE_STRONGARM_UART
);
1631 qdev_prop_set_chr(dev
, "chardev", serial_hds
[i
]);
1632 qdev_init_nofail(dev
);
1633 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1634 sa_serial
[i
].io_base
);
1635 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1636 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1639 s
->ssp
= sysbus_create_varargs(TYPE_STRONGARM_SSP
, 0x80070000,
1640 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1641 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1646 static void strongarm_register_types(void)
1648 type_register_static(&strongarm_pic_info
);
1649 type_register_static(&strongarm_rtc_sysbus_info
);
1650 type_register_static(&strongarm_gpio_info
);
1651 type_register_static(&strongarm_ppc_info
);
1652 type_register_static(&strongarm_uart_info
);
1653 type_register_static(&strongarm_ssp_info
);
1656 type_init(strongarm_register_types
)