hw/ppc/ppc440_bamboo.c

   1 /*
   2  * QEMU PowerPC 440 Bamboo board emulation
   3  *
   4  * Copyright 2007 IBM Corporation.
   5  * Authors:
   6  *      Jerone Young <jyoung5@us.ibm.com>
   7  *      Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
   8  *      Hollis Blanchard <hollisb@us.ibm.com>
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/error-report.h"
  17 #include "qemu-common.h"
  18 #include "qemu/error-report.h"
  19 #include "net/net.h"
  20 #include "hw/hw.h"
  21 #include "hw/pci/pci.h"
  22 #include "hw/boards.h"
  23 #include "sysemu/kvm.h"
  24 #include "kvm_ppc.h"
  25 #include "sysemu/device_tree.h"
  26 #include "hw/loader.h"
  27 #include "elf.h"
  28 #include "exec/address-spaces.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/ppc/ppc.h"
  31 #include "ppc405.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/qtest.h"
  34 #include "hw/sysbus.h"
  35
  36 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
  37
  38 /* from u-boot */
  39 #define KERNEL_ADDR  0x1000000
  40 #define FDT_ADDR     0x1800000
  41 #define RAMDISK_ADDR 0x1900000
  42
  43 #define PPC440EP_PCI_CONFIG     0xeec00000
  44 #define PPC440EP_PCI_INTACK     0xeed00000
  45 #define PPC440EP_PCI_SPECIAL    0xeed00000
  46 #define PPC440EP_PCI_REGS       0xef400000
  47 #define PPC440EP_PCI_IO         0xe8000000
  48 #define PPC440EP_PCI_IOLEN      0x00010000
  49
  50 #define PPC440EP_SDRAM_NR_BANKS 4
  51
  52 static const unsigned int ppc440ep_sdram_bank_sizes[] = {
  53     256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
  54 };
  55
  56 static hwaddr entry;
  57
  58 static int bamboo_load_device_tree(hwaddr addr,
  59                                      uint32_t ramsize,
  60                                      hwaddr initrd_base,
  61                                      hwaddr initrd_size,
  62                                      const char *kernel_cmdline)
  63 {
  64     int ret = -1;
  65     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
  66     char *filename;
  67     int fdt_size;
  68     void *fdt;
  69     uint32_t tb_freq = 400000000;
  70     uint32_t clock_freq = 400000000;
  71
  72     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
  73     if (!filename) {
  74         goto out;
  75     }
  76     fdt = load_device_tree(filename, &fdt_size);
  77     g_free(filename);
  78     if (fdt == NULL) {
  79         goto out;
  80     }
  81
  82     /* Manipulate device tree in memory. */
  83
  84     ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
  85                            sizeof(mem_reg_property));
  86     if (ret < 0)
  87         fprintf(stderr, "couldn't set /memory/reg\n");
  88
  89     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
  90                                 initrd_base);
  91     if (ret < 0)
  92         fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
  93
  94     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
  95                                 (initrd_base + initrd_size));
  96     if (ret < 0)
  97         fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
  98
  99     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 100                                   kernel_cmdline);
 101     if (ret < 0)
 102         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 103
 104     /* Copy data from the host device tree into the guest. Since the guest can
 105      * directly access the timebase without host involvement, we must expose
 106      * the correct frequencies. */
 107     if (kvm_enabled()) {
 108         tb_freq = kvmppc_get_tbfreq();
 109         clock_freq = kvmppc_get_clockfreq();
 110     }
 111
 112     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 113                           clock_freq);
 114     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 115                           tb_freq);
 116
 117     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 118     g_free(fdt);
 119     return 0;
 120
 121 out:
 122
 123     return ret;
 124 }
 125
 126 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 127 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 128                                      target_ulong va,
 129                                      hwaddr pa)
 130 {
 131     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 132
 133     tlb->attr = 0;
 134     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 135     tlb->size = 1U << 31; /* up to 0x80000000  */
 136     tlb->EPN = va & TARGET_PAGE_MASK;
 137     tlb->RPN = pa & TARGET_PAGE_MASK;
 138     tlb->PID = 0;
 139
 140     tlb = &env->tlb.tlbe[1];
 141     tlb->attr = 0;
 142     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 143     tlb->size = 1U << 31; /* up to 0xffffffff  */
 144     tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
 145     tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
 146     tlb->PID = 0;
 147 }
 148
 149 static void main_cpu_reset(void *opaque)
 150 {
 151     PowerPCCPU *cpu = opaque;
 152     CPUPPCState *env = &cpu->env;
 153
 154     cpu_reset(CPU(cpu));
 155     env->gpr[1] = (16 * MiB) - 8;
 156     env->gpr[3] = FDT_ADDR;
 157     env->nip = entry;
 158
 159     /* Create a mapping for the kernel.  */
 160     mmubooke_create_initial_mapping(env, 0, 0);
 161 }
 162
 163 static void bamboo_init(MachineState *machine)
 164 {
 165     ram_addr_t ram_size = machine->ram_size;
 166     const char *kernel_filename = machine->kernel_filename;
 167     const char *kernel_cmdline = machine->kernel_cmdline;
 168     const char *initrd_filename = machine->initrd_filename;
 169     unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
 170     MemoryRegion *address_space_mem = get_system_memory();
 171     MemoryRegion *isa = g_new(MemoryRegion, 1);
 172     MemoryRegion *ram_memories
 173         = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
 174     hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
 175     hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
 176     qemu_irq *pic;
 177     qemu_irq *irqs;
 178     PCIBus *pcibus;
 179     PowerPCCPU *cpu;
 180     CPUPPCState *env;
 181     uint64_t elf_entry;
 182     uint64_t elf_lowaddr;
 183     hwaddr loadaddr = 0;
 184     target_long initrd_size = 0;
 185     DeviceState *dev;
 186     int success;
 187     int i;
 188
 189     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 190     env = &cpu->env;
 191
 192     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 193         error_report("MMU model %i not supported by this machine",
 194                      env->mmu_model);
 195         exit(1);
 196     }
 197
 198     qemu_register_reset(main_cpu_reset, cpu);
 199     ppc_booke_timers_init(cpu, 400000000, 0);
 200     ppc_dcr_init(env, NULL, NULL);
 201
 202     /* interrupt controller */
 203     irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
 204     irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
 205     irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
 206     pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
 207
 208     /* SDRAM controller */
 209     memset(ram_bases, 0, sizeof(ram_bases));
 210     memset(ram_sizes, 0, sizeof(ram_sizes));
 211     ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS,
 212                                    ram_memories,
 213                                    ram_bases, ram_sizes,
 214                                    ppc440ep_sdram_bank_sizes);
 215     /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
 216     ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
 217                       ram_bases, ram_sizes, 1);
 218
 219     /* PCI */
 220     dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
 221                                 PPC440EP_PCI_CONFIG,
 222                                 pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
 223                                 pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
 224                                 NULL);
 225     pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 226     if (!pcibus) {
 227         error_report("couldn't create PCI controller");
 228         exit(1);
 229     }
 230
 231     memory_region_init_alias(isa, NULL, "isa_mmio",
 232                              get_system_io(), 0, PPC440EP_PCI_IOLEN);
 233     memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
 234
 235     if (serial_hd(0) != NULL) {
 236         serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
 237                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
 238                        DEVICE_BIG_ENDIAN);
 239     }
 240     if (serial_hd(1) != NULL) {
 241         serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
 242                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
 243                        DEVICE_BIG_ENDIAN);
 244     }
 245
 246     if (pcibus) {
 247         /* Register network interfaces. */
 248         for (i = 0; i < nb_nics; i++) {
 249             /* There are no PCI NICs on the Bamboo board, but there are
 250              * PCI slots, so we can pick whatever default model we want. */
 251             pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
 252         }
 253     }
 254
 255     /* Load kernel. */
 256     if (kernel_filename) {
 257         success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
 258                               NULL, NULL);
 259         if (success < 0) {
 260             success = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 261                                &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE,
 262                                0, 0);
 263             entry = elf_entry;
 264             loadaddr = elf_lowaddr;
 265         }
 266         /* XXX try again as binary */
 267         if (success < 0) {
 268             error_report("could not load kernel '%s'", kernel_filename);
 269             exit(1);
 270         }
 271     }
 272
 273     /* Load initrd. */
 274     if (initrd_filename) {
 275         initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
 276                                           ram_size - RAMDISK_ADDR);
 277
 278         if (initrd_size < 0) {
 279             error_report("could not load ram disk '%s' at %x",
 280                          initrd_filename, RAMDISK_ADDR);
 281             exit(1);
 282         }
 283     }
 284
 285     /* If we're loading a kernel directly, we must load the device tree too. */
 286     if (kernel_filename) {
 287         if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR,
 288                                     initrd_size, kernel_cmdline) < 0) {
 289             error_report("couldn't load device tree");
 290             exit(1);
 291         }
 292     }
 293 }
 294
 295 static void bamboo_machine_init(MachineClass *mc)
 296 {
 297     mc->desc = "bamboo";
 298     mc->init = bamboo_init;
 299     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
 300 }
 301
 302 DEFINE_MACHINE("bamboo", bamboo_machine_init)