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target/mips: Refactor and fix COPY_U.<B|H|W> instructions
[qemu/ar7.git] / target / mips / msa_helper.c
blob52680fe5dde3426f913a5ca14528e9caeaaef21e
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
28
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
31
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
34
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
37
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
41
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
44
45 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
46 {
47 uint32_t i;
48
49 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
50 pwd->d[i] = pws->d[i];
51 }
52 }
53
54 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
55 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
56 uint32_t i8) \
57 { \
58 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
59 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
60 uint32_t i; \
61 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
62 DEST = OPERATION; \
63 } \
64 }
65
66 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
67 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
68 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
69 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
70
71 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
72 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
73 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
74 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
75
76 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
77 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
78 MSA_FN_IMM8(bmzi_b, pwd->b[i],
79 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
80
81 #define BIT_SELECT(dest, arg1, arg2, df) \
82 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
83 MSA_FN_IMM8(bseli_b, pwd->b[i],
84 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
85
86 #undef MSA_FN_IMM8
87
88 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
89
90 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
91 uint32_t ws, uint32_t imm)
92 {
93 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
94 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
95 wr_t wx, *pwx = &wx;
96 uint32_t i;
97
98 switch (df) {
99 case DF_BYTE:
100 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
101 pwx->b[i] = pws->b[SHF_POS(i, imm)];
102 }
103 break;
104 case DF_HALF:
105 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
106 pwx->h[i] = pws->h[SHF_POS(i, imm)];
107 }
108 break;
109 case DF_WORD:
110 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
111 pwx->w[i] = pws->w[SHF_POS(i, imm)];
112 }
113 break;
114 default:
115 assert(0);
116 }
117 msa_move_v(pwd, pwx);
118 }
119
120 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
121 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
122 uint32_t wt) \
123 { \
124 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
125 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
126 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
127 uint32_t i; \
128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
129 DEST = OPERATION; \
130 } \
131 }
132
133 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
134 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
135 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
136 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
137 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
138 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
139 MSA_FN_VECTOR(bmz_v, pwd->d[i],
140 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
141 MSA_FN_VECTOR(bsel_v, pwd->d[i],
142 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
143 #undef BIT_MOVE_IF_NOT_ZERO
144 #undef BIT_MOVE_IF_ZERO
145 #undef BIT_SELECT
146 #undef MSA_FN_VECTOR
147
148 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
149 {
150 return arg1 + arg2;
151 }
152
153 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
154 {
155 return arg1 - arg2;
156 }
157
158 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
159 {
160 return arg1 == arg2 ? -1 : 0;
161 }
162
163 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
164 {
165 return arg1 <= arg2 ? -1 : 0;
166 }
167
168 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
169 {
170 uint64_t u_arg1 = UNSIGNED(arg1, df);
171 uint64_t u_arg2 = UNSIGNED(arg2, df);
172 return u_arg1 <= u_arg2 ? -1 : 0;
173 }
174
175 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
176 {
177 return arg1 < arg2 ? -1 : 0;
178 }
179
180 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
181 {
182 uint64_t u_arg1 = UNSIGNED(arg1, df);
183 uint64_t u_arg2 = UNSIGNED(arg2, df);
184 return u_arg1 < u_arg2 ? -1 : 0;
185 }
186
187 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
188 {
189 return arg1 > arg2 ? arg1 : arg2;
190 }
191
192 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
193 {
194 uint64_t u_arg1 = UNSIGNED(arg1, df);
195 uint64_t u_arg2 = UNSIGNED(arg2, df);
196 return u_arg1 > u_arg2 ? arg1 : arg2;
197 }
198
199 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
200 {
201 return arg1 < arg2 ? arg1 : arg2;
202 }
203
204 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
205 {
206 uint64_t u_arg1 = UNSIGNED(arg1, df);
207 uint64_t u_arg2 = UNSIGNED(arg2, df);
208 return u_arg1 < u_arg2 ? arg1 : arg2;
209 }
210
211 #define MSA_BINOP_IMM_DF(helper, func) \
212 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
213 uint32_t wd, uint32_t ws, int32_t u5) \
214 { \
215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
216 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
217 uint32_t i; \
218 \
219 switch (df) { \
220 case DF_BYTE: \
221 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
222 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
223 } \
224 break; \
225 case DF_HALF: \
226 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
227 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
228 } \
229 break; \
230 case DF_WORD: \
231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
232 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
233 } \
234 break; \
235 case DF_DOUBLE: \
236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
237 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
238 } \
239 break; \
240 default: \
241 assert(0); \
242 } \
243 }
244
245 MSA_BINOP_IMM_DF(addvi, addv)
246 MSA_BINOP_IMM_DF(subvi, subv)
247 MSA_BINOP_IMM_DF(ceqi, ceq)
248 MSA_BINOP_IMM_DF(clei_s, cle_s)
249 MSA_BINOP_IMM_DF(clei_u, cle_u)
250 MSA_BINOP_IMM_DF(clti_s, clt_s)
251 MSA_BINOP_IMM_DF(clti_u, clt_u)
252 MSA_BINOP_IMM_DF(maxi_s, max_s)
253 MSA_BINOP_IMM_DF(maxi_u, max_u)
254 MSA_BINOP_IMM_DF(mini_s, min_s)
255 MSA_BINOP_IMM_DF(mini_u, min_u)
256 #undef MSA_BINOP_IMM_DF
257
258 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
259 int32_t s10)
260 {
261 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
262 uint32_t i;
263
264 switch (df) {
265 case DF_BYTE:
266 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
267 pwd->b[i] = (int8_t)s10;
268 }
269 break;
270 case DF_HALF:
271 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
272 pwd->h[i] = (int16_t)s10;
273 }
274 break;
275 case DF_WORD:
276 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
277 pwd->w[i] = (int32_t)s10;
278 }
279 break;
280 case DF_DOUBLE:
281 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
282 pwd->d[i] = (int64_t)s10;
283 }
284 break;
285 default:
286 assert(0);
287 }
288 }
289
290 /* Data format bit position and unsigned values */
291 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
292
293 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
294 {
295 int32_t b_arg2 = BIT_POSITION(arg2, df);
296 return arg1 << b_arg2;
297 }
298
299 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
300 {
301 int32_t b_arg2 = BIT_POSITION(arg2, df);
302 return arg1 >> b_arg2;
303 }
304
305 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
306 {
307 uint64_t u_arg1 = UNSIGNED(arg1, df);
308 int32_t b_arg2 = BIT_POSITION(arg2, df);
309 return u_arg1 >> b_arg2;
310 }
311
312 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
313 {
314 int32_t b_arg2 = BIT_POSITION(arg2, df);
315 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
316 }
317
318 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
319 int64_t arg2)
320 {
321 int32_t b_arg2 = BIT_POSITION(arg2, df);
322 return UNSIGNED(arg1 | (1LL << b_arg2), df);
323 }
324
325 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
326 {
327 int32_t b_arg2 = BIT_POSITION(arg2, df);
328 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
329 }
330
331 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
332 int64_t arg2)
333 {
334 uint64_t u_arg1 = UNSIGNED(arg1, df);
335 uint64_t u_dest = UNSIGNED(dest, df);
336 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
337 int32_t sh_a = DF_BITS(df) - sh_d;
338 if (sh_d == DF_BITS(df)) {
339 return u_arg1;
340 } else {
341 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
342 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
343 }
344 }
345
346 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
347 int64_t arg2)
348 {
349 uint64_t u_arg1 = UNSIGNED(arg1, df);
350 uint64_t u_dest = UNSIGNED(dest, df);
351 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
352 int32_t sh_a = DF_BITS(df) - sh_d;
353 if (sh_d == DF_BITS(df)) {
354 return u_arg1;
355 } else {
356 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
357 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
358 }
359 }
360
361 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
362 {
363 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
364 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
365 arg;
366 }
367
368 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
369 {
370 uint64_t u_arg = UNSIGNED(arg, df);
371 return u_arg < M_MAX_UINT(m+1) ? u_arg :
372 M_MAX_UINT(m+1);
373 }
374
375 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
376 {
377 int32_t b_arg2 = BIT_POSITION(arg2, df);
378 if (b_arg2 == 0) {
379 return arg1;
380 } else {
381 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
382 return (arg1 >> b_arg2) + r_bit;
383 }
384 }
385
386 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
387 {
388 uint64_t u_arg1 = UNSIGNED(arg1, df);
389 int32_t b_arg2 = BIT_POSITION(arg2, df);
390 if (b_arg2 == 0) {
391 return u_arg1;
392 } else {
393 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
394 return (u_arg1 >> b_arg2) + r_bit;
395 }
396 }
397
398 #define MSA_BINOP_IMMU_DF(helper, func) \
399 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
400 uint32_t ws, uint32_t u5) \
401 { \
402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
403 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
404 uint32_t i; \
405 \
406 switch (df) { \
407 case DF_BYTE: \
408 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
409 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
410 } \
411 break; \
412 case DF_HALF: \
413 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
414 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
415 } \
416 break; \
417 case DF_WORD: \
418 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
419 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
420 } \
421 break; \
422 case DF_DOUBLE: \
423 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
424 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
425 } \
426 break; \
427 default: \
428 assert(0); \
429 } \
430 }
431
432 MSA_BINOP_IMMU_DF(slli, sll)
433 MSA_BINOP_IMMU_DF(srai, sra)
434 MSA_BINOP_IMMU_DF(srli, srl)
435 MSA_BINOP_IMMU_DF(bclri, bclr)
436 MSA_BINOP_IMMU_DF(bseti, bset)
437 MSA_BINOP_IMMU_DF(bnegi, bneg)
438 MSA_BINOP_IMMU_DF(sat_s, sat_s)
439 MSA_BINOP_IMMU_DF(sat_u, sat_u)
440 MSA_BINOP_IMMU_DF(srari, srar)
441 MSA_BINOP_IMMU_DF(srlri, srlr)
442 #undef MSA_BINOP_IMMU_DF
443
444 #define MSA_TEROP_IMMU_DF(helper, func) \
445 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
446 uint32_t wd, uint32_t ws, uint32_t u5) \
447 { \
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
450 uint32_t i; \
451 \
452 switch (df) { \
453 case DF_BYTE: \
454 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
455 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
456 u5); \
457 } \
458 break; \
459 case DF_HALF: \
460 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
461 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
462 u5); \
463 } \
464 break; \
465 case DF_WORD: \
466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
467 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
468 u5); \
469 } \
470 break; \
471 case DF_DOUBLE: \
472 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
473 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
474 u5); \
475 } \
476 break; \
477 default: \
478 assert(0); \
479 } \
480 }
481
482 MSA_TEROP_IMMU_DF(binsli, binsl)
483 MSA_TEROP_IMMU_DF(binsri, binsr)
484 #undef MSA_TEROP_IMMU_DF
485
486 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
487 {
488 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
489 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
490 return abs_arg1 > abs_arg2 ? arg1 : arg2;
491 }
492
493 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
494 {
495 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
496 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
497 return abs_arg1 < abs_arg2 ? arg1 : arg2;
498 }
499
500 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
501 {
502 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
503 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
504 return abs_arg1 + abs_arg2;
505 }
506
507 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
508 {
509 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
510 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
511 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
512 if (abs_arg1 > max_int || abs_arg2 > max_int) {
513 return (int64_t)max_int;
514 } else {
515 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
516 }
517 }
518
519 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
520 {
521 int64_t max_int = DF_MAX_INT(df);
522 int64_t min_int = DF_MIN_INT(df);
523 if (arg1 < 0) {
524 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
525 } else {
526 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
527 }
528 }
529
530 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
531 {
532 uint64_t max_uint = DF_MAX_UINT(df);
533 uint64_t u_arg1 = UNSIGNED(arg1, df);
534 uint64_t u_arg2 = UNSIGNED(arg2, df);
535 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
536 }
537
538 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
539 {
540 /* signed shift */
541 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
542 }
543
544 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
545 {
546 uint64_t u_arg1 = UNSIGNED(arg1, df);
547 uint64_t u_arg2 = UNSIGNED(arg2, df);
548 /* unsigned shift */
549 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
550 }
551
552 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
553 {
554 /* signed shift */
555 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
556 }
557
558 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
559 {
560 uint64_t u_arg1 = UNSIGNED(arg1, df);
561 uint64_t u_arg2 = UNSIGNED(arg2, df);
562 /* unsigned shift */
563 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
564 }
565
566 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
567 {
568 int64_t max_int = DF_MAX_INT(df);
569 int64_t min_int = DF_MIN_INT(df);
570 if (arg2 > 0) {
571 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
572 } else {
573 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
574 }
575 }
576
577 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
578 {
579 uint64_t u_arg1 = UNSIGNED(arg1, df);
580 uint64_t u_arg2 = UNSIGNED(arg2, df);
581 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
582 }
583
584 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
585 {
586 uint64_t u_arg1 = UNSIGNED(arg1, df);
587 uint64_t max_uint = DF_MAX_UINT(df);
588 if (arg2 >= 0) {
589 uint64_t u_arg2 = (uint64_t)arg2;
590 return (u_arg1 > u_arg2) ?
591 (int64_t)(u_arg1 - u_arg2) :
592 0;
593 } else {
594 uint64_t u_arg2 = (uint64_t)(-arg2);
595 return (u_arg1 < max_uint - u_arg2) ?
596 (int64_t)(u_arg1 + u_arg2) :
597 (int64_t)max_uint;
598 }
599 }
600
601 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
602 {
603 uint64_t u_arg1 = UNSIGNED(arg1, df);
604 uint64_t u_arg2 = UNSIGNED(arg2, df);
605 int64_t max_int = DF_MAX_INT(df);
606 int64_t min_int = DF_MIN_INT(df);
607 if (u_arg1 > u_arg2) {
608 return u_arg1 - u_arg2 < (uint64_t)max_int ?
609 (int64_t)(u_arg1 - u_arg2) :
610 max_int;
611 } else {
612 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
613 (int64_t)(u_arg1 - u_arg2) :
614 min_int;
615 }
616 }
617
618 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
619 {
620 /* signed compare */
621 return (arg1 < arg2) ?
622 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
623 }
624
625 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
626 {
627 uint64_t u_arg1 = UNSIGNED(arg1, df);
628 uint64_t u_arg2 = UNSIGNED(arg2, df);
629 /* unsigned compare */
630 return (u_arg1 < u_arg2) ?
631 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
632 }
633
634 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
635 {
636 return arg1 * arg2;
637 }
638
639 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
640 {
641 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
642 return DF_MIN_INT(df);
643 }
644 return arg2 ? arg1 / arg2
645 : arg1 >= 0 ? -1 : 1;
646 }
647
648 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
649 {
650 uint64_t u_arg1 = UNSIGNED(arg1, df);
651 uint64_t u_arg2 = UNSIGNED(arg2, df);
652 return arg2 ? u_arg1 / u_arg2 : -1;
653 }
654
655 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
656 {
657 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
658 return 0;
659 }
660 return arg2 ? arg1 % arg2 : arg1;
661 }
662
663 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
664 {
665 uint64_t u_arg1 = UNSIGNED(arg1, df);
666 uint64_t u_arg2 = UNSIGNED(arg2, df);
667 return u_arg2 ? u_arg1 % u_arg2 : u_arg1;
668 }
669
670 #define SIGNED_EVEN(a, df) \
671 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
672
673 #define UNSIGNED_EVEN(a, df) \
674 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
675
676 #define SIGNED_ODD(a, df) \
677 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
678
679 #define UNSIGNED_ODD(a, df) \
680 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
681
682 #define SIGNED_EXTRACT(e, o, a, df) \
683 do { \
684 e = SIGNED_EVEN(a, df); \
685 o = SIGNED_ODD(a, df); \
686 } while (0)
687
688 #define UNSIGNED_EXTRACT(e, o, a, df) \
689 do { \
690 e = UNSIGNED_EVEN(a, df); \
691 o = UNSIGNED_ODD(a, df); \
692 } while (0)
693
694 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
695 {
696 int64_t even_arg1;
697 int64_t even_arg2;
698 int64_t odd_arg1;
699 int64_t odd_arg2;
700 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
701 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
702 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
703 }
704
705 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
706 {
707 int64_t even_arg1;
708 int64_t even_arg2;
709 int64_t odd_arg1;
710 int64_t odd_arg2;
711 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
712 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
713 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
714 }
715
716 #define CONCATENATE_AND_SLIDE(s, k) \
717 do { \
718 for (i = 0; i < s; i++) { \
719 v[i] = pws->b[s * k + i]; \
720 v[i + s] = pwd->b[s * k + i]; \
721 } \
722 for (i = 0; i < s; i++) { \
723 pwd->b[s * k + i] = v[i + n]; \
724 } \
725 } while (0)
726
727 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
728 wr_t *pws, target_ulong rt)
729 {
730 uint32_t n = rt % DF_ELEMENTS(df);
731 uint8_t v[64];
732 uint32_t i, k;
733
734 switch (df) {
735 case DF_BYTE:
736 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
737 break;
738 case DF_HALF:
739 for (k = 0; k < 2; k++) {
740 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
741 }
742 break;
743 case DF_WORD:
744 for (k = 0; k < 4; k++) {
745 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
746 }
747 break;
748 case DF_DOUBLE:
749 for (k = 0; k < 8; k++) {
750 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
751 }
752 break;
753 default:
754 assert(0);
755 }
756 }
757
758 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
759 {
760 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
761 }
762
763 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
764 {
765 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
766 }
767
768 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
769 {
770 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
771 }
772
773 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
774 {
775 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
776 }
777
778 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
779 {
780 int64_t q_min = DF_MIN_INT(df);
781 int64_t q_max = DF_MAX_INT(df);
782
783 if (arg1 == q_min && arg2 == q_min) {
784 return q_max;
785 }
786 return (arg1 * arg2) >> (DF_BITS(df) - 1);
787 }
788
789 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
790 {
791 int64_t q_min = DF_MIN_INT(df);
792 int64_t q_max = DF_MAX_INT(df);
793 int64_t r_bit = 1 << (DF_BITS(df) - 2);
794
795 if (arg1 == q_min && arg2 == q_min) {
796 return q_max;
797 }
798 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
799 }
800
801 #define MSA_BINOP_DF(func) \
802 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
803 uint32_t wd, uint32_t ws, uint32_t wt) \
804 { \
805 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
806 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
807 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
808 uint32_t i; \
809 \
810 switch (df) { \
811 case DF_BYTE: \
812 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
813 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
814 } \
815 break; \
816 case DF_HALF: \
817 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
818 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
819 } \
820 break; \
821 case DF_WORD: \
822 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
823 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
824 } \
825 break; \
826 case DF_DOUBLE: \
827 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
828 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
829 } \
830 break; \
831 default: \
832 assert(0); \
833 } \
834 }
835
836 MSA_BINOP_DF(sll)
837 MSA_BINOP_DF(sra)
838 MSA_BINOP_DF(srl)
839 MSA_BINOP_DF(bclr)
840 MSA_BINOP_DF(bset)
841 MSA_BINOP_DF(bneg)
842 MSA_BINOP_DF(addv)
843 MSA_BINOP_DF(subv)
844 MSA_BINOP_DF(max_s)
845 MSA_BINOP_DF(max_u)
846 MSA_BINOP_DF(min_s)
847 MSA_BINOP_DF(min_u)
848 MSA_BINOP_DF(max_a)
849 MSA_BINOP_DF(min_a)
850 MSA_BINOP_DF(ceq)
851 MSA_BINOP_DF(clt_s)
852 MSA_BINOP_DF(clt_u)
853 MSA_BINOP_DF(cle_s)
854 MSA_BINOP_DF(cle_u)
855 MSA_BINOP_DF(add_a)
856 MSA_BINOP_DF(adds_a)
857 MSA_BINOP_DF(adds_s)
858 MSA_BINOP_DF(adds_u)
859 MSA_BINOP_DF(ave_s)
860 MSA_BINOP_DF(ave_u)
861 MSA_BINOP_DF(aver_s)
862 MSA_BINOP_DF(aver_u)
863 MSA_BINOP_DF(subs_s)
864 MSA_BINOP_DF(subs_u)
865 MSA_BINOP_DF(subsus_u)
866 MSA_BINOP_DF(subsuu_s)
867 MSA_BINOP_DF(asub_s)
868 MSA_BINOP_DF(asub_u)
869 MSA_BINOP_DF(mulv)
870 MSA_BINOP_DF(div_s)
871 MSA_BINOP_DF(div_u)
872 MSA_BINOP_DF(mod_s)
873 MSA_BINOP_DF(mod_u)
874 MSA_BINOP_DF(dotp_s)
875 MSA_BINOP_DF(dotp_u)
876 MSA_BINOP_DF(srar)
877 MSA_BINOP_DF(srlr)
878 MSA_BINOP_DF(hadd_s)
879 MSA_BINOP_DF(hadd_u)
880 MSA_BINOP_DF(hsub_s)
881 MSA_BINOP_DF(hsub_u)
882
883 MSA_BINOP_DF(mul_q)
884 MSA_BINOP_DF(mulr_q)
885 #undef MSA_BINOP_DF
886
887 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
888 uint32_t ws, uint32_t rt)
889 {
890 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
891 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
892
893 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
894 }
895
896 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
897 int64_t arg2)
898 {
899 return dest + arg1 * arg2;
900 }
901
902 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
903 int64_t arg2)
904 {
905 return dest - arg1 * arg2;
906 }
907
908 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
909 int64_t arg2)
910 {
911 int64_t even_arg1;
912 int64_t even_arg2;
913 int64_t odd_arg1;
914 int64_t odd_arg2;
915 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
916 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
917 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
918 }
919
920 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
921 int64_t arg2)
922 {
923 int64_t even_arg1;
924 int64_t even_arg2;
925 int64_t odd_arg1;
926 int64_t odd_arg2;
927 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
928 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
929 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
930 }
931
932 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
933 int64_t arg2)
934 {
935 int64_t even_arg1;
936 int64_t even_arg2;
937 int64_t odd_arg1;
938 int64_t odd_arg2;
939 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
940 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
941 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
942 }
943
944 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
945 int64_t arg2)
946 {
947 int64_t even_arg1;
948 int64_t even_arg2;
949 int64_t odd_arg1;
950 int64_t odd_arg2;
951 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
952 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
953 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
954 }
955
956 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
957 int64_t arg2)
958 {
959 int64_t q_prod, q_ret;
960
961 int64_t q_max = DF_MAX_INT(df);
962 int64_t q_min = DF_MIN_INT(df);
963
964 q_prod = arg1 * arg2;
965 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
966
967 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
968 }
969
970 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
971 int64_t arg2)
972 {
973 int64_t q_prod, q_ret;
974
975 int64_t q_max = DF_MAX_INT(df);
976 int64_t q_min = DF_MIN_INT(df);
977
978 q_prod = arg1 * arg2;
979 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
980
981 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
982 }
983
984 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
985 int64_t arg2)
986 {
987 int64_t q_prod, q_ret;
988
989 int64_t q_max = DF_MAX_INT(df);
990 int64_t q_min = DF_MIN_INT(df);
991 int64_t r_bit = 1 << (DF_BITS(df) - 2);
992
993 q_prod = arg1 * arg2;
994 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
995
996 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
997 }
998
999 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
1000 int64_t arg2)
1001 {
1002 int64_t q_prod, q_ret;
1003
1004 int64_t q_max = DF_MAX_INT(df);
1005 int64_t q_min = DF_MIN_INT(df);
1006 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1007
1008 q_prod = arg1 * arg2;
1009 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1010
1011 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1012 }
1013
1014 #define MSA_TEROP_DF(func) \
1015 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1016 uint32_t ws, uint32_t wt) \
1017 { \
1018 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1019 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1020 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1021 uint32_t i; \
1022 \
1023 switch (df) { \
1024 case DF_BYTE: \
1025 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1026 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1027 pwt->b[i]); \
1028 } \
1029 break; \
1030 case DF_HALF: \
1031 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1032 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1033 pwt->h[i]); \
1034 } \
1035 break; \
1036 case DF_WORD: \
1037 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1038 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1039 pwt->w[i]); \
1040 } \
1041 break; \
1042 case DF_DOUBLE: \
1043 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1044 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1045 pwt->d[i]); \
1046 } \
1047 break; \
1048 default: \
1049 assert(0); \
1050 } \
1051 }
1052
1053 MSA_TEROP_DF(maddv)
1054 MSA_TEROP_DF(msubv)
1055 MSA_TEROP_DF(dpadd_s)
1056 MSA_TEROP_DF(dpadd_u)
1057 MSA_TEROP_DF(dpsub_s)
1058 MSA_TEROP_DF(dpsub_u)
1059 MSA_TEROP_DF(binsl)
1060 MSA_TEROP_DF(binsr)
1061 MSA_TEROP_DF(madd_q)
1062 MSA_TEROP_DF(msub_q)
1063 MSA_TEROP_DF(maddr_q)
1064 MSA_TEROP_DF(msubr_q)
1065 #undef MSA_TEROP_DF
1066
1067 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1068 wr_t *pws, target_ulong rt)
1069 {
1070 uint32_t n = rt % DF_ELEMENTS(df);
1071 uint32_t i;
1072
1073 switch (df) {
1074 case DF_BYTE:
1075 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1076 pwd->b[i] = pws->b[n];
1077 }
1078 break;
1079 case DF_HALF:
1080 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1081 pwd->h[i] = pws->h[n];
1082 }
1083 break;
1084 case DF_WORD:
1085 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1086 pwd->w[i] = pws->w[n];
1087 }
1088 break;
1089 case DF_DOUBLE:
1090 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1091 pwd->d[i] = pws->d[n];
1092 }
1093 break;
1094 default:
1095 assert(0);
1096 }
1097 }
1098
1099 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1100 uint32_t ws, uint32_t rt)
1101 {
1102 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1103 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1104
1105 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1106 }
1107
1108 #define MSA_DO_B MSA_DO(b)
1109 #define MSA_DO_H MSA_DO(h)
1110 #define MSA_DO_W MSA_DO(w)
1111 #define MSA_DO_D MSA_DO(d)
1112
1113 #define MSA_LOOP_B MSA_LOOP(B)
1114 #define MSA_LOOP_H MSA_LOOP(H)
1115 #define MSA_LOOP_W MSA_LOOP(W)
1116 #define MSA_LOOP_D MSA_LOOP(D)
1117
1118 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1119 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1120 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1121 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1122
1123 #define MSA_LOOP(DF) \
1124 do { \
1125 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1126 MSA_DO_ ## DF; \
1127 } \
1128 } while (0)
1129
1130 #define MSA_FN_DF(FUNC) \
1131 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1132 uint32_t ws, uint32_t wt) \
1133 { \
1134 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1135 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1136 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1137 wr_t wx, *pwx = &wx; \
1138 uint32_t i; \
1139 switch (df) { \
1140 case DF_BYTE: \
1141 MSA_LOOP_B; \
1142 break; \
1143 case DF_HALF: \
1144 MSA_LOOP_H; \
1145 break; \
1146 case DF_WORD: \
1147 MSA_LOOP_W; \
1148 break; \
1149 case DF_DOUBLE: \
1150 MSA_LOOP_D; \
1151 break; \
1152 default: \
1153 assert(0); \
1154 } \
1155 msa_move_v(pwd, pwx); \
1156 }
1157
1158 #define MSA_LOOP_COND(DF) \
1159 (DF_ELEMENTS(DF) / 2)
1160
1161 #define Rb(pwr, i) (pwr->b[i])
1162 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1163 #define Rh(pwr, i) (pwr->h[i])
1164 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1165 #define Rw(pwr, i) (pwr->w[i])
1166 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1167 #define Rd(pwr, i) (pwr->d[i])
1168 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1169
1170 #define MSA_DO(DF) \
1171 do { \
1172 R##DF(pwx, i) = pwt->DF[2*i]; \
1173 L##DF(pwx, i) = pws->DF[2*i]; \
1174 } while (0)
1175 MSA_FN_DF(pckev_df)
1176 #undef MSA_DO
1177
1178 #define MSA_DO(DF) \
1179 do { \
1180 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1181 L##DF(pwx, i) = pws->DF[2*i+1]; \
1182 } while (0)
1183 MSA_FN_DF(pckod_df)
1184 #undef MSA_DO
1185
1186 #define MSA_DO(DF) \
1187 do { \
1188 pwx->DF[2*i] = L##DF(pwt, i); \
1189 pwx->DF[2*i+1] = L##DF(pws, i); \
1190 } while (0)
1191 MSA_FN_DF(ilvl_df)
1192 #undef MSA_DO
1193
1194 #define MSA_DO(DF) \
1195 do { \
1196 pwx->DF[2*i] = R##DF(pwt, i); \
1197 pwx->DF[2*i+1] = R##DF(pws, i); \
1198 } while (0)
1199 MSA_FN_DF(ilvr_df)
1200 #undef MSA_DO
1201
1202 #define MSA_DO(DF) \
1203 do { \
1204 pwx->DF[2*i] = pwt->DF[2*i]; \
1205 pwx->DF[2*i+1] = pws->DF[2*i]; \
1206 } while (0)
1207 MSA_FN_DF(ilvev_df)
1208 #undef MSA_DO
1209
1210 #define MSA_DO(DF) \
1211 do { \
1212 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1213 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1214 } while (0)
1215 MSA_FN_DF(ilvod_df)
1216 #undef MSA_DO
1217 #undef MSA_LOOP_COND
1218
1219 #define MSA_LOOP_COND(DF) \
1220 (DF_ELEMENTS(DF))
1221
1222 #define MSA_DO(DF) \
1223 do { \
1224 uint32_t n = DF_ELEMENTS(df); \
1225 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1226 pwx->DF[i] = \
1227 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1228 } while (0)
1229 MSA_FN_DF(vshf_df)
1230 #undef MSA_DO
1231 #undef MSA_LOOP_COND
1232 #undef MSA_FN_DF
1233
1234 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1235 uint32_t ws, uint32_t n)
1236 {
1237 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1238 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1239
1240 msa_sld_df(df, pwd, pws, n);
1241 }
1242
1243 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1244 uint32_t ws, uint32_t n)
1245 {
1246 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1247 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1248
1249 msa_splat_df(df, pwd, pws, n);
1250 }
1251
1252 void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
1253 uint32_t ws, uint32_t n)
1254 {
1255 n %= 16;
1256 #if defined(HOST_WORDS_BIGENDIAN)
1257 if (n < 8) {
1258 n = 8 - n - 1;
1259 } else {
1260 n = 24 - n - 1;
1261 }
1262 #endif
1263 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1264 }
1265
1266 void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
1267 uint32_t ws, uint32_t n)
1268 {
1269 n %= 8;
1270 #if defined(HOST_WORDS_BIGENDIAN)
1271 if (n < 4) {
1272 n = 4 - n - 1;
1273 } else {
1274 n = 12 - n - 1;
1275 }
1276 #endif
1277 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1278 }
1279
1280 void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
1281 uint32_t ws, uint32_t n)
1282 {
1283 n %= 4;
1284 #if defined(HOST_WORDS_BIGENDIAN)
1285 if (n < 2) {
1286 n = 2 - n - 1;
1287 } else {
1288 n = 6 - n - 1;
1289 }
1290 #endif
1291 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1292 }
1293
1294 void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
1295 uint32_t ws, uint32_t n)
1296 {
1297 n %= 2;
1298 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1299 }
1300
1301 void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
1302 uint32_t ws, uint32_t n)
1303 {
1304 n %= 16;
1305 #if defined(HOST_WORDS_BIGENDIAN)
1306 if (n < 8) {
1307 n = 8 - n - 1;
1308 } else {
1309 n = 24 - n - 1;
1310 }
1311 #endif
1312 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1313 }
1314
1315 void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
1316 uint32_t ws, uint32_t n)
1317 {
1318 n %= 8;
1319 #if defined(HOST_WORDS_BIGENDIAN)
1320 if (n < 4) {
1321 n = 4 - n - 1;
1322 } else {
1323 n = 12 - n - 1;
1324 }
1325 #endif
1326 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1327 }
1328
1329 void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
1330 uint32_t ws, uint32_t n)
1331 {
1332 n %= 4;
1333 #if defined(HOST_WORDS_BIGENDIAN)
1334 if (n < 2) {
1335 n = 2 - n - 1;
1336 } else {
1337 n = 6 - n - 1;
1338 }
1339 #endif
1340 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1341 }
1342
1343 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1344 uint32_t rs_num, uint32_t n)
1345 {
1346 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1347 target_ulong rs = env->active_tc.gpr[rs_num];
1348
1349 switch (df) {
1350 case DF_BYTE:
1351 pwd->b[n] = (int8_t)rs;
1352 break;
1353 case DF_HALF:
1354 pwd->h[n] = (int16_t)rs;
1355 break;
1356 case DF_WORD:
1357 pwd->w[n] = (int32_t)rs;
1358 break;
1359 case DF_DOUBLE:
1360 pwd->d[n] = (int64_t)rs;
1361 break;
1362 default:
1363 assert(0);
1364 }
1365 }
1366
1367 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1368 uint32_t ws, uint32_t n)
1369 {
1370 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1371 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1372
1373 switch (df) {
1374 case DF_BYTE:
1375 pwd->b[n] = (int8_t)pws->b[0];
1376 break;
1377 case DF_HALF:
1378 pwd->h[n] = (int16_t)pws->h[0];
1379 break;
1380 case DF_WORD:
1381 pwd->w[n] = (int32_t)pws->w[0];
1382 break;
1383 case DF_DOUBLE:
1384 pwd->d[n] = (int64_t)pws->d[0];
1385 break;
1386 default:
1387 assert(0);
1388 }
1389 }
1390
1391 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1392 {
1393 switch (cd) {
1394 case 0:
1395 break;
1396 case 1:
1397 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1398 restore_msa_fp_status(env);
1399 /* check exception */
1400 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1401 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1402 do_raise_exception(env, EXCP_MSAFPE, GETPC());
1403 }
1404 break;
1405 }
1406 }
1407
1408 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1409 {
1410 switch (cs) {
1411 case 0:
1412 return env->msair;
1413 case 1:
1414 return env->active_tc.msacsr & MSACSR_MASK;
1415 }
1416 return 0;
1417 }
1418
1419 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1420 {
1421 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1422 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1423
1424 msa_move_v(pwd, pws);
1425 }
1426
1427 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1428 {
1429 uint64_t x;
1430
1431 x = UNSIGNED(arg, df);
1432
1433 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1434 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1435 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1436 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1437 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1438 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1439
1440 return x;
1441 }
1442
1443 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1444 {
1445 uint64_t x, y;
1446 int n, c;
1447
1448 x = UNSIGNED(arg, df);
1449 n = DF_BITS(df);
1450 c = DF_BITS(df) / 2;
1451
1452 do {
1453 y = x >> c;
1454 if (y != 0) {
1455 n = n - c;
1456 x = y;
1457 }
1458 c = c >> 1;
1459 } while (c != 0);
1460
1461 return n - x;
1462 }
1463
1464 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1465 {
1466 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1467 }
1468
1469 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1470 uint32_t rs)
1471 {
1472 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1473 uint32_t i;
1474
1475 switch (df) {
1476 case DF_BYTE:
1477 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1478 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1479 }
1480 break;
1481 case DF_HALF:
1482 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1483 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1484 }
1485 break;
1486 case DF_WORD:
1487 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1488 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1489 }
1490 break;
1491 case DF_DOUBLE:
1492 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1493 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1494 }
1495 break;
1496 default:
1497 assert(0);
1498 }
1499 }
1500
1501 #define MSA_UNOP_DF(func) \
1502 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1503 uint32_t wd, uint32_t ws) \
1504 { \
1505 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1506 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1507 uint32_t i; \
1508 \
1509 switch (df) { \
1510 case DF_BYTE: \
1511 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1512 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1513 } \
1514 break; \
1515 case DF_HALF: \
1516 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1517 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1518 } \
1519 break; \
1520 case DF_WORD: \
1521 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1522 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1523 } \
1524 break; \
1525 case DF_DOUBLE: \
1526 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1527 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1528 } \
1529 break; \
1530 default: \
1531 assert(0); \
1532 } \
1533 }
1534
1535 MSA_UNOP_DF(nlzc)
1536 MSA_UNOP_DF(nloc)
1537 MSA_UNOP_DF(pcnt)
1538 #undef MSA_UNOP_DF
1539
1540 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1541 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1542
1543 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
1544 /* 0x7c20 */
1545 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
1546 /* 0x7f800020 */
1547 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
1548 /* 0x7ff0000000000020 */
1549
1550 static inline void clear_msacsr_cause(CPUMIPSState *env)
1551 {
1552 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1553 }
1554
1555 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
1556 {
1557 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1558 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1559 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1560 GET_FP_CAUSE(env->active_tc.msacsr));
1561 } else {
1562 do_raise_exception(env, EXCP_MSAFPE, retaddr);
1563 }
1564 }
1565
1566 /* Flush-to-zero use cases for update_msacsr() */
1567 #define CLEAR_FS_UNDERFLOW 1
1568 #define CLEAR_IS_INEXACT 2
1569 #define RECIPROCAL_INEXACT 4
1570
1571 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1572 {
1573 int ieee_ex;
1574
1575 int c;
1576 int cause;
1577 int enable;
1578
1579 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1580
1581 /* QEMU softfloat does not signal all underflow cases */
1582 if (denormal) {
1583 ieee_ex |= float_flag_underflow;
1584 }
1585
1586 c = ieee_ex_to_mips(ieee_ex);
1587 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1588
1589 /* Set Inexact (I) when flushing inputs to zero */
1590 if ((ieee_ex & float_flag_input_denormal) &&
1591 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1592 if (action & CLEAR_IS_INEXACT) {
1593 c &= ~FP_INEXACT;
1594 } else {
1595 c |= FP_INEXACT;
1596 }
1597 }
1598
1599 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1600 if ((ieee_ex & float_flag_output_denormal) &&
1601 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1602 c |= FP_INEXACT;
1603 if (action & CLEAR_FS_UNDERFLOW) {
1604 c &= ~FP_UNDERFLOW;
1605 } else {
1606 c |= FP_UNDERFLOW;
1607 }
1608 }
1609
1610 /* Set Inexact (I) when Overflow (O) is not enabled */
1611 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1612 c |= FP_INEXACT;
1613 }
1614
1615 /* Clear Exact Underflow when Underflow (U) is not enabled */
1616 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1617 (c & FP_INEXACT) == 0) {
1618 c &= ~FP_UNDERFLOW;
1619 }
1620
1621 /* Reciprocal operations set only Inexact when valid and not
1622 divide by zero */
1623 if ((action & RECIPROCAL_INEXACT) &&
1624 (c & (FP_INVALID | FP_DIV0)) == 0) {
1625 c = FP_INEXACT;
1626 }
1627
1628 cause = c & enable; /* all current enabled exceptions */
1629
1630 if (cause == 0) {
1631 /* No enabled exception, update the MSACSR Cause
1632 with all current exceptions */
1633 SET_FP_CAUSE(env->active_tc.msacsr,
1634 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1635 } else {
1636 /* Current exceptions are enabled */
1637 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1638 /* Exception(s) will trap, update MSACSR Cause
1639 with all enabled exceptions */
1640 SET_FP_CAUSE(env->active_tc.msacsr,
1641 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1642 }
1643 }
1644
1645 return c;
1646 }
1647
1648 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1649 {
1650 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1651 return c & enable;
1652 }
1653
1654 static inline float16 float16_from_float32(int32_t a, flag ieee,
1655 float_status *status)
1656 {
1657 float16 f_val;
1658
1659 f_val = float32_to_float16((float32)a, ieee, status);
1660
1661 return a < 0 ? (f_val | (1 << 15)) : f_val;
1662 }
1663
1664 static inline float32 float32_from_float64(int64_t a, float_status *status)
1665 {
1666 float32 f_val;
1667
1668 f_val = float64_to_float32((float64)a, status);
1669
1670 return a < 0 ? (f_val | (1 << 31)) : f_val;
1671 }
1672
1673 static inline float32 float32_from_float16(int16_t a, flag ieee,
1674 float_status *status)
1675 {
1676 float32 f_val;
1677
1678 f_val = float16_to_float32((float16)a, ieee, status);
1679
1680 return a < 0 ? (f_val | (1 << 31)) : f_val;
1681 }
1682
1683 static inline float64 float64_from_float32(int32_t a, float_status *status)
1684 {
1685 float64 f_val;
1686
1687 f_val = float32_to_float64((float64)a, status);
1688
1689 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1690 }
1691
1692 static inline float32 float32_from_q16(int16_t a, float_status *status)
1693 {
1694 float32 f_val;
1695
1696 /* conversion as integer and scaling */
1697 f_val = int32_to_float32(a, status);
1698 f_val = float32_scalbn(f_val, -15, status);
1699
1700 return f_val;
1701 }
1702
1703 static inline float64 float64_from_q32(int32_t a, float_status *status)
1704 {
1705 float64 f_val;
1706
1707 /* conversion as integer and scaling */
1708 f_val = int32_to_float64(a, status);
1709 f_val = float64_scalbn(f_val, -31, status);
1710
1711 return f_val;
1712 }
1713
1714 static inline int16_t float32_to_q16(float32 a, float_status *status)
1715 {
1716 int32_t q_val;
1717 int32_t q_min = 0xffff8000;
1718 int32_t q_max = 0x00007fff;
1719
1720 int ieee_ex;
1721
1722 if (float32_is_any_nan(a)) {
1723 float_raise(float_flag_invalid, status);
1724 return 0;
1725 }
1726
1727 /* scaling */
1728 a = float32_scalbn(a, 15, status);
1729
1730 ieee_ex = get_float_exception_flags(status);
1731 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1732 , status);
1733
1734 if (ieee_ex & float_flag_overflow) {
1735 float_raise(float_flag_inexact, status);
1736 return (int32_t)a < 0 ? q_min : q_max;
1737 }
1738
1739 /* conversion to int */
1740 q_val = float32_to_int32(a, status);
1741
1742 ieee_ex = get_float_exception_flags(status);
1743 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1744 , status);
1745
1746 if (ieee_ex & float_flag_invalid) {
1747 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1748 , status);
1749 float_raise(float_flag_overflow | float_flag_inexact, status);
1750 return (int32_t)a < 0 ? q_min : q_max;
1751 }
1752
1753 if (q_val < q_min) {
1754 float_raise(float_flag_overflow | float_flag_inexact, status);
1755 return (int16_t)q_min;
1756 }
1757
1758 if (q_max < q_val) {
1759 float_raise(float_flag_overflow | float_flag_inexact, status);
1760 return (int16_t)q_max;
1761 }
1762
1763 return (int16_t)q_val;
1764 }
1765
1766 static inline int32_t float64_to_q32(float64 a, float_status *status)
1767 {
1768 int64_t q_val;
1769 int64_t q_min = 0xffffffff80000000LL;
1770 int64_t q_max = 0x000000007fffffffLL;
1771
1772 int ieee_ex;
1773
1774 if (float64_is_any_nan(a)) {
1775 float_raise(float_flag_invalid, status);
1776 return 0;
1777 }
1778
1779 /* scaling */
1780 a = float64_scalbn(a, 31, status);
1781
1782 ieee_ex = get_float_exception_flags(status);
1783 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1784 , status);
1785
1786 if (ieee_ex & float_flag_overflow) {
1787 float_raise(float_flag_inexact, status);
1788 return (int64_t)a < 0 ? q_min : q_max;
1789 }
1790
1791 /* conversion to integer */
1792 q_val = float64_to_int64(a, status);
1793
1794 ieee_ex = get_float_exception_flags(status);
1795 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1796 , status);
1797
1798 if (ieee_ex & float_flag_invalid) {
1799 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1800 , status);
1801 float_raise(float_flag_overflow | float_flag_inexact, status);
1802 return (int64_t)a < 0 ? q_min : q_max;
1803 }
1804
1805 if (q_val < q_min) {
1806 float_raise(float_flag_overflow | float_flag_inexact, status);
1807 return (int32_t)q_min;
1808 }
1809
1810 if (q_max < q_val) {
1811 float_raise(float_flag_overflow | float_flag_inexact, status);
1812 return (int32_t)q_max;
1813 }
1814
1815 return (int32_t)q_val;
1816 }
1817
1818 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1819 do { \
1820 float_status *status = &env->active_tc.msa_fp_status; \
1821 int c; \
1822 int64_t cond; \
1823 set_float_exception_flags(0, status); \
1824 if (!QUIET) { \
1825 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1826 } else { \
1827 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1828 } \
1829 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1830 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1831 \
1832 if (get_enabled_exceptions(env, c)) { \
1833 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
1834 } \
1835 } while (0)
1836
1837 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1838 do { \
1839 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1840 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1841 DEST = 0; \
1842 } \
1843 } while (0)
1844
1845 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1846 do { \
1847 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1848 if (DEST == 0) { \
1849 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1850 } \
1851 } while (0)
1852
1853 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1854 do { \
1855 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1856 if (DEST == 0) { \
1857 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1858 } \
1859 } while (0)
1860
1861 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1862 do { \
1863 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1864 if (DEST == 0) { \
1865 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1866 if (DEST == 0) { \
1867 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1868 } \
1869 } \
1870 } while (0)
1871
1872 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1873 do { \
1874 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1875 if (DEST == 0) { \
1876 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1877 } \
1878 } while (0)
1879
1880 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1881 do { \
1882 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1883 if (DEST == 0) { \
1884 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1885 } \
1886 } while (0)
1887
1888 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1889 do { \
1890 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1891 if (DEST == 0) { \
1892 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1893 } \
1894 } while (0)
1895
1896 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1897 wr_t *pwt, uint32_t df, int quiet,
1898 uintptr_t retaddr)
1899 {
1900 wr_t wx, *pwx = &wx;
1901 uint32_t i;
1902
1903 clear_msacsr_cause(env);
1904
1905 switch (df) {
1906 case DF_WORD:
1907 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1908 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1909 }
1910 break;
1911 case DF_DOUBLE:
1912 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1913 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1914 }
1915 break;
1916 default:
1917 assert(0);
1918 }
1919
1920 check_msacsr_cause(env, retaddr);
1921
1922 msa_move_v(pwd, pwx);
1923 }
1924
1925 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1926 wr_t *pwt, uint32_t df, int quiet,
1927 uintptr_t retaddr)
1928 {
1929 wr_t wx, *pwx = &wx;
1930 uint32_t i;
1931
1932 clear_msacsr_cause(env);
1933
1934 switch (df) {
1935 case DF_WORD:
1936 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1937 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1938 quiet);
1939 }
1940 break;
1941 case DF_DOUBLE:
1942 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1943 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1944 quiet);
1945 }
1946 break;
1947 default:
1948 assert(0);
1949 }
1950
1951 check_msacsr_cause(env, retaddr);
1952
1953 msa_move_v(pwd, pwx);
1954 }
1955
1956 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1957 wr_t *pwt, uint32_t df, int quiet,
1958 uintptr_t retaddr)
1959 {
1960 wr_t wx, *pwx = &wx;
1961 uint32_t i;
1962
1963 clear_msacsr_cause(env);
1964
1965 switch (df) {
1966 case DF_WORD:
1967 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1968 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1969 }
1970 break;
1971 case DF_DOUBLE:
1972 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1973 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1974 }
1975 break;
1976 default:
1977 assert(0);
1978 }
1979
1980 check_msacsr_cause(env, retaddr);
1981
1982 msa_move_v(pwd, pwx);
1983 }
1984
1985 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1986 wr_t *pwt, uint32_t df, int quiet,
1987 uintptr_t retaddr)
1988 {
1989 wr_t wx, *pwx = &wx;
1990 uint32_t i;
1991
1992 clear_msacsr_cause(env);
1993
1994 switch (df) {
1995 case DF_WORD:
1996 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1997 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1998 }
1999 break;
2000 case DF_DOUBLE:
2001 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2002 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2003 }
2004 break;
2005 default:
2006 assert(0);
2007 }
2008
2009 check_msacsr_cause(env, retaddr);
2010
2011 msa_move_v(pwd, pwx);
2012 }
2013
2014 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2015 wr_t *pwt, uint32_t df, int quiet,
2016 uintptr_t retaddr)
2017 {
2018 wr_t wx, *pwx = &wx;
2019 uint32_t i;
2020
2021 clear_msacsr_cause(env);
2022
2023 switch (df) {
2024 case DF_WORD:
2025 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2026 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
2027 }
2028 break;
2029 case DF_DOUBLE:
2030 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2031 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
2032 }
2033 break;
2034 default:
2035 assert(0);
2036 }
2037
2038 check_msacsr_cause(env, retaddr);
2039
2040 msa_move_v(pwd, pwx);
2041 }
2042
2043 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2044 wr_t *pwt, uint32_t df, int quiet,
2045 uintptr_t retaddr)
2046 {
2047 wr_t wx, *pwx = &wx;
2048 uint32_t i;
2049
2050 clear_msacsr_cause(env);
2051
2052 switch (df) {
2053 case DF_WORD:
2054 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2055 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2056 }
2057 break;
2058 case DF_DOUBLE:
2059 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2060 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2061 }
2062 break;
2063 default:
2064 assert(0);
2065 }
2066
2067 check_msacsr_cause(env, retaddr);
2068
2069 msa_move_v(pwd, pwx);
2070 }
2071
2072 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2073 wr_t *pwt, uint32_t df, int quiet,
2074 uintptr_t retaddr)
2075 {
2076 wr_t wx, *pwx = &wx;
2077 uint32_t i;
2078
2079 clear_msacsr_cause(env);
2080
2081 switch (df) {
2082 case DF_WORD:
2083 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2084 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2085 }
2086 break;
2087 case DF_DOUBLE:
2088 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2089 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2090 }
2091 break;
2092 default:
2093 assert(0);
2094 }
2095
2096 check_msacsr_cause(env, retaddr);
2097
2098 msa_move_v(pwd, pwx);
2099 }
2100
2101 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2102 wr_t *pwt, uint32_t df, int quiet,
2103 uintptr_t retaddr)
2104 {
2105 wr_t wx, *pwx = &wx;
2106 uint32_t i;
2107
2108 clear_msacsr_cause(env);
2109
2110 switch (df) {
2111 case DF_WORD:
2112 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2113 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2114 }
2115 break;
2116 case DF_DOUBLE:
2117 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2118 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2119 }
2120 break;
2121 default:
2122 assert(0);
2123 }
2124
2125 check_msacsr_cause(env, retaddr);
2126
2127 msa_move_v(pwd, pwx);
2128 }
2129
2130 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2131 wr_t *pwt, uint32_t df, int quiet,
2132 uintptr_t retaddr)
2133 {
2134 wr_t wx, *pwx = &wx;
2135 uint32_t i;
2136
2137 clear_msacsr_cause(env);
2138
2139 switch (df) {
2140 case DF_WORD:
2141 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2142 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2143 }
2144 break;
2145 case DF_DOUBLE:
2146 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2147 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2148 }
2149 break;
2150 default:
2151 assert(0);
2152 }
2153
2154 check_msacsr_cause(env, retaddr);
2155
2156 msa_move_v(pwd, pwx);
2157 }
2158
2159 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2160 wr_t *pwt, uint32_t df, int quiet,
2161 uintptr_t retaddr)
2162 {
2163 wr_t wx, *pwx = &wx;
2164 uint32_t i;
2165
2166 clear_msacsr_cause(env);
2167
2168 switch (df) {
2169 case DF_WORD:
2170 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2171 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2172 }
2173 break;
2174 case DF_DOUBLE:
2175 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2176 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2177 }
2178 break;
2179 default:
2180 assert(0);
2181 }
2182
2183 check_msacsr_cause(env, retaddr);
2184
2185 msa_move_v(pwd, pwx);
2186 }
2187
2188 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2189 wr_t *pwt, uint32_t df, int quiet,
2190 uintptr_t retaddr)
2191 {
2192 wr_t wx, *pwx = &wx;
2193 uint32_t i;
2194
2195 clear_msacsr_cause(env);
2196
2197 switch (df) {
2198 case DF_WORD:
2199 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2200 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2201 }
2202 break;
2203 case DF_DOUBLE:
2204 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2205 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2206 }
2207 break;
2208 default:
2209 assert(0);
2210 }
2211
2212 check_msacsr_cause(env, retaddr);
2213
2214 msa_move_v(pwd, pwx);
2215 }
2216
2217 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2218 uint32_t ws, uint32_t wt)
2219 {
2220 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2221 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2222 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2223 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
2224 }
2225
2226 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2227 uint32_t ws, uint32_t wt)
2228 {
2229 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2230 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2231 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2232 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
2233 }
2234
2235 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2236 uint32_t ws, uint32_t wt)
2237 {
2238 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2239 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2240 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2241 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
2242 }
2243
2244 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2245 uint32_t ws, uint32_t wt)
2246 {
2247 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2248 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2249 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2250 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
2251 }
2252
2253 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2254 uint32_t ws, uint32_t wt)
2255 {
2256 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2257 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2258 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2259 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
2260 }
2261
2262 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2263 uint32_t ws, uint32_t wt)
2264 {
2265 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2266 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2267 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2268 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
2269 }
2270
2271 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2272 uint32_t ws, uint32_t wt)
2273 {
2274 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2275 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2276 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2277 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
2278 }
2279
2280 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2281 uint32_t ws, uint32_t wt)
2282 {
2283 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2284 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2285 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2286 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
2287 }
2288
2289 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2290 uint32_t ws, uint32_t wt)
2291 {
2292 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2293 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2294 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2295 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
2296 }
2297
2298 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2299 uint32_t ws, uint32_t wt)
2300 {
2301 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2302 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2303 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2304 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
2305 }
2306
2307 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2308 uint32_t ws, uint32_t wt)
2309 {
2310 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2311 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2312 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2313 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
2314 }
2315
2316 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2317 uint32_t ws, uint32_t wt)
2318 {
2319 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2320 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2321 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2322 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
2323 }
2324
2325 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2326 uint32_t ws, uint32_t wt)
2327 {
2328 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2329 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2330 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2331 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
2332 }
2333
2334 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2335 uint32_t ws, uint32_t wt)
2336 {
2337 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2338 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2339 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2340 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
2341 }
2342
2343 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2344 uint32_t ws, uint32_t wt)
2345 {
2346 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2347 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2348 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2349 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
2350 }
2351
2352 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2353 uint32_t ws, uint32_t wt)
2354 {
2355 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2356 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2357 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2358 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
2359 }
2360
2361 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2362 uint32_t ws, uint32_t wt)
2363 {
2364 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2365 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2366 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2367 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
2368 }
2369
2370 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2371 uint32_t ws, uint32_t wt)
2372 {
2373 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2374 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2375 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2376 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
2377 }
2378
2379 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2380 uint32_t ws, uint32_t wt)
2381 {
2382 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2383 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2384 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2385 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
2386 }
2387
2388 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2389 uint32_t ws, uint32_t wt)
2390 {
2391 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2392 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2393 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2394 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
2395 }
2396
2397 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2398 uint32_t ws, uint32_t wt)
2399 {
2400 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2401 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2402 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2403 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
2404 }
2405
2406 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2407 uint32_t ws, uint32_t wt)
2408 {
2409 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2410 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2411 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2412 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
2413 }
2414
2415 #define float16_is_zero(ARG) 0
2416 #define float16_is_zero_or_denormal(ARG) 0
2417
2418 #define IS_DENORMAL(ARG, BITS) \
2419 (!float ## BITS ## _is_zero(ARG) \
2420 && float ## BITS ## _is_zero_or_denormal(ARG))
2421
2422 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2423 do { \
2424 float_status *status = &env->active_tc.msa_fp_status; \
2425 int c; \
2426 \
2427 set_float_exception_flags(0, status); \
2428 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2429 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2430 \
2431 if (get_enabled_exceptions(env, c)) { \
2432 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2433 } \
2434 } while (0)
2435
2436 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2437 uint32_t ws, uint32_t wt)
2438 {
2439 wr_t wx, *pwx = &wx;
2440 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2441 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2442 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2443 uint32_t i;
2444
2445 clear_msacsr_cause(env);
2446
2447 switch (df) {
2448 case DF_WORD:
2449 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2450 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2451 }
2452 break;
2453 case DF_DOUBLE:
2454 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2455 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2456 }
2457 break;
2458 default:
2459 assert(0);
2460 }
2461
2462 check_msacsr_cause(env, GETPC());
2463 msa_move_v(pwd, pwx);
2464 }
2465
2466 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2467 uint32_t ws, uint32_t wt)
2468 {
2469 wr_t wx, *pwx = &wx;
2470 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2471 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2472 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2473 uint32_t i;
2474
2475 clear_msacsr_cause(env);
2476
2477 switch (df) {
2478 case DF_WORD:
2479 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2480 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2481 }
2482 break;
2483 case DF_DOUBLE:
2484 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2485 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2486 }
2487 break;
2488 default:
2489 assert(0);
2490 }
2491
2492 check_msacsr_cause(env, GETPC());
2493 msa_move_v(pwd, pwx);
2494 }
2495
2496 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2497 uint32_t ws, uint32_t wt)
2498 {
2499 wr_t wx, *pwx = &wx;
2500 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2501 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2502 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2503 uint32_t i;
2504
2505 clear_msacsr_cause(env);
2506
2507 switch (df) {
2508 case DF_WORD:
2509 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2510 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2511 }
2512 break;
2513 case DF_DOUBLE:
2514 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2515 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2516 }
2517 break;
2518 default:
2519 assert(0);
2520 }
2521
2522 check_msacsr_cause(env, GETPC());
2523
2524 msa_move_v(pwd, pwx);
2525 }
2526
2527 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2528 uint32_t ws, uint32_t wt)
2529 {
2530 wr_t wx, *pwx = &wx;
2531 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2532 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2533 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2534 uint32_t i;
2535
2536 clear_msacsr_cause(env);
2537
2538 switch (df) {
2539 case DF_WORD:
2540 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2541 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2542 }
2543 break;
2544 case DF_DOUBLE:
2545 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2546 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2547 }
2548 break;
2549 default:
2550 assert(0);
2551 }
2552
2553 check_msacsr_cause(env, GETPC());
2554
2555 msa_move_v(pwd, pwx);
2556 }
2557
2558 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2559 do { \
2560 float_status *status = &env->active_tc.msa_fp_status; \
2561 int c; \
2562 \
2563 set_float_exception_flags(0, status); \
2564 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2565 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2566 \
2567 if (get_enabled_exceptions(env, c)) { \
2568 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2569 } \
2570 } while (0)
2571
2572 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2573 uint32_t ws, uint32_t wt)
2574 {
2575 wr_t wx, *pwx = &wx;
2576 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2577 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2578 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2579 uint32_t i;
2580
2581 clear_msacsr_cause(env);
2582
2583 switch (df) {
2584 case DF_WORD:
2585 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2586 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2587 pws->w[i], pwt->w[i], 0, 32);
2588 }
2589 break;
2590 case DF_DOUBLE:
2591 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2592 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2593 pws->d[i], pwt->d[i], 0, 64);
2594 }
2595 break;
2596 default:
2597 assert(0);
2598 }
2599
2600 check_msacsr_cause(env, GETPC());
2601
2602 msa_move_v(pwd, pwx);
2603 }
2604
2605 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2606 uint32_t ws, uint32_t wt)
2607 {
2608 wr_t wx, *pwx = &wx;
2609 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2610 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2611 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2612 uint32_t i;
2613
2614 clear_msacsr_cause(env);
2615
2616 switch (df) {
2617 case DF_WORD:
2618 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2619 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2620 pws->w[i], pwt->w[i],
2621 float_muladd_negate_product, 32);
2622 }
2623 break;
2624 case DF_DOUBLE:
2625 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2626 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2627 pws->d[i], pwt->d[i],
2628 float_muladd_negate_product, 64);
2629 }
2630 break;
2631 default:
2632 assert(0);
2633 }
2634
2635 check_msacsr_cause(env, GETPC());
2636
2637 msa_move_v(pwd, pwx);
2638 }
2639
2640 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2641 uint32_t ws, uint32_t wt)
2642 {
2643 wr_t wx, *pwx = &wx;
2644 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2645 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2646 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2647 uint32_t i;
2648
2649 clear_msacsr_cause(env);
2650
2651 switch (df) {
2652 case DF_WORD:
2653 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2654 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2655 pwt->w[i] > 0x200 ? 0x200 :
2656 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2657 32);
2658 }
2659 break;
2660 case DF_DOUBLE:
2661 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2662 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2663 pwt->d[i] > 0x1000 ? 0x1000 :
2664 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2665 64);
2666 }
2667 break;
2668 default:
2669 assert(0);
2670 }
2671
2672 check_msacsr_cause(env, GETPC());
2673
2674 msa_move_v(pwd, pwx);
2675 }
2676
2677 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2678 do { \
2679 float_status *status = &env->active_tc.msa_fp_status; \
2680 int c; \
2681 \
2682 set_float_exception_flags(0, status); \
2683 DEST = float ## BITS ## _ ## OP(ARG, status); \
2684 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2685 \
2686 if (get_enabled_exceptions(env, c)) { \
2687 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2688 } \
2689 } while (0)
2690
2691 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2692 uint32_t ws, uint32_t wt)
2693 {
2694 wr_t wx, *pwx = &wx;
2695 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2696 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2697 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2698 uint32_t i;
2699
2700 clear_msacsr_cause(env);
2701
2702 switch (df) {
2703 case DF_WORD:
2704 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2705 /* Half precision floats come in two formats: standard
2706 IEEE and "ARM" format. The latter gains extra exponent
2707 range by omitting the NaN/Inf encodings. */
2708 flag ieee = 1;
2709
2710 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2711 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2712 }
2713 break;
2714 case DF_DOUBLE:
2715 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2716 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2717 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2718 }
2719 break;
2720 default:
2721 assert(0);
2722 }
2723
2724 check_msacsr_cause(env, GETPC());
2725 msa_move_v(pwd, pwx);
2726 }
2727
2728 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2729 do { \
2730 float_status *status = &env->active_tc.msa_fp_status; \
2731 int c; \
2732 \
2733 set_float_exception_flags(0, status); \
2734 DEST = float ## BITS ## _ ## OP(ARG, status); \
2735 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2736 \
2737 if (get_enabled_exceptions(env, c)) { \
2738 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
2739 } \
2740 } while (0)
2741
2742 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2743 uint32_t ws, uint32_t wt)
2744 {
2745 wr_t wx, *pwx = &wx;
2746 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2747 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2748 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2749 uint32_t i;
2750
2751 clear_msacsr_cause(env);
2752
2753 switch (df) {
2754 case DF_WORD:
2755 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2756 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2757 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2758 }
2759 break;
2760 case DF_DOUBLE:
2761 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2762 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2763 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2764 }
2765 break;
2766 default:
2767 assert(0);
2768 }
2769
2770 check_msacsr_cause(env, GETPC());
2771
2772 msa_move_v(pwd, pwx);
2773 }
2774
2775 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
2776 !float ## BITS ## _is_any_nan(ARG1) \
2777 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
2778
2779 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2780 do { \
2781 float_status *status = &env->active_tc.msa_fp_status; \
2782 int c; \
2783 \
2784 set_float_exception_flags(0, status); \
2785 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2786 c = update_msacsr(env, 0, 0); \
2787 \
2788 if (get_enabled_exceptions(env, c)) { \
2789 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2790 } \
2791 } while (0)
2792
2793 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
2794 do { \
2795 uint## BITS ##_t S = _S, T = _T; \
2796 uint## BITS ##_t as, at, xs, xt, xd; \
2797 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
2798 T = S; \
2799 } \
2800 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
2801 S = T; \
2802 } \
2803 as = float## BITS ##_abs(S); \
2804 at = float## BITS ##_abs(T); \
2805 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2806 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2807 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2808 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2809 } while (0)
2810
2811 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2812 uint32_t ws, uint32_t wt)
2813 {
2814 float_status *status = &env->active_tc.msa_fp_status;
2815 wr_t wx, *pwx = &wx;
2816 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2817 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2818 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2819 uint32_t i;
2820
2821 clear_msacsr_cause(env);
2822
2823 switch (df) {
2824 case DF_WORD:
2825 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2826 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
2827 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2828 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
2829 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2830 } else {
2831 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2832 }
2833 }
2834 break;
2835 case DF_DOUBLE:
2836 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2837 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
2838 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2839 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
2840 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2841 } else {
2842 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2843 }
2844 }
2845 break;
2846 default:
2847 assert(0);
2848 }
2849
2850 check_msacsr_cause(env, GETPC());
2851
2852 msa_move_v(pwd, pwx);
2853 }
2854
2855 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2856 uint32_t ws, uint32_t wt)
2857 {
2858 float_status *status = &env->active_tc.msa_fp_status;
2859 wr_t wx, *pwx = &wx;
2860 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2861 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2862 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2863 uint32_t i;
2864
2865 clear_msacsr_cause(env);
2866
2867 switch (df) {
2868 case DF_WORD:
2869 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2870 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
2871 }
2872 break;
2873 case DF_DOUBLE:
2874 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2875 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
2876 }
2877 break;
2878 default:
2879 assert(0);
2880 }
2881
2882 check_msacsr_cause(env, GETPC());
2883
2884 msa_move_v(pwd, pwx);
2885 }
2886
2887 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2888 uint32_t ws, uint32_t wt)
2889 {
2890 float_status *status = &env->active_tc.msa_fp_status;
2891 wr_t wx, *pwx = &wx;
2892 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2893 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2894 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2895 uint32_t i;
2896
2897 clear_msacsr_cause(env);
2898
2899 switch (df) {
2900 case DF_WORD:
2901 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2902 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
2903 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2904 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
2905 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2906 } else {
2907 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2908 }
2909 }
2910 break;
2911 case DF_DOUBLE:
2912 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2913 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
2914 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2915 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
2916 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2917 } else {
2918 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2919 }
2920 }
2921 break;
2922 default:
2923 assert(0);
2924 }
2925
2926 check_msacsr_cause(env, GETPC());
2927
2928 msa_move_v(pwd, pwx);
2929 }
2930
2931 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2932 uint32_t ws, uint32_t wt)
2933 {
2934 float_status *status = &env->active_tc.msa_fp_status;
2935 wr_t wx, *pwx = &wx;
2936 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2937 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2938 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2939 uint32_t i;
2940
2941 clear_msacsr_cause(env);
2942
2943 switch (df) {
2944 case DF_WORD:
2945 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2946 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
2947 }
2948 break;
2949 case DF_DOUBLE:
2950 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2951 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
2952 }
2953 break;
2954 default:
2955 assert(0);
2956 }
2957
2958 check_msacsr_cause(env, GETPC());
2959
2960 msa_move_v(pwd, pwx);
2961 }
2962
2963 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2964 uint32_t wd, uint32_t ws)
2965 {
2966 float_status* status = &env->active_tc.msa_fp_status;
2967
2968 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2969 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2970 if (df == DF_WORD) {
2971 pwd->w[0] = float_class_s(pws->w[0], status);
2972 pwd->w[1] = float_class_s(pws->w[1], status);
2973 pwd->w[2] = float_class_s(pws->w[2], status);
2974 pwd->w[3] = float_class_s(pws->w[3], status);
2975 } else {
2976 pwd->d[0] = float_class_d(pws->d[0], status);
2977 pwd->d[1] = float_class_d(pws->d[1], status);
2978 }
2979 }
2980
2981 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2982 do { \
2983 float_status *status = &env->active_tc.msa_fp_status; \
2984 int c; \
2985 \
2986 set_float_exception_flags(0, status); \
2987 DEST = float ## BITS ## _ ## OP(ARG, status); \
2988 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2989 \
2990 if (get_enabled_exceptions(env, c)) { \
2991 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2992 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2993 DEST = 0; \
2994 } \
2995 } while (0)
2996
2997 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2998 uint32_t ws)
2999 {
3000 wr_t wx, *pwx = &wx;
3001 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3002 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3003 uint32_t i;
3004
3005 clear_msacsr_cause(env);
3006
3007 switch (df) {
3008 case DF_WORD:
3009 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3010 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
3011 }
3012 break;
3013 case DF_DOUBLE:
3014 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3015 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
3016 }
3017 break;
3018 default:
3019 assert(0);
3020 }
3021
3022 check_msacsr_cause(env, GETPC());
3023
3024 msa_move_v(pwd, pwx);
3025 }
3026
3027 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3028 uint32_t ws)
3029 {
3030 wr_t wx, *pwx = &wx;
3031 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3032 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3033 uint32_t i;
3034
3035 clear_msacsr_cause(env);
3036
3037 switch (df) {
3038 case DF_WORD:
3039 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3040 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
3041 }
3042 break;
3043 case DF_DOUBLE:
3044 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3045 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
3046 }
3047 break;
3048 default:
3049 assert(0);
3050 }
3051
3052 check_msacsr_cause(env, GETPC());
3053
3054 msa_move_v(pwd, pwx);
3055 }
3056
3057 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3058 uint32_t ws)
3059 {
3060 wr_t wx, *pwx = &wx;
3061 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3062 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3063 uint32_t i;
3064
3065 clear_msacsr_cause(env);
3066
3067 switch (df) {
3068 case DF_WORD:
3069 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3070 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3071 }
3072 break;
3073 case DF_DOUBLE:
3074 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3075 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3076 }
3077 break;
3078 default:
3079 assert(0);
3080 }
3081
3082 check_msacsr_cause(env, GETPC());
3083
3084 msa_move_v(pwd, pwx);
3085 }
3086
3087 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3088 do { \
3089 float_status *status = &env->active_tc.msa_fp_status; \
3090 int c; \
3091 \
3092 set_float_exception_flags(0, status); \
3093 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3094 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3095 float ## BITS ## _is_quiet_nan(DEST, status) ? \
3096 0 : RECIPROCAL_INEXACT, \
3097 IS_DENORMAL(DEST, BITS)); \
3098 \
3099 if (get_enabled_exceptions(env, c)) { \
3100 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3101 } \
3102 } while (0)
3103
3104 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3105 uint32_t ws)
3106 {
3107 wr_t wx, *pwx = &wx;
3108 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3109 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3110 uint32_t i;
3111
3112 clear_msacsr_cause(env);
3113
3114 switch (df) {
3115 case DF_WORD:
3116 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3117 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3118 &env->active_tc.msa_fp_status), 32);
3119 }
3120 break;
3121 case DF_DOUBLE:
3122 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3123 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3124 &env->active_tc.msa_fp_status), 64);
3125 }
3126 break;
3127 default:
3128 assert(0);
3129 }
3130
3131 check_msacsr_cause(env, GETPC());
3132
3133 msa_move_v(pwd, pwx);
3134 }
3135
3136 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3137 uint32_t ws)
3138 {
3139 wr_t wx, *pwx = &wx;
3140 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3141 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3142 uint32_t i;
3143
3144 clear_msacsr_cause(env);
3145
3146 switch (df) {
3147 case DF_WORD:
3148 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3149 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3150 }
3151 break;
3152 case DF_DOUBLE:
3153 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3154 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3155 }
3156 break;
3157 default:
3158 assert(0);
3159 }
3160
3161 check_msacsr_cause(env, GETPC());
3162
3163 msa_move_v(pwd, pwx);
3164 }
3165
3166 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3167 uint32_t ws)
3168 {
3169 wr_t wx, *pwx = &wx;
3170 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3171 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3172 uint32_t i;
3173
3174 clear_msacsr_cause(env);
3175
3176 switch (df) {
3177 case DF_WORD:
3178 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3179 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3180 }
3181 break;
3182 case DF_DOUBLE:
3183 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3184 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3185 }
3186 break;
3187 default:
3188 assert(0);
3189 }
3190
3191 check_msacsr_cause(env, GETPC());
3192
3193 msa_move_v(pwd, pwx);
3194 }
3195
3196 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3197 do { \
3198 float_status *status = &env->active_tc.msa_fp_status; \
3199 int c; \
3200 \
3201 set_float_exception_flags(0, status); \
3202 set_float_rounding_mode(float_round_down, status); \
3203 DEST = float ## BITS ## _ ## log2(ARG, status); \
3204 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3205 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3206 MSACSR_RM_MASK) >> MSACSR_RM], \
3207 status); \
3208 \
3209 set_float_exception_flags(get_float_exception_flags(status) & \
3210 (~float_flag_inexact), \
3211 status); \
3212 \
3213 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3214 \
3215 if (get_enabled_exceptions(env, c)) { \
3216 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3217 } \
3218 } while (0)
3219
3220 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3221 uint32_t ws)
3222 {
3223 wr_t wx, *pwx = &wx;
3224 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3225 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3226 uint32_t i;
3227
3228 clear_msacsr_cause(env);
3229
3230 switch (df) {
3231 case DF_WORD:
3232 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3233 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3234 }
3235 break;
3236 case DF_DOUBLE:
3237 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3238 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3239 }
3240 break;
3241 default:
3242 assert(0);
3243 }
3244
3245 check_msacsr_cause(env, GETPC());
3246
3247 msa_move_v(pwd, pwx);
3248 }
3249
3250 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3251 uint32_t ws)
3252 {
3253 wr_t wx, *pwx = &wx;
3254 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3255 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3256 uint32_t i;
3257
3258 clear_msacsr_cause(env);
3259
3260 switch (df) {
3261 case DF_WORD:
3262 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3263 /* Half precision floats come in two formats: standard
3264 IEEE and "ARM" format. The latter gains extra exponent
3265 range by omitting the NaN/Inf encodings. */
3266 flag ieee = 1;
3267
3268 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3269 }
3270 break;
3271 case DF_DOUBLE:
3272 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3273 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3274 }
3275 break;
3276 default:
3277 assert(0);
3278 }
3279
3280 check_msacsr_cause(env, GETPC());
3281 msa_move_v(pwd, pwx);
3282 }
3283
3284 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3285 uint32_t ws)
3286 {
3287 wr_t wx, *pwx = &wx;
3288 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3289 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3290 uint32_t i;
3291
3292 clear_msacsr_cause(env);
3293
3294 switch (df) {
3295 case DF_WORD:
3296 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3297 /* Half precision floats come in two formats: standard
3298 IEEE and "ARM" format. The latter gains extra exponent
3299 range by omitting the NaN/Inf encodings. */
3300 flag ieee = 1;
3301
3302 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3303 }
3304 break;
3305 case DF_DOUBLE:
3306 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3307 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3308 }
3309 break;
3310 default:
3311 assert(0);
3312 }
3313
3314 check_msacsr_cause(env, GETPC());
3315 msa_move_v(pwd, pwx);
3316 }
3317
3318 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3319 uint32_t ws)
3320 {
3321 wr_t wx, *pwx = &wx;
3322 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3323 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3324 uint32_t i;
3325
3326 switch (df) {
3327 case DF_WORD:
3328 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3329 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3330 }
3331 break;
3332 case DF_DOUBLE:
3333 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3334 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3335 }
3336 break;
3337 default:
3338 assert(0);
3339 }
3340
3341 msa_move_v(pwd, pwx);
3342 }
3343
3344 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3345 uint32_t ws)
3346 {
3347 wr_t wx, *pwx = &wx;
3348 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3349 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3350 uint32_t i;
3351
3352 switch (df) {
3353 case DF_WORD:
3354 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3355 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3356 }
3357 break;
3358 case DF_DOUBLE:
3359 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3360 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3361 }
3362 break;
3363 default:
3364 assert(0);
3365 }
3366
3367 msa_move_v(pwd, pwx);
3368 }
3369
3370 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3371 uint32_t ws)
3372 {
3373 wr_t wx, *pwx = &wx;
3374 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3375 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3376 uint32_t i;
3377
3378 clear_msacsr_cause(env);
3379
3380 switch (df) {
3381 case DF_WORD:
3382 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3383 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3384 }
3385 break;
3386 case DF_DOUBLE:
3387 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3388 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3389 }
3390 break;
3391 default:
3392 assert(0);
3393 }
3394
3395 check_msacsr_cause(env, GETPC());
3396
3397 msa_move_v(pwd, pwx);
3398 }
3399
3400 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3401 uint32_t ws)
3402 {
3403 wr_t wx, *pwx = &wx;
3404 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3405 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3406 uint32_t i;
3407
3408 clear_msacsr_cause(env);
3409
3410 switch (df) {
3411 case DF_WORD:
3412 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3413 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3414 }
3415 break;
3416 case DF_DOUBLE:
3417 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3418 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3419 }
3420 break;
3421 default:
3422 assert(0);
3423 }
3424
3425 check_msacsr_cause(env, GETPC());
3426
3427 msa_move_v(pwd, pwx);
3428 }
3429
3430 #define float32_from_int32 int32_to_float32
3431 #define float32_from_uint32 uint32_to_float32
3432
3433 #define float64_from_int64 int64_to_float64
3434 #define float64_from_uint64 uint64_to_float64
3435
3436 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3437 uint32_t ws)
3438 {
3439 wr_t wx, *pwx = &wx;
3440 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3441 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3442 uint32_t i;
3443
3444 clear_msacsr_cause(env);
3445
3446 switch (df) {
3447 case DF_WORD:
3448 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3449 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3450 }
3451 break;
3452 case DF_DOUBLE:
3453 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3454 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3455 }
3456 break;
3457 default:
3458 assert(0);
3459 }
3460
3461 check_msacsr_cause(env, GETPC());
3462
3463 msa_move_v(pwd, pwx);
3464 }
3465
3466 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3467 uint32_t ws)
3468 {
3469 wr_t wx, *pwx = &wx;
3470 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3471 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3472 uint32_t i;
3473
3474 clear_msacsr_cause(env);
3475
3476 switch (df) {
3477 case DF_WORD:
3478 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3479 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3480 }
3481 break;
3482 case DF_DOUBLE:
3483 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3484 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3485 }
3486 break;
3487 default:
3488 assert(0);
3489 }
3490
3491 check_msacsr_cause(env, GETPC());
3492
3493 msa_move_v(pwd, pwx);
3494 }
AR7 emulation for QEMU