2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * This source file covers the following FPGA images, for TrustZone cores:
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
22 * Links to the TRM for the board itself and to the various Application
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
27 * https://developer.arm.com/documentation/100112/latest/
28 * Application Note AN505:
29 * https://developer.arm.com/documentation/dai0505/latest/
30 * Application Note AN521:
31 * https://developer.arm.com/documentation/dai0521/latest/
32 * Application Note AN524:
33 * https://developer.arm.com/documentation/dai0524/latest/
34 * Application Note AN547:
35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
38 * (ARM ECM0601256) for the details of some of the device layout:
39 * https://developer.arm.com/documentation/ecm0601256/latest
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
41 * most of the device layout:
42 * https://developer.arm.com/documentation/101104/latest/
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
44 * https://developer.arm.com/documentation/101773/latest/
47 #include "qemu/osdep.h"
48 #include "qemu/units.h"
49 #include "qemu/cutils.h"
50 #include "qapi/error.h"
51 #include "qemu/error-report.h"
52 #include "hw/arm/boot.h"
53 #include "hw/arm/armv7m.h"
54 #include "hw/or-irq.h"
55 #include "hw/boards.h"
56 #include "exec/address-spaces.h"
57 #include "sysemu/sysemu.h"
58 #include "hw/misc/unimp.h"
59 #include "hw/char/cmsdk-apb-uart.h"
60 #include "hw/timer/cmsdk-apb-timer.h"
61 #include "hw/misc/mps2-scc.h"
62 #include "hw/misc/mps2-fpgaio.h"
63 #include "hw/misc/tz-mpc.h"
64 #include "hw/misc/tz-msc.h"
65 #include "hw/arm/armsse.h"
66 #include "hw/dma/pl080.h"
67 #include "hw/rtc/pl031.h"
68 #include "hw/ssi/pl022.h"
69 #include "hw/i2c/arm_sbcon_i2c.h"
70 #include "hw/net/lan9118.h"
72 #include "hw/core/split-irq.h"
73 #include "hw/qdev-clock.h"
74 #include "qom/object.h"
76 #define MPS2TZ_NUMIRQ_MAX 96
77 #define MPS2TZ_RAM_MAX 5
79 typedef enum MPS2TZFPGAType
{
87 * Define the layout of RAM in a board, including which parts are
89 * mrindex specifies the index into mms->ram[] to use for the backing RAM;
90 * -1 means "use the system RAM".
92 typedef struct RAMInfo
{
96 int mpc
; /* MPC number, -1 for "not behind an MPC" */
103 * IS_ALIAS: this RAM area is an alias to the upstream end of the
104 * MPC specified by its .mpc value
105 * IS_ROM: this RAM area is read-only
110 struct MPS2TZMachineClass
{
112 MPS2TZFPGAType fpga_type
;
114 uint32_t sysclk_frq
; /* Main SYSCLK frequency in Hz */
115 uint32_t apb_periph_frq
; /* APB peripheral frequency in Hz */
117 const uint32_t *oscclk
;
118 uint32_t fpgaio_num_leds
; /* Number of LEDs in FPGAIO LED0 register */
119 bool fpgaio_has_switches
; /* Does FPGAIO have SWITCH register? */
120 bool fpgaio_has_dbgctrl
; /* Does FPGAIO have DBGCTRL register? */
121 int numirq
; /* Number of external interrupts */
122 int uart_overflow_irq
; /* number of the combined UART overflow IRQ */
123 uint32_t init_svtor
; /* init-svtor setting for SSE */
124 const RAMInfo
*raminfo
;
125 const char *armsse_type
;
128 struct MPS2TZMachineState
{
132 MemoryRegion ram
[MPS2TZ_RAM_MAX
];
133 MemoryRegion eth_usb_container
;
140 ArmSbconI2CState i2c
[5];
141 UnimplementedDeviceState i2s_audio
;
142 UnimplementedDeviceState gpio
[4];
143 UnimplementedDeviceState gfx
;
144 UnimplementedDeviceState cldc
;
145 UnimplementedDeviceState usb
;
149 CMSDKAPBUART uart
[6];
150 SplitIRQ sec_resp_splitter
;
151 qemu_or_irq uart_irq_orgate
;
152 DeviceState
*lan9118
;
153 SplitIRQ cpu_irq_splitter
[MPS2TZ_NUMIRQ_MAX
];
158 #define TYPE_MPS2TZ_MACHINE "mps2tz"
159 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
160 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
161 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
162 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
164 OBJECT_DECLARE_TYPE(MPS2TZMachineState
, MPS2TZMachineClass
, MPS2TZ_MACHINE
)
166 /* Slow 32Khz S32KCLK frequency in Hz */
167 #define S32KCLK_FRQ (32 * 1000)
170 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
171 * emulation of that much guest RAM, so artificially make it smaller.
173 #if HOST_LONG_BITS == 32
174 #define MPS3_DDR_SIZE (1 * GiB)
176 #define MPS3_DDR_SIZE (2 * GiB)
179 static const uint32_t an505_oscclk
[] = {
185 static const uint32_t an524_oscclk
[] = {
194 static const RAMInfo an505_raminfo
[] = { {
213 .name
= "ssram-0-alias",
220 /* Use the largest bit of contiguous RAM as our "system memory" */
231 static const RAMInfo an524_raminfo
[] = { {
240 .size
= 32 * 4 * KiB
,
244 /* We don't model QSPI flash yet; for now expose it as simple ROM */
254 .size
= MPS3_DDR_SIZE
,
262 static const RAMInfo an547_raminfo
[] = { {
277 .size
= 4 * 128 * KiB
,
287 /* We don't model QSPI flash yet; for now expose it as simple ROM */
297 .size
= MPS3_DDR_SIZE
,
305 static const RAMInfo
*find_raminfo_for_mpc(MPS2TZMachineState
*mms
, int mpc
)
307 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
310 for (p
= mmc
->raminfo
; p
->name
; p
++) {
311 if (p
->mpc
== mpc
&& !(p
->flags
& IS_ALIAS
)) {
315 /* if raminfo array doesn't have an entry for each MPC this is a bug */
316 g_assert_not_reached();
319 static MemoryRegion
*mr_for_raminfo(MPS2TZMachineState
*mms
,
320 const RAMInfo
*raminfo
)
322 /* Return an initialized MemoryRegion for the RAMInfo. */
325 if (raminfo
->mrindex
< 0) {
326 /* Means this RAMInfo is for QEMU's "system memory" */
327 MachineState
*machine
= MACHINE(mms
);
328 assert(!(raminfo
->flags
& IS_ROM
));
332 assert(raminfo
->mrindex
< MPS2TZ_RAM_MAX
);
333 ram
= &mms
->ram
[raminfo
->mrindex
];
335 memory_region_init_ram(ram
, NULL
, raminfo
->name
,
336 raminfo
->size
, &error_fatal
);
337 if (raminfo
->flags
& IS_ROM
) {
338 memory_region_set_readonly(ram
, true);
343 /* Create an alias of an entire original MemoryRegion @orig
344 * located at @base in the memory map.
346 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
347 MemoryRegion
*orig
, hwaddr base
)
349 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
350 memory_region_size(orig
));
351 memory_region_add_subregion(get_system_memory(), base
, mr
);
354 static qemu_irq
get_sse_irq_in(MPS2TZMachineState
*mms
, int irqno
)
357 * Return a qemu_irq which will signal IRQ n to all CPUs in the
358 * SSE. The irqno should be as the CPU sees it, so the first
359 * external-to-the-SSE interrupt is 32.
361 MachineClass
*mc
= MACHINE_GET_CLASS(mms
);
362 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
364 assert(irqno
>= 32 && irqno
< (mmc
->numirq
+ 32));
367 * Convert from "CPU irq number" (as listed in the FPGA image
368 * documentation) to the SSE external-interrupt number.
372 if (mc
->max_cpus
> 1) {
373 return qdev_get_gpio_in(DEVICE(&mms
->cpu_irq_splitter
[irqno
]), 0);
375 return qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
), "EXP_IRQ", irqno
);
379 /* Most of the devices in the AN505 FPGA image sit behind
380 * Peripheral Protection Controllers. These data structures
381 * define the layout of which devices sit behind which PPCs.
382 * The devfn for each port is a function which creates, configures
383 * and initializes the device, returning the MemoryRegion which
384 * needs to be plugged into the downstream end of the PPC port.
386 typedef MemoryRegion
*MakeDevFn(MPS2TZMachineState
*mms
, void *opaque
,
387 const char *name
, hwaddr size
,
390 typedef struct PPCPortInfo
{
396 int irqs
[3]; /* currently no device needs more IRQ lines than this */
399 typedef struct PPCInfo
{
401 PPCPortInfo ports
[TZ_NUM_PORTS
];
404 static MemoryRegion
*make_unimp_dev(MPS2TZMachineState
*mms
,
406 const char *name
, hwaddr size
,
409 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
410 * and return a pointer to its MemoryRegion.
412 UnimplementedDeviceState
*uds
= opaque
;
414 object_initialize_child(OBJECT(mms
), name
, uds
, TYPE_UNIMPLEMENTED_DEVICE
);
415 qdev_prop_set_string(DEVICE(uds
), "name", name
);
416 qdev_prop_set_uint64(DEVICE(uds
), "size", size
);
417 sysbus_realize(SYS_BUS_DEVICE(uds
), &error_fatal
);
418 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds
), 0);
421 static MemoryRegion
*make_uart(MPS2TZMachineState
*mms
, void *opaque
,
422 const char *name
, hwaddr size
,
425 /* The irq[] array is tx, rx, combined, in that order */
426 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
427 CMSDKAPBUART
*uart
= opaque
;
428 int i
= uart
- &mms
->uart
[0];
430 DeviceState
*orgate_dev
= DEVICE(&mms
->uart_irq_orgate
);
432 object_initialize_child(OBJECT(mms
), name
, uart
, TYPE_CMSDK_APB_UART
);
433 qdev_prop_set_chr(DEVICE(uart
), "chardev", serial_hd(i
));
434 qdev_prop_set_uint32(DEVICE(uart
), "pclk-frq", mmc
->apb_periph_frq
);
435 sysbus_realize(SYS_BUS_DEVICE(uart
), &error_fatal
);
436 s
= SYS_BUS_DEVICE(uart
);
437 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
438 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
439 sysbus_connect_irq(s
, 2, qdev_get_gpio_in(orgate_dev
, i
* 2));
440 sysbus_connect_irq(s
, 3, qdev_get_gpio_in(orgate_dev
, i
* 2 + 1));
441 sysbus_connect_irq(s
, 4, get_sse_irq_in(mms
, irqs
[2]));
442 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart
), 0);
445 static MemoryRegion
*make_scc(MPS2TZMachineState
*mms
, void *opaque
,
446 const char *name
, hwaddr size
,
449 MPS2SCC
*scc
= opaque
;
451 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
454 object_initialize_child(OBJECT(mms
), "scc", scc
, TYPE_MPS2_SCC
);
455 sccdev
= DEVICE(scc
);
456 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
457 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
458 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
459 qdev_prop_set_uint32(sccdev
, "len-oscclk", mmc
->len_oscclk
);
460 for (i
= 0; i
< mmc
->len_oscclk
; i
++) {
461 g_autofree
char *propname
= g_strdup_printf("oscclk[%u]", i
);
462 qdev_prop_set_uint32(sccdev
, propname
, mmc
->oscclk
[i
]);
464 sysbus_realize(SYS_BUS_DEVICE(scc
), &error_fatal
);
465 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev
), 0);
468 static MemoryRegion
*make_fpgaio(MPS2TZMachineState
*mms
, void *opaque
,
469 const char *name
, hwaddr size
,
472 MPS2FPGAIO
*fpgaio
= opaque
;
473 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
475 object_initialize_child(OBJECT(mms
), "fpgaio", fpgaio
, TYPE_MPS2_FPGAIO
);
476 qdev_prop_set_uint32(DEVICE(fpgaio
), "num-leds", mmc
->fpgaio_num_leds
);
477 qdev_prop_set_bit(DEVICE(fpgaio
), "has-switches", mmc
->fpgaio_has_switches
);
478 qdev_prop_set_bit(DEVICE(fpgaio
), "has-dbgctrl", mmc
->fpgaio_has_dbgctrl
);
479 sysbus_realize(SYS_BUS_DEVICE(fpgaio
), &error_fatal
);
480 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio
), 0);
483 static MemoryRegion
*make_eth_dev(MPS2TZMachineState
*mms
, void *opaque
,
484 const char *name
, hwaddr size
,
488 NICInfo
*nd
= &nd_table
[0];
490 /* In hardware this is a LAN9220; the LAN9118 is software compatible
491 * except that it doesn't support the checksum-offload feature.
493 qemu_check_nic_model(nd
, "lan9118");
494 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
495 qdev_set_nic_properties(mms
->lan9118
, nd
);
497 s
= SYS_BUS_DEVICE(mms
->lan9118
);
498 sysbus_realize_and_unref(s
, &error_fatal
);
499 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
500 return sysbus_mmio_get_region(s
, 0);
503 static MemoryRegion
*make_eth_usb(MPS2TZMachineState
*mms
, void *opaque
,
504 const char *name
, hwaddr size
,
508 * The AN524 makes the ethernet and USB share a PPC port.
509 * irqs[] is the ethernet IRQ.
512 NICInfo
*nd
= &nd_table
[0];
514 memory_region_init(&mms
->eth_usb_container
, OBJECT(mms
),
515 "mps2-tz-eth-usb-container", 0x200000);
518 * In hardware this is a LAN9220; the LAN9118 is software compatible
519 * except that it doesn't support the checksum-offload feature.
521 qemu_check_nic_model(nd
, "lan9118");
522 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
523 qdev_set_nic_properties(mms
->lan9118
, nd
);
525 s
= SYS_BUS_DEVICE(mms
->lan9118
);
526 sysbus_realize_and_unref(s
, &error_fatal
);
527 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
529 memory_region_add_subregion(&mms
->eth_usb_container
,
530 0, sysbus_mmio_get_region(s
, 0));
532 /* The USB OTG controller is an ISP1763; we don't have a model of it. */
533 object_initialize_child(OBJECT(mms
), "usb-otg",
534 &mms
->usb
, TYPE_UNIMPLEMENTED_DEVICE
);
535 qdev_prop_set_string(DEVICE(&mms
->usb
), "name", "usb-otg");
536 qdev_prop_set_uint64(DEVICE(&mms
->usb
), "size", 0x100000);
537 s
= SYS_BUS_DEVICE(&mms
->usb
);
538 sysbus_realize(s
, &error_fatal
);
540 memory_region_add_subregion(&mms
->eth_usb_container
,
541 0x100000, sysbus_mmio_get_region(s
, 0));
543 return &mms
->eth_usb_container
;
546 static MemoryRegion
*make_mpc(MPS2TZMachineState
*mms
, void *opaque
,
547 const char *name
, hwaddr size
,
551 int i
= mpc
- &mms
->mpc
[0];
552 MemoryRegion
*upstream
;
553 const RAMInfo
*raminfo
= find_raminfo_for_mpc(mms
, i
);
554 MemoryRegion
*ram
= mr_for_raminfo(mms
, raminfo
);
556 object_initialize_child(OBJECT(mms
), name
, mpc
, TYPE_TZ_MPC
);
557 object_property_set_link(OBJECT(mpc
), "downstream", OBJECT(ram
),
559 sysbus_realize(SYS_BUS_DEVICE(mpc
), &error_fatal
);
560 /* Map the upstream end of the MPC into system memory */
561 upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 1);
562 memory_region_add_subregion(get_system_memory(), raminfo
->base
, upstream
);
563 /* and connect its interrupt to the IoTKit */
564 qdev_connect_gpio_out_named(DEVICE(mpc
), "irq", 0,
565 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
566 "mpcexp_status", i
));
568 /* Return the register interface MR for our caller to map behind the PPC */
569 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 0);
572 static MemoryRegion
*make_dma(MPS2TZMachineState
*mms
, void *opaque
,
573 const char *name
, hwaddr size
,
576 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */
577 PL080State
*dma
= opaque
;
578 int i
= dma
- &mms
->dma
[0];
580 char *mscname
= g_strdup_printf("%s-msc", name
);
581 TZMSC
*msc
= &mms
->msc
[i
];
582 DeviceState
*iotkitdev
= DEVICE(&mms
->iotkit
);
583 MemoryRegion
*msc_upstream
;
584 MemoryRegion
*msc_downstream
;
587 * Each DMA device is a PL081 whose transaction master interface
588 * is guarded by a Master Security Controller. The downstream end of
589 * the MSC connects to the IoTKit AHB Slave Expansion port, so the
590 * DMA devices can see all devices and memory that the CPU does.
592 object_initialize_child(OBJECT(mms
), mscname
, msc
, TYPE_TZ_MSC
);
593 msc_downstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms
->iotkit
), 0);
594 object_property_set_link(OBJECT(msc
), "downstream",
595 OBJECT(msc_downstream
), &error_fatal
);
596 object_property_set_link(OBJECT(msc
), "idau", OBJECT(mms
), &error_fatal
);
597 sysbus_realize(SYS_BUS_DEVICE(msc
), &error_fatal
);
599 qdev_connect_gpio_out_named(DEVICE(msc
), "irq", 0,
600 qdev_get_gpio_in_named(iotkitdev
,
601 "mscexp_status", i
));
602 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_clear", i
,
603 qdev_get_gpio_in_named(DEVICE(msc
),
605 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_ns", i
,
606 qdev_get_gpio_in_named(DEVICE(msc
),
608 qdev_connect_gpio_out(DEVICE(&mms
->sec_resp_splitter
),
609 ARRAY_SIZE(mms
->ppc
) + i
,
610 qdev_get_gpio_in_named(DEVICE(msc
),
612 msc_upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(msc
), 0);
614 object_initialize_child(OBJECT(mms
), name
, dma
, TYPE_PL081
);
615 object_property_set_link(OBJECT(dma
), "downstream", OBJECT(msc_upstream
),
617 sysbus_realize(SYS_BUS_DEVICE(dma
), &error_fatal
);
619 s
= SYS_BUS_DEVICE(dma
);
620 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
621 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
622 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
623 sysbus_connect_irq(s
, 2, get_sse_irq_in(mms
, irqs
[2]));
626 return sysbus_mmio_get_region(s
, 0);
629 static MemoryRegion
*make_spi(MPS2TZMachineState
*mms
, void *opaque
,
630 const char *name
, hwaddr size
,
634 * The AN505 has five PL022 SPI controllers.
635 * One of these should have the LCD controller behind it; the others
636 * are connected only to the FPGA's "general purpose SPI connector"
637 * or "shield" expansion connectors.
638 * Note that if we do implement devices behind SPI, the chip select
639 * lines are set via the "MISC" register in the MPS2 FPGAIO device.
641 PL022State
*spi
= opaque
;
644 object_initialize_child(OBJECT(mms
), name
, spi
, TYPE_PL022
);
645 sysbus_realize(SYS_BUS_DEVICE(spi
), &error_fatal
);
646 s
= SYS_BUS_DEVICE(spi
);
647 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
648 return sysbus_mmio_get_region(s
, 0);
651 static MemoryRegion
*make_i2c(MPS2TZMachineState
*mms
, void *opaque
,
652 const char *name
, hwaddr size
,
655 ArmSbconI2CState
*i2c
= opaque
;
658 object_initialize_child(OBJECT(mms
), name
, i2c
, TYPE_ARM_SBCON_I2C
);
659 s
= SYS_BUS_DEVICE(i2c
);
660 sysbus_realize(s
, &error_fatal
);
661 return sysbus_mmio_get_region(s
, 0);
664 static MemoryRegion
*make_rtc(MPS2TZMachineState
*mms
, void *opaque
,
665 const char *name
, hwaddr size
,
668 PL031State
*pl031
= opaque
;
671 object_initialize_child(OBJECT(mms
), name
, pl031
, TYPE_PL031
);
672 s
= SYS_BUS_DEVICE(pl031
);
673 sysbus_realize(s
, &error_fatal
);
675 * The board docs don't give an IRQ number for the PL031, so
676 * presumably it is not connected.
678 return sysbus_mmio_get_region(s
, 0);
681 static void create_non_mpc_ram(MPS2TZMachineState
*mms
)
684 * Handle the RAMs which are either not behind MPCs or which are
685 * aliases to another MPC.
688 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
690 for (p
= mmc
->raminfo
; p
->name
; p
++) {
691 if (p
->flags
& IS_ALIAS
) {
692 SysBusDevice
*mpc_sbd
= SYS_BUS_DEVICE(&mms
->mpc
[p
->mpc
]);
693 MemoryRegion
*upstream
= sysbus_mmio_get_region(mpc_sbd
, 1);
694 make_ram_alias(&mms
->ram
[p
->mrindex
], p
->name
, upstream
, p
->base
);
695 } else if (p
->mpc
== -1) {
696 /* RAM not behind an MPC */
697 MemoryRegion
*mr
= mr_for_raminfo(mms
, p
);
698 memory_region_add_subregion(get_system_memory(), p
->base
, mr
);
703 static uint32_t boot_ram_size(MPS2TZMachineState
*mms
)
705 /* Return the size of the RAM block at guest address zero */
707 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
709 for (p
= mmc
->raminfo
; p
->name
; p
++) {
714 g_assert_not_reached();
717 static void mps2tz_common_init(MachineState
*machine
)
719 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(machine
);
720 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
721 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
722 MemoryRegion
*system_memory
= get_system_memory();
723 DeviceState
*iotkitdev
;
724 DeviceState
*dev_splitter
;
729 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
730 error_report("This board can only be used with CPU %s",
731 mc
->default_cpu_type
);
735 if (machine
->ram_size
!= mc
->default_ram_size
) {
736 char *sz
= size_to_str(mc
->default_ram_size
);
737 error_report("Invalid RAM size, should be %s", sz
);
742 /* These clocks don't need migration because they are fixed-frequency */
743 mms
->sysclk
= clock_new(OBJECT(machine
), "SYSCLK");
744 clock_set_hz(mms
->sysclk
, mmc
->sysclk_frq
);
745 mms
->s32kclk
= clock_new(OBJECT(machine
), "S32KCLK");
746 clock_set_hz(mms
->s32kclk
, S32KCLK_FRQ
);
748 object_initialize_child(OBJECT(machine
), TYPE_IOTKIT
, &mms
->iotkit
,
750 iotkitdev
= DEVICE(&mms
->iotkit
);
751 object_property_set_link(OBJECT(&mms
->iotkit
), "memory",
752 OBJECT(system_memory
), &error_abort
);
753 qdev_prop_set_uint32(iotkitdev
, "EXP_NUMIRQ", mmc
->numirq
);
754 qdev_prop_set_uint32(iotkitdev
, "init-svtor", mmc
->init_svtor
);
755 qdev_connect_clock_in(iotkitdev
, "MAINCLK", mms
->sysclk
);
756 qdev_connect_clock_in(iotkitdev
, "S32KCLK", mms
->s32kclk
);
757 sysbus_realize(SYS_BUS_DEVICE(&mms
->iotkit
), &error_fatal
);
760 * If this board has more than one CPU, then we need to create splitters
761 * to feed the IRQ inputs for each CPU in the SSE from each device in the
762 * board. If there is only one CPU, we can just wire the device IRQ
763 * directly to the SSE's IRQ input.
765 assert(mmc
->numirq
<= MPS2TZ_NUMIRQ_MAX
);
766 if (mc
->max_cpus
> 1) {
767 for (i
= 0; i
< mmc
->numirq
; i
++) {
768 char *name
= g_strdup_printf("mps2-irq-splitter%d", i
);
769 SplitIRQ
*splitter
= &mms
->cpu_irq_splitter
[i
];
771 object_initialize_child_with_props(OBJECT(machine
), name
,
772 splitter
, sizeof(*splitter
),
773 TYPE_SPLIT_IRQ
, &error_fatal
,
777 object_property_set_int(OBJECT(splitter
), "num-lines", 2,
779 qdev_realize(DEVICE(splitter
), NULL
, &error_fatal
);
780 qdev_connect_gpio_out(DEVICE(splitter
), 0,
781 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
783 qdev_connect_gpio_out(DEVICE(splitter
), 1,
784 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
789 /* The sec_resp_cfg output from the IoTKit must be split into multiple
790 * lines, one for each of the PPCs we create here, plus one per MSC.
792 object_initialize_child(OBJECT(machine
), "sec-resp-splitter",
793 &mms
->sec_resp_splitter
, TYPE_SPLIT_IRQ
);
794 object_property_set_int(OBJECT(&mms
->sec_resp_splitter
), "num-lines",
795 ARRAY_SIZE(mms
->ppc
) + ARRAY_SIZE(mms
->msc
),
797 qdev_realize(DEVICE(&mms
->sec_resp_splitter
), NULL
, &error_fatal
);
798 dev_splitter
= DEVICE(&mms
->sec_resp_splitter
);
799 qdev_connect_gpio_out_named(iotkitdev
, "sec_resp_cfg", 0,
800 qdev_get_gpio_in(dev_splitter
, 0));
803 * The IoTKit sets up much of the memory layout, including
804 * the aliases between secure and non-secure regions in the
805 * address space, and also most of the devices in the system.
806 * The FPGA itself contains various RAMs and some additional devices.
807 * The FPGA images have an odd combination of different RAMs,
808 * because in hardware they are different implementations and
809 * connected to different buses, giving varying performance/size
810 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
811 * call the largest lump our "system memory".
815 * The overflow IRQs for all UARTs are ORed together.
816 * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
817 * Create the OR gate for this: it has one input for the TX overflow
818 * and one for the RX overflow for each UART we might have.
819 * (If the board has fewer than the maximum possible number of UARTs
820 * those inputs are never wired up and are treated as always-zero.)
822 object_initialize_child(OBJECT(mms
), "uart-irq-orgate",
823 &mms
->uart_irq_orgate
, TYPE_OR_IRQ
);
824 object_property_set_int(OBJECT(&mms
->uart_irq_orgate
), "num-lines",
825 2 * ARRAY_SIZE(mms
->uart
),
827 qdev_realize(DEVICE(&mms
->uart_irq_orgate
), NULL
, &error_fatal
);
828 qdev_connect_gpio_out(DEVICE(&mms
->uart_irq_orgate
), 0,
829 get_sse_irq_in(mms
, mmc
->uart_overflow_irq
));
831 /* Most of the devices in the FPGA are behind Peripheral Protection
832 * Controllers. The required order for initializing things is:
833 * + initialize the PPC
834 * + initialize, configure and realize downstream devices
835 * + connect downstream device MemoryRegions to the PPC
837 * + map the PPC's MemoryRegions to the places in the address map
838 * where the downstream devices should appear
839 * + wire up the PPC's control lines to the IoTKit object
842 const PPCInfo an505_ppcs
[] = { {
843 .name
= "apb_ppcexp0",
845 { "ssram-0-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
846 { "ssram-1-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
847 { "ssram-2-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
850 .name
= "apb_ppcexp1",
852 { "spi0", make_spi
, &mms
->spi
[0], 0x40205000, 0x1000, { 51 } },
853 { "spi1", make_spi
, &mms
->spi
[1], 0x40206000, 0x1000, { 52 } },
854 { "spi2", make_spi
, &mms
->spi
[2], 0x40209000, 0x1000, { 53 } },
855 { "spi3", make_spi
, &mms
->spi
[3], 0x4020a000, 0x1000, { 54 } },
856 { "spi4", make_spi
, &mms
->spi
[4], 0x4020b000, 0x1000, { 55 } },
857 { "uart0", make_uart
, &mms
->uart
[0], 0x40200000, 0x1000, { 32, 33, 42 } },
858 { "uart1", make_uart
, &mms
->uart
[1], 0x40201000, 0x1000, { 34, 35, 43 } },
859 { "uart2", make_uart
, &mms
->uart
[2], 0x40202000, 0x1000, { 36, 37, 44 } },
860 { "uart3", make_uart
, &mms
->uart
[3], 0x40203000, 0x1000, { 38, 39, 45 } },
861 { "uart4", make_uart
, &mms
->uart
[4], 0x40204000, 0x1000, { 40, 41, 46 } },
862 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x40207000, 0x1000 },
863 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x40208000, 0x1000 },
864 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x4020c000, 0x1000 },
865 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x4020d000, 0x1000 },
868 .name
= "apb_ppcexp2",
870 { "scc", make_scc
, &mms
->scc
, 0x40300000, 0x1000 },
871 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
872 0x40301000, 0x1000 },
873 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x40302000, 0x1000 },
876 .name
= "ahb_ppcexp0",
878 { "gfx", make_unimp_dev
, &mms
->gfx
, 0x41000000, 0x140000 },
879 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x40100000, 0x1000 },
880 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x40101000, 0x1000 },
881 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x40102000, 0x1000 },
882 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x40103000, 0x1000 },
883 { "eth", make_eth_dev
, NULL
, 0x42000000, 0x100000, { 48 } },
886 .name
= "ahb_ppcexp1",
888 { "dma0", make_dma
, &mms
->dma
[0], 0x40110000, 0x1000, { 58, 56, 57 } },
889 { "dma1", make_dma
, &mms
->dma
[1], 0x40111000, 0x1000, { 61, 59, 60 } },
890 { "dma2", make_dma
, &mms
->dma
[2], 0x40112000, 0x1000, { 64, 62, 63 } },
891 { "dma3", make_dma
, &mms
->dma
[3], 0x40113000, 0x1000, { 67, 65, 66 } },
896 const PPCInfo an524_ppcs
[] = { {
897 .name
= "apb_ppcexp0",
899 { "bram-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
900 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
901 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
904 .name
= "apb_ppcexp1",
906 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x41200000, 0x1000 },
907 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x41201000, 0x1000 },
908 { "spi0", make_spi
, &mms
->spi
[0], 0x41202000, 0x1000, { 52 } },
909 { "spi1", make_spi
, &mms
->spi
[1], 0x41203000, 0x1000, { 53 } },
910 { "spi2", make_spi
, &mms
->spi
[2], 0x41204000, 0x1000, { 54 } },
911 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x41205000, 0x1000 },
912 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x41206000, 0x1000 },
913 { /* port 7 reserved */ },
914 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x41208000, 0x1000 },
917 .name
= "apb_ppcexp2",
919 { "scc", make_scc
, &mms
->scc
, 0x41300000, 0x1000 },
920 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
921 0x41301000, 0x1000 },
922 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x41302000, 0x1000 },
923 { "uart0", make_uart
, &mms
->uart
[0], 0x41303000, 0x1000, { 32, 33, 42 } },
924 { "uart1", make_uart
, &mms
->uart
[1], 0x41304000, 0x1000, { 34, 35, 43 } },
925 { "uart2", make_uart
, &mms
->uart
[2], 0x41305000, 0x1000, { 36, 37, 44 } },
926 { "uart3", make_uart
, &mms
->uart
[3], 0x41306000, 0x1000, { 38, 39, 45 } },
927 { "uart4", make_uart
, &mms
->uart
[4], 0x41307000, 0x1000, { 40, 41, 46 } },
928 { "uart5", make_uart
, &mms
->uart
[5], 0x41308000, 0x1000, { 124, 125, 126 } },
930 { /* port 9 reserved */ },
931 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4130a000, 0x1000 },
932 { "rtc", make_rtc
, &mms
->rtc
, 0x4130b000, 0x1000 },
935 .name
= "ahb_ppcexp0",
937 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
938 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
939 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
940 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
941 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 48 } },
946 const PPCInfo an547_ppcs
[] = { {
947 .name
= "apb_ppcexp0",
949 { "ssram-mpc", make_mpc
, &mms
->mpc
[0], 0x57000000, 0x1000 },
950 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x57001000, 0x1000 },
951 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x57002000, 0x1000 },
954 .name
= "apb_ppcexp1",
956 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x49200000, 0x1000 },
957 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x49201000, 0x1000 },
958 { "spi0", make_spi
, &mms
->spi
[0], 0x49202000, 0x1000, { 53 } },
959 { "spi1", make_spi
, &mms
->spi
[1], 0x49203000, 0x1000, { 54 } },
960 { "spi2", make_spi
, &mms
->spi
[2], 0x49204000, 0x1000, { 55 } },
961 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x49205000, 0x1000 },
962 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x49206000, 0x1000 },
963 { /* port 7 reserved */ },
964 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x49208000, 0x1000 },
967 .name
= "apb_ppcexp2",
969 { "scc", make_scc
, &mms
->scc
, 0x49300000, 0x1000 },
970 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
, 0x49301000, 0x1000 },
971 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x49302000, 0x1000 },
972 { "uart0", make_uart
, &mms
->uart
[0], 0x49303000, 0x1000, { 33, 34, 43 } },
973 { "uart1", make_uart
, &mms
->uart
[1], 0x49304000, 0x1000, { 35, 36, 44 } },
974 { "uart2", make_uart
, &mms
->uart
[2], 0x49305000, 0x1000, { 37, 38, 45 } },
975 { "uart3", make_uart
, &mms
->uart
[3], 0x49306000, 0x1000, { 39, 40, 46 } },
976 { "uart4", make_uart
, &mms
->uart
[4], 0x49307000, 0x1000, { 41, 42, 47 } },
977 { "uart5", make_uart
, &mms
->uart
[5], 0x49308000, 0x1000, { 125, 126, 127 } },
979 { /* port 9 reserved */ },
980 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4930a000, 0x1000 },
981 { "rtc", make_rtc
, &mms
->rtc
, 0x4930b000, 0x1000 },
984 .name
= "ahb_ppcexp0",
986 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
987 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
988 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
989 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
990 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 49 } },
995 switch (mmc
->fpga_type
) {
999 num_ppcs
= ARRAY_SIZE(an505_ppcs
);
1003 num_ppcs
= ARRAY_SIZE(an524_ppcs
);
1007 num_ppcs
= ARRAY_SIZE(an547_ppcs
);
1010 g_assert_not_reached();
1013 for (i
= 0; i
< num_ppcs
; i
++) {
1014 const PPCInfo
*ppcinfo
= &ppcs
[i
];
1015 TZPPC
*ppc
= &mms
->ppc
[i
];
1016 DeviceState
*ppcdev
;
1020 object_initialize_child(OBJECT(machine
), ppcinfo
->name
, ppc
,
1022 ppcdev
= DEVICE(ppc
);
1024 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
1025 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
1029 if (!pinfo
->devfn
) {
1033 mr
= pinfo
->devfn(mms
, pinfo
->opaque
, pinfo
->name
, pinfo
->size
,
1035 portname
= g_strdup_printf("port[%d]", port
);
1036 object_property_set_link(OBJECT(ppc
), portname
, OBJECT(mr
),
1041 sysbus_realize(SYS_BUS_DEVICE(ppc
), &error_fatal
);
1043 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
1044 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
1046 if (!pinfo
->devfn
) {
1049 sysbus_mmio_map(SYS_BUS_DEVICE(ppc
), port
, pinfo
->addr
);
1051 gpioname
= g_strdup_printf("%s_nonsec", ppcinfo
->name
);
1052 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
1053 qdev_get_gpio_in_named(ppcdev
,
1057 gpioname
= g_strdup_printf("%s_ap", ppcinfo
->name
);
1058 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
1059 qdev_get_gpio_in_named(ppcdev
,
1064 gpioname
= g_strdup_printf("%s_irq_enable", ppcinfo
->name
);
1065 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
1066 qdev_get_gpio_in_named(ppcdev
,
1069 gpioname
= g_strdup_printf("%s_irq_clear", ppcinfo
->name
);
1070 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
1071 qdev_get_gpio_in_named(ppcdev
,
1074 gpioname
= g_strdup_printf("%s_irq_status", ppcinfo
->name
);
1075 qdev_connect_gpio_out_named(ppcdev
, "irq", 0,
1076 qdev_get_gpio_in_named(iotkitdev
,
1080 qdev_connect_gpio_out(dev_splitter
, i
,
1081 qdev_get_gpio_in_named(ppcdev
,
1082 "cfg_sec_resp", 0));
1085 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
1087 if (mmc
->fpga_type
== FPGA_AN547
) {
1088 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000);
1089 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000);
1092 create_non_mpc_ram(mms
);
1094 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
1095 boot_ram_size(mms
));
1098 static void mps2_tz_idau_check(IDAUInterface
*ii
, uint32_t address
,
1099 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1102 * The MPS2 TZ FPGA images have IDAUs in them which are connected to
1103 * the Master Security Controllers. Thes have the same logic as
1104 * is used by the IoTKit for the IDAU connected to the CPU, except
1105 * that MSCs don't care about the NSC attribute.
1107 int region
= extract32(address
, 28, 4);
1109 *ns
= !(region
& 1);
1111 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1112 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1116 static void mps2tz_class_init(ObjectClass
*oc
, void *data
)
1118 MachineClass
*mc
= MACHINE_CLASS(oc
);
1119 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(oc
);
1121 mc
->init
= mps2tz_common_init
;
1122 iic
->check
= mps2_tz_idau_check
;
1125 static void mps2tz_set_default_ram_info(MPS2TZMachineClass
*mmc
)
1128 * Set mc->default_ram_size and default_ram_id from the
1129 * information in mmc->raminfo.
1131 MachineClass
*mc
= MACHINE_CLASS(mmc
);
1134 for (p
= mmc
->raminfo
; p
->name
; p
++) {
1135 if (p
->mrindex
< 0) {
1136 /* Found the entry for "system memory" */
1137 mc
->default_ram_size
= p
->size
;
1138 mc
->default_ram_id
= p
->name
;
1142 g_assert_not_reached();
1145 static void mps2tz_an505_class_init(ObjectClass
*oc
, void *data
)
1147 MachineClass
*mc
= MACHINE_CLASS(oc
);
1148 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1150 mc
->desc
= "ARM MPS2 with AN505 FPGA image for Cortex-M33";
1151 mc
->default_cpus
= 1;
1152 mc
->min_cpus
= mc
->default_cpus
;
1153 mc
->max_cpus
= mc
->default_cpus
;
1154 mmc
->fpga_type
= FPGA_AN505
;
1155 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1156 mmc
->scc_id
= 0x41045050;
1157 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1158 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1159 mmc
->oscclk
= an505_oscclk
;
1160 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1161 mmc
->fpgaio_num_leds
= 2;
1162 mmc
->fpgaio_has_switches
= false;
1163 mmc
->fpgaio_has_dbgctrl
= false;
1165 mmc
->uart_overflow_irq
= 47;
1166 mmc
->init_svtor
= 0x10000000;
1167 mmc
->raminfo
= an505_raminfo
;
1168 mmc
->armsse_type
= TYPE_IOTKIT
;
1169 mps2tz_set_default_ram_info(mmc
);
1172 static void mps2tz_an521_class_init(ObjectClass
*oc
, void *data
)
1174 MachineClass
*mc
= MACHINE_CLASS(oc
);
1175 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1177 mc
->desc
= "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
1178 mc
->default_cpus
= 2;
1179 mc
->min_cpus
= mc
->default_cpus
;
1180 mc
->max_cpus
= mc
->default_cpus
;
1181 mmc
->fpga_type
= FPGA_AN521
;
1182 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1183 mmc
->scc_id
= 0x41045210;
1184 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1185 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1186 mmc
->oscclk
= an505_oscclk
; /* AN521 is the same as AN505 here */
1187 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1188 mmc
->fpgaio_num_leds
= 2;
1189 mmc
->fpgaio_has_switches
= false;
1190 mmc
->fpgaio_has_dbgctrl
= false;
1192 mmc
->uart_overflow_irq
= 47;
1193 mmc
->init_svtor
= 0x10000000;
1194 mmc
->raminfo
= an505_raminfo
; /* AN521 is the same as AN505 here */
1195 mmc
->armsse_type
= TYPE_SSE200
;
1196 mps2tz_set_default_ram_info(mmc
);
1199 static void mps3tz_an524_class_init(ObjectClass
*oc
, void *data
)
1201 MachineClass
*mc
= MACHINE_CLASS(oc
);
1202 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1204 mc
->desc
= "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
1205 mc
->default_cpus
= 2;
1206 mc
->min_cpus
= mc
->default_cpus
;
1207 mc
->max_cpus
= mc
->default_cpus
;
1208 mmc
->fpga_type
= FPGA_AN524
;
1209 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1210 mmc
->scc_id
= 0x41045240;
1211 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1212 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1213 mmc
->oscclk
= an524_oscclk
;
1214 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1215 mmc
->fpgaio_num_leds
= 10;
1216 mmc
->fpgaio_has_switches
= true;
1217 mmc
->fpgaio_has_dbgctrl
= false;
1219 mmc
->uart_overflow_irq
= 47;
1220 mmc
->init_svtor
= 0x10000000;
1221 mmc
->raminfo
= an524_raminfo
;
1222 mmc
->armsse_type
= TYPE_SSE200
;
1223 mps2tz_set_default_ram_info(mmc
);
1226 static void mps3tz_an547_class_init(ObjectClass
*oc
, void *data
)
1228 MachineClass
*mc
= MACHINE_CLASS(oc
);
1229 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1231 mc
->desc
= "ARM MPS3 with AN547 FPGA image for Cortex-M55";
1232 mc
->default_cpus
= 1;
1233 mc
->min_cpus
= mc
->default_cpus
;
1234 mc
->max_cpus
= mc
->default_cpus
;
1235 mmc
->fpga_type
= FPGA_AN547
;
1236 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m55");
1237 mmc
->scc_id
= 0x41055470;
1238 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1239 mmc
->apb_periph_frq
= 25 * 1000 * 1000; /* 25MHz */
1240 mmc
->oscclk
= an524_oscclk
; /* same as AN524 */
1241 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1242 mmc
->fpgaio_num_leds
= 10;
1243 mmc
->fpgaio_has_switches
= true;
1244 mmc
->fpgaio_has_dbgctrl
= true;
1246 mmc
->uart_overflow_irq
= 48;
1247 mmc
->init_svtor
= 0x00000000;
1248 mmc
->raminfo
= an547_raminfo
;
1249 mmc
->armsse_type
= TYPE_SSE300
;
1250 mps2tz_set_default_ram_info(mmc
);
1253 static const TypeInfo mps2tz_info
= {
1254 .name
= TYPE_MPS2TZ_MACHINE
,
1255 .parent
= TYPE_MACHINE
,
1257 .instance_size
= sizeof(MPS2TZMachineState
),
1258 .class_size
= sizeof(MPS2TZMachineClass
),
1259 .class_init
= mps2tz_class_init
,
1260 .interfaces
= (InterfaceInfo
[]) {
1261 { TYPE_IDAU_INTERFACE
},
1266 static const TypeInfo mps2tz_an505_info
= {
1267 .name
= TYPE_MPS2TZ_AN505_MACHINE
,
1268 .parent
= TYPE_MPS2TZ_MACHINE
,
1269 .class_init
= mps2tz_an505_class_init
,
1272 static const TypeInfo mps2tz_an521_info
= {
1273 .name
= TYPE_MPS2TZ_AN521_MACHINE
,
1274 .parent
= TYPE_MPS2TZ_MACHINE
,
1275 .class_init
= mps2tz_an521_class_init
,
1278 static const TypeInfo mps3tz_an524_info
= {
1279 .name
= TYPE_MPS3TZ_AN524_MACHINE
,
1280 .parent
= TYPE_MPS2TZ_MACHINE
,
1281 .class_init
= mps3tz_an524_class_init
,
1284 static const TypeInfo mps3tz_an547_info
= {
1285 .name
= TYPE_MPS3TZ_AN547_MACHINE
,
1286 .parent
= TYPE_MPS2TZ_MACHINE
,
1287 .class_init
= mps3tz_an547_class_init
,
1290 static void mps2tz_machine_init(void)
1292 type_register_static(&mps2tz_info
);
1293 type_register_static(&mps2tz_an505_info
);
1294 type_register_static(&mps2tz_an521_info
);
1295 type_register_static(&mps3tz_an524_info
);
1296 type_register_static(&mps3tz_an547_info
);
1299 type_init(mps2tz_machine_init
);