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block: Use BDRV_REQUEST_MAX_BYTES instead of BDRV_REQUEST_MAX_SECTORS
[qemu/ar7.git] / hw / sparc / sun4m.c
blob07d126aea820bd44e35a252cba757490a02441ff
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/sysbus.h"
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "hw/sparc/sun4m_iommu.h"
33 #include "hw/timer/m48t59.h"
34 #include "hw/sparc/sparc32_dma.h"
35 #include "hw/block/fdc.h"
36 #include "sysemu/sysemu.h"
37 #include "net/net.h"
38 #include "hw/boards.h"
39 #include "hw/scsi/esp.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "trace.h"
48
49 /*
50 * Sun4m architecture was used in the following machines:
51 *
52 * SPARCserver 6xxMP/xx
53 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
54 * SPARCclassic X (4/10)
55 * SPARCstation LX/ZX (4/30)
56 * SPARCstation Voyager
57 * SPARCstation 10/xx, SPARCserver 10/xx
58 * SPARCstation 5, SPARCserver 5
59 * SPARCstation 20/xx, SPARCserver 20
60 * SPARCstation 4
61 *
62 * See for example: http://www.sunhelp.org/faq/sunref1.html
63 */
64
65 #define KERNEL_LOAD_ADDR 0x00004000
66 #define CMDLINE_ADDR 0x007ff000
67 #define INITRD_LOAD_ADDR 0x00800000
68 #define PROM_SIZE_MAX (1 * MiB)
69 #define PROM_VADDR 0xffd00000
70 #define PROM_FILENAME "openbios-sparc32"
71 #define CFG_ADDR 0xd00000510ULL
72 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
73 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
74 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
75
76 #define MAX_CPUS 16
77 #define MAX_PILS 16
78 #define MAX_VSIMMS 4
79
80 #define ESCC_CLOCK 4915200
81
82 struct sun4m_hwdef {
83 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
84 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
85 hwaddr serial_base, fd_base;
86 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
87 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
88 hwaddr bpp_base, dbri_base, sx_base;
89 struct {
90 hwaddr reg_base, vram_base;
91 } vsimm[MAX_VSIMMS];
92 hwaddr ecc_base;
93 uint64_t max_mem;
94 uint32_t ecc_version;
95 uint32_t iommu_version;
96 uint16_t machine_id;
97 uint8_t nvram_machine_id;
98 };
99
100 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
101 Error **errp)
102 {
103 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
104 }
105
106 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
107 const char *cmdline, const char *boot_devices,
108 ram_addr_t RAM_size, uint32_t kernel_size,
109 int width, int height, int depth,
110 int nvram_machine_id, const char *arch)
111 {
112 unsigned int i;
113 int sysp_end;
114 uint8_t image[0x1ff0];
115 NvramClass *k = NVRAM_GET_CLASS(nvram);
116
117 memset(image, '\0', sizeof(image));
118
119 /* OpenBIOS nvram variables partition */
120 sysp_end = chrp_nvram_create_system_partition(image, 0);
121
122 /* Free space partition */
123 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
124
125 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
126 nvram_machine_id);
127
128 for (i = 0; i < sizeof(image); i++) {
129 (k->write)(nvram, i, image[i]);
130 }
131 }
132
133 void cpu_check_irqs(CPUSPARCState *env)
134 {
135 CPUState *cs;
136
137 /* We should be holding the BQL before we mess with IRQs */
138 g_assert(qemu_mutex_iothread_locked());
139
140 if (env->pil_in && (env->interrupt_index == 0 ||
141 (env->interrupt_index & ~15) == TT_EXTINT)) {
142 unsigned int i;
143
144 for (i = 15; i > 0; i--) {
145 if (env->pil_in & (1 << i)) {
146 int old_interrupt = env->interrupt_index;
147
148 env->interrupt_index = TT_EXTINT | i;
149 if (old_interrupt != env->interrupt_index) {
150 cs = CPU(sparc_env_get_cpu(env));
151 trace_sun4m_cpu_interrupt(i);
152 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
153 }
154 break;
155 }
156 }
157 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
158 cs = CPU(sparc_env_get_cpu(env));
159 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
160 env->interrupt_index = 0;
161 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
162 }
163 }
164
165 static void cpu_kick_irq(SPARCCPU *cpu)
166 {
167 CPUSPARCState *env = &cpu->env;
168 CPUState *cs = CPU(cpu);
169
170 cs->halted = 0;
171 cpu_check_irqs(env);
172 qemu_cpu_kick(cs);
173 }
174
175 static void cpu_set_irq(void *opaque, int irq, int level)
176 {
177 SPARCCPU *cpu = opaque;
178 CPUSPARCState *env = &cpu->env;
179
180 if (level) {
181 trace_sun4m_cpu_set_irq_raise(irq);
182 env->pil_in |= 1 << irq;
183 cpu_kick_irq(cpu);
184 } else {
185 trace_sun4m_cpu_set_irq_lower(irq);
186 env->pil_in &= ~(1 << irq);
187 cpu_check_irqs(env);
188 }
189 }
190
191 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
192 {
193 }
194
195 static void main_cpu_reset(void *opaque)
196 {
197 SPARCCPU *cpu = opaque;
198 CPUState *cs = CPU(cpu);
199
200 cpu_reset(cs);
201 cs->halted = 0;
202 }
203
204 static void secondary_cpu_reset(void *opaque)
205 {
206 SPARCCPU *cpu = opaque;
207 CPUState *cs = CPU(cpu);
208
209 cpu_reset(cs);
210 cs->halted = 1;
211 }
212
213 static void cpu_halt_signal(void *opaque, int irq, int level)
214 {
215 if (level && current_cpu) {
216 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
217 }
218 }
219
220 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
221 {
222 return addr - 0xf0000000ULL;
223 }
224
225 static unsigned long sun4m_load_kernel(const char *kernel_filename,
226 const char *initrd_filename,
227 ram_addr_t RAM_size,
228 uint32_t *initrd_size)
229 {
230 int linux_boot;
231 unsigned int i;
232 long kernel_size;
233 uint8_t *ptr;
234
235 linux_boot = (kernel_filename != NULL);
236
237 kernel_size = 0;
238 if (linux_boot) {
239 int bswap_needed;
240
241 #ifdef BSWAP_NEEDED
242 bswap_needed = 1;
243 #else
244 bswap_needed = 0;
245 #endif
246 kernel_size = load_elf(kernel_filename, NULL,
247 translate_kernel_address, NULL,
248 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
249 if (kernel_size < 0)
250 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
251 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
252 TARGET_PAGE_SIZE);
253 if (kernel_size < 0)
254 kernel_size = load_image_targphys(kernel_filename,
255 KERNEL_LOAD_ADDR,
256 RAM_size - KERNEL_LOAD_ADDR);
257 if (kernel_size < 0) {
258 error_report("could not load kernel '%s'", kernel_filename);
259 exit(1);
260 }
261
262 /* load initrd */
263 *initrd_size = 0;
264 if (initrd_filename) {
265 *initrd_size = load_image_targphys(initrd_filename,
266 INITRD_LOAD_ADDR,
267 RAM_size - INITRD_LOAD_ADDR);
268 if ((int)*initrd_size < 0) {
269 error_report("could not load initial ram disk '%s'",
270 initrd_filename);
271 exit(1);
272 }
273 }
274 if (*initrd_size > 0) {
275 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
276 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
277 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
278 stl_p(ptr + 16, INITRD_LOAD_ADDR);
279 stl_p(ptr + 20, *initrd_size);
280 break;
281 }
282 }
283 }
284 }
285 return kernel_size;
286 }
287
288 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
289 {
290 DeviceState *dev;
291 SysBusDevice *s;
292
293 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
294 qdev_prop_set_uint32(dev, "version", version);
295 qdev_init_nofail(dev);
296 s = SYS_BUS_DEVICE(dev);
297 sysbus_connect_irq(s, 0, irq);
298 sysbus_mmio_map(s, 0, addr);
299
300 return s;
301 }
302
303 static void *sparc32_dma_init(hwaddr dma_base,
304 hwaddr esp_base, qemu_irq espdma_irq,
305 hwaddr le_base, qemu_irq ledma_irq)
306 {
307 DeviceState *dma;
308 ESPDMADeviceState *espdma;
309 LEDMADeviceState *ledma;
310 SysBusESPState *esp;
311 SysBusPCNetState *lance;
312
313 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
314 qdev_init_nofail(dma);
315 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
316
317 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
318 OBJECT(dma), "espdma"));
319 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
320
321 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
322 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
323 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
324
325 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
326 OBJECT(dma), "ledma"));
327 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
328
329 lance = SYSBUS_PCNET(object_resolve_path_component(
330 OBJECT(ledma), "lance"));
331 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
332
333 return dma;
334 }
335
336 static DeviceState *slavio_intctl_init(hwaddr addr,
337 hwaddr addrg,
338 qemu_irq **parent_irq)
339 {
340 DeviceState *dev;
341 SysBusDevice *s;
342 unsigned int i, j;
343
344 dev = qdev_create(NULL, "slavio_intctl");
345 qdev_init_nofail(dev);
346
347 s = SYS_BUS_DEVICE(dev);
348
349 for (i = 0; i < MAX_CPUS; i++) {
350 for (j = 0; j < MAX_PILS; j++) {
351 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
352 }
353 }
354 sysbus_mmio_map(s, 0, addrg);
355 for (i = 0; i < MAX_CPUS; i++) {
356 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
357 }
358
359 return dev;
360 }
361
362 #define SYS_TIMER_OFFSET 0x10000ULL
363 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
364
365 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
366 qemu_irq *cpu_irqs, unsigned int num_cpus)
367 {
368 DeviceState *dev;
369 SysBusDevice *s;
370 unsigned int i;
371
372 dev = qdev_create(NULL, "slavio_timer");
373 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
374 qdev_init_nofail(dev);
375 s = SYS_BUS_DEVICE(dev);
376 sysbus_connect_irq(s, 0, master_irq);
377 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
378
379 for (i = 0; i < MAX_CPUS; i++) {
380 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
381 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
382 }
383 }
384
385 static qemu_irq slavio_system_powerdown;
386
387 static void slavio_powerdown_req(Notifier *n, void *opaque)
388 {
389 qemu_irq_raise(slavio_system_powerdown);
390 }
391
392 static Notifier slavio_system_powerdown_notifier = {
393 .notify = slavio_powerdown_req
394 };
395
396 #define MISC_LEDS 0x01600000
397 #define MISC_CFG 0x01800000
398 #define MISC_DIAG 0x01a00000
399 #define MISC_MDM 0x01b00000
400 #define MISC_SYS 0x01f00000
401
402 static void slavio_misc_init(hwaddr base,
403 hwaddr aux1_base,
404 hwaddr aux2_base, qemu_irq irq,
405 qemu_irq fdc_tc)
406 {
407 DeviceState *dev;
408 SysBusDevice *s;
409
410 dev = qdev_create(NULL, "slavio_misc");
411 qdev_init_nofail(dev);
412 s = SYS_BUS_DEVICE(dev);
413 if (base) {
414 /* 8 bit registers */
415 /* Slavio control */
416 sysbus_mmio_map(s, 0, base + MISC_CFG);
417 /* Diagnostics */
418 sysbus_mmio_map(s, 1, base + MISC_DIAG);
419 /* Modem control */
420 sysbus_mmio_map(s, 2, base + MISC_MDM);
421 /* 16 bit registers */
422 /* ss600mp diag LEDs */
423 sysbus_mmio_map(s, 3, base + MISC_LEDS);
424 /* 32 bit registers */
425 /* System control */
426 sysbus_mmio_map(s, 4, base + MISC_SYS);
427 }
428 if (aux1_base) {
429 /* AUX 1 (Misc System Functions) */
430 sysbus_mmio_map(s, 5, aux1_base);
431 }
432 if (aux2_base) {
433 /* AUX 2 (Software Powerdown Control) */
434 sysbus_mmio_map(s, 6, aux2_base);
435 }
436 sysbus_connect_irq(s, 0, irq);
437 sysbus_connect_irq(s, 1, fdc_tc);
438 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
439 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
440 }
441
442 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
443 {
444 DeviceState *dev;
445 SysBusDevice *s;
446
447 dev = qdev_create(NULL, "eccmemctl");
448 qdev_prop_set_uint32(dev, "version", version);
449 qdev_init_nofail(dev);
450 s = SYS_BUS_DEVICE(dev);
451 sysbus_connect_irq(s, 0, irq);
452 sysbus_mmio_map(s, 0, base);
453 if (version == 0) { // SS-600MP only
454 sysbus_mmio_map(s, 1, base + 0x1000);
455 }
456 }
457
458 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
459 {
460 DeviceState *dev;
461 SysBusDevice *s;
462
463 dev = qdev_create(NULL, "apc");
464 qdev_init_nofail(dev);
465 s = SYS_BUS_DEVICE(dev);
466 /* Power management (APC) XXX: not a Slavio device */
467 sysbus_mmio_map(s, 0, power_base);
468 sysbus_connect_irq(s, 0, cpu_halt);
469 }
470
471 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
472 int height, int depth)
473 {
474 DeviceState *dev;
475 SysBusDevice *s;
476
477 dev = qdev_create(NULL, "SUNW,tcx");
478 qdev_prop_set_uint32(dev, "vram_size", vram_size);
479 qdev_prop_set_uint16(dev, "width", width);
480 qdev_prop_set_uint16(dev, "height", height);
481 qdev_prop_set_uint16(dev, "depth", depth);
482 qdev_init_nofail(dev);
483 s = SYS_BUS_DEVICE(dev);
484
485 /* 10/ROM : FCode ROM */
486 sysbus_mmio_map(s, 0, addr);
487 /* 2/STIP : Stipple */
488 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
489 /* 3/BLIT : Blitter */
490 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
491 /* 5/RSTIP : Raw Stipple */
492 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
493 /* 6/RBLIT : Raw Blitter */
494 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
495 /* 7/TEC : Transform Engine */
496 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
497 /* 8/CMAP : DAC */
498 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
499 /* 9/THC : */
500 if (depth == 8) {
501 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
502 } else {
503 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
504 }
505 /* 11/DHC : */
506 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
507 /* 12/ALT : */
508 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
509 /* 0/DFB8 : 8-bit plane */
510 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
511 /* 1/DFB24 : 24bit plane */
512 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
513 /* 4/RDFB32: Raw framebuffer. Control plane */
514 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
515 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
516 if (depth == 8) {
517 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
518 }
519
520 sysbus_connect_irq(s, 0, irq);
521 }
522
523 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
524 int height, int depth)
525 {
526 DeviceState *dev;
527 SysBusDevice *s;
528
529 dev = qdev_create(NULL, "cgthree");
530 qdev_prop_set_uint32(dev, "vram-size", vram_size);
531 qdev_prop_set_uint16(dev, "width", width);
532 qdev_prop_set_uint16(dev, "height", height);
533 qdev_prop_set_uint16(dev, "depth", depth);
534 qdev_init_nofail(dev);
535 s = SYS_BUS_DEVICE(dev);
536
537 /* FCode ROM */
538 sysbus_mmio_map(s, 0, addr);
539 /* DAC */
540 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
541 /* 8-bit plane */
542 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
543
544 sysbus_connect_irq(s, 0, irq);
545 }
546
547 /* NCR89C100/MACIO Internal ID register */
548
549 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
550
551 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
552
553 static void idreg_init(hwaddr addr)
554 {
555 DeviceState *dev;
556 SysBusDevice *s;
557
558 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
559 qdev_init_nofail(dev);
560 s = SYS_BUS_DEVICE(dev);
561
562 sysbus_mmio_map(s, 0, addr);
563 address_space_write_rom(&address_space_memory, addr,
564 MEMTXATTRS_UNSPECIFIED,
565 idreg_data, sizeof(idreg_data));
566 }
567
568 #define MACIO_ID_REGISTER(obj) \
569 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
570
571 typedef struct IDRegState {
572 SysBusDevice parent_obj;
573
574 MemoryRegion mem;
575 } IDRegState;
576
577 static void idreg_realize(DeviceState *ds, Error **errp)
578 {
579 IDRegState *s = MACIO_ID_REGISTER(ds);
580 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
581 Error *local_err = NULL;
582
583 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
584 sizeof(idreg_data), &local_err);
585 if (local_err) {
586 error_propagate(errp, local_err);
587 return;
588 }
589
590 vmstate_register_ram_global(&s->mem);
591 memory_region_set_readonly(&s->mem, true);
592 sysbus_init_mmio(dev, &s->mem);
593 }
594
595 static void idreg_class_init(ObjectClass *oc, void *data)
596 {
597 DeviceClass *dc = DEVICE_CLASS(oc);
598
599 dc->realize = idreg_realize;
600 }
601
602 static const TypeInfo idreg_info = {
603 .name = TYPE_MACIO_ID_REGISTER,
604 .parent = TYPE_SYS_BUS_DEVICE,
605 .instance_size = sizeof(IDRegState),
606 .class_init = idreg_class_init,
607 };
608
609 #define TYPE_TCX_AFX "tcx_afx"
610 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
611
612 typedef struct AFXState {
613 SysBusDevice parent_obj;
614
615 MemoryRegion mem;
616 } AFXState;
617
618 /* SS-5 TCX AFX register */
619 static void afx_init(hwaddr addr)
620 {
621 DeviceState *dev;
622 SysBusDevice *s;
623
624 dev = qdev_create(NULL, TYPE_TCX_AFX);
625 qdev_init_nofail(dev);
626 s = SYS_BUS_DEVICE(dev);
627
628 sysbus_mmio_map(s, 0, addr);
629 }
630
631 static void afx_realize(DeviceState *ds, Error **errp)
632 {
633 AFXState *s = TCX_AFX(ds);
634 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
635 Error *local_err = NULL;
636
637 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
638 &local_err);
639 if (local_err) {
640 error_propagate(errp, local_err);
641 return;
642 }
643
644 vmstate_register_ram_global(&s->mem);
645 sysbus_init_mmio(dev, &s->mem);
646 }
647
648 static void afx_class_init(ObjectClass *oc, void *data)
649 {
650 DeviceClass *dc = DEVICE_CLASS(oc);
651
652 dc->realize = afx_realize;
653 }
654
655 static const TypeInfo afx_info = {
656 .name = TYPE_TCX_AFX,
657 .parent = TYPE_SYS_BUS_DEVICE,
658 .instance_size = sizeof(AFXState),
659 .class_init = afx_class_init,
660 };
661
662 #define TYPE_OPENPROM "openprom"
663 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
664
665 typedef struct PROMState {
666 SysBusDevice parent_obj;
667
668 MemoryRegion prom;
669 } PROMState;
670
671 /* Boot PROM (OpenBIOS) */
672 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
673 {
674 hwaddr *base_addr = (hwaddr *)opaque;
675 return addr + *base_addr - PROM_VADDR;
676 }
677
678 static void prom_init(hwaddr addr, const char *bios_name)
679 {
680 DeviceState *dev;
681 SysBusDevice *s;
682 char *filename;
683 int ret;
684
685 dev = qdev_create(NULL, TYPE_OPENPROM);
686 qdev_init_nofail(dev);
687 s = SYS_BUS_DEVICE(dev);
688
689 sysbus_mmio_map(s, 0, addr);
690
691 /* load boot prom */
692 if (bios_name == NULL) {
693 bios_name = PROM_FILENAME;
694 }
695 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
696 if (filename) {
697 ret = load_elf(filename, NULL,
698 translate_prom_address, &addr, NULL,
699 NULL, NULL, 1, EM_SPARC, 0, 0);
700 if (ret < 0 || ret > PROM_SIZE_MAX) {
701 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
702 }
703 g_free(filename);
704 } else {
705 ret = -1;
706 }
707 if (ret < 0 || ret > PROM_SIZE_MAX) {
708 error_report("could not load prom '%s'", bios_name);
709 exit(1);
710 }
711 }
712
713 static void prom_realize(DeviceState *ds, Error **errp)
714 {
715 PROMState *s = OPENPROM(ds);
716 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
717 Error *local_err = NULL;
718
719 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
720 PROM_SIZE_MAX, &local_err);
721 if (local_err) {
722 error_propagate(errp, local_err);
723 return;
724 }
725
726 vmstate_register_ram_global(&s->prom);
727 memory_region_set_readonly(&s->prom, true);
728 sysbus_init_mmio(dev, &s->prom);
729 }
730
731 static Property prom_properties[] = {
732 {/* end of property list */},
733 };
734
735 static void prom_class_init(ObjectClass *klass, void *data)
736 {
737 DeviceClass *dc = DEVICE_CLASS(klass);
738
739 dc->props = prom_properties;
740 dc->realize = prom_realize;
741 }
742
743 static const TypeInfo prom_info = {
744 .name = TYPE_OPENPROM,
745 .parent = TYPE_SYS_BUS_DEVICE,
746 .instance_size = sizeof(PROMState),
747 .class_init = prom_class_init,
748 };
749
750 #define TYPE_SUN4M_MEMORY "memory"
751 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
752
753 typedef struct RamDevice {
754 SysBusDevice parent_obj;
755
756 MemoryRegion ram;
757 uint64_t size;
758 } RamDevice;
759
760 /* System RAM */
761 static void ram_realize(DeviceState *dev, Error **errp)
762 {
763 RamDevice *d = SUN4M_RAM(dev);
764 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
765
766 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
767 d->size);
768 sysbus_init_mmio(sbd, &d->ram);
769 }
770
771 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
772 uint64_t max_mem)
773 {
774 DeviceState *dev;
775 SysBusDevice *s;
776 RamDevice *d;
777
778 /* allocate RAM */
779 if ((uint64_t)RAM_size > max_mem) {
780 error_report("Too much memory for this machine: %" PRId64 ","
781 " maximum %" PRId64,
782 RAM_size / MiB, max_mem / MiB);
783 exit(1);
784 }
785 dev = qdev_create(NULL, "memory");
786 s = SYS_BUS_DEVICE(dev);
787
788 d = SUN4M_RAM(dev);
789 d->size = RAM_size;
790 qdev_init_nofail(dev);
791
792 sysbus_mmio_map(s, 0, addr);
793 }
794
795 static Property ram_properties[] = {
796 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
797 DEFINE_PROP_END_OF_LIST(),
798 };
799
800 static void ram_class_init(ObjectClass *klass, void *data)
801 {
802 DeviceClass *dc = DEVICE_CLASS(klass);
803
804 dc->realize = ram_realize;
805 dc->props = ram_properties;
806 }
807
808 static const TypeInfo ram_info = {
809 .name = TYPE_SUN4M_MEMORY,
810 .parent = TYPE_SYS_BUS_DEVICE,
811 .instance_size = sizeof(RamDevice),
812 .class_init = ram_class_init,
813 };
814
815 static void cpu_devinit(const char *cpu_type, unsigned int id,
816 uint64_t prom_addr, qemu_irq **cpu_irqs)
817 {
818 CPUState *cs;
819 SPARCCPU *cpu;
820 CPUSPARCState *env;
821
822 cpu = SPARC_CPU(cpu_create(cpu_type));
823 env = &cpu->env;
824
825 cpu_sparc_set_id(env, id);
826 if (id == 0) {
827 qemu_register_reset(main_cpu_reset, cpu);
828 } else {
829 qemu_register_reset(secondary_cpu_reset, cpu);
830 cs = CPU(cpu);
831 cs->halted = 1;
832 }
833 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
834 env->prom_addr = prom_addr;
835 }
836
837 static void dummy_fdc_tc(void *opaque, int irq, int level)
838 {
839 }
840
841 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
842 MachineState *machine)
843 {
844 DeviceState *slavio_intctl;
845 unsigned int i;
846 void *nvram;
847 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
848 qemu_irq fdc_tc;
849 unsigned long kernel_size;
850 uint32_t initrd_size;
851 DriveInfo *fd[MAX_FD];
852 FWCfgState *fw_cfg;
853 DeviceState *dev;
854 SysBusDevice *s;
855
856 /* init CPUs */
857 for(i = 0; i < smp_cpus; i++) {
858 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
859 }
860
861 for (i = smp_cpus; i < MAX_CPUS; i++)
862 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
863
864
865 /* set up devices */
866 ram_init(0, machine->ram_size, hwdef->max_mem);
867 /* models without ECC don't trap when missing ram is accessed */
868 if (!hwdef->ecc_base) {
869 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
870 }
871
872 prom_init(hwdef->slavio_base, bios_name);
873
874 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
875 hwdef->intctl_base + 0x10000ULL,
876 cpu_irqs);
877
878 for (i = 0; i < 32; i++) {
879 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
880 }
881 for (i = 0; i < MAX_CPUS; i++) {
882 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
883 }
884
885 if (hwdef->idreg_base) {
886 idreg_init(hwdef->idreg_base);
887 }
888
889 if (hwdef->afx_base) {
890 afx_init(hwdef->afx_base);
891 }
892
893 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
894
895 if (hwdef->iommu_pad_base) {
896 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
897 Software shouldn't use aliased addresses, neither should it crash
898 when does. Using empty_slot instead of aliasing can help with
899 debugging such accesses */
900 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
901 }
902
903 sparc32_dma_init(hwdef->dma_base,
904 hwdef->esp_base, slavio_irq[18],
905 hwdef->le_base, slavio_irq[16]);
906
907 if (graphic_depth != 8 && graphic_depth != 24) {
908 error_report("Unsupported depth: %d", graphic_depth);
909 exit (1);
910 }
911 if (vga_interface_type != VGA_NONE) {
912 if (vga_interface_type == VGA_CG3) {
913 if (graphic_depth != 8) {
914 error_report("Unsupported depth: %d", graphic_depth);
915 exit(1);
916 }
917
918 if (!(graphic_width == 1024 && graphic_height == 768) &&
919 !(graphic_width == 1152 && graphic_height == 900)) {
920 error_report("Unsupported resolution: %d x %d", graphic_width,
921 graphic_height);
922 exit(1);
923 }
924
925 /* sbus irq 5 */
926 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
927 graphic_width, graphic_height, graphic_depth);
928 } else {
929 /* If no display specified, default to TCX */
930 if (graphic_depth != 8 && graphic_depth != 24) {
931 error_report("Unsupported depth: %d", graphic_depth);
932 exit(1);
933 }
934
935 if (!(graphic_width == 1024 && graphic_height == 768)) {
936 error_report("Unsupported resolution: %d x %d",
937 graphic_width, graphic_height);
938 exit(1);
939 }
940
941 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
942 graphic_width, graphic_height, graphic_depth);
943 }
944 }
945
946 for (i = 0; i < MAX_VSIMMS; i++) {
947 /* vsimm registers probed by OBP */
948 if (hwdef->vsimm[i].reg_base) {
949 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
950 }
951 }
952
953 if (hwdef->sx_base) {
954 empty_slot_init(hwdef->sx_base, 0x2000);
955 }
956
957 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
958
959 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
960
961 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
962 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
963 dev = qdev_create(NULL, TYPE_ESCC);
964 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
965 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
966 qdev_prop_set_uint32(dev, "it_shift", 1);
967 qdev_prop_set_chr(dev, "chrB", NULL);
968 qdev_prop_set_chr(dev, "chrA", NULL);
969 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
970 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
971 qdev_init_nofail(dev);
972 s = SYS_BUS_DEVICE(dev);
973 sysbus_connect_irq(s, 0, slavio_irq[14]);
974 sysbus_connect_irq(s, 1, slavio_irq[14]);
975 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
976
977 dev = qdev_create(NULL, TYPE_ESCC);
978 qdev_prop_set_uint32(dev, "disabled", 0);
979 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
980 qdev_prop_set_uint32(dev, "it_shift", 1);
981 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
982 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
983 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
984 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
985 qdev_init_nofail(dev);
986
987 s = SYS_BUS_DEVICE(dev);
988 sysbus_connect_irq(s, 0, slavio_irq[15]);
989 sysbus_connect_irq(s, 1, slavio_irq[15]);
990 sysbus_mmio_map(s, 0, hwdef->serial_base);
991
992 if (hwdef->apc_base) {
993 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
994 }
995
996 if (hwdef->fd_base) {
997 /* there is zero or one floppy drive */
998 memset(fd, 0, sizeof(fd));
999 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1000 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1001 &fdc_tc);
1002 } else {
1003 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1004 }
1005
1006 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1007 slavio_irq[30], fdc_tc);
1008
1009 if (hwdef->cs_base) {
1010 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1011 slavio_irq[5]);
1012 }
1013
1014 if (hwdef->dbri_base) {
1015 /* ISDN chip with attached CS4215 audio codec */
1016 /* prom space */
1017 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1018 /* reg space */
1019 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1020 }
1021
1022 if (hwdef->bpp_base) {
1023 /* parallel port */
1024 empty_slot_init(hwdef->bpp_base, 0x20);
1025 }
1026
1027 initrd_size = 0;
1028 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1029 machine->initrd_filename,
1030 machine->ram_size, &initrd_size);
1031
1032 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1033 machine->boot_order, machine->ram_size, kernel_size,
1034 graphic_width, graphic_height, graphic_depth,
1035 hwdef->nvram_machine_id, "Sun4m");
1036
1037 if (hwdef->ecc_base)
1038 ecc_init(hwdef->ecc_base, slavio_irq[28],
1039 hwdef->ecc_version);
1040
1041 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1042 fw_cfg = FW_CFG(dev);
1043 qdev_prop_set_uint32(dev, "data_width", 1);
1044 qdev_prop_set_bit(dev, "dma_enabled", false);
1045 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1046 OBJECT(fw_cfg), NULL);
1047 qdev_init_nofail(dev);
1048 s = SYS_BUS_DEVICE(dev);
1049 sysbus_mmio_map(s, 0, CFG_ADDR);
1050 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1051
1052 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1053 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1054 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1055 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1056 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1057 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1058 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1059 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1060 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1061 if (machine->kernel_cmdline) {
1062 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1063 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1064 machine->kernel_cmdline);
1065 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1066 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1067 strlen(machine->kernel_cmdline) + 1);
1068 } else {
1069 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1070 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1071 }
1072 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1073 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1074 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1075 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1076 }
1077
1078 enum {
1079 ss5_id = 32,
1080 vger_id,
1081 lx_id,
1082 ss4_id,
1083 scls_id,
1084 sbook_id,
1085 ss10_id = 64,
1086 ss20_id,
1087 ss600mp_id,
1088 };
1089
1090 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1091 /* SS-5 */
1092 {
1093 .iommu_base = 0x10000000,
1094 .iommu_pad_base = 0x10004000,
1095 .iommu_pad_len = 0x0fffb000,
1096 .tcx_base = 0x50000000,
1097 .cs_base = 0x6c000000,
1098 .slavio_base = 0x70000000,
1099 .ms_kb_base = 0x71000000,
1100 .serial_base = 0x71100000,
1101 .nvram_base = 0x71200000,
1102 .fd_base = 0x71400000,
1103 .counter_base = 0x71d00000,
1104 .intctl_base = 0x71e00000,
1105 .idreg_base = 0x78000000,
1106 .dma_base = 0x78400000,
1107 .esp_base = 0x78800000,
1108 .le_base = 0x78c00000,
1109 .apc_base = 0x6a000000,
1110 .afx_base = 0x6e000000,
1111 .aux1_base = 0x71900000,
1112 .aux2_base = 0x71910000,
1113 .nvram_machine_id = 0x80,
1114 .machine_id = ss5_id,
1115 .iommu_version = 0x05000000,
1116 .max_mem = 0x10000000,
1117 },
1118 /* SS-10 */
1119 {
1120 .iommu_base = 0xfe0000000ULL,
1121 .tcx_base = 0xe20000000ULL,
1122 .slavio_base = 0xff0000000ULL,
1123 .ms_kb_base = 0xff1000000ULL,
1124 .serial_base = 0xff1100000ULL,
1125 .nvram_base = 0xff1200000ULL,
1126 .fd_base = 0xff1700000ULL,
1127 .counter_base = 0xff1300000ULL,
1128 .intctl_base = 0xff1400000ULL,
1129 .idreg_base = 0xef0000000ULL,
1130 .dma_base = 0xef0400000ULL,
1131 .esp_base = 0xef0800000ULL,
1132 .le_base = 0xef0c00000ULL,
1133 .apc_base = 0xefa000000ULL, // XXX should not exist
1134 .aux1_base = 0xff1800000ULL,
1135 .aux2_base = 0xff1a01000ULL,
1136 .ecc_base = 0xf00000000ULL,
1137 .ecc_version = 0x10000000, // version 0, implementation 1
1138 .nvram_machine_id = 0x72,
1139 .machine_id = ss10_id,
1140 .iommu_version = 0x03000000,
1141 .max_mem = 0xf00000000ULL,
1142 },
1143 /* SS-600MP */
1144 {
1145 .iommu_base = 0xfe0000000ULL,
1146 .tcx_base = 0xe20000000ULL,
1147 .slavio_base = 0xff0000000ULL,
1148 .ms_kb_base = 0xff1000000ULL,
1149 .serial_base = 0xff1100000ULL,
1150 .nvram_base = 0xff1200000ULL,
1151 .counter_base = 0xff1300000ULL,
1152 .intctl_base = 0xff1400000ULL,
1153 .dma_base = 0xef0081000ULL,
1154 .esp_base = 0xef0080000ULL,
1155 .le_base = 0xef0060000ULL,
1156 .apc_base = 0xefa000000ULL, // XXX should not exist
1157 .aux1_base = 0xff1800000ULL,
1158 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1159 .ecc_base = 0xf00000000ULL,
1160 .ecc_version = 0x00000000, // version 0, implementation 0
1161 .nvram_machine_id = 0x71,
1162 .machine_id = ss600mp_id,
1163 .iommu_version = 0x01000000,
1164 .max_mem = 0xf00000000ULL,
1165 },
1166 /* SS-20 */
1167 {
1168 .iommu_base = 0xfe0000000ULL,
1169 .tcx_base = 0xe20000000ULL,
1170 .slavio_base = 0xff0000000ULL,
1171 .ms_kb_base = 0xff1000000ULL,
1172 .serial_base = 0xff1100000ULL,
1173 .nvram_base = 0xff1200000ULL,
1174 .fd_base = 0xff1700000ULL,
1175 .counter_base = 0xff1300000ULL,
1176 .intctl_base = 0xff1400000ULL,
1177 .idreg_base = 0xef0000000ULL,
1178 .dma_base = 0xef0400000ULL,
1179 .esp_base = 0xef0800000ULL,
1180 .le_base = 0xef0c00000ULL,
1181 .bpp_base = 0xef4800000ULL,
1182 .apc_base = 0xefa000000ULL, // XXX should not exist
1183 .aux1_base = 0xff1800000ULL,
1184 .aux2_base = 0xff1a01000ULL,
1185 .dbri_base = 0xee0000000ULL,
1186 .sx_base = 0xf80000000ULL,
1187 .vsimm = {
1188 {
1189 .reg_base = 0x9c000000ULL,
1190 .vram_base = 0xfc000000ULL
1191 }, {
1192 .reg_base = 0x90000000ULL,
1193 .vram_base = 0xf0000000ULL
1194 }, {
1195 .reg_base = 0x94000000ULL
1196 }, {
1197 .reg_base = 0x98000000ULL
1198 }
1199 },
1200 .ecc_base = 0xf00000000ULL,
1201 .ecc_version = 0x20000000, // version 0, implementation 2
1202 .nvram_machine_id = 0x72,
1203 .machine_id = ss20_id,
1204 .iommu_version = 0x13000000,
1205 .max_mem = 0xf00000000ULL,
1206 },
1207 /* Voyager */
1208 {
1209 .iommu_base = 0x10000000,
1210 .tcx_base = 0x50000000,
1211 .slavio_base = 0x70000000,
1212 .ms_kb_base = 0x71000000,
1213 .serial_base = 0x71100000,
1214 .nvram_base = 0x71200000,
1215 .fd_base = 0x71400000,
1216 .counter_base = 0x71d00000,
1217 .intctl_base = 0x71e00000,
1218 .idreg_base = 0x78000000,
1219 .dma_base = 0x78400000,
1220 .esp_base = 0x78800000,
1221 .le_base = 0x78c00000,
1222 .apc_base = 0x71300000, // pmc
1223 .aux1_base = 0x71900000,
1224 .aux2_base = 0x71910000,
1225 .nvram_machine_id = 0x80,
1226 .machine_id = vger_id,
1227 .iommu_version = 0x05000000,
1228 .max_mem = 0x10000000,
1229 },
1230 /* LX */
1231 {
1232 .iommu_base = 0x10000000,
1233 .iommu_pad_base = 0x10004000,
1234 .iommu_pad_len = 0x0fffb000,
1235 .tcx_base = 0x50000000,
1236 .slavio_base = 0x70000000,
1237 .ms_kb_base = 0x71000000,
1238 .serial_base = 0x71100000,
1239 .nvram_base = 0x71200000,
1240 .fd_base = 0x71400000,
1241 .counter_base = 0x71d00000,
1242 .intctl_base = 0x71e00000,
1243 .idreg_base = 0x78000000,
1244 .dma_base = 0x78400000,
1245 .esp_base = 0x78800000,
1246 .le_base = 0x78c00000,
1247 .aux1_base = 0x71900000,
1248 .aux2_base = 0x71910000,
1249 .nvram_machine_id = 0x80,
1250 .machine_id = lx_id,
1251 .iommu_version = 0x04000000,
1252 .max_mem = 0x10000000,
1253 },
1254 /* SS-4 */
1255 {
1256 .iommu_base = 0x10000000,
1257 .tcx_base = 0x50000000,
1258 .cs_base = 0x6c000000,
1259 .slavio_base = 0x70000000,
1260 .ms_kb_base = 0x71000000,
1261 .serial_base = 0x71100000,
1262 .nvram_base = 0x71200000,
1263 .fd_base = 0x71400000,
1264 .counter_base = 0x71d00000,
1265 .intctl_base = 0x71e00000,
1266 .idreg_base = 0x78000000,
1267 .dma_base = 0x78400000,
1268 .esp_base = 0x78800000,
1269 .le_base = 0x78c00000,
1270 .apc_base = 0x6a000000,
1271 .aux1_base = 0x71900000,
1272 .aux2_base = 0x71910000,
1273 .nvram_machine_id = 0x80,
1274 .machine_id = ss4_id,
1275 .iommu_version = 0x05000000,
1276 .max_mem = 0x10000000,
1277 },
1278 /* SPARCClassic */
1279 {
1280 .iommu_base = 0x10000000,
1281 .tcx_base = 0x50000000,
1282 .slavio_base = 0x70000000,
1283 .ms_kb_base = 0x71000000,
1284 .serial_base = 0x71100000,
1285 .nvram_base = 0x71200000,
1286 .fd_base = 0x71400000,
1287 .counter_base = 0x71d00000,
1288 .intctl_base = 0x71e00000,
1289 .idreg_base = 0x78000000,
1290 .dma_base = 0x78400000,
1291 .esp_base = 0x78800000,
1292 .le_base = 0x78c00000,
1293 .apc_base = 0x6a000000,
1294 .aux1_base = 0x71900000,
1295 .aux2_base = 0x71910000,
1296 .nvram_machine_id = 0x80,
1297 .machine_id = scls_id,
1298 .iommu_version = 0x05000000,
1299 .max_mem = 0x10000000,
1300 },
1301 /* SPARCbook */
1302 {
1303 .iommu_base = 0x10000000,
1304 .tcx_base = 0x50000000, // XXX
1305 .slavio_base = 0x70000000,
1306 .ms_kb_base = 0x71000000,
1307 .serial_base = 0x71100000,
1308 .nvram_base = 0x71200000,
1309 .fd_base = 0x71400000,
1310 .counter_base = 0x71d00000,
1311 .intctl_base = 0x71e00000,
1312 .idreg_base = 0x78000000,
1313 .dma_base = 0x78400000,
1314 .esp_base = 0x78800000,
1315 .le_base = 0x78c00000,
1316 .apc_base = 0x6a000000,
1317 .aux1_base = 0x71900000,
1318 .aux2_base = 0x71910000,
1319 .nvram_machine_id = 0x80,
1320 .machine_id = sbook_id,
1321 .iommu_version = 0x05000000,
1322 .max_mem = 0x10000000,
1323 },
1324 };
1325
1326 /* SPARCstation 5 hardware initialisation */
1327 static void ss5_init(MachineState *machine)
1328 {
1329 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1330 }
1331
1332 /* SPARCstation 10 hardware initialisation */
1333 static void ss10_init(MachineState *machine)
1334 {
1335 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1336 }
1337
1338 /* SPARCserver 600MP hardware initialisation */
1339 static void ss600mp_init(MachineState *machine)
1340 {
1341 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1342 }
1343
1344 /* SPARCstation 20 hardware initialisation */
1345 static void ss20_init(MachineState *machine)
1346 {
1347 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1348 }
1349
1350 /* SPARCstation Voyager hardware initialisation */
1351 static void vger_init(MachineState *machine)
1352 {
1353 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1354 }
1355
1356 /* SPARCstation LX hardware initialisation */
1357 static void ss_lx_init(MachineState *machine)
1358 {
1359 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1360 }
1361
1362 /* SPARCstation 4 hardware initialisation */
1363 static void ss4_init(MachineState *machine)
1364 {
1365 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1366 }
1367
1368 /* SPARCClassic hardware initialisation */
1369 static void scls_init(MachineState *machine)
1370 {
1371 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1372 }
1373
1374 /* SPARCbook hardware initialisation */
1375 static void sbook_init(MachineState *machine)
1376 {
1377 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1378 }
1379
1380 static void ss5_class_init(ObjectClass *oc, void *data)
1381 {
1382 MachineClass *mc = MACHINE_CLASS(oc);
1383
1384 mc->desc = "Sun4m platform, SPARCstation 5";
1385 mc->init = ss5_init;
1386 mc->block_default_type = IF_SCSI;
1387 mc->is_default = 1;
1388 mc->default_boot_order = "c";
1389 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1390 }
1391
1392 static const TypeInfo ss5_type = {
1393 .name = MACHINE_TYPE_NAME("SS-5"),
1394 .parent = TYPE_MACHINE,
1395 .class_init = ss5_class_init,
1396 };
1397
1398 static void ss10_class_init(ObjectClass *oc, void *data)
1399 {
1400 MachineClass *mc = MACHINE_CLASS(oc);
1401
1402 mc->desc = "Sun4m platform, SPARCstation 10";
1403 mc->init = ss10_init;
1404 mc->block_default_type = IF_SCSI;
1405 mc->max_cpus = 4;
1406 mc->default_boot_order = "c";
1407 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1408 }
1409
1410 static const TypeInfo ss10_type = {
1411 .name = MACHINE_TYPE_NAME("SS-10"),
1412 .parent = TYPE_MACHINE,
1413 .class_init = ss10_class_init,
1414 };
1415
1416 static void ss600mp_class_init(ObjectClass *oc, void *data)
1417 {
1418 MachineClass *mc = MACHINE_CLASS(oc);
1419
1420 mc->desc = "Sun4m platform, SPARCserver 600MP";
1421 mc->init = ss600mp_init;
1422 mc->block_default_type = IF_SCSI;
1423 mc->max_cpus = 4;
1424 mc->default_boot_order = "c";
1425 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1426 }
1427
1428 static const TypeInfo ss600mp_type = {
1429 .name = MACHINE_TYPE_NAME("SS-600MP"),
1430 .parent = TYPE_MACHINE,
1431 .class_init = ss600mp_class_init,
1432 };
1433
1434 static void ss20_class_init(ObjectClass *oc, void *data)
1435 {
1436 MachineClass *mc = MACHINE_CLASS(oc);
1437
1438 mc->desc = "Sun4m platform, SPARCstation 20";
1439 mc->init = ss20_init;
1440 mc->block_default_type = IF_SCSI;
1441 mc->max_cpus = 4;
1442 mc->default_boot_order = "c";
1443 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1444 }
1445
1446 static const TypeInfo ss20_type = {
1447 .name = MACHINE_TYPE_NAME("SS-20"),
1448 .parent = TYPE_MACHINE,
1449 .class_init = ss20_class_init,
1450 };
1451
1452 static void voyager_class_init(ObjectClass *oc, void *data)
1453 {
1454 MachineClass *mc = MACHINE_CLASS(oc);
1455
1456 mc->desc = "Sun4m platform, SPARCstation Voyager";
1457 mc->init = vger_init;
1458 mc->block_default_type = IF_SCSI;
1459 mc->default_boot_order = "c";
1460 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1461 }
1462
1463 static const TypeInfo voyager_type = {
1464 .name = MACHINE_TYPE_NAME("Voyager"),
1465 .parent = TYPE_MACHINE,
1466 .class_init = voyager_class_init,
1467 };
1468
1469 static void ss_lx_class_init(ObjectClass *oc, void *data)
1470 {
1471 MachineClass *mc = MACHINE_CLASS(oc);
1472
1473 mc->desc = "Sun4m platform, SPARCstation LX";
1474 mc->init = ss_lx_init;
1475 mc->block_default_type = IF_SCSI;
1476 mc->default_boot_order = "c";
1477 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1478 }
1479
1480 static const TypeInfo ss_lx_type = {
1481 .name = MACHINE_TYPE_NAME("LX"),
1482 .parent = TYPE_MACHINE,
1483 .class_init = ss_lx_class_init,
1484 };
1485
1486 static void ss4_class_init(ObjectClass *oc, void *data)
1487 {
1488 MachineClass *mc = MACHINE_CLASS(oc);
1489
1490 mc->desc = "Sun4m platform, SPARCstation 4";
1491 mc->init = ss4_init;
1492 mc->block_default_type = IF_SCSI;
1493 mc->default_boot_order = "c";
1494 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1495 }
1496
1497 static const TypeInfo ss4_type = {
1498 .name = MACHINE_TYPE_NAME("SS-4"),
1499 .parent = TYPE_MACHINE,
1500 .class_init = ss4_class_init,
1501 };
1502
1503 static void scls_class_init(ObjectClass *oc, void *data)
1504 {
1505 MachineClass *mc = MACHINE_CLASS(oc);
1506
1507 mc->desc = "Sun4m platform, SPARCClassic";
1508 mc->init = scls_init;
1509 mc->block_default_type = IF_SCSI;
1510 mc->default_boot_order = "c";
1511 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1512 }
1513
1514 static const TypeInfo scls_type = {
1515 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1516 .parent = TYPE_MACHINE,
1517 .class_init = scls_class_init,
1518 };
1519
1520 static void sbook_class_init(ObjectClass *oc, void *data)
1521 {
1522 MachineClass *mc = MACHINE_CLASS(oc);
1523
1524 mc->desc = "Sun4m platform, SPARCbook";
1525 mc->init = sbook_init;
1526 mc->block_default_type = IF_SCSI;
1527 mc->default_boot_order = "c";
1528 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1529 }
1530
1531 static const TypeInfo sbook_type = {
1532 .name = MACHINE_TYPE_NAME("SPARCbook"),
1533 .parent = TYPE_MACHINE,
1534 .class_init = sbook_class_init,
1535 };
1536
1537 static void sun4m_register_types(void)
1538 {
1539 type_register_static(&idreg_info);
1540 type_register_static(&afx_info);
1541 type_register_static(&prom_info);
1542 type_register_static(&ram_info);
1543
1544 type_register_static(&ss5_type);
1545 type_register_static(&ss10_type);
1546 type_register_static(&ss600mp_type);
1547 type_register_static(&ss20_type);
1548 type_register_static(&voyager_type);
1549 type_register_static(&ss_lx_type);
1550 type_register_static(&ss4_type);
1551 type_register_static(&scls_type);
1552 type_register_static(&sbook_type);
1553 }
1554
1555 type_init(sun4m_register_types)
AR7 emulation for QEMU