2 * QEMU Firmware configuration device emulation
4 * Copyright (c) 2008 Gleb Natapov
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/dma.h"
29 #include "sysemu/reset.h"
30 #include "hw/boards.h"
31 #include "hw/nvram/fw_cfg.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/qemu-file-types.h"
35 #include "migration/vmstate.h"
37 #include "qemu/error-report.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qemu/cutils.h"
41 #include "qapi/error.h"
42 #include "hw/acpi/aml-build.h"
43 #include "hw/pci/pci_bus.h"
45 #define FW_CFG_FILE_SLOTS_DFLT 0x20
47 /* FW_CFG_VERSION bits */
48 #define FW_CFG_VERSION 0x01
49 #define FW_CFG_VERSION_DMA 0x02
51 /* FW_CFG_DMA_CONTROL bits */
52 #define FW_CFG_DMA_CTL_ERROR 0x01
53 #define FW_CFG_DMA_CTL_READ 0x02
54 #define FW_CFG_DMA_CTL_SKIP 0x04
55 #define FW_CFG_DMA_CTL_SELECT 0x08
56 #define FW_CFG_DMA_CTL_WRITE 0x10
58 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
64 void *callback_opaque
;
65 FWCfgCallback select_cb
;
66 FWCfgWriteCallback write_cb
;
72 * @key: The uint16 selector key.
74 * Returns: The stringified name if the selector refers to a well-known
75 * numerically defined item, or NULL on key lookup failure.
77 static const char *key_name(uint16_t key
)
79 static const char *fw_cfg_wellknown_keys
[FW_CFG_FILE_FIRST
] = {
80 [FW_CFG_SIGNATURE
] = "signature",
82 [FW_CFG_UUID
] = "uuid",
83 [FW_CFG_RAM_SIZE
] = "ram_size",
84 [FW_CFG_NOGRAPHIC
] = "nographic",
85 [FW_CFG_NB_CPUS
] = "nb_cpus",
86 [FW_CFG_MACHINE_ID
] = "machine_id",
87 [FW_CFG_KERNEL_ADDR
] = "kernel_addr",
88 [FW_CFG_KERNEL_SIZE
] = "kernel_size",
89 [FW_CFG_KERNEL_CMDLINE
] = "kernel_cmdline",
90 [FW_CFG_INITRD_ADDR
] = "initrd_addr",
91 [FW_CFG_INITRD_SIZE
] = "initdr_size",
92 [FW_CFG_BOOT_DEVICE
] = "boot_device",
93 [FW_CFG_NUMA
] = "numa",
94 [FW_CFG_BOOT_MENU
] = "boot_menu",
95 [FW_CFG_MAX_CPUS
] = "max_cpus",
96 [FW_CFG_KERNEL_ENTRY
] = "kernel_entry",
97 [FW_CFG_KERNEL_DATA
] = "kernel_data",
98 [FW_CFG_INITRD_DATA
] = "initrd_data",
99 [FW_CFG_CMDLINE_ADDR
] = "cmdline_addr",
100 [FW_CFG_CMDLINE_SIZE
] = "cmdline_size",
101 [FW_CFG_CMDLINE_DATA
] = "cmdline_data",
102 [FW_CFG_SETUP_ADDR
] = "setup_addr",
103 [FW_CFG_SETUP_SIZE
] = "setup_size",
104 [FW_CFG_SETUP_DATA
] = "setup_data",
105 [FW_CFG_FILE_DIR
] = "file_dir",
108 if (key
& FW_CFG_ARCH_LOCAL
) {
109 return fw_cfg_arch_key_name(key
);
111 if (key
< FW_CFG_FILE_FIRST
) {
112 return fw_cfg_wellknown_keys
[key
];
118 static inline const char *trace_key_name(uint16_t key
)
120 const char *name
= key_name(key
);
122 return name
? name
: "unknown";
128 static char *read_splashfile(char *filename
, gsize
*file_sizep
,
134 unsigned int filehead
;
137 if (!g_file_get_contents(filename
, &content
, file_sizep
, &err
)) {
138 error_report("failed to read splash file '%s': %s",
139 filename
, err
->message
);
144 /* check file size */
145 if (*file_sizep
< 30) {
150 filehead
= lduw_le_p(content
);
151 if (filehead
== 0xd8ff) {
152 file_type
= JPG_FILE
;
153 } else if (filehead
== 0x4d42) {
154 file_type
= BMP_FILE
;
160 if (file_type
== BMP_FILE
) {
161 bmp_bpp
= lduw_le_p(&content
[28]);
168 *file_typep
= file_type
;
173 error_report("splash file '%s' format not recognized; must be JPEG "
174 "or 24 bit BMP", filename
);
179 static void fw_cfg_bootsplash(FWCfgState
*s
)
181 const char *boot_splash_filename
= NULL
;
182 const char *boot_splash_time
= NULL
;
183 char *filename
, *file_data
;
187 /* get user configuration */
188 QemuOptsList
*plist
= qemu_find_opts("boot-opts");
189 QemuOpts
*opts
= QTAILQ_FIRST(&plist
->head
);
190 boot_splash_filename
= qemu_opt_get(opts
, "splash");
191 boot_splash_time
= qemu_opt_get(opts
, "splash-time");
193 /* insert splash time if user configurated */
194 if (boot_splash_time
) {
195 int64_t bst_val
= qemu_opt_get_number(opts
, "splash-time", -1);
198 /* validate the input */
199 if (bst_val
< 0 || bst_val
> 0xffff) {
200 error_report("splash-time is invalid,"
201 "it should be a value between 0 and 65535");
204 /* use little endian format */
205 bst_le16
= cpu_to_le16(bst_val
);
206 fw_cfg_add_file(s
, "etc/boot-menu-wait",
207 g_memdup(&bst_le16
, sizeof bst_le16
), sizeof bst_le16
);
210 /* insert splash file if user configurated */
211 if (boot_splash_filename
) {
212 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, boot_splash_filename
);
213 if (filename
== NULL
) {
214 error_report("failed to find file '%s'", boot_splash_filename
);
218 /* loading file data */
219 file_data
= read_splashfile(filename
, &file_size
, &file_type
);
220 if (file_data
== NULL
) {
224 g_free(boot_splash_filedata
);
225 boot_splash_filedata
= (uint8_t *)file_data
;
228 if (file_type
== JPG_FILE
) {
229 fw_cfg_add_file(s
, "bootsplash.jpg",
230 boot_splash_filedata
, file_size
);
232 fw_cfg_add_file(s
, "bootsplash.bmp",
233 boot_splash_filedata
, file_size
);
239 static void fw_cfg_reboot(FWCfgState
*s
)
241 const char *reboot_timeout
= NULL
;
242 uint64_t rt_val
= -1;
245 /* get user configuration */
246 QemuOptsList
*plist
= qemu_find_opts("boot-opts");
247 QemuOpts
*opts
= QTAILQ_FIRST(&plist
->head
);
248 reboot_timeout
= qemu_opt_get(opts
, "reboot-timeout");
250 if (reboot_timeout
) {
251 rt_val
= qemu_opt_get_number(opts
, "reboot-timeout", -1);
253 /* validate the input */
254 if (rt_val
> 0xffff && rt_val
!= (uint64_t)-1) {
255 error_report("reboot timeout is invalid,"
256 "it should be a value between -1 and 65535");
261 rt_le32
= cpu_to_le32(rt_val
);
262 fw_cfg_add_file(s
, "etc/boot-fail-wait", g_memdup(&rt_le32
, 4), 4);
265 static void fw_cfg_write(FWCfgState
*s
, uint8_t value
)
267 /* nothing, write support removed in QEMU v2.4+ */
270 static inline uint16_t fw_cfg_file_slots(const FWCfgState
*s
)
272 return s
->file_slots
;
275 /* Note: this function returns an exclusive limit. */
276 static inline uint32_t fw_cfg_max_entry(const FWCfgState
*s
)
278 return FW_CFG_FILE_FIRST
+ fw_cfg_file_slots(s
);
281 static int fw_cfg_select(FWCfgState
*s
, uint16_t key
)
287 if ((key
& FW_CFG_ENTRY_MASK
) >= fw_cfg_max_entry(s
)) {
288 s
->cur_entry
= FW_CFG_INVALID
;
293 /* entry successfully selected, now run callback if present */
294 arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
295 e
= &s
->entries
[arch
][key
& FW_CFG_ENTRY_MASK
];
297 e
->select_cb(e
->callback_opaque
);
301 trace_fw_cfg_select(s
, key
, trace_key_name(key
), ret
);
305 static uint64_t fw_cfg_data_read(void *opaque
, hwaddr addr
, unsigned size
)
307 FWCfgState
*s
= opaque
;
308 int arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
309 FWCfgEntry
*e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
310 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
313 assert(size
> 0 && size
<= sizeof(value
));
314 if (s
->cur_entry
!= FW_CFG_INVALID
&& e
->data
&& s
->cur_offset
< e
->len
) {
315 /* The least significant 'size' bytes of the return value are
316 * expected to contain a string preserving portion of the item
317 * data, padded with zeros on the right in case we run out early.
318 * In technical terms, we're composing the host-endian representation
319 * of the big endian interpretation of the fw_cfg string.
322 value
= (value
<< 8) | e
->data
[s
->cur_offset
++];
323 } while (--size
&& s
->cur_offset
< e
->len
);
324 /* If size is still not zero, we *did* run out early, so continue
325 * left-shifting, to add the appropriate number of padding zeros
331 trace_fw_cfg_read(s
, value
);
335 static void fw_cfg_data_mem_write(void *opaque
, hwaddr addr
,
336 uint64_t value
, unsigned size
)
338 FWCfgState
*s
= opaque
;
342 fw_cfg_write(s
, value
>> (8 * --i
));
346 static void fw_cfg_dma_transfer(FWCfgState
*s
)
352 int read
= 0, write
= 0;
355 /* Reset the address before the next access */
356 dma_addr
= s
->dma_addr
;
359 if (dma_memory_read(s
->dma_as
, dma_addr
, &dma
, sizeof(dma
))) {
360 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
361 FW_CFG_DMA_CTL_ERROR
);
365 dma
.address
= be64_to_cpu(dma
.address
);
366 dma
.length
= be32_to_cpu(dma
.length
);
367 dma
.control
= be32_to_cpu(dma
.control
);
369 if (dma
.control
& FW_CFG_DMA_CTL_SELECT
) {
370 fw_cfg_select(s
, dma
.control
>> 16);
373 arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
374 e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
375 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
377 if (dma
.control
& FW_CFG_DMA_CTL_READ
) {
380 } else if (dma
.control
& FW_CFG_DMA_CTL_WRITE
) {
383 } else if (dma
.control
& FW_CFG_DMA_CTL_SKIP
) {
392 while (dma
.length
> 0 && !(dma
.control
& FW_CFG_DMA_CTL_ERROR
)) {
393 if (s
->cur_entry
== FW_CFG_INVALID
|| !e
->data
||
394 s
->cur_offset
>= e
->len
) {
397 /* If the access is not a read access, it will be a skip access,
401 if (dma_memory_set(s
->dma_as
, dma
.address
, 0, len
)) {
402 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
406 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
409 if (dma
.length
<= (e
->len
- s
->cur_offset
)) {
412 len
= (e
->len
- s
->cur_offset
);
415 /* If the access is not a read access, it will be a skip access,
419 if (dma_memory_write(s
->dma_as
, dma
.address
,
420 &e
->data
[s
->cur_offset
], len
)) {
421 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
425 if (!e
->allow_write
||
427 dma_memory_read(s
->dma_as
, dma
.address
,
428 &e
->data
[s
->cur_offset
], len
)) {
429 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
430 } else if (e
->write_cb
) {
431 e
->write_cb(e
->callback_opaque
, s
->cur_offset
, len
);
435 s
->cur_offset
+= len
;
443 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
446 trace_fw_cfg_read(s
, 0);
449 static uint64_t fw_cfg_dma_mem_read(void *opaque
, hwaddr addr
,
452 /* Return a signature value (and handle various read sizes) */
453 return extract64(FW_CFG_DMA_SIGNATURE
, (8 - addr
- size
) * 8, size
* 8);
456 static void fw_cfg_dma_mem_write(void *opaque
, hwaddr addr
,
457 uint64_t value
, unsigned size
)
459 FWCfgState
*s
= opaque
;
463 /* FWCfgDmaAccess high address */
464 s
->dma_addr
= value
<< 32;
465 } else if (addr
== 4) {
466 /* FWCfgDmaAccess low address */
467 s
->dma_addr
|= value
;
468 fw_cfg_dma_transfer(s
);
470 } else if (size
== 8 && addr
== 0) {
472 fw_cfg_dma_transfer(s
);
476 static bool fw_cfg_dma_mem_valid(void *opaque
, hwaddr addr
,
477 unsigned size
, bool is_write
,
480 return !is_write
|| ((size
== 4 && (addr
== 0 || addr
== 4)) ||
481 (size
== 8 && addr
== 0));
484 static bool fw_cfg_data_mem_valid(void *opaque
, hwaddr addr
,
485 unsigned size
, bool is_write
,
491 static uint64_t fw_cfg_ctl_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
496 static void fw_cfg_ctl_mem_write(void *opaque
, hwaddr addr
,
497 uint64_t value
, unsigned size
)
499 fw_cfg_select(opaque
, (uint16_t)value
);
502 static bool fw_cfg_ctl_mem_valid(void *opaque
, hwaddr addr
,
503 unsigned size
, bool is_write
,
506 return is_write
&& size
== 2;
509 static void fw_cfg_comb_write(void *opaque
, hwaddr addr
,
510 uint64_t value
, unsigned size
)
514 fw_cfg_write(opaque
, (uint8_t)value
);
517 fw_cfg_select(opaque
, (uint16_t)value
);
522 static bool fw_cfg_comb_valid(void *opaque
, hwaddr addr
,
523 unsigned size
, bool is_write
,
526 return (size
== 1) || (is_write
&& size
== 2);
529 static const MemoryRegionOps fw_cfg_ctl_mem_ops
= {
530 .read
= fw_cfg_ctl_mem_read
,
531 .write
= fw_cfg_ctl_mem_write
,
532 .endianness
= DEVICE_BIG_ENDIAN
,
533 .valid
.accepts
= fw_cfg_ctl_mem_valid
,
536 static const MemoryRegionOps fw_cfg_data_mem_ops
= {
537 .read
= fw_cfg_data_read
,
538 .write
= fw_cfg_data_mem_write
,
539 .endianness
= DEVICE_BIG_ENDIAN
,
541 .min_access_size
= 1,
542 .max_access_size
= 1,
543 .accepts
= fw_cfg_data_mem_valid
,
547 static const MemoryRegionOps fw_cfg_comb_mem_ops
= {
548 .read
= fw_cfg_data_read
,
549 .write
= fw_cfg_comb_write
,
550 .endianness
= DEVICE_LITTLE_ENDIAN
,
551 .valid
.accepts
= fw_cfg_comb_valid
,
554 static const MemoryRegionOps fw_cfg_dma_mem_ops
= {
555 .read
= fw_cfg_dma_mem_read
,
556 .write
= fw_cfg_dma_mem_write
,
557 .endianness
= DEVICE_BIG_ENDIAN
,
558 .valid
.accepts
= fw_cfg_dma_mem_valid
,
559 .valid
.max_access_size
= 8,
560 .impl
.max_access_size
= 8,
563 static void fw_cfg_reset(DeviceState
*d
)
565 FWCfgState
*s
= FW_CFG(d
);
567 /* we never register a read callback for FW_CFG_SIGNATURE */
568 fw_cfg_select(s
, FW_CFG_SIGNATURE
);
571 /* Save restore 32 bit int as uint16_t
572 This is a Big hack, but it is how the old state did it.
573 Or we broke compatibility in the state, or we can't use struct tm
576 static int get_uint32_as_uint16(QEMUFile
*f
, void *pv
, size_t size
,
577 const VMStateField
*field
)
580 *v
= qemu_get_be16(f
);
584 static int put_unused(QEMUFile
*f
, void *pv
, size_t size
,
585 const VMStateField
*field
, QJSON
*vmdesc
)
587 fprintf(stderr
, "uint32_as_uint16 is only used for backward compatibility.\n");
588 fprintf(stderr
, "This functions shouldn't be called.\n");
593 static const VMStateInfo vmstate_hack_uint32_as_uint16
= {
594 .name
= "int32_as_uint16",
595 .get
= get_uint32_as_uint16
,
599 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
600 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
603 static bool is_version_1(void *opaque
, int version_id
)
605 return version_id
== 1;
608 bool fw_cfg_dma_enabled(void *opaque
)
610 FWCfgState
*s
= opaque
;
612 return s
->dma_enabled
;
615 static bool fw_cfg_acpi_mr_restore(void *opaque
)
617 FWCfgState
*s
= opaque
;
620 mr_aligned
= QEMU_IS_ALIGNED(s
->table_mr_size
, qemu_real_host_page_size
) &&
621 QEMU_IS_ALIGNED(s
->linker_mr_size
, qemu_real_host_page_size
) &&
622 QEMU_IS_ALIGNED(s
->rsdp_mr_size
, qemu_real_host_page_size
);
623 return s
->acpi_mr_restore
&& !mr_aligned
;
626 static void fw_cfg_update_mr(FWCfgState
*s
, uint16_t key
, size_t size
)
630 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
633 key
&= FW_CFG_ENTRY_MASK
;
634 assert(key
< fw_cfg_max_entry(s
));
636 ptr
= s
->entries
[arch
][key
].data
;
637 mr
= memory_region_from_host(ptr
, &offset
);
639 memory_region_ram_resize(mr
, size
, &error_abort
);
642 static int fw_cfg_acpi_mr_restore_post_load(void *opaque
, int version_id
)
644 FWCfgState
*s
= opaque
;
649 index
= be32_to_cpu(s
->files
->count
);
651 for (i
= 0; i
< index
; i
++) {
652 if (!strcmp(s
->files
->f
[i
].name
, ACPI_BUILD_TABLE_FILE
)) {
653 fw_cfg_update_mr(s
, FW_CFG_FILE_FIRST
+ i
, s
->table_mr_size
);
654 } else if (!strcmp(s
->files
->f
[i
].name
, ACPI_BUILD_LOADER_FILE
)) {
655 fw_cfg_update_mr(s
, FW_CFG_FILE_FIRST
+ i
, s
->linker_mr_size
);
656 } else if (!strcmp(s
->files
->f
[i
].name
, ACPI_BUILD_RSDP_FILE
)) {
657 fw_cfg_update_mr(s
, FW_CFG_FILE_FIRST
+ i
, s
->rsdp_mr_size
);
664 static const VMStateDescription vmstate_fw_cfg_dma
= {
665 .name
= "fw_cfg/dma",
666 .needed
= fw_cfg_dma_enabled
,
667 .fields
= (VMStateField
[]) {
668 VMSTATE_UINT64(dma_addr
, FWCfgState
),
669 VMSTATE_END_OF_LIST()
673 static const VMStateDescription vmstate_fw_cfg_acpi_mr
= {
674 .name
= "fw_cfg/acpi_mr",
676 .minimum_version_id
= 1,
677 .needed
= fw_cfg_acpi_mr_restore
,
678 .post_load
= fw_cfg_acpi_mr_restore_post_load
,
679 .fields
= (VMStateField
[]) {
680 VMSTATE_UINT64(table_mr_size
, FWCfgState
),
681 VMSTATE_UINT64(linker_mr_size
, FWCfgState
),
682 VMSTATE_UINT64(rsdp_mr_size
, FWCfgState
),
683 VMSTATE_END_OF_LIST()
687 static const VMStateDescription vmstate_fw_cfg
= {
690 .minimum_version_id
= 1,
691 .fields
= (VMStateField
[]) {
692 VMSTATE_UINT16(cur_entry
, FWCfgState
),
693 VMSTATE_UINT16_HACK(cur_offset
, FWCfgState
, is_version_1
),
694 VMSTATE_UINT32_V(cur_offset
, FWCfgState
, 2),
695 VMSTATE_END_OF_LIST()
697 .subsections
= (const VMStateDescription
*[]) {
699 &vmstate_fw_cfg_acpi_mr
,
704 static void fw_cfg_add_bytes_callback(FWCfgState
*s
, uint16_t key
,
705 FWCfgCallback select_cb
,
706 FWCfgWriteCallback write_cb
,
707 void *callback_opaque
,
708 void *data
, size_t len
,
711 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
713 key
&= FW_CFG_ENTRY_MASK
;
715 assert(key
< fw_cfg_max_entry(s
) && len
< UINT32_MAX
);
716 assert(s
->entries
[arch
][key
].data
== NULL
); /* avoid key conflict */
718 s
->entries
[arch
][key
].data
= data
;
719 s
->entries
[arch
][key
].len
= (uint32_t)len
;
720 s
->entries
[arch
][key
].select_cb
= select_cb
;
721 s
->entries
[arch
][key
].write_cb
= write_cb
;
722 s
->entries
[arch
][key
].callback_opaque
= callback_opaque
;
723 s
->entries
[arch
][key
].allow_write
= !read_only
;
726 static void *fw_cfg_modify_bytes_read(FWCfgState
*s
, uint16_t key
,
727 void *data
, size_t len
)
730 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
732 key
&= FW_CFG_ENTRY_MASK
;
734 assert(key
< fw_cfg_max_entry(s
) && len
< UINT32_MAX
);
736 /* return the old data to the function caller, avoid memory leak */
737 ptr
= s
->entries
[arch
][key
].data
;
738 s
->entries
[arch
][key
].data
= data
;
739 s
->entries
[arch
][key
].len
= len
;
740 s
->entries
[arch
][key
].callback_opaque
= NULL
;
741 s
->entries
[arch
][key
].allow_write
= false;
746 void fw_cfg_add_bytes(FWCfgState
*s
, uint16_t key
, void *data
, size_t len
)
748 trace_fw_cfg_add_bytes(key
, trace_key_name(key
), len
);
749 fw_cfg_add_bytes_callback(s
, key
, NULL
, NULL
, NULL
, data
, len
, true);
752 void fw_cfg_add_string(FWCfgState
*s
, uint16_t key
, const char *value
)
754 size_t sz
= strlen(value
) + 1;
756 trace_fw_cfg_add_string(key
, trace_key_name(key
), value
);
757 fw_cfg_add_bytes(s
, key
, g_memdup(value
, sz
), sz
);
760 void fw_cfg_modify_string(FWCfgState
*s
, uint16_t key
, const char *value
)
762 size_t sz
= strlen(value
) + 1;
765 old
= fw_cfg_modify_bytes_read(s
, key
, g_memdup(value
, sz
), sz
);
769 void fw_cfg_add_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
773 copy
= g_malloc(sizeof(value
));
774 *copy
= cpu_to_le16(value
);
775 trace_fw_cfg_add_i16(key
, trace_key_name(key
), value
);
776 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
779 void fw_cfg_modify_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
781 uint16_t *copy
, *old
;
783 copy
= g_malloc(sizeof(value
));
784 *copy
= cpu_to_le16(value
);
785 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
789 void fw_cfg_add_i32(FWCfgState
*s
, uint16_t key
, uint32_t value
)
793 copy
= g_malloc(sizeof(value
));
794 *copy
= cpu_to_le32(value
);
795 trace_fw_cfg_add_i32(key
, trace_key_name(key
), value
);
796 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
799 void fw_cfg_modify_i32(FWCfgState
*s
, uint16_t key
, uint32_t value
)
801 uint32_t *copy
, *old
;
803 copy
= g_malloc(sizeof(value
));
804 *copy
= cpu_to_le32(value
);
805 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
809 void fw_cfg_add_i64(FWCfgState
*s
, uint16_t key
, uint64_t value
)
813 copy
= g_malloc(sizeof(value
));
814 *copy
= cpu_to_le64(value
);
815 trace_fw_cfg_add_i64(key
, trace_key_name(key
), value
);
816 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
819 void fw_cfg_modify_i64(FWCfgState
*s
, uint16_t key
, uint64_t value
)
821 uint64_t *copy
, *old
;
823 copy
= g_malloc(sizeof(value
));
824 *copy
= cpu_to_le64(value
);
825 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
829 void fw_cfg_set_order_override(FWCfgState
*s
, int order
)
831 assert(s
->fw_cfg_order_override
== 0);
832 s
->fw_cfg_order_override
= order
;
835 void fw_cfg_reset_order_override(FWCfgState
*s
)
837 assert(s
->fw_cfg_order_override
!= 0);
838 s
->fw_cfg_order_override
= 0;
842 * This is the legacy order list. For legacy systems, files are in
843 * the fw_cfg in the order defined below, by the "order" value. Note
844 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
845 * specific area, but there may be more than one and they occur in the
846 * order that the user specifies them on the command line. Those are
847 * handled in a special manner, using the order override above.
849 * For non-legacy, the files are sorted by filename to avoid this kind
850 * of complexity in the future.
852 * This is only for x86, other arches don't implement versioning so
853 * they won't set legacy mode.
859 { "etc/boot-menu-wait", 10 },
860 { "bootsplash.jpg", 11 },
861 { "bootsplash.bmp", 12 },
862 { "etc/boot-fail-wait", 15 },
863 { "etc/smbios/smbios-tables", 20 },
864 { "etc/smbios/smbios-anchor", 30 },
866 { "etc/reserved-memory-end", 50 },
867 { "genroms/kvmvapic.bin", 55 },
868 { "genroms/linuxboot.bin", 60 },
869 { }, /* VGA ROMs from pc_vga_init come here, 70. */
870 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
871 { "etc/system-states", 90 },
872 { }, /* User ROMs come here, 100. */
873 { }, /* Device FW comes here, 110. */
874 { "etc/extra-pci-roots", 120 },
875 { "etc/acpi/tables", 130 },
876 { "etc/table-loader", 140 },
877 { "etc/tpm/log", 150 },
878 { "etc/acpi/rsdp", 160 },
879 { "bootorder", 170 },
881 #define FW_CFG_ORDER_OVERRIDE_LAST 200
885 * Any sub-page size update to these table MRs will be lost during migration,
886 * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
887 * In order to avoid the inconsistency in sizes save them seperately and
888 * migrate over in vmstate post_load().
890 static void fw_cfg_acpi_mr_save(FWCfgState
*s
, const char *filename
, size_t len
)
892 if (!strcmp(filename
, ACPI_BUILD_TABLE_FILE
)) {
893 s
->table_mr_size
= len
;
894 } else if (!strcmp(filename
, ACPI_BUILD_LOADER_FILE
)) {
895 s
->linker_mr_size
= len
;
896 } else if (!strcmp(filename
, ACPI_BUILD_RSDP_FILE
)) {
897 s
->rsdp_mr_size
= len
;
901 static int get_fw_cfg_order(FWCfgState
*s
, const char *name
)
905 if (s
->fw_cfg_order_override
> 0) {
906 return s
->fw_cfg_order_override
;
909 for (i
= 0; i
< ARRAY_SIZE(fw_cfg_order
); i
++) {
910 if (fw_cfg_order
[i
].name
== NULL
) {
914 if (strcmp(name
, fw_cfg_order
[i
].name
) == 0) {
915 return fw_cfg_order
[i
].order
;
919 /* Stick unknown stuff at the end. */
920 warn_report("Unknown firmware file in legacy mode: %s", name
);
921 return FW_CFG_ORDER_OVERRIDE_LAST
;
924 void fw_cfg_add_file_callback(FWCfgState
*s
, const char *filename
,
925 FWCfgCallback select_cb
,
926 FWCfgWriteCallback write_cb
,
927 void *callback_opaque
,
928 void *data
, size_t len
, bool read_only
)
932 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
936 dsize
= sizeof(uint32_t) + sizeof(FWCfgFile
) * fw_cfg_file_slots(s
);
937 s
->files
= g_malloc0(dsize
);
938 fw_cfg_add_bytes(s
, FW_CFG_FILE_DIR
, s
->files
, dsize
);
941 count
= be32_to_cpu(s
->files
->count
);
942 assert(count
< fw_cfg_file_slots(s
));
944 /* Find the insertion point. */
945 if (mc
->legacy_fw_cfg_order
) {
947 * Sort by order. For files with the same order, we keep them
948 * in the sequence in which they were added.
950 order
= get_fw_cfg_order(s
, filename
);
952 index
> 0 && order
< s
->entry_order
[index
- 1];
955 /* Sort by file name. */
957 index
> 0 && strcmp(filename
, s
->files
->f
[index
- 1].name
) < 0;
962 * Move all the entries from the index point and after down one
963 * to create a slot for the new entry. Because calculations are
964 * being done with the index, make it so that "i" is the current
965 * index and "i - 1" is the one being copied from, thus the
966 * unusual start and end in the for statement.
968 for (i
= count
; i
> index
; i
--) {
969 s
->files
->f
[i
] = s
->files
->f
[i
- 1];
970 s
->files
->f
[i
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ i
);
971 s
->entries
[0][FW_CFG_FILE_FIRST
+ i
] =
972 s
->entries
[0][FW_CFG_FILE_FIRST
+ i
- 1];
973 s
->entry_order
[i
] = s
->entry_order
[i
- 1];
976 memset(&s
->files
->f
[index
], 0, sizeof(FWCfgFile
));
977 memset(&s
->entries
[0][FW_CFG_FILE_FIRST
+ index
], 0, sizeof(FWCfgEntry
));
979 pstrcpy(s
->files
->f
[index
].name
, sizeof(s
->files
->f
[index
].name
), filename
);
980 for (i
= 0; i
<= count
; i
++) {
982 strcmp(s
->files
->f
[index
].name
, s
->files
->f
[i
].name
) == 0) {
983 error_report("duplicate fw_cfg file name: %s",
984 s
->files
->f
[index
].name
);
989 fw_cfg_add_bytes_callback(s
, FW_CFG_FILE_FIRST
+ index
,
991 callback_opaque
, data
, len
,
994 s
->files
->f
[index
].size
= cpu_to_be32(len
);
995 s
->files
->f
[index
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ index
);
996 s
->entry_order
[index
] = order
;
997 trace_fw_cfg_add_file(s
, index
, s
->files
->f
[index
].name
, len
);
999 s
->files
->count
= cpu_to_be32(count
+1);
1000 fw_cfg_acpi_mr_save(s
, filename
, len
);
1003 void fw_cfg_add_file(FWCfgState
*s
, const char *filename
,
1004 void *data
, size_t len
)
1006 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, NULL
, data
, len
, true);
1009 void *fw_cfg_modify_file(FWCfgState
*s
, const char *filename
,
1010 void *data
, size_t len
)
1017 index
= be32_to_cpu(s
->files
->count
);
1019 for (i
= 0; i
< index
; i
++) {
1020 if (strcmp(filename
, s
->files
->f
[i
].name
) == 0) {
1021 ptr
= fw_cfg_modify_bytes_read(s
, FW_CFG_FILE_FIRST
+ i
,
1023 s
->files
->f
[i
].size
= cpu_to_be32(len
);
1024 fw_cfg_acpi_mr_save(s
, filename
, len
);
1029 assert(index
< fw_cfg_file_slots(s
));
1032 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, NULL
, data
, len
, true);
1036 bool fw_cfg_add_from_generator(FWCfgState
*s
, const char *filename
,
1037 const char *gen_id
, Error
**errp
)
1039 FWCfgDataGeneratorClass
*klass
;
1044 obj
= object_resolve_path_component(object_get_objects_root(), gen_id
);
1046 error_setg(errp
, "Cannot find object ID '%s'", gen_id
);
1049 if (!object_dynamic_cast(obj
, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE
)) {
1050 error_setg(errp
, "Object ID '%s' is not a '%s' subclass",
1051 gen_id
, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE
);
1054 klass
= FW_CFG_DATA_GENERATOR_GET_CLASS(obj
);
1055 array
= klass
->get_data(obj
, errp
);
1060 fw_cfg_add_file(s
, filename
, g_byte_array_free(array
, FALSE
), size
);
1065 void fw_cfg_add_extra_pci_roots(PCIBus
*bus
, FWCfgState
*s
)
1067 int extra_hosts
= 0;
1073 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1074 /* look for expander root buses */
1075 if (pci_bus_is_root(bus
)) {
1080 if (extra_hosts
&& s
) {
1081 uint64_t *val
= g_malloc(sizeof(*val
));
1082 *val
= cpu_to_le64(extra_hosts
);
1083 fw_cfg_add_file(s
, "etc/extra-pci-roots", val
, sizeof(*val
));
1087 static void fw_cfg_machine_reset(void *opaque
)
1089 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
1090 FWCfgState
*s
= opaque
;
1095 buf
= get_boot_devices_list(&len
);
1096 ptr
= fw_cfg_modify_file(s
, "bootorder", (uint8_t *)buf
, len
);
1099 if (!mc
->legacy_fw_cfg_order
) {
1100 buf
= get_boot_devices_lchs_list(&len
);
1101 ptr
= fw_cfg_modify_file(s
, "bios-geometry", (uint8_t *)buf
, len
);
1106 static void fw_cfg_machine_ready(struct Notifier
*n
, void *data
)
1108 FWCfgState
*s
= container_of(n
, FWCfgState
, machine_ready
);
1109 qemu_register_reset(fw_cfg_machine_reset
, s
);
1112 static Property fw_cfg_properties
[] = {
1113 DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState
, acpi_mr_restore
, true),
1114 DEFINE_PROP_END_OF_LIST(),
1117 static void fw_cfg_common_realize(DeviceState
*dev
, Error
**errp
)
1119 FWCfgState
*s
= FW_CFG(dev
);
1120 MachineState
*machine
= MACHINE(qdev_get_machine());
1121 uint32_t version
= FW_CFG_VERSION
;
1123 if (!fw_cfg_find()) {
1124 error_setg(errp
, "at most one %s device is permitted", TYPE_FW_CFG
);
1128 fw_cfg_add_bytes(s
, FW_CFG_SIGNATURE
, (char *)"QEMU", 4);
1129 fw_cfg_add_bytes(s
, FW_CFG_UUID
, &qemu_uuid
, 16);
1130 fw_cfg_add_i16(s
, FW_CFG_NOGRAPHIC
, (uint16_t)!machine
->enable_graphics
);
1131 fw_cfg_add_i16(s
, FW_CFG_BOOT_MENU
, (uint16_t)boot_menu
);
1132 fw_cfg_bootsplash(s
);
1135 if (s
->dma_enabled
) {
1136 version
|= FW_CFG_VERSION_DMA
;
1139 fw_cfg_add_i32(s
, FW_CFG_ID
, version
);
1141 s
->machine_ready
.notify
= fw_cfg_machine_ready
;
1142 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
1145 FWCfgState
*fw_cfg_init_io_dma(uint32_t iobase
, uint32_t dma_iobase
,
1146 AddressSpace
*dma_as
)
1152 bool dma_requested
= dma_iobase
&& dma_as
;
1154 dev
= qdev_new(TYPE_FW_CFG_IO
);
1155 if (!dma_requested
) {
1156 qdev_prop_set_bit(dev
, "dma_enabled", false);
1159 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG
,
1162 sbd
= SYS_BUS_DEVICE(dev
);
1163 sysbus_realize_and_unref(sbd
, &error_fatal
);
1164 ios
= FW_CFG_IO(dev
);
1165 sysbus_add_io(sbd
, iobase
, &ios
->comb_iomem
);
1169 if (s
->dma_enabled
) {
1170 /* 64 bits for the address field */
1173 sysbus_add_io(sbd
, dma_iobase
, &s
->dma_iomem
);
1179 FWCfgState
*fw_cfg_init_io(uint32_t iobase
)
1181 return fw_cfg_init_io_dma(iobase
, 0, NULL
);
1184 FWCfgState
*fw_cfg_init_mem_wide(hwaddr ctl_addr
,
1185 hwaddr data_addr
, uint32_t data_width
,
1186 hwaddr dma_addr
, AddressSpace
*dma_as
)
1191 bool dma_requested
= dma_addr
&& dma_as
;
1193 dev
= qdev_new(TYPE_FW_CFG_MEM
);
1194 qdev_prop_set_uint32(dev
, "data_width", data_width
);
1195 if (!dma_requested
) {
1196 qdev_prop_set_bit(dev
, "dma_enabled", false);
1199 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG
,
1202 sbd
= SYS_BUS_DEVICE(dev
);
1203 sysbus_realize_and_unref(sbd
, &error_fatal
);
1204 sysbus_mmio_map(sbd
, 0, ctl_addr
);
1205 sysbus_mmio_map(sbd
, 1, data_addr
);
1209 if (s
->dma_enabled
) {
1212 sysbus_mmio_map(sbd
, 2, dma_addr
);
1218 FWCfgState
*fw_cfg_init_mem(hwaddr ctl_addr
, hwaddr data_addr
)
1220 return fw_cfg_init_mem_wide(ctl_addr
, data_addr
,
1221 fw_cfg_data_mem_ops
.valid
.max_access_size
,
1226 FWCfgState
*fw_cfg_find(void)
1228 /* Returns NULL unless there is exactly one fw_cfg device */
1229 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG
, NULL
));
1233 static void fw_cfg_class_init(ObjectClass
*klass
, void *data
)
1235 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1237 dc
->reset
= fw_cfg_reset
;
1238 dc
->vmsd
= &vmstate_fw_cfg
;
1240 device_class_set_props(dc
, fw_cfg_properties
);
1243 static const TypeInfo fw_cfg_info
= {
1244 .name
= TYPE_FW_CFG
,
1245 .parent
= TYPE_SYS_BUS_DEVICE
,
1247 .instance_size
= sizeof(FWCfgState
),
1248 .class_init
= fw_cfg_class_init
,
1251 static void fw_cfg_file_slots_allocate(FWCfgState
*s
, Error
**errp
)
1253 uint16_t file_slots_max
;
1255 if (fw_cfg_file_slots(s
) < FW_CFG_FILE_SLOTS_MIN
) {
1256 error_setg(errp
, "\"file_slots\" must be at least 0x%x",
1257 FW_CFG_FILE_SLOTS_MIN
);
1261 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1262 * that we permit. The actual (exclusive) value coming from the
1263 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1264 file_slots_max
= (UINT16_MAX
& FW_CFG_ENTRY_MASK
) - FW_CFG_FILE_FIRST
+ 1;
1265 if (fw_cfg_file_slots(s
) > file_slots_max
) {
1266 error_setg(errp
, "\"file_slots\" must not exceed 0x%" PRIx16
,
1271 s
->entries
[0] = g_new0(FWCfgEntry
, fw_cfg_max_entry(s
));
1272 s
->entries
[1] = g_new0(FWCfgEntry
, fw_cfg_max_entry(s
));
1273 s
->entry_order
= g_new0(int, fw_cfg_max_entry(s
));
1276 static Property fw_cfg_io_properties
[] = {
1277 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState
, parent_obj
.dma_enabled
,
1279 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState
, parent_obj
.file_slots
,
1280 FW_CFG_FILE_SLOTS_DFLT
),
1281 DEFINE_PROP_END_OF_LIST(),
1284 static void fw_cfg_io_realize(DeviceState
*dev
, Error
**errp
)
1287 FWCfgIoState
*s
= FW_CFG_IO(dev
);
1289 fw_cfg_file_slots_allocate(FW_CFG(s
), errp
);
1294 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1295 * with half of the 16-bit control register. Hence, the total size
1296 * of the i/o region used is FW_CFG_CTL_SIZE */
1297 memory_region_init_io(&s
->comb_iomem
, OBJECT(s
), &fw_cfg_comb_mem_ops
,
1298 FW_CFG(s
), "fwcfg", FW_CFG_CTL_SIZE
);
1300 if (FW_CFG(s
)->dma_enabled
) {
1301 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
1302 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
1303 sizeof(dma_addr_t
));
1306 fw_cfg_common_realize(dev
, errp
);
1309 static void fw_cfg_io_class_init(ObjectClass
*klass
, void *data
)
1311 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1313 dc
->realize
= fw_cfg_io_realize
;
1314 device_class_set_props(dc
, fw_cfg_io_properties
);
1317 static const TypeInfo fw_cfg_io_info
= {
1318 .name
= TYPE_FW_CFG_IO
,
1319 .parent
= TYPE_FW_CFG
,
1320 .instance_size
= sizeof(FWCfgIoState
),
1321 .class_init
= fw_cfg_io_class_init
,
1325 static Property fw_cfg_mem_properties
[] = {
1326 DEFINE_PROP_UINT32("data_width", FWCfgMemState
, data_width
, -1),
1327 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState
, parent_obj
.dma_enabled
,
1329 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState
, parent_obj
.file_slots
,
1330 FW_CFG_FILE_SLOTS_DFLT
),
1331 DEFINE_PROP_END_OF_LIST(),
1334 static void fw_cfg_mem_realize(DeviceState
*dev
, Error
**errp
)
1337 FWCfgMemState
*s
= FW_CFG_MEM(dev
);
1338 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1339 const MemoryRegionOps
*data_ops
= &fw_cfg_data_mem_ops
;
1341 fw_cfg_file_slots_allocate(FW_CFG(s
), errp
);
1346 memory_region_init_io(&s
->ctl_iomem
, OBJECT(s
), &fw_cfg_ctl_mem_ops
,
1347 FW_CFG(s
), "fwcfg.ctl", FW_CFG_CTL_SIZE
);
1348 sysbus_init_mmio(sbd
, &s
->ctl_iomem
);
1350 if (s
->data_width
> data_ops
->valid
.max_access_size
) {
1351 s
->wide_data_ops
= *data_ops
;
1353 s
->wide_data_ops
.valid
.max_access_size
= s
->data_width
;
1354 s
->wide_data_ops
.impl
.max_access_size
= s
->data_width
;
1355 data_ops
= &s
->wide_data_ops
;
1357 memory_region_init_io(&s
->data_iomem
, OBJECT(s
), data_ops
, FW_CFG(s
),
1358 "fwcfg.data", data_ops
->valid
.max_access_size
);
1359 sysbus_init_mmio(sbd
, &s
->data_iomem
);
1361 if (FW_CFG(s
)->dma_enabled
) {
1362 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
1363 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
1364 sizeof(dma_addr_t
));
1365 sysbus_init_mmio(sbd
, &FW_CFG(s
)->dma_iomem
);
1368 fw_cfg_common_realize(dev
, errp
);
1371 static void fw_cfg_mem_class_init(ObjectClass
*klass
, void *data
)
1373 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1375 dc
->realize
= fw_cfg_mem_realize
;
1376 device_class_set_props(dc
, fw_cfg_mem_properties
);
1379 static const TypeInfo fw_cfg_mem_info
= {
1380 .name
= TYPE_FW_CFG_MEM
,
1381 .parent
= TYPE_FW_CFG
,
1382 .instance_size
= sizeof(FWCfgMemState
),
1383 .class_init
= fw_cfg_mem_class_init
,
1386 static void fw_cfg_register_types(void)
1388 type_register_static(&fw_cfg_info
);
1389 type_register_static(&fw_cfg_io_info
);
1390 type_register_static(&fw_cfg_mem_info
);
1393 type_init(fw_cfg_register_types
)