2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/i386/pc.h"
40 #include "hw/isa/isa.h"
41 #include "hw/nvram/sun_nvram.h"
42 #include "hw/nvram/chrp_nvram.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/char/escc.h"
45 #include "hw/empty_slot.h"
46 #include "hw/loader.h"
48 #include "sysemu/block-backend.h"
50 #include "qemu/cutils.h"
53 * Sun4m architecture was used in the following machines:
55 * SPARCserver 6xxMP/xx
56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
57 * SPARCclassic X (4/10)
58 * SPARCstation LX/ZX (4/30)
59 * SPARCstation Voyager
60 * SPARCstation 10/xx, SPARCserver 10/xx
61 * SPARCstation 5, SPARCserver 5
62 * SPARCstation 20/xx, SPARCserver 20
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 #define KERNEL_LOAD_ADDR 0x00004000
69 #define CMDLINE_ADDR 0x007ff000
70 #define INITRD_LOAD_ADDR 0x00800000
71 #define PROM_SIZE_MAX (1024 * 1024)
72 #define PROM_VADDR 0xffd00000
73 #define PROM_FILENAME "openbios-sparc32"
74 #define CFG_ADDR 0xd00000510ULL
75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
83 #define ESCC_CLOCK 4915200
86 hwaddr iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
87 hwaddr intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
88 hwaddr serial_base
, fd_base
;
89 hwaddr afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
90 hwaddr tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
91 hwaddr bpp_base
, dbri_base
, sx_base
;
93 hwaddr reg_base
, vram_base
;
97 const char * const default_cpu_model
;
99 uint32_t iommu_version
;
101 uint8_t nvram_machine_id
;
104 void DMA_init(ISABus
*bus
, int high_page_enable
)
108 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
111 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
114 static void nvram_init(Nvram
*nvram
, uint8_t *macaddr
,
115 const char *cmdline
, const char *boot_devices
,
116 ram_addr_t RAM_size
, uint32_t kernel_size
,
117 int width
, int height
, int depth
,
118 int nvram_machine_id
, const char *arch
)
122 uint8_t image
[0x1ff0];
123 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
125 memset(image
, '\0', sizeof(image
));
127 /* OpenBIOS nvram variables partition */
128 sysp_end
= chrp_nvram_create_system_partition(image
, 0);
130 /* Free space partition */
131 chrp_nvram_create_free_partition(&image
[sysp_end
], 0x1fd0 - sysp_end
);
133 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
136 for (i
= 0; i
< sizeof(image
); i
++) {
137 (k
->write
)(nvram
, i
, image
[i
]);
141 void cpu_check_irqs(CPUSPARCState
*env
)
145 /* We should be holding the BQL before we mess with IRQs */
146 g_assert(qemu_mutex_iothread_locked());
148 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
149 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
152 for (i
= 15; i
> 0; i
--) {
153 if (env
->pil_in
& (1 << i
)) {
154 int old_interrupt
= env
->interrupt_index
;
156 env
->interrupt_index
= TT_EXTINT
| i
;
157 if (old_interrupt
!= env
->interrupt_index
) {
158 cs
= CPU(sparc_env_get_cpu(env
));
159 trace_sun4m_cpu_interrupt(i
);
160 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
165 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
166 cs
= CPU(sparc_env_get_cpu(env
));
167 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
168 env
->interrupt_index
= 0;
169 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
173 static void cpu_kick_irq(SPARCCPU
*cpu
)
175 CPUSPARCState
*env
= &cpu
->env
;
176 CPUState
*cs
= CPU(cpu
);
183 static void cpu_set_irq(void *opaque
, int irq
, int level
)
185 SPARCCPU
*cpu
= opaque
;
186 CPUSPARCState
*env
= &cpu
->env
;
189 trace_sun4m_cpu_set_irq_raise(irq
);
190 env
->pil_in
|= 1 << irq
;
193 trace_sun4m_cpu_set_irq_lower(irq
);
194 env
->pil_in
&= ~(1 << irq
);
199 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
203 static void main_cpu_reset(void *opaque
)
205 SPARCCPU
*cpu
= opaque
;
206 CPUState
*cs
= CPU(cpu
);
212 static void secondary_cpu_reset(void *opaque
)
214 SPARCCPU
*cpu
= opaque
;
215 CPUState
*cs
= CPU(cpu
);
221 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
223 if (level
&& current_cpu
) {
224 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
228 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
230 return addr
- 0xf0000000ULL
;
233 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
234 const char *initrd_filename
,
239 long initrd_size
, kernel_size
;
242 linux_boot
= (kernel_filename
!= NULL
);
253 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
254 NULL
, NULL
, NULL
, 1, EM_SPARC
, 0, 0);
256 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
257 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
260 kernel_size
= load_image_targphys(kernel_filename
,
262 RAM_size
- KERNEL_LOAD_ADDR
);
263 if (kernel_size
< 0) {
264 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
271 if (initrd_filename
) {
272 initrd_size
= load_image_targphys(initrd_filename
,
274 RAM_size
- INITRD_LOAD_ADDR
);
275 if (initrd_size
< 0) {
276 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
281 if (initrd_size
> 0) {
282 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
283 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
284 if (ldl_p(ptr
) == 0x48647253) { // HdrS
285 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
286 stl_p(ptr
+ 20, initrd_size
);
295 static void *iommu_init(hwaddr addr
, uint32_t version
, qemu_irq irq
)
300 dev
= qdev_create(NULL
, "iommu");
301 qdev_prop_set_uint32(dev
, "version", version
);
302 qdev_init_nofail(dev
);
303 s
= SYS_BUS_DEVICE(dev
);
304 sysbus_connect_irq(s
, 0, irq
);
305 sysbus_mmio_map(s
, 0, addr
);
310 static void *sparc32_dma_init(hwaddr daddr
, qemu_irq parent_irq
,
311 void *iommu
, qemu_irq
*dev_irq
, int is_ledma
)
316 dev
= qdev_create(NULL
, "sparc32_dma");
317 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
318 qdev_prop_set_uint32(dev
, "is_ledma", is_ledma
);
319 qdev_init_nofail(dev
);
320 s
= SYS_BUS_DEVICE(dev
);
321 sysbus_connect_irq(s
, 0, parent_irq
);
322 *dev_irq
= qdev_get_gpio_in(dev
, 0);
323 sysbus_mmio_map(s
, 0, daddr
);
328 static void lance_init(NICInfo
*nd
, hwaddr leaddr
,
329 void *dma_opaque
, qemu_irq irq
)
335 qemu_check_nic_model(&nd_table
[0], "lance");
337 dev
= qdev_create(NULL
, "lance");
338 qdev_set_nic_properties(dev
, nd
);
339 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
340 qdev_init_nofail(dev
);
341 s
= SYS_BUS_DEVICE(dev
);
342 sysbus_mmio_map(s
, 0, leaddr
);
343 sysbus_connect_irq(s
, 0, irq
);
344 reset
= qdev_get_gpio_in(dev
, 0);
345 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
348 static DeviceState
*slavio_intctl_init(hwaddr addr
,
350 qemu_irq
**parent_irq
)
356 dev
= qdev_create(NULL
, "slavio_intctl");
357 qdev_init_nofail(dev
);
359 s
= SYS_BUS_DEVICE(dev
);
361 for (i
= 0; i
< MAX_CPUS
; i
++) {
362 for (j
= 0; j
< MAX_PILS
; j
++) {
363 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
366 sysbus_mmio_map(s
, 0, addrg
);
367 for (i
= 0; i
< MAX_CPUS
; i
++) {
368 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
374 #define SYS_TIMER_OFFSET 0x10000ULL
375 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
377 static void slavio_timer_init_all(hwaddr addr
, qemu_irq master_irq
,
378 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
384 dev
= qdev_create(NULL
, "slavio_timer");
385 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
386 qdev_init_nofail(dev
);
387 s
= SYS_BUS_DEVICE(dev
);
388 sysbus_connect_irq(s
, 0, master_irq
);
389 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
391 for (i
= 0; i
< MAX_CPUS
; i
++) {
392 sysbus_mmio_map(s
, i
+ 1, addr
+ (hwaddr
)CPU_TIMER_OFFSET(i
));
393 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
397 static qemu_irq slavio_system_powerdown
;
399 static void slavio_powerdown_req(Notifier
*n
, void *opaque
)
401 qemu_irq_raise(slavio_system_powerdown
);
404 static Notifier slavio_system_powerdown_notifier
= {
405 .notify
= slavio_powerdown_req
408 #define MISC_LEDS 0x01600000
409 #define MISC_CFG 0x01800000
410 #define MISC_DIAG 0x01a00000
411 #define MISC_MDM 0x01b00000
412 #define MISC_SYS 0x01f00000
414 static void slavio_misc_init(hwaddr base
,
416 hwaddr aux2_base
, qemu_irq irq
,
422 dev
= qdev_create(NULL
, "slavio_misc");
423 qdev_init_nofail(dev
);
424 s
= SYS_BUS_DEVICE(dev
);
426 /* 8 bit registers */
428 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
430 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
432 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
433 /* 16 bit registers */
434 /* ss600mp diag LEDs */
435 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
436 /* 32 bit registers */
438 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
441 /* AUX 1 (Misc System Functions) */
442 sysbus_mmio_map(s
, 5, aux1_base
);
445 /* AUX 2 (Software Powerdown Control) */
446 sysbus_mmio_map(s
, 6, aux2_base
);
448 sysbus_connect_irq(s
, 0, irq
);
449 sysbus_connect_irq(s
, 1, fdc_tc
);
450 slavio_system_powerdown
= qdev_get_gpio_in(dev
, 0);
451 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier
);
454 static void ecc_init(hwaddr base
, qemu_irq irq
, uint32_t version
)
459 dev
= qdev_create(NULL
, "eccmemctl");
460 qdev_prop_set_uint32(dev
, "version", version
);
461 qdev_init_nofail(dev
);
462 s
= SYS_BUS_DEVICE(dev
);
463 sysbus_connect_irq(s
, 0, irq
);
464 sysbus_mmio_map(s
, 0, base
);
465 if (version
== 0) { // SS-600MP only
466 sysbus_mmio_map(s
, 1, base
+ 0x1000);
470 static void apc_init(hwaddr power_base
, qemu_irq cpu_halt
)
475 dev
= qdev_create(NULL
, "apc");
476 qdev_init_nofail(dev
);
477 s
= SYS_BUS_DEVICE(dev
);
478 /* Power management (APC) XXX: not a Slavio device */
479 sysbus_mmio_map(s
, 0, power_base
);
480 sysbus_connect_irq(s
, 0, cpu_halt
);
483 static void tcx_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
484 int height
, int depth
)
489 dev
= qdev_create(NULL
, "SUNW,tcx");
490 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
491 qdev_prop_set_uint16(dev
, "width", width
);
492 qdev_prop_set_uint16(dev
, "height", height
);
493 qdev_prop_set_uint16(dev
, "depth", depth
);
494 qdev_init_nofail(dev
);
495 s
= SYS_BUS_DEVICE(dev
);
497 /* 10/ROM : FCode ROM */
498 sysbus_mmio_map(s
, 0, addr
);
499 /* 2/STIP : Stipple */
500 sysbus_mmio_map(s
, 1, addr
+ 0x04000000ULL
);
501 /* 3/BLIT : Blitter */
502 sysbus_mmio_map(s
, 2, addr
+ 0x06000000ULL
);
503 /* 5/RSTIP : Raw Stipple */
504 sysbus_mmio_map(s
, 3, addr
+ 0x0c000000ULL
);
505 /* 6/RBLIT : Raw Blitter */
506 sysbus_mmio_map(s
, 4, addr
+ 0x0e000000ULL
);
507 /* 7/TEC : Transform Engine */
508 sysbus_mmio_map(s
, 5, addr
+ 0x00700000ULL
);
510 sysbus_mmio_map(s
, 6, addr
+ 0x00200000ULL
);
513 sysbus_mmio_map(s
, 7, addr
+ 0x00300000ULL
);
515 sysbus_mmio_map(s
, 7, addr
+ 0x00301000ULL
);
518 sysbus_mmio_map(s
, 8, addr
+ 0x00240000ULL
);
520 sysbus_mmio_map(s
, 9, addr
+ 0x00280000ULL
);
521 /* 0/DFB8 : 8-bit plane */
522 sysbus_mmio_map(s
, 10, addr
+ 0x00800000ULL
);
523 /* 1/DFB24 : 24bit plane */
524 sysbus_mmio_map(s
, 11, addr
+ 0x02000000ULL
);
525 /* 4/RDFB32: Raw framebuffer. Control plane */
526 sysbus_mmio_map(s
, 12, addr
+ 0x0a000000ULL
);
527 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
529 sysbus_mmio_map(s
, 13, addr
+ 0x00301000ULL
);
532 sysbus_connect_irq(s
, 0, irq
);
535 static void cg3_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
536 int height
, int depth
)
541 dev
= qdev_create(NULL
, "cgthree");
542 qdev_prop_set_uint32(dev
, "vram-size", vram_size
);
543 qdev_prop_set_uint16(dev
, "width", width
);
544 qdev_prop_set_uint16(dev
, "height", height
);
545 qdev_prop_set_uint16(dev
, "depth", depth
);
546 qdev_init_nofail(dev
);
547 s
= SYS_BUS_DEVICE(dev
);
550 sysbus_mmio_map(s
, 0, addr
);
552 sysbus_mmio_map(s
, 1, addr
+ 0x400000ULL
);
554 sysbus_mmio_map(s
, 2, addr
+ 0x800000ULL
);
556 sysbus_connect_irq(s
, 0, irq
);
559 /* NCR89C100/MACIO Internal ID register */
561 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
563 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
565 static void idreg_init(hwaddr addr
)
570 dev
= qdev_create(NULL
, TYPE_MACIO_ID_REGISTER
);
571 qdev_init_nofail(dev
);
572 s
= SYS_BUS_DEVICE(dev
);
574 sysbus_mmio_map(s
, 0, addr
);
575 cpu_physical_memory_write_rom(&address_space_memory
,
576 addr
, idreg_data
, sizeof(idreg_data
));
579 #define MACIO_ID_REGISTER(obj) \
580 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
582 typedef struct IDRegState
{
583 SysBusDevice parent_obj
;
588 static void idreg_init1(Object
*obj
)
590 IDRegState
*s
= MACIO_ID_REGISTER(obj
);
591 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
593 memory_region_init_ram_nomigrate(&s
->mem
, obj
,
594 "sun4m.idreg", sizeof(idreg_data
), &error_fatal
);
595 vmstate_register_ram_global(&s
->mem
);
596 memory_region_set_readonly(&s
->mem
, true);
597 sysbus_init_mmio(dev
, &s
->mem
);
600 static const TypeInfo idreg_info
= {
601 .name
= TYPE_MACIO_ID_REGISTER
,
602 .parent
= TYPE_SYS_BUS_DEVICE
,
603 .instance_size
= sizeof(IDRegState
),
604 .instance_init
= idreg_init1
,
607 #define TYPE_TCX_AFX "tcx_afx"
608 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
610 typedef struct AFXState
{
611 SysBusDevice parent_obj
;
616 /* SS-5 TCX AFX register */
617 static void afx_init(hwaddr addr
)
622 dev
= qdev_create(NULL
, TYPE_TCX_AFX
);
623 qdev_init_nofail(dev
);
624 s
= SYS_BUS_DEVICE(dev
);
626 sysbus_mmio_map(s
, 0, addr
);
629 static void afx_init1(Object
*obj
)
631 AFXState
*s
= TCX_AFX(obj
);
632 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
634 memory_region_init_ram_nomigrate(&s
->mem
, obj
, "sun4m.afx", 4, &error_fatal
);
635 vmstate_register_ram_global(&s
->mem
);
636 sysbus_init_mmio(dev
, &s
->mem
);
639 static const TypeInfo afx_info
= {
640 .name
= TYPE_TCX_AFX
,
641 .parent
= TYPE_SYS_BUS_DEVICE
,
642 .instance_size
= sizeof(AFXState
),
643 .instance_init
= afx_init1
,
646 #define TYPE_OPENPROM "openprom"
647 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
649 typedef struct PROMState
{
650 SysBusDevice parent_obj
;
655 /* Boot PROM (OpenBIOS) */
656 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
658 hwaddr
*base_addr
= (hwaddr
*)opaque
;
659 return addr
+ *base_addr
- PROM_VADDR
;
662 static void prom_init(hwaddr addr
, const char *bios_name
)
669 dev
= qdev_create(NULL
, TYPE_OPENPROM
);
670 qdev_init_nofail(dev
);
671 s
= SYS_BUS_DEVICE(dev
);
673 sysbus_mmio_map(s
, 0, addr
);
676 if (bios_name
== NULL
) {
677 bios_name
= PROM_FILENAME
;
679 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
681 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
682 NULL
, NULL
, 1, EM_SPARC
, 0, 0);
683 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
684 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
690 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
691 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
696 static void prom_init1(Object
*obj
)
698 PROMState
*s
= OPENPROM(obj
);
699 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
701 memory_region_init_ram_nomigrate(&s
->prom
, obj
, "sun4m.prom", PROM_SIZE_MAX
,
703 vmstate_register_ram_global(&s
->prom
);
704 memory_region_set_readonly(&s
->prom
, true);
705 sysbus_init_mmio(dev
, &s
->prom
);
708 static Property prom_properties
[] = {
709 {/* end of property list */},
712 static void prom_class_init(ObjectClass
*klass
, void *data
)
714 DeviceClass
*dc
= DEVICE_CLASS(klass
);
716 dc
->props
= prom_properties
;
719 static const TypeInfo prom_info
= {
720 .name
= TYPE_OPENPROM
,
721 .parent
= TYPE_SYS_BUS_DEVICE
,
722 .instance_size
= sizeof(PROMState
),
723 .class_init
= prom_class_init
,
724 .instance_init
= prom_init1
,
727 #define TYPE_SUN4M_MEMORY "memory"
728 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
730 typedef struct RamDevice
{
731 SysBusDevice parent_obj
;
738 static void ram_realize(DeviceState
*dev
, Error
**errp
)
740 RamDevice
*d
= SUN4M_RAM(dev
);
741 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
743 memory_region_allocate_system_memory(&d
->ram
, OBJECT(d
), "sun4m.ram",
745 sysbus_init_mmio(sbd
, &d
->ram
);
748 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
,
756 if ((uint64_t)RAM_size
> max_mem
) {
758 "qemu: Too much memory for this machine: %d, maximum %d\n",
759 (unsigned int)(RAM_size
/ (1024 * 1024)),
760 (unsigned int)(max_mem
/ (1024 * 1024)));
763 dev
= qdev_create(NULL
, "memory");
764 s
= SYS_BUS_DEVICE(dev
);
768 qdev_init_nofail(dev
);
770 sysbus_mmio_map(s
, 0, addr
);
773 static Property ram_properties
[] = {
774 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
775 DEFINE_PROP_END_OF_LIST(),
778 static void ram_class_init(ObjectClass
*klass
, void *data
)
780 DeviceClass
*dc
= DEVICE_CLASS(klass
);
782 dc
->realize
= ram_realize
;
783 dc
->props
= ram_properties
;
786 static const TypeInfo ram_info
= {
787 .name
= TYPE_SUN4M_MEMORY
,
788 .parent
= TYPE_SYS_BUS_DEVICE
,
789 .instance_size
= sizeof(RamDevice
),
790 .class_init
= ram_class_init
,
793 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
794 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
800 cpu
= cpu_sparc_init(cpu_model
);
802 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
807 cpu_sparc_set_id(env
, id
);
809 qemu_register_reset(main_cpu_reset
, cpu
);
811 qemu_register_reset(secondary_cpu_reset
, cpu
);
815 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, cpu
, MAX_PILS
);
816 env
->prom_addr
= prom_addr
;
819 static void dummy_fdc_tc(void *opaque
, int irq
, int level
)
823 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
,
824 MachineState
*machine
)
826 DeviceState
*slavio_intctl
;
827 const char *cpu_model
= machine
->cpu_model
;
829 void *iommu
, *espdma
, *ledma
, *nvram
;
830 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
831 espdma_irq
, ledma_irq
;
832 qemu_irq esp_reset
, dma_enable
;
834 unsigned long kernel_size
;
835 DriveInfo
*fd
[MAX_FD
];
837 unsigned int num_vsimms
;
841 cpu_model
= hwdef
->default_cpu_model
;
843 for(i
= 0; i
< smp_cpus
; i
++) {
844 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
847 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
848 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
852 ram_init(0, machine
->ram_size
, hwdef
->max_mem
);
853 /* models without ECC don't trap when missing ram is accessed */
854 if (!hwdef
->ecc_base
) {
855 empty_slot_init(machine
->ram_size
, hwdef
->max_mem
- machine
->ram_size
);
858 prom_init(hwdef
->slavio_base
, bios_name
);
860 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
861 hwdef
->intctl_base
+ 0x10000ULL
,
864 for (i
= 0; i
< 32; i
++) {
865 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
867 for (i
= 0; i
< MAX_CPUS
; i
++) {
868 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
871 if (hwdef
->idreg_base
) {
872 idreg_init(hwdef
->idreg_base
);
875 if (hwdef
->afx_base
) {
876 afx_init(hwdef
->afx_base
);
879 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
882 if (hwdef
->iommu_pad_base
) {
883 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
884 Software shouldn't use aliased addresses, neither should it crash
885 when does. Using empty_slot instead of aliasing can help with
886 debugging such accesses */
887 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
890 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
891 iommu
, &espdma_irq
, 0);
893 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
894 slavio_irq
[16], iommu
, &ledma_irq
, 1);
896 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
897 error_report("Unsupported depth: %d", graphic_depth
);
901 if (num_vsimms
== 0) {
902 if (vga_interface_type
== VGA_CG3
) {
903 if (graphic_depth
!= 8) {
904 error_report("Unsupported depth: %d", graphic_depth
);
908 if (!(graphic_width
== 1024 && graphic_height
== 768) &&
909 !(graphic_width
== 1152 && graphic_height
== 900)) {
910 error_report("Unsupported resolution: %d x %d", graphic_width
,
916 cg3_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
917 graphic_width
, graphic_height
, graphic_depth
);
919 /* If no display specified, default to TCX */
920 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
921 error_report("Unsupported depth: %d", graphic_depth
);
925 if (!(graphic_width
== 1024 && graphic_height
== 768)) {
926 error_report("Unsupported resolution: %d x %d",
927 graphic_width
, graphic_height
);
931 tcx_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
932 graphic_width
, graphic_height
, graphic_depth
);
936 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
937 /* vsimm registers probed by OBP */
938 if (hwdef
->vsimm
[i
].reg_base
) {
939 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
943 if (hwdef
->sx_base
) {
944 empty_slot_init(hwdef
->sx_base
, 0x2000);
947 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
949 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 1968, 8);
951 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
953 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
954 !machine
->enable_graphics
, ESCC_CLOCK
, 1);
955 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
956 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
957 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
958 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
960 if (hwdef
->apc_base
) {
961 apc_init(hwdef
->apc_base
, qemu_allocate_irq(cpu_halt_signal
, NULL
, 0));
964 if (hwdef
->fd_base
) {
965 /* there is zero or one floppy drive */
966 memset(fd
, 0, sizeof(fd
));
967 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
968 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
971 fdc_tc
= qemu_allocate_irq(dummy_fdc_tc
, NULL
, 0);
974 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
975 slavio_irq
[30], fdc_tc
);
977 esp_init(hwdef
->esp_base
, 2,
978 espdma_memory_read
, espdma_memory_write
,
979 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
981 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
982 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
984 if (hwdef
->cs_base
) {
985 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
989 if (hwdef
->dbri_base
) {
990 /* ISDN chip with attached CS4215 audio codec */
992 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
994 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
997 if (hwdef
->bpp_base
) {
999 empty_slot_init(hwdef
->bpp_base
, 0x20);
1002 kernel_size
= sun4m_load_kernel(machine
->kernel_filename
,
1003 machine
->initrd_filename
,
1006 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, machine
->kernel_cmdline
,
1007 machine
->boot_order
, machine
->ram_size
, kernel_size
,
1008 graphic_width
, graphic_height
, graphic_depth
,
1009 hwdef
->nvram_machine_id
, "Sun4m");
1011 if (hwdef
->ecc_base
)
1012 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
1013 hwdef
->ecc_version
);
1015 fw_cfg
= fw_cfg_init_mem(CFG_ADDR
, CFG_ADDR
+ 2);
1016 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
1017 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
1018 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1019 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1020 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1021 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_WIDTH
, graphic_width
);
1022 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_HEIGHT
, graphic_height
);
1023 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1024 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1025 if (machine
->kernel_cmdline
) {
1026 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1027 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
,
1028 machine
->kernel_cmdline
);
1029 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
1030 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1031 strlen(machine
->kernel_cmdline
) + 1);
1033 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1034 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1036 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1037 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1038 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
1039 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1054 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1057 .iommu_base
= 0x10000000,
1058 .iommu_pad_base
= 0x10004000,
1059 .iommu_pad_len
= 0x0fffb000,
1060 .tcx_base
= 0x50000000,
1061 .cs_base
= 0x6c000000,
1062 .slavio_base
= 0x70000000,
1063 .ms_kb_base
= 0x71000000,
1064 .serial_base
= 0x71100000,
1065 .nvram_base
= 0x71200000,
1066 .fd_base
= 0x71400000,
1067 .counter_base
= 0x71d00000,
1068 .intctl_base
= 0x71e00000,
1069 .idreg_base
= 0x78000000,
1070 .dma_base
= 0x78400000,
1071 .esp_base
= 0x78800000,
1072 .le_base
= 0x78c00000,
1073 .apc_base
= 0x6a000000,
1074 .afx_base
= 0x6e000000,
1075 .aux1_base
= 0x71900000,
1076 .aux2_base
= 0x71910000,
1077 .nvram_machine_id
= 0x80,
1078 .machine_id
= ss5_id
,
1079 .iommu_version
= 0x05000000,
1080 .max_mem
= 0x10000000,
1081 .default_cpu_model
= "Fujitsu MB86904",
1085 .iommu_base
= 0xfe0000000ULL
,
1086 .tcx_base
= 0xe20000000ULL
,
1087 .slavio_base
= 0xff0000000ULL
,
1088 .ms_kb_base
= 0xff1000000ULL
,
1089 .serial_base
= 0xff1100000ULL
,
1090 .nvram_base
= 0xff1200000ULL
,
1091 .fd_base
= 0xff1700000ULL
,
1092 .counter_base
= 0xff1300000ULL
,
1093 .intctl_base
= 0xff1400000ULL
,
1094 .idreg_base
= 0xef0000000ULL
,
1095 .dma_base
= 0xef0400000ULL
,
1096 .esp_base
= 0xef0800000ULL
,
1097 .le_base
= 0xef0c00000ULL
,
1098 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1099 .aux1_base
= 0xff1800000ULL
,
1100 .aux2_base
= 0xff1a01000ULL
,
1101 .ecc_base
= 0xf00000000ULL
,
1102 .ecc_version
= 0x10000000, // version 0, implementation 1
1103 .nvram_machine_id
= 0x72,
1104 .machine_id
= ss10_id
,
1105 .iommu_version
= 0x03000000,
1106 .max_mem
= 0xf00000000ULL
,
1107 .default_cpu_model
= "TI SuperSparc II",
1111 .iommu_base
= 0xfe0000000ULL
,
1112 .tcx_base
= 0xe20000000ULL
,
1113 .slavio_base
= 0xff0000000ULL
,
1114 .ms_kb_base
= 0xff1000000ULL
,
1115 .serial_base
= 0xff1100000ULL
,
1116 .nvram_base
= 0xff1200000ULL
,
1117 .counter_base
= 0xff1300000ULL
,
1118 .intctl_base
= 0xff1400000ULL
,
1119 .dma_base
= 0xef0081000ULL
,
1120 .esp_base
= 0xef0080000ULL
,
1121 .le_base
= 0xef0060000ULL
,
1122 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1123 .aux1_base
= 0xff1800000ULL
,
1124 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1125 .ecc_base
= 0xf00000000ULL
,
1126 .ecc_version
= 0x00000000, // version 0, implementation 0
1127 .nvram_machine_id
= 0x71,
1128 .machine_id
= ss600mp_id
,
1129 .iommu_version
= 0x01000000,
1130 .max_mem
= 0xf00000000ULL
,
1131 .default_cpu_model
= "TI SuperSparc II",
1135 .iommu_base
= 0xfe0000000ULL
,
1136 .tcx_base
= 0xe20000000ULL
,
1137 .slavio_base
= 0xff0000000ULL
,
1138 .ms_kb_base
= 0xff1000000ULL
,
1139 .serial_base
= 0xff1100000ULL
,
1140 .nvram_base
= 0xff1200000ULL
,
1141 .fd_base
= 0xff1700000ULL
,
1142 .counter_base
= 0xff1300000ULL
,
1143 .intctl_base
= 0xff1400000ULL
,
1144 .idreg_base
= 0xef0000000ULL
,
1145 .dma_base
= 0xef0400000ULL
,
1146 .esp_base
= 0xef0800000ULL
,
1147 .le_base
= 0xef0c00000ULL
,
1148 .bpp_base
= 0xef4800000ULL
,
1149 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1150 .aux1_base
= 0xff1800000ULL
,
1151 .aux2_base
= 0xff1a01000ULL
,
1152 .dbri_base
= 0xee0000000ULL
,
1153 .sx_base
= 0xf80000000ULL
,
1156 .reg_base
= 0x9c000000ULL
,
1157 .vram_base
= 0xfc000000ULL
1159 .reg_base
= 0x90000000ULL
,
1160 .vram_base
= 0xf0000000ULL
1162 .reg_base
= 0x94000000ULL
1164 .reg_base
= 0x98000000ULL
1167 .ecc_base
= 0xf00000000ULL
,
1168 .ecc_version
= 0x20000000, // version 0, implementation 2
1169 .nvram_machine_id
= 0x72,
1170 .machine_id
= ss20_id
,
1171 .iommu_version
= 0x13000000,
1172 .max_mem
= 0xf00000000ULL
,
1173 .default_cpu_model
= "TI SuperSparc II",
1177 .iommu_base
= 0x10000000,
1178 .tcx_base
= 0x50000000,
1179 .slavio_base
= 0x70000000,
1180 .ms_kb_base
= 0x71000000,
1181 .serial_base
= 0x71100000,
1182 .nvram_base
= 0x71200000,
1183 .fd_base
= 0x71400000,
1184 .counter_base
= 0x71d00000,
1185 .intctl_base
= 0x71e00000,
1186 .idreg_base
= 0x78000000,
1187 .dma_base
= 0x78400000,
1188 .esp_base
= 0x78800000,
1189 .le_base
= 0x78c00000,
1190 .apc_base
= 0x71300000, // pmc
1191 .aux1_base
= 0x71900000,
1192 .aux2_base
= 0x71910000,
1193 .nvram_machine_id
= 0x80,
1194 .machine_id
= vger_id
,
1195 .iommu_version
= 0x05000000,
1196 .max_mem
= 0x10000000,
1197 .default_cpu_model
= "Fujitsu MB86904",
1201 .iommu_base
= 0x10000000,
1202 .iommu_pad_base
= 0x10004000,
1203 .iommu_pad_len
= 0x0fffb000,
1204 .tcx_base
= 0x50000000,
1205 .slavio_base
= 0x70000000,
1206 .ms_kb_base
= 0x71000000,
1207 .serial_base
= 0x71100000,
1208 .nvram_base
= 0x71200000,
1209 .fd_base
= 0x71400000,
1210 .counter_base
= 0x71d00000,
1211 .intctl_base
= 0x71e00000,
1212 .idreg_base
= 0x78000000,
1213 .dma_base
= 0x78400000,
1214 .esp_base
= 0x78800000,
1215 .le_base
= 0x78c00000,
1216 .aux1_base
= 0x71900000,
1217 .aux2_base
= 0x71910000,
1218 .nvram_machine_id
= 0x80,
1219 .machine_id
= lx_id
,
1220 .iommu_version
= 0x04000000,
1221 .max_mem
= 0x10000000,
1222 .default_cpu_model
= "TI MicroSparc I",
1226 .iommu_base
= 0x10000000,
1227 .tcx_base
= 0x50000000,
1228 .cs_base
= 0x6c000000,
1229 .slavio_base
= 0x70000000,
1230 .ms_kb_base
= 0x71000000,
1231 .serial_base
= 0x71100000,
1232 .nvram_base
= 0x71200000,
1233 .fd_base
= 0x71400000,
1234 .counter_base
= 0x71d00000,
1235 .intctl_base
= 0x71e00000,
1236 .idreg_base
= 0x78000000,
1237 .dma_base
= 0x78400000,
1238 .esp_base
= 0x78800000,
1239 .le_base
= 0x78c00000,
1240 .apc_base
= 0x6a000000,
1241 .aux1_base
= 0x71900000,
1242 .aux2_base
= 0x71910000,
1243 .nvram_machine_id
= 0x80,
1244 .machine_id
= ss4_id
,
1245 .iommu_version
= 0x05000000,
1246 .max_mem
= 0x10000000,
1247 .default_cpu_model
= "Fujitsu MB86904",
1251 .iommu_base
= 0x10000000,
1252 .tcx_base
= 0x50000000,
1253 .slavio_base
= 0x70000000,
1254 .ms_kb_base
= 0x71000000,
1255 .serial_base
= 0x71100000,
1256 .nvram_base
= 0x71200000,
1257 .fd_base
= 0x71400000,
1258 .counter_base
= 0x71d00000,
1259 .intctl_base
= 0x71e00000,
1260 .idreg_base
= 0x78000000,
1261 .dma_base
= 0x78400000,
1262 .esp_base
= 0x78800000,
1263 .le_base
= 0x78c00000,
1264 .apc_base
= 0x6a000000,
1265 .aux1_base
= 0x71900000,
1266 .aux2_base
= 0x71910000,
1267 .nvram_machine_id
= 0x80,
1268 .machine_id
= scls_id
,
1269 .iommu_version
= 0x05000000,
1270 .max_mem
= 0x10000000,
1271 .default_cpu_model
= "TI MicroSparc I",
1275 .iommu_base
= 0x10000000,
1276 .tcx_base
= 0x50000000, // XXX
1277 .slavio_base
= 0x70000000,
1278 .ms_kb_base
= 0x71000000,
1279 .serial_base
= 0x71100000,
1280 .nvram_base
= 0x71200000,
1281 .fd_base
= 0x71400000,
1282 .counter_base
= 0x71d00000,
1283 .intctl_base
= 0x71e00000,
1284 .idreg_base
= 0x78000000,
1285 .dma_base
= 0x78400000,
1286 .esp_base
= 0x78800000,
1287 .le_base
= 0x78c00000,
1288 .apc_base
= 0x6a000000,
1289 .aux1_base
= 0x71900000,
1290 .aux2_base
= 0x71910000,
1291 .nvram_machine_id
= 0x80,
1292 .machine_id
= sbook_id
,
1293 .iommu_version
= 0x05000000,
1294 .max_mem
= 0x10000000,
1295 .default_cpu_model
= "TI MicroSparc I",
1299 /* SPARCstation 5 hardware initialisation */
1300 static void ss5_init(MachineState
*machine
)
1302 sun4m_hw_init(&sun4m_hwdefs
[0], machine
);
1305 /* SPARCstation 10 hardware initialisation */
1306 static void ss10_init(MachineState
*machine
)
1308 sun4m_hw_init(&sun4m_hwdefs
[1], machine
);
1311 /* SPARCserver 600MP hardware initialisation */
1312 static void ss600mp_init(MachineState
*machine
)
1314 sun4m_hw_init(&sun4m_hwdefs
[2], machine
);
1317 /* SPARCstation 20 hardware initialisation */
1318 static void ss20_init(MachineState
*machine
)
1320 sun4m_hw_init(&sun4m_hwdefs
[3], machine
);
1323 /* SPARCstation Voyager hardware initialisation */
1324 static void vger_init(MachineState
*machine
)
1326 sun4m_hw_init(&sun4m_hwdefs
[4], machine
);
1329 /* SPARCstation LX hardware initialisation */
1330 static void ss_lx_init(MachineState
*machine
)
1332 sun4m_hw_init(&sun4m_hwdefs
[5], machine
);
1335 /* SPARCstation 4 hardware initialisation */
1336 static void ss4_init(MachineState
*machine
)
1338 sun4m_hw_init(&sun4m_hwdefs
[6], machine
);
1341 /* SPARCClassic hardware initialisation */
1342 static void scls_init(MachineState
*machine
)
1344 sun4m_hw_init(&sun4m_hwdefs
[7], machine
);
1347 /* SPARCbook hardware initialisation */
1348 static void sbook_init(MachineState
*machine
)
1350 sun4m_hw_init(&sun4m_hwdefs
[8], machine
);
1353 static void ss5_class_init(ObjectClass
*oc
, void *data
)
1355 MachineClass
*mc
= MACHINE_CLASS(oc
);
1357 mc
->desc
= "Sun4m platform, SPARCstation 5";
1358 mc
->init
= ss5_init
;
1359 mc
->block_default_type
= IF_SCSI
;
1361 mc
->default_boot_order
= "c";
1364 static const TypeInfo ss5_type
= {
1365 .name
= MACHINE_TYPE_NAME("SS-5"),
1366 .parent
= TYPE_MACHINE
,
1367 .class_init
= ss5_class_init
,
1370 static void ss10_class_init(ObjectClass
*oc
, void *data
)
1372 MachineClass
*mc
= MACHINE_CLASS(oc
);
1374 mc
->desc
= "Sun4m platform, SPARCstation 10";
1375 mc
->init
= ss10_init
;
1376 mc
->block_default_type
= IF_SCSI
;
1378 mc
->default_boot_order
= "c";
1381 static const TypeInfo ss10_type
= {
1382 .name
= MACHINE_TYPE_NAME("SS-10"),
1383 .parent
= TYPE_MACHINE
,
1384 .class_init
= ss10_class_init
,
1387 static void ss600mp_class_init(ObjectClass
*oc
, void *data
)
1389 MachineClass
*mc
= MACHINE_CLASS(oc
);
1391 mc
->desc
= "Sun4m platform, SPARCserver 600MP";
1392 mc
->init
= ss600mp_init
;
1393 mc
->block_default_type
= IF_SCSI
;
1395 mc
->default_boot_order
= "c";
1398 static const TypeInfo ss600mp_type
= {
1399 .name
= MACHINE_TYPE_NAME("SS-600MP"),
1400 .parent
= TYPE_MACHINE
,
1401 .class_init
= ss600mp_class_init
,
1404 static void ss20_class_init(ObjectClass
*oc
, void *data
)
1406 MachineClass
*mc
= MACHINE_CLASS(oc
);
1408 mc
->desc
= "Sun4m platform, SPARCstation 20";
1409 mc
->init
= ss20_init
;
1410 mc
->block_default_type
= IF_SCSI
;
1412 mc
->default_boot_order
= "c";
1415 static const TypeInfo ss20_type
= {
1416 .name
= MACHINE_TYPE_NAME("SS-20"),
1417 .parent
= TYPE_MACHINE
,
1418 .class_init
= ss20_class_init
,
1421 static void voyager_class_init(ObjectClass
*oc
, void *data
)
1423 MachineClass
*mc
= MACHINE_CLASS(oc
);
1425 mc
->desc
= "Sun4m platform, SPARCstation Voyager";
1426 mc
->init
= vger_init
;
1427 mc
->block_default_type
= IF_SCSI
;
1428 mc
->default_boot_order
= "c";
1431 static const TypeInfo voyager_type
= {
1432 .name
= MACHINE_TYPE_NAME("Voyager"),
1433 .parent
= TYPE_MACHINE
,
1434 .class_init
= voyager_class_init
,
1437 static void ss_lx_class_init(ObjectClass
*oc
, void *data
)
1439 MachineClass
*mc
= MACHINE_CLASS(oc
);
1441 mc
->desc
= "Sun4m platform, SPARCstation LX";
1442 mc
->init
= ss_lx_init
;
1443 mc
->block_default_type
= IF_SCSI
;
1444 mc
->default_boot_order
= "c";
1447 static const TypeInfo ss_lx_type
= {
1448 .name
= MACHINE_TYPE_NAME("LX"),
1449 .parent
= TYPE_MACHINE
,
1450 .class_init
= ss_lx_class_init
,
1453 static void ss4_class_init(ObjectClass
*oc
, void *data
)
1455 MachineClass
*mc
= MACHINE_CLASS(oc
);
1457 mc
->desc
= "Sun4m platform, SPARCstation 4";
1458 mc
->init
= ss4_init
;
1459 mc
->block_default_type
= IF_SCSI
;
1460 mc
->default_boot_order
= "c";
1463 static const TypeInfo ss4_type
= {
1464 .name
= MACHINE_TYPE_NAME("SS-4"),
1465 .parent
= TYPE_MACHINE
,
1466 .class_init
= ss4_class_init
,
1469 static void scls_class_init(ObjectClass
*oc
, void *data
)
1471 MachineClass
*mc
= MACHINE_CLASS(oc
);
1473 mc
->desc
= "Sun4m platform, SPARCClassic";
1474 mc
->init
= scls_init
;
1475 mc
->block_default_type
= IF_SCSI
;
1476 mc
->default_boot_order
= "c";
1479 static const TypeInfo scls_type
= {
1480 .name
= MACHINE_TYPE_NAME("SPARCClassic"),
1481 .parent
= TYPE_MACHINE
,
1482 .class_init
= scls_class_init
,
1485 static void sbook_class_init(ObjectClass
*oc
, void *data
)
1487 MachineClass
*mc
= MACHINE_CLASS(oc
);
1489 mc
->desc
= "Sun4m platform, SPARCbook";
1490 mc
->init
= sbook_init
;
1491 mc
->block_default_type
= IF_SCSI
;
1492 mc
->default_boot_order
= "c";
1495 static const TypeInfo sbook_type
= {
1496 .name
= MACHINE_TYPE_NAME("SPARCbook"),
1497 .parent
= TYPE_MACHINE
,
1498 .class_init
= sbook_class_init
,
1501 static void sun4m_register_types(void)
1503 type_register_static(&idreg_info
);
1504 type_register_static(&afx_info
);
1505 type_register_static(&prom_info
);
1506 type_register_static(&ram_info
);
1508 type_register_static(&ss5_type
);
1509 type_register_static(&ss10_type
);
1510 type_register_static(&ss600mp_type
);
1511 type_register_static(&ss20_type
);
1512 type_register_static(&voyager_type
);
1513 type_register_static(&ss_lx_type
);
1514 type_register_static(&ss4_type
);
1515 type_register_static(&scls_type
);
1516 type_register_static(&sbook_type
);
1519 type_init(sun4m_register_types
)