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target-ppc: implement branch-less divd[o][.]
[qemu/ar7.git] / target-ppc / translate.c
blob5fe7a9dbce8609d263496a5ff8efcf53f9ecf64a
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip - 4);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 typedef struct opcode_t {
380 unsigned char opc1, opc2, opc3, opc4;
381 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
382 unsigned char pad[4];
383 #endif
384 opc_handler_t handler;
385 const char *oname;
386 } opcode_t;
387
388 /* Helpers for priv. check */
389 #define GEN_PRIV \
390 do { \
391 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
392 } while (0)
393
394 #if defined(CONFIG_USER_ONLY)
395 #define CHK_HV GEN_PRIV
396 #define CHK_SV GEN_PRIV
397 #define CHK_HVRM GEN_PRIV
398 #else
399 #define CHK_HV \
400 do { \
401 if (unlikely(ctx->pr || !ctx->hv)) { \
402 GEN_PRIV; \
403 } \
404 } while (0)
405 #define CHK_SV \
406 do { \
407 if (unlikely(ctx->pr)) { \
408 GEN_PRIV; \
409 } \
410 } while (0)
411 #define CHK_HVRM \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #endif
418
419 #define CHK_NONE
420
421
422 /*****************************************************************************/
423 /*** Instruction decoding ***/
424 #define EXTRACT_HELPER(name, shift, nb) \
425 static inline uint32_t name(uint32_t opcode) \
426 { \
427 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
428 }
429
430 #define EXTRACT_SHELPER(name, shift, nb) \
431 static inline int32_t name(uint32_t opcode) \
432 { \
433 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
437 static inline uint32_t name(uint32_t opcode) \
438 { \
439 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
440 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
441 }
442
443 #define EXTRACT_HELPER_DXFORM(name, \
444 d0_bits, shift_op_d0, shift_d0, \
445 d1_bits, shift_op_d1, shift_d1, \
446 d2_bits, shift_op_d2, shift_d2) \
447 static inline int16_t name(uint32_t opcode) \
448 { \
449 return \
450 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
451 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
452 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
453 }
454
455
456 /* Opcode part 1 */
457 EXTRACT_HELPER(opc1, 26, 6);
458 /* Opcode part 2 */
459 EXTRACT_HELPER(opc2, 1, 5);
460 /* Opcode part 3 */
461 EXTRACT_HELPER(opc3, 6, 5);
462 /* Opcode part 4 */
463 EXTRACT_HELPER(opc4, 16, 5);
464 /* Update Cr0 flags */
465 EXTRACT_HELPER(Rc, 0, 1);
466 /* Update Cr6 flags (Altivec) */
467 EXTRACT_HELPER(Rc21, 10, 1);
468 /* Destination */
469 EXTRACT_HELPER(rD, 21, 5);
470 /* Source */
471 EXTRACT_HELPER(rS, 21, 5);
472 /* First operand */
473 EXTRACT_HELPER(rA, 16, 5);
474 /* Second operand */
475 EXTRACT_HELPER(rB, 11, 5);
476 /* Third operand */
477 EXTRACT_HELPER(rC, 6, 5);
478 /*** Get CRn ***/
479 EXTRACT_HELPER(crfD, 23, 3);
480 EXTRACT_HELPER(crfS, 18, 3);
481 EXTRACT_HELPER(crbD, 21, 5);
482 EXTRACT_HELPER(crbA, 16, 5);
483 EXTRACT_HELPER(crbB, 11, 5);
484 /* SPR / TBL */
485 EXTRACT_HELPER(_SPR, 11, 10);
486 static inline uint32_t SPR(uint32_t opcode)
487 {
488 uint32_t sprn = _SPR(opcode);
489
490 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
491 }
492 /*** Get constants ***/
493 /* 16 bits signed immediate value */
494 EXTRACT_SHELPER(SIMM, 0, 16);
495 /* 16 bits unsigned immediate value */
496 EXTRACT_HELPER(UIMM, 0, 16);
497 /* 5 bits signed immediate value */
498 EXTRACT_HELPER(SIMM5, 16, 5);
499 /* 5 bits signed immediate value */
500 EXTRACT_HELPER(UIMM5, 16, 5);
501 /* Bit count */
502 EXTRACT_HELPER(NB, 11, 5);
503 /* Shift count */
504 EXTRACT_HELPER(SH, 11, 5);
505 /* Vector shift count */
506 EXTRACT_HELPER(VSH, 6, 4);
507 /* Mask start */
508 EXTRACT_HELPER(MB, 6, 5);
509 /* Mask end */
510 EXTRACT_HELPER(ME, 1, 5);
511 /* Trap operand */
512 EXTRACT_HELPER(TO, 21, 5);
513
514 EXTRACT_HELPER(CRM, 12, 8);
515
516 #ifndef CONFIG_USER_ONLY
517 EXTRACT_HELPER(SR, 16, 4);
518 #endif
519
520 /* mtfsf/mtfsfi */
521 EXTRACT_HELPER(FPBF, 23, 3);
522 EXTRACT_HELPER(FPIMM, 12, 4);
523 EXTRACT_HELPER(FPL, 25, 1);
524 EXTRACT_HELPER(FPFLM, 17, 8);
525 EXTRACT_HELPER(FPW, 16, 1);
526
527 /* addpcis */
528 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
529
530 /*** Jump target decoding ***/
531 /* Immediate address */
532 static inline target_ulong LI(uint32_t opcode)
533 {
534 return (opcode >> 0) & 0x03FFFFFC;
535 }
536
537 static inline uint32_t BD(uint32_t opcode)
538 {
539 return (opcode >> 0) & 0xFFFC;
540 }
541
542 EXTRACT_HELPER(BO, 21, 5);
543 EXTRACT_HELPER(BI, 16, 5);
544 /* Absolute/relative address */
545 EXTRACT_HELPER(AA, 1, 1);
546 /* Link */
547 EXTRACT_HELPER(LK, 0, 1);
548
549 /* DFP Z22-form */
550 EXTRACT_HELPER(DCM, 10, 6)
551
552 /* DFP Z23-form */
553 EXTRACT_HELPER(RMC, 9, 2)
554
555 /* Create a mask between <start> and <end> bits */
556 static inline target_ulong MASK(uint32_t start, uint32_t end)
557 {
558 target_ulong ret;
559
560 #if defined(TARGET_PPC64)
561 if (likely(start == 0)) {
562 ret = UINT64_MAX << (63 - end);
563 } else if (likely(end == 63)) {
564 ret = UINT64_MAX >> start;
565 }
566 #else
567 if (likely(start == 0)) {
568 ret = UINT32_MAX << (31 - end);
569 } else if (likely(end == 31)) {
570 ret = UINT32_MAX >> start;
571 }
572 #endif
573 else {
574 ret = (((target_ulong)(-1ULL)) >> (start)) ^
575 (((target_ulong)(-1ULL) >> (end)) >> 1);
576 if (unlikely(start > end))
577 return ~ret;
578 }
579
580 return ret;
581 }
582
583 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
585 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
586 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
587 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
588 EXTRACT_HELPER(DM, 8, 2);
589 EXTRACT_HELPER(UIM, 16, 2);
590 EXTRACT_HELPER(SHW, 8, 2);
591 EXTRACT_HELPER(SP, 19, 2);
592 /*****************************************************************************/
593 /* PowerPC instructions table */
594
595 #if defined(DO_PPC_STATISTICS)
596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
597 { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .opc4 = 0xff, \
602 .handler = { \
603 .inval1 = invl, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 .oname = stringify(name), \
608 }, \
609 .oname = stringify(name), \
610 }
611 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
612 { \
613 .opc1 = op1, \
614 .opc2 = op2, \
615 .opc3 = op3, \
616 .opc4 = 0xff, \
617 .handler = { \
618 .inval1 = invl1, \
619 .inval2 = invl2, \
620 .type = _typ, \
621 .type2 = _typ2, \
622 .handler = &gen_##name, \
623 .oname = stringify(name), \
624 }, \
625 .oname = stringify(name), \
626 }
627 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
628 { \
629 .opc1 = op1, \
630 .opc2 = op2, \
631 .opc3 = op3, \
632 .opc4 = 0xff, \
633 .handler = { \
634 .inval1 = invl, \
635 .type = _typ, \
636 .type2 = _typ2, \
637 .handler = &gen_##name, \
638 .oname = onam, \
639 }, \
640 .oname = onam, \
641 }
642 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
643 { \
644 .opc1 = op1, \
645 .opc2 = op2, \
646 .opc3 = op3, \
647 .opc4 = op4, \
648 .handler = { \
649 .inval1 = invl, \
650 .type = _typ, \
651 .type2 = _typ2, \
652 .handler = &gen_##name, \
653 .oname = stringify(name), \
654 }, \
655 .oname = stringify(name), \
656 }
657 #else
658 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
659 { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .opc4 = 0xff, \
664 .handler = { \
665 .inval1 = invl, \
666 .type = _typ, \
667 .type2 = _typ2, \
668 .handler = &gen_##name, \
669 }, \
670 .oname = stringify(name), \
671 }
672 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
673 { \
674 .opc1 = op1, \
675 .opc2 = op2, \
676 .opc3 = op3, \
677 .opc4 = 0xff, \
678 .handler = { \
679 .inval1 = invl1, \
680 .inval2 = invl2, \
681 .type = _typ, \
682 .type2 = _typ2, \
683 .handler = &gen_##name, \
684 }, \
685 .oname = stringify(name), \
686 }
687 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
688 { \
689 .opc1 = op1, \
690 .opc2 = op2, \
691 .opc3 = op3, \
692 .opc4 = 0xff, \
693 .handler = { \
694 .inval1 = invl, \
695 .type = _typ, \
696 .type2 = _typ2, \
697 .handler = &gen_##name, \
698 }, \
699 .oname = onam, \
700 }
701 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
702 { \
703 .opc1 = op1, \
704 .opc2 = op2, \
705 .opc3 = op3, \
706 .opc4 = op4, \
707 .handler = { \
708 .inval1 = invl, \
709 .type = _typ, \
710 .type2 = _typ2, \
711 .handler = &gen_##name, \
712 }, \
713 .oname = stringify(name), \
714 }
715 #endif
716
717 /* SPR load/store helpers */
718 static inline void gen_load_spr(TCGv t, int reg)
719 {
720 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
721 }
722
723 static inline void gen_store_spr(int reg, TCGv t)
724 {
725 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
726 }
727
728 /* Invalid instruction */
729 static void gen_invalid(DisasContext *ctx)
730 {
731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
732 }
733
734 static opc_handler_t invalid_handler = {
735 .inval1 = 0xFFFFFFFF,
736 .inval2 = 0xFFFFFFFF,
737 .type = PPC_NONE,
738 .type2 = PPC_NONE,
739 .handler = gen_invalid,
740 };
741
742 /*** Integer comparison ***/
743
744 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
745 {
746 TCGv t0 = tcg_temp_new();
747 TCGv_i32 t1 = tcg_temp_new_i32();
748
749 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
750
751 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
752 tcg_gen_trunc_tl_i32(t1, t0);
753 tcg_gen_shli_i32(t1, t1, CRF_LT);
754 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
755
756 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
757 tcg_gen_trunc_tl_i32(t1, t0);
758 tcg_gen_shli_i32(t1, t1, CRF_GT);
759 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
760
761 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
762 tcg_gen_trunc_tl_i32(t1, t0);
763 tcg_gen_shli_i32(t1, t1, CRF_EQ);
764 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
765
766 tcg_temp_free(t0);
767 tcg_temp_free_i32(t1);
768 }
769
770 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
771 {
772 TCGv t0 = tcg_const_tl(arg1);
773 gen_op_cmp(arg0, t0, s, crf);
774 tcg_temp_free(t0);
775 }
776
777 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
778 {
779 TCGv t0, t1;
780 t0 = tcg_temp_new();
781 t1 = tcg_temp_new();
782 if (s) {
783 tcg_gen_ext32s_tl(t0, arg0);
784 tcg_gen_ext32s_tl(t1, arg1);
785 } else {
786 tcg_gen_ext32u_tl(t0, arg0);
787 tcg_gen_ext32u_tl(t1, arg1);
788 }
789 gen_op_cmp(t0, t1, s, crf);
790 tcg_temp_free(t1);
791 tcg_temp_free(t0);
792 }
793
794 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
795 {
796 TCGv t0 = tcg_const_tl(arg1);
797 gen_op_cmp32(arg0, t0, s, crf);
798 tcg_temp_free(t0);
799 }
800
801 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
802 {
803 if (NARROW_MODE(ctx)) {
804 gen_op_cmpi32(reg, 0, 1, 0);
805 } else {
806 gen_op_cmpi(reg, 0, 1, 0);
807 }
808 }
809
810 /* cmp */
811 static void gen_cmp(DisasContext *ctx)
812 {
813 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 1, crfD(ctx->opcode));
816 } else {
817 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 1, crfD(ctx->opcode));
819 }
820 }
821
822 /* cmpi */
823 static void gen_cmpi(DisasContext *ctx)
824 {
825 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
826 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
827 1, crfD(ctx->opcode));
828 } else {
829 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
830 1, crfD(ctx->opcode));
831 }
832 }
833
834 /* cmpl */
835 static void gen_cmpl(DisasContext *ctx)
836 {
837 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
838 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
839 0, crfD(ctx->opcode));
840 } else {
841 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
842 0, crfD(ctx->opcode));
843 }
844 }
845
846 /* cmpli */
847 static void gen_cmpli(DisasContext *ctx)
848 {
849 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
850 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
851 0, crfD(ctx->opcode));
852 } else {
853 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
854 0, crfD(ctx->opcode));
855 }
856 }
857
858 /* cmprb - range comparison: isupper, isaplha, islower*/
859 static void gen_cmprb(DisasContext *ctx)
860 {
861 TCGv_i32 src1 = tcg_temp_new_i32();
862 TCGv_i32 src2 = tcg_temp_new_i32();
863 TCGv_i32 src2lo = tcg_temp_new_i32();
864 TCGv_i32 src2hi = tcg_temp_new_i32();
865 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
866
867 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
868 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
869
870 tcg_gen_andi_i32(src1, src1, 0xFF);
871 tcg_gen_ext8u_i32(src2lo, src2);
872 tcg_gen_shri_i32(src2, src2, 8);
873 tcg_gen_ext8u_i32(src2hi, src2);
874
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
876 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
877 tcg_gen_and_i32(crf, src2lo, src2hi);
878
879 if (ctx->opcode & 0x00200000) {
880 tcg_gen_shri_i32(src2, src2, 8);
881 tcg_gen_ext8u_i32(src2lo, src2);
882 tcg_gen_shri_i32(src2, src2, 8);
883 tcg_gen_ext8u_i32(src2hi, src2);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
885 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
886 tcg_gen_and_i32(src2lo, src2lo, src2hi);
887 tcg_gen_or_i32(crf, crf, src2lo);
888 }
889 tcg_gen_shli_i32(crf, crf, CRF_GT);
890 tcg_temp_free_i32(src1);
891 tcg_temp_free_i32(src2);
892 tcg_temp_free_i32(src2lo);
893 tcg_temp_free_i32(src2hi);
894 }
895
896 #if defined(TARGET_PPC64)
897 /* cmpeqb */
898 static void gen_cmpeqb(DisasContext *ctx)
899 {
900 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
901 cpu_gpr[rB(ctx->opcode)]);
902 }
903 #endif
904
905 /* isel (PowerPC 2.03 specification) */
906 static void gen_isel(DisasContext *ctx)
907 {
908 uint32_t bi = rC(ctx->opcode);
909 uint32_t mask = 0x08 >> (bi & 0x03);
910 TCGv t0 = tcg_temp_new();
911 TCGv zr;
912
913 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
914 tcg_gen_andi_tl(t0, t0, mask);
915
916 zr = tcg_const_tl(0);
917 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
918 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
919 cpu_gpr[rB(ctx->opcode)]);
920 tcg_temp_free(zr);
921 tcg_temp_free(t0);
922 }
923
924 /* cmpb: PowerPC 2.05 specification */
925 static void gen_cmpb(DisasContext *ctx)
926 {
927 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
928 cpu_gpr[rB(ctx->opcode)]);
929 }
930
931 /*** Integer arithmetic ***/
932
933 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
934 TCGv arg1, TCGv arg2, int sub)
935 {
936 TCGv t0 = tcg_temp_new();
937
938 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
939 tcg_gen_xor_tl(t0, arg1, arg2);
940 if (sub) {
941 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
942 } else {
943 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
944 }
945 tcg_temp_free(t0);
946 if (NARROW_MODE(ctx)) {
947 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
948 }
949 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
950 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
951 }
952
953 /* Common add function */
954 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
955 TCGv arg2, bool add_ca, bool compute_ca,
956 bool compute_ov, bool compute_rc0)
957 {
958 TCGv t0 = ret;
959
960 if (compute_ca || compute_ov) {
961 t0 = tcg_temp_new();
962 }
963
964 if (compute_ca) {
965 if (NARROW_MODE(ctx)) {
966 /* Caution: a non-obvious corner case of the spec is that we
967 must produce the *entire* 64-bit addition, but produce the
968 carry into bit 32. */
969 TCGv t1 = tcg_temp_new();
970 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
971 tcg_gen_add_tl(t0, arg1, arg2);
972 if (add_ca) {
973 tcg_gen_add_tl(t0, t0, cpu_ca);
974 }
975 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
976 tcg_temp_free(t1);
977 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
978 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
979 } else {
980 TCGv zero = tcg_const_tl(0);
981 if (add_ca) {
982 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
983 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
984 } else {
985 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
986 }
987 tcg_temp_free(zero);
988 }
989 } else {
990 tcg_gen_add_tl(t0, arg1, arg2);
991 if (add_ca) {
992 tcg_gen_add_tl(t0, t0, cpu_ca);
993 }
994 }
995
996 if (compute_ov) {
997 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
998 }
999 if (unlikely(compute_rc0)) {
1000 gen_set_Rc0(ctx, t0);
1001 }
1002
1003 if (!TCGV_EQUAL(t0, ret)) {
1004 tcg_gen_mov_tl(ret, t0);
1005 tcg_temp_free(t0);
1006 }
1007 }
1008 /* Add functions with two operands */
1009 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1015 }
1016 /* Add functions with one operand and one immediate */
1017 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1018 add_ca, compute_ca, compute_ov) \
1019 static void glue(gen_, name)(DisasContext *ctx) \
1020 { \
1021 TCGv t0 = tcg_const_tl(const_val); \
1022 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1023 cpu_gpr[rA(ctx->opcode)], t0, \
1024 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1025 tcg_temp_free(t0); \
1026 }
1027
1028 /* add add. addo addo. */
1029 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1030 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1031 /* addc addc. addco addco. */
1032 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1033 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1034 /* adde adde. addeo addeo. */
1035 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1036 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1037 /* addme addme. addmeo addmeo. */
1038 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1039 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1040 /* addze addze. addzeo addzeo.*/
1041 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1042 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1043 /* addi */
1044 static void gen_addi(DisasContext *ctx)
1045 {
1046 target_long simm = SIMM(ctx->opcode);
1047
1048 if (rA(ctx->opcode) == 0) {
1049 /* li case */
1050 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1051 } else {
1052 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1053 cpu_gpr[rA(ctx->opcode)], simm);
1054 }
1055 }
1056 /* addic addic.*/
1057 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1058 {
1059 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1060 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1061 c, 0, 1, 0, compute_rc0);
1062 tcg_temp_free(c);
1063 }
1064
1065 static void gen_addic(DisasContext *ctx)
1066 {
1067 gen_op_addic(ctx, 0);
1068 }
1069
1070 static void gen_addic_(DisasContext *ctx)
1071 {
1072 gen_op_addic(ctx, 1);
1073 }
1074
1075 /* addis */
1076 static void gen_addis(DisasContext *ctx)
1077 {
1078 target_long simm = SIMM(ctx->opcode);
1079
1080 if (rA(ctx->opcode) == 0) {
1081 /* lis case */
1082 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1083 } else {
1084 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], simm << 16);
1086 }
1087 }
1088
1089 /* addpcis */
1090 static void gen_addpcis(DisasContext *ctx)
1091 {
1092 target_long d = DX(ctx->opcode);
1093
1094 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1095 }
1096
1097 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1098 TCGv arg2, int sign, int compute_ov)
1099 {
1100 TCGv_i32 t0 = tcg_temp_new_i32();
1101 TCGv_i32 t1 = tcg_temp_new_i32();
1102 TCGv_i32 t2 = tcg_temp_new_i32();
1103 TCGv_i32 t3 = tcg_temp_new_i32();
1104
1105 tcg_gen_trunc_tl_i32(t0, arg1);
1106 tcg_gen_trunc_tl_i32(t1, arg2);
1107 if (sign) {
1108 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1109 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1110 tcg_gen_and_i32(t2, t2, t3);
1111 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1112 tcg_gen_or_i32(t2, t2, t3);
1113 tcg_gen_movi_i32(t3, 0);
1114 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1115 tcg_gen_div_i32(t3, t0, t1);
1116 tcg_gen_extu_i32_tl(ret, t3);
1117 } else {
1118 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1119 tcg_gen_movi_i32(t3, 0);
1120 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1121 tcg_gen_divu_i32(t3, t0, t1);
1122 tcg_gen_extu_i32_tl(ret, t3);
1123 }
1124 if (compute_ov) {
1125 tcg_gen_extu_i32_tl(cpu_ov, t2);
1126 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1127 }
1128 tcg_temp_free_i32(t0);
1129 tcg_temp_free_i32(t1);
1130 tcg_temp_free_i32(t2);
1131 tcg_temp_free_i32(t3);
1132
1133 if (unlikely(Rc(ctx->opcode) != 0))
1134 gen_set_Rc0(ctx, ret);
1135 }
1136 /* Div functions */
1137 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1138 static void glue(gen_, name)(DisasContext *ctx) \
1139 { \
1140 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1141 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1142 sign, compute_ov); \
1143 }
1144 /* divwu divwu. divwuo divwuo. */
1145 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1146 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1147 /* divw divw. divwo divwo. */
1148 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1149 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1150
1151 /* div[wd]eu[o][.] */
1152 #define GEN_DIVE(name, hlpr, compute_ov) \
1153 static void gen_##name(DisasContext *ctx) \
1154 { \
1155 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1156 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1157 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1158 tcg_temp_free_i32(t0); \
1159 if (unlikely(Rc(ctx->opcode) != 0)) { \
1160 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1161 } \
1162 }
1163
1164 GEN_DIVE(divweu, divweu, 0);
1165 GEN_DIVE(divweuo, divweu, 1);
1166 GEN_DIVE(divwe, divwe, 0);
1167 GEN_DIVE(divweo, divwe, 1);
1168
1169 #if defined(TARGET_PPC64)
1170 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1171 TCGv arg2, int sign, int compute_ov)
1172 {
1173 TCGv_i64 t0 = tcg_temp_new_i64();
1174 TCGv_i64 t1 = tcg_temp_new_i64();
1175 TCGv_i64 t2 = tcg_temp_new_i64();
1176 TCGv_i64 t3 = tcg_temp_new_i64();
1177
1178 tcg_gen_mov_i64(t0, arg1);
1179 tcg_gen_mov_i64(t1, arg2);
1180 if (sign) {
1181 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1182 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1183 tcg_gen_and_i64(t2, t2, t3);
1184 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1185 tcg_gen_or_i64(t2, t2, t3);
1186 tcg_gen_movi_i64(t3, 0);
1187 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1188 tcg_gen_div_i64(ret, t0, t1);
1189 } else {
1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1191 tcg_gen_movi_i64(t3, 0);
1192 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1193 tcg_gen_divu_i64(ret, t0, t1);
1194 }
1195 if (compute_ov) {
1196 tcg_gen_mov_tl(cpu_ov, t2);
1197 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1198 }
1199 tcg_temp_free_i64(t0);
1200 tcg_temp_free_i64(t1);
1201 tcg_temp_free_i64(t2);
1202 tcg_temp_free_i64(t3);
1203
1204 if (unlikely(Rc(ctx->opcode) != 0))
1205 gen_set_Rc0(ctx, ret);
1206 }
1207
1208 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1209 static void glue(gen_, name)(DisasContext *ctx) \
1210 { \
1211 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1212 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1213 sign, compute_ov); \
1214 }
1215 /* divwu divwu. divwuo divwuo. */
1216 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1217 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1218 /* divw divw. divwo divwo. */
1219 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1220 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1221
1222 GEN_DIVE(divdeu, divdeu, 0);
1223 GEN_DIVE(divdeuo, divdeu, 1);
1224 GEN_DIVE(divde, divde, 0);
1225 GEN_DIVE(divdeo, divde, 1);
1226 #endif
1227
1228 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1229 TCGv arg2, int sign)
1230 {
1231 TCGv_i32 t0 = tcg_temp_new_i32();
1232 TCGv_i32 t1 = tcg_temp_new_i32();
1233
1234 tcg_gen_trunc_tl_i32(t0, arg1);
1235 tcg_gen_trunc_tl_i32(t1, arg2);
1236 if (sign) {
1237 TCGv_i32 t2 = tcg_temp_new_i32();
1238 TCGv_i32 t3 = tcg_temp_new_i32();
1239 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1240 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1241 tcg_gen_and_i32(t2, t2, t3);
1242 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1243 tcg_gen_or_i32(t2, t2, t3);
1244 tcg_gen_movi_i32(t3, 0);
1245 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1246 tcg_gen_rem_i32(t3, t0, t1);
1247 tcg_gen_ext_i32_tl(ret, t3);
1248 tcg_temp_free_i32(t2);
1249 tcg_temp_free_i32(t3);
1250 } else {
1251 TCGv_i32 t2 = tcg_const_i32(1);
1252 TCGv_i32 t3 = tcg_const_i32(0);
1253 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1254 tcg_gen_remu_i32(t3, t0, t1);
1255 tcg_gen_extu_i32_tl(ret, t3);
1256 tcg_temp_free_i32(t2);
1257 tcg_temp_free_i32(t3);
1258 }
1259 tcg_temp_free_i32(t0);
1260 tcg_temp_free_i32(t1);
1261 }
1262
1263 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1264 static void glue(gen_, name)(DisasContext *ctx) \
1265 { \
1266 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1267 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1268 sign); \
1269 }
1270
1271 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1272 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1273
1274 #if defined(TARGET_PPC64)
1275 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1276 TCGv arg2, int sign)
1277 {
1278 TCGv_i64 t0 = tcg_temp_new_i64();
1279 TCGv_i64 t1 = tcg_temp_new_i64();
1280
1281 tcg_gen_mov_i64(t0, arg1);
1282 tcg_gen_mov_i64(t1, arg2);
1283 if (sign) {
1284 TCGv_i64 t2 = tcg_temp_new_i64();
1285 TCGv_i64 t3 = tcg_temp_new_i64();
1286 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1287 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1288 tcg_gen_and_i64(t2, t2, t3);
1289 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1290 tcg_gen_or_i64(t2, t2, t3);
1291 tcg_gen_movi_i64(t3, 0);
1292 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1293 tcg_gen_rem_i64(ret, t0, t1);
1294 tcg_temp_free_i64(t2);
1295 tcg_temp_free_i64(t3);
1296 } else {
1297 TCGv_i64 t2 = tcg_const_i64(1);
1298 TCGv_i64 t3 = tcg_const_i64(0);
1299 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1300 tcg_gen_remu_i64(ret, t0, t1);
1301 tcg_temp_free_i64(t2);
1302 tcg_temp_free_i64(t3);
1303 }
1304 tcg_temp_free_i64(t0);
1305 tcg_temp_free_i64(t1);
1306 }
1307
1308 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1309 static void glue(gen_, name)(DisasContext *ctx) \
1310 { \
1311 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1312 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1313 sign); \
1314 }
1315
1316 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1317 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1318 #endif
1319
1320 /* mulhw mulhw. */
1321 static void gen_mulhw(DisasContext *ctx)
1322 {
1323 TCGv_i32 t0 = tcg_temp_new_i32();
1324 TCGv_i32 t1 = tcg_temp_new_i32();
1325
1326 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1327 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1328 tcg_gen_muls2_i32(t0, t1, t0, t1);
1329 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1330 tcg_temp_free_i32(t0);
1331 tcg_temp_free_i32(t1);
1332 if (unlikely(Rc(ctx->opcode) != 0))
1333 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1334 }
1335
1336 /* mulhwu mulhwu. */
1337 static void gen_mulhwu(DisasContext *ctx)
1338 {
1339 TCGv_i32 t0 = tcg_temp_new_i32();
1340 TCGv_i32 t1 = tcg_temp_new_i32();
1341
1342 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1343 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1344 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1345 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1346 tcg_temp_free_i32(t0);
1347 tcg_temp_free_i32(t1);
1348 if (unlikely(Rc(ctx->opcode) != 0))
1349 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1350 }
1351
1352 /* mullw mullw. */
1353 static void gen_mullw(DisasContext *ctx)
1354 {
1355 #if defined(TARGET_PPC64)
1356 TCGv_i64 t0, t1;
1357 t0 = tcg_temp_new_i64();
1358 t1 = tcg_temp_new_i64();
1359 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1360 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1361 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1362 tcg_temp_free(t0);
1363 tcg_temp_free(t1);
1364 #else
1365 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1366 cpu_gpr[rB(ctx->opcode)]);
1367 #endif
1368 if (unlikely(Rc(ctx->opcode) != 0))
1369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1370 }
1371
1372 /* mullwo mullwo. */
1373 static void gen_mullwo(DisasContext *ctx)
1374 {
1375 TCGv_i32 t0 = tcg_temp_new_i32();
1376 TCGv_i32 t1 = tcg_temp_new_i32();
1377
1378 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1379 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1380 tcg_gen_muls2_i32(t0, t1, t0, t1);
1381 #if defined(TARGET_PPC64)
1382 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1383 #else
1384 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1385 #endif
1386
1387 tcg_gen_sari_i32(t0, t0, 31);
1388 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1389 tcg_gen_extu_i32_tl(cpu_ov, t0);
1390 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1391
1392 tcg_temp_free_i32(t0);
1393 tcg_temp_free_i32(t1);
1394 if (unlikely(Rc(ctx->opcode) != 0))
1395 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1396 }
1397
1398 /* mulli */
1399 static void gen_mulli(DisasContext *ctx)
1400 {
1401 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1402 SIMM(ctx->opcode));
1403 }
1404
1405 #if defined(TARGET_PPC64)
1406 /* mulhd mulhd. */
1407 static void gen_mulhd(DisasContext *ctx)
1408 {
1409 TCGv lo = tcg_temp_new();
1410 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1411 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1412 tcg_temp_free(lo);
1413 if (unlikely(Rc(ctx->opcode) != 0)) {
1414 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1415 }
1416 }
1417
1418 /* mulhdu mulhdu. */
1419 static void gen_mulhdu(DisasContext *ctx)
1420 {
1421 TCGv lo = tcg_temp_new();
1422 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1423 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1424 tcg_temp_free(lo);
1425 if (unlikely(Rc(ctx->opcode) != 0)) {
1426 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1427 }
1428 }
1429
1430 /* mulld mulld. */
1431 static void gen_mulld(DisasContext *ctx)
1432 {
1433 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1434 cpu_gpr[rB(ctx->opcode)]);
1435 if (unlikely(Rc(ctx->opcode) != 0))
1436 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1437 }
1438
1439 /* mulldo mulldo. */
1440 static void gen_mulldo(DisasContext *ctx)
1441 {
1442 TCGv_i64 t0 = tcg_temp_new_i64();
1443 TCGv_i64 t1 = tcg_temp_new_i64();
1444
1445 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1446 cpu_gpr[rB(ctx->opcode)]);
1447 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1448
1449 tcg_gen_sari_i64(t0, t0, 63);
1450 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1451 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1452
1453 tcg_temp_free_i64(t0);
1454 tcg_temp_free_i64(t1);
1455
1456 if (unlikely(Rc(ctx->opcode) != 0)) {
1457 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1458 }
1459 }
1460 #endif
1461
1462 /* Common subf function */
1463 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1464 TCGv arg2, bool add_ca, bool compute_ca,
1465 bool compute_ov, bool compute_rc0)
1466 {
1467 TCGv t0 = ret;
1468
1469 if (compute_ca || compute_ov) {
1470 t0 = tcg_temp_new();
1471 }
1472
1473 if (compute_ca) {
1474 /* dest = ~arg1 + arg2 [+ ca]. */
1475 if (NARROW_MODE(ctx)) {
1476 /* Caution: a non-obvious corner case of the spec is that we
1477 must produce the *entire* 64-bit addition, but produce the
1478 carry into bit 32. */
1479 TCGv inv1 = tcg_temp_new();
1480 TCGv t1 = tcg_temp_new();
1481 tcg_gen_not_tl(inv1, arg1);
1482 if (add_ca) {
1483 tcg_gen_add_tl(t0, arg2, cpu_ca);
1484 } else {
1485 tcg_gen_addi_tl(t0, arg2, 1);
1486 }
1487 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1488 tcg_gen_add_tl(t0, t0, inv1);
1489 tcg_temp_free(inv1);
1490 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1491 tcg_temp_free(t1);
1492 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1493 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1494 } else if (add_ca) {
1495 TCGv zero, inv1 = tcg_temp_new();
1496 tcg_gen_not_tl(inv1, arg1);
1497 zero = tcg_const_tl(0);
1498 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1499 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1500 tcg_temp_free(zero);
1501 tcg_temp_free(inv1);
1502 } else {
1503 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1504 tcg_gen_sub_tl(t0, arg2, arg1);
1505 }
1506 } else if (add_ca) {
1507 /* Since we're ignoring carry-out, we can simplify the
1508 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1509 tcg_gen_sub_tl(t0, arg2, arg1);
1510 tcg_gen_add_tl(t0, t0, cpu_ca);
1511 tcg_gen_subi_tl(t0, t0, 1);
1512 } else {
1513 tcg_gen_sub_tl(t0, arg2, arg1);
1514 }
1515
1516 if (compute_ov) {
1517 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1518 }
1519 if (unlikely(compute_rc0)) {
1520 gen_set_Rc0(ctx, t0);
1521 }
1522
1523 if (!TCGV_EQUAL(t0, ret)) {
1524 tcg_gen_mov_tl(ret, t0);
1525 tcg_temp_free(t0);
1526 }
1527 }
1528 /* Sub functions with Two operands functions */
1529 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1530 static void glue(gen_, name)(DisasContext *ctx) \
1531 { \
1532 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1533 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1534 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1535 }
1536 /* Sub functions with one operand and one immediate */
1537 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1538 add_ca, compute_ca, compute_ov) \
1539 static void glue(gen_, name)(DisasContext *ctx) \
1540 { \
1541 TCGv t0 = tcg_const_tl(const_val); \
1542 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1543 cpu_gpr[rA(ctx->opcode)], t0, \
1544 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1545 tcg_temp_free(t0); \
1546 }
1547 /* subf subf. subfo subfo. */
1548 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1549 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1550 /* subfc subfc. subfco subfco. */
1551 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1552 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1553 /* subfe subfe. subfeo subfo. */
1554 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1555 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1556 /* subfme subfme. subfmeo subfmeo. */
1557 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1558 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1559 /* subfze subfze. subfzeo subfzeo.*/
1560 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1561 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1562
1563 /* subfic */
1564 static void gen_subfic(DisasContext *ctx)
1565 {
1566 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1567 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1568 c, 0, 1, 0, 0);
1569 tcg_temp_free(c);
1570 }
1571
1572 /* neg neg. nego nego. */
1573 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1574 {
1575 TCGv zero = tcg_const_tl(0);
1576 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1577 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1578 tcg_temp_free(zero);
1579 }
1580
1581 static void gen_neg(DisasContext *ctx)
1582 {
1583 gen_op_arith_neg(ctx, 0);
1584 }
1585
1586 static void gen_nego(DisasContext *ctx)
1587 {
1588 gen_op_arith_neg(ctx, 1);
1589 }
1590
1591 /*** Integer logical ***/
1592 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1593 static void glue(gen_, name)(DisasContext *ctx) \
1594 { \
1595 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1596 cpu_gpr[rB(ctx->opcode)]); \
1597 if (unlikely(Rc(ctx->opcode) != 0)) \
1598 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1599 }
1600
1601 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1602 static void glue(gen_, name)(DisasContext *ctx) \
1603 { \
1604 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1605 if (unlikely(Rc(ctx->opcode) != 0)) \
1606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1607 }
1608
1609 /* and & and. */
1610 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1611 /* andc & andc. */
1612 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1613
1614 /* andi. */
1615 static void gen_andi_(DisasContext *ctx)
1616 {
1617 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1618 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1619 }
1620
1621 /* andis. */
1622 static void gen_andis_(DisasContext *ctx)
1623 {
1624 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1626 }
1627
1628 /* cntlzw */
1629 static void gen_cntlzw(DisasContext *ctx)
1630 {
1631 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1632 if (unlikely(Rc(ctx->opcode) != 0))
1633 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1634 }
1635
1636 /* cnttzw */
1637 static void gen_cnttzw(DisasContext *ctx)
1638 {
1639 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1640 if (unlikely(Rc(ctx->opcode) != 0)) {
1641 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1642 }
1643 }
1644
1645 /* eqv & eqv. */
1646 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1647 /* extsb & extsb. */
1648 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1649 /* extsh & extsh. */
1650 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1651 /* nand & nand. */
1652 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1653 /* nor & nor. */
1654 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1655
1656 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1657 static void gen_pause(DisasContext *ctx)
1658 {
1659 TCGv_i32 t0 = tcg_const_i32(0);
1660 tcg_gen_st_i32(t0, cpu_env,
1661 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1662 tcg_temp_free_i32(t0);
1663
1664 /* Stop translation, this gives other CPUs a chance to run */
1665 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1666 }
1667 #endif /* defined(TARGET_PPC64) */
1668
1669 /* or & or. */
1670 static void gen_or(DisasContext *ctx)
1671 {
1672 int rs, ra, rb;
1673
1674 rs = rS(ctx->opcode);
1675 ra = rA(ctx->opcode);
1676 rb = rB(ctx->opcode);
1677 /* Optimisation for mr. ri case */
1678 if (rs != ra || rs != rb) {
1679 if (rs != rb)
1680 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1681 else
1682 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1683 if (unlikely(Rc(ctx->opcode) != 0))
1684 gen_set_Rc0(ctx, cpu_gpr[ra]);
1685 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1686 gen_set_Rc0(ctx, cpu_gpr[rs]);
1687 #if defined(TARGET_PPC64)
1688 } else if (rs != 0) { /* 0 is nop */
1689 int prio = 0;
1690
1691 switch (rs) {
1692 case 1:
1693 /* Set process priority to low */
1694 prio = 2;
1695 break;
1696 case 6:
1697 /* Set process priority to medium-low */
1698 prio = 3;
1699 break;
1700 case 2:
1701 /* Set process priority to normal */
1702 prio = 4;
1703 break;
1704 #if !defined(CONFIG_USER_ONLY)
1705 case 31:
1706 if (!ctx->pr) {
1707 /* Set process priority to very low */
1708 prio = 1;
1709 }
1710 break;
1711 case 5:
1712 if (!ctx->pr) {
1713 /* Set process priority to medium-hight */
1714 prio = 5;
1715 }
1716 break;
1717 case 3:
1718 if (!ctx->pr) {
1719 /* Set process priority to high */
1720 prio = 6;
1721 }
1722 break;
1723 case 7:
1724 if (ctx->hv && !ctx->pr) {
1725 /* Set process priority to very high */
1726 prio = 7;
1727 }
1728 break;
1729 #endif
1730 default:
1731 break;
1732 }
1733 if (prio) {
1734 TCGv t0 = tcg_temp_new();
1735 gen_load_spr(t0, SPR_PPR);
1736 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1737 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1738 gen_store_spr(SPR_PPR, t0);
1739 tcg_temp_free(t0);
1740 }
1741 #if !defined(CONFIG_USER_ONLY)
1742 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1743 * CPU and the kernel hangs. This applies to all encodings other
1744 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1745 * and all currently undefined.
1746 */
1747 gen_pause(ctx);
1748 #endif
1749 #endif
1750 }
1751 }
1752 /* orc & orc. */
1753 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1754
1755 /* xor & xor. */
1756 static void gen_xor(DisasContext *ctx)
1757 {
1758 /* Optimisation for "set to zero" case */
1759 if (rS(ctx->opcode) != rB(ctx->opcode))
1760 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1761 else
1762 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766
1767 /* ori */
1768 static void gen_ori(DisasContext *ctx)
1769 {
1770 target_ulong uimm = UIMM(ctx->opcode);
1771
1772 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1773 return;
1774 }
1775 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1776 }
1777
1778 /* oris */
1779 static void gen_oris(DisasContext *ctx)
1780 {
1781 target_ulong uimm = UIMM(ctx->opcode);
1782
1783 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1784 /* NOP */
1785 return;
1786 }
1787 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1788 }
1789
1790 /* xori */
1791 static void gen_xori(DisasContext *ctx)
1792 {
1793 target_ulong uimm = UIMM(ctx->opcode);
1794
1795 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1796 /* NOP */
1797 return;
1798 }
1799 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1800 }
1801
1802 /* xoris */
1803 static void gen_xoris(DisasContext *ctx)
1804 {
1805 target_ulong uimm = UIMM(ctx->opcode);
1806
1807 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1808 /* NOP */
1809 return;
1810 }
1811 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1812 }
1813
1814 /* popcntb : PowerPC 2.03 specification */
1815 static void gen_popcntb(DisasContext *ctx)
1816 {
1817 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1818 }
1819
1820 static void gen_popcntw(DisasContext *ctx)
1821 {
1822 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1823 }
1824
1825 #if defined(TARGET_PPC64)
1826 /* popcntd: PowerPC 2.06 specification */
1827 static void gen_popcntd(DisasContext *ctx)
1828 {
1829 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1830 }
1831 #endif
1832
1833 /* prtyw: PowerPC 2.05 specification */
1834 static void gen_prtyw(DisasContext *ctx)
1835 {
1836 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1837 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1838 TCGv t0 = tcg_temp_new();
1839 tcg_gen_shri_tl(t0, rs, 16);
1840 tcg_gen_xor_tl(ra, rs, t0);
1841 tcg_gen_shri_tl(t0, ra, 8);
1842 tcg_gen_xor_tl(ra, ra, t0);
1843 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1844 tcg_temp_free(t0);
1845 }
1846
1847 #if defined(TARGET_PPC64)
1848 /* prtyd: PowerPC 2.05 specification */
1849 static void gen_prtyd(DisasContext *ctx)
1850 {
1851 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1852 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1853 TCGv t0 = tcg_temp_new();
1854 tcg_gen_shri_tl(t0, rs, 32);
1855 tcg_gen_xor_tl(ra, rs, t0);
1856 tcg_gen_shri_tl(t0, ra, 16);
1857 tcg_gen_xor_tl(ra, ra, t0);
1858 tcg_gen_shri_tl(t0, ra, 8);
1859 tcg_gen_xor_tl(ra, ra, t0);
1860 tcg_gen_andi_tl(ra, ra, 1);
1861 tcg_temp_free(t0);
1862 }
1863 #endif
1864
1865 #if defined(TARGET_PPC64)
1866 /* bpermd */
1867 static void gen_bpermd(DisasContext *ctx)
1868 {
1869 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1870 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1871 }
1872 #endif
1873
1874 #if defined(TARGET_PPC64)
1875 /* extsw & extsw. */
1876 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1877
1878 /* cntlzd */
1879 static void gen_cntlzd(DisasContext *ctx)
1880 {
1881 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1882 if (unlikely(Rc(ctx->opcode) != 0))
1883 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1884 }
1885
1886 /* cnttzd */
1887 static void gen_cnttzd(DisasContext *ctx)
1888 {
1889 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1890 if (unlikely(Rc(ctx->opcode) != 0)) {
1891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1892 }
1893 }
1894 #endif
1895
1896 /*** Integer rotate ***/
1897
1898 /* rlwimi & rlwimi. */
1899 static void gen_rlwimi(DisasContext *ctx)
1900 {
1901 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1902 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1903 uint32_t sh = SH(ctx->opcode);
1904 uint32_t mb = MB(ctx->opcode);
1905 uint32_t me = ME(ctx->opcode);
1906
1907 if (sh == (31-me) && mb <= me) {
1908 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1909 } else {
1910 target_ulong mask;
1911 TCGv t1;
1912
1913 #if defined(TARGET_PPC64)
1914 mb += 32;
1915 me += 32;
1916 #endif
1917 mask = MASK(mb, me);
1918
1919 t1 = tcg_temp_new();
1920 if (mask <= 0xffffffffu) {
1921 TCGv_i32 t0 = tcg_temp_new_i32();
1922 tcg_gen_trunc_tl_i32(t0, t_rs);
1923 tcg_gen_rotli_i32(t0, t0, sh);
1924 tcg_gen_extu_i32_tl(t1, t0);
1925 tcg_temp_free_i32(t0);
1926 } else {
1927 #if defined(TARGET_PPC64)
1928 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1929 tcg_gen_rotli_i64(t1, t1, sh);
1930 #else
1931 g_assert_not_reached();
1932 #endif
1933 }
1934
1935 tcg_gen_andi_tl(t1, t1, mask);
1936 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1937 tcg_gen_or_tl(t_ra, t_ra, t1);
1938 tcg_temp_free(t1);
1939 }
1940 if (unlikely(Rc(ctx->opcode) != 0)) {
1941 gen_set_Rc0(ctx, t_ra);
1942 }
1943 }
1944
1945 /* rlwinm & rlwinm. */
1946 static void gen_rlwinm(DisasContext *ctx)
1947 {
1948 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1949 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1950 uint32_t sh = SH(ctx->opcode);
1951 uint32_t mb = MB(ctx->opcode);
1952 uint32_t me = ME(ctx->opcode);
1953
1954 if (mb == 0 && me == (31 - sh)) {
1955 tcg_gen_shli_tl(t_ra, t_rs, sh);
1956 tcg_gen_ext32u_tl(t_ra, t_ra);
1957 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1958 tcg_gen_ext32u_tl(t_ra, t_rs);
1959 tcg_gen_shri_tl(t_ra, t_ra, mb);
1960 } else {
1961 target_ulong mask;
1962 #if defined(TARGET_PPC64)
1963 mb += 32;
1964 me += 32;
1965 #endif
1966 mask = MASK(mb, me);
1967
1968 if (mask <= 0xffffffffu) {
1969 TCGv_i32 t0 = tcg_temp_new_i32();
1970 tcg_gen_trunc_tl_i32(t0, t_rs);
1971 tcg_gen_rotli_i32(t0, t0, sh);
1972 tcg_gen_andi_i32(t0, t0, mask);
1973 tcg_gen_extu_i32_tl(t_ra, t0);
1974 tcg_temp_free_i32(t0);
1975 } else {
1976 #if defined(TARGET_PPC64)
1977 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1978 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1979 tcg_gen_andi_i64(t_ra, t_ra, mask);
1980 #else
1981 g_assert_not_reached();
1982 #endif
1983 }
1984 }
1985 if (unlikely(Rc(ctx->opcode) != 0)) {
1986 gen_set_Rc0(ctx, t_ra);
1987 }
1988 }
1989
1990 /* rlwnm & rlwnm. */
1991 static void gen_rlwnm(DisasContext *ctx)
1992 {
1993 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1994 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1995 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1996 uint32_t mb = MB(ctx->opcode);
1997 uint32_t me = ME(ctx->opcode);
1998 target_ulong mask;
1999
2000 #if defined(TARGET_PPC64)
2001 mb += 32;
2002 me += 32;
2003 #endif
2004 mask = MASK(mb, me);
2005
2006 if (mask <= 0xffffffffu) {
2007 TCGv_i32 t0 = tcg_temp_new_i32();
2008 TCGv_i32 t1 = tcg_temp_new_i32();
2009 tcg_gen_trunc_tl_i32(t0, t_rb);
2010 tcg_gen_trunc_tl_i32(t1, t_rs);
2011 tcg_gen_andi_i32(t0, t0, 0x1f);
2012 tcg_gen_rotl_i32(t1, t1, t0);
2013 tcg_gen_extu_i32_tl(t_ra, t1);
2014 tcg_temp_free_i32(t0);
2015 tcg_temp_free_i32(t1);
2016 } else {
2017 #if defined(TARGET_PPC64)
2018 TCGv_i64 t0 = tcg_temp_new_i64();
2019 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2020 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2021 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2022 tcg_temp_free_i64(t0);
2023 #else
2024 g_assert_not_reached();
2025 #endif
2026 }
2027
2028 tcg_gen_andi_tl(t_ra, t_ra, mask);
2029
2030 if (unlikely(Rc(ctx->opcode) != 0)) {
2031 gen_set_Rc0(ctx, t_ra);
2032 }
2033 }
2034
2035 #if defined(TARGET_PPC64)
2036 #define GEN_PPC64_R2(name, opc1, opc2) \
2037 static void glue(gen_, name##0)(DisasContext *ctx) \
2038 { \
2039 gen_##name(ctx, 0); \
2040 } \
2041 \
2042 static void glue(gen_, name##1)(DisasContext *ctx) \
2043 { \
2044 gen_##name(ctx, 1); \
2045 }
2046 #define GEN_PPC64_R4(name, opc1, opc2) \
2047 static void glue(gen_, name##0)(DisasContext *ctx) \
2048 { \
2049 gen_##name(ctx, 0, 0); \
2050 } \
2051 \
2052 static void glue(gen_, name##1)(DisasContext *ctx) \
2053 { \
2054 gen_##name(ctx, 0, 1); \
2055 } \
2056 \
2057 static void glue(gen_, name##2)(DisasContext *ctx) \
2058 { \
2059 gen_##name(ctx, 1, 0); \
2060 } \
2061 \
2062 static void glue(gen_, name##3)(DisasContext *ctx) \
2063 { \
2064 gen_##name(ctx, 1, 1); \
2065 }
2066
2067 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2068 {
2069 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2070 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2071
2072 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2073 tcg_gen_shli_tl(t_ra, t_rs, sh);
2074 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2075 tcg_gen_shri_tl(t_ra, t_rs, mb);
2076 } else {
2077 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2078 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2079 }
2080 if (unlikely(Rc(ctx->opcode) != 0)) {
2081 gen_set_Rc0(ctx, t_ra);
2082 }
2083 }
2084
2085 /* rldicl - rldicl. */
2086 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2087 {
2088 uint32_t sh, mb;
2089
2090 sh = SH(ctx->opcode) | (shn << 5);
2091 mb = MB(ctx->opcode) | (mbn << 5);
2092 gen_rldinm(ctx, mb, 63, sh);
2093 }
2094 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2095
2096 /* rldicr - rldicr. */
2097 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2098 {
2099 uint32_t sh, me;
2100
2101 sh = SH(ctx->opcode) | (shn << 5);
2102 me = MB(ctx->opcode) | (men << 5);
2103 gen_rldinm(ctx, 0, me, sh);
2104 }
2105 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2106
2107 /* rldic - rldic. */
2108 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2109 {
2110 uint32_t sh, mb;
2111
2112 sh = SH(ctx->opcode) | (shn << 5);
2113 mb = MB(ctx->opcode) | (mbn << 5);
2114 gen_rldinm(ctx, mb, 63 - sh, sh);
2115 }
2116 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2117
2118 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2119 {
2120 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2121 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2122 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2123 TCGv t0;
2124
2125 t0 = tcg_temp_new();
2126 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2127 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2128 tcg_temp_free(t0);
2129
2130 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2131 if (unlikely(Rc(ctx->opcode) != 0)) {
2132 gen_set_Rc0(ctx, t_ra);
2133 }
2134 }
2135
2136 /* rldcl - rldcl. */
2137 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2138 {
2139 uint32_t mb;
2140
2141 mb = MB(ctx->opcode) | (mbn << 5);
2142 gen_rldnm(ctx, mb, 63);
2143 }
2144 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2145
2146 /* rldcr - rldcr. */
2147 static inline void gen_rldcr(DisasContext *ctx, int men)
2148 {
2149 uint32_t me;
2150
2151 me = MB(ctx->opcode) | (men << 5);
2152 gen_rldnm(ctx, 0, me);
2153 }
2154 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2155
2156 /* rldimi - rldimi. */
2157 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2158 {
2159 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2160 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2161 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2162 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2163 uint32_t me = 63 - sh;
2164
2165 if (mb <= me) {
2166 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2167 } else {
2168 target_ulong mask = MASK(mb, me);
2169 TCGv t1 = tcg_temp_new();
2170
2171 tcg_gen_rotli_tl(t1, t_rs, sh);
2172 tcg_gen_andi_tl(t1, t1, mask);
2173 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2174 tcg_gen_or_tl(t_ra, t_ra, t1);
2175 tcg_temp_free(t1);
2176 }
2177 if (unlikely(Rc(ctx->opcode) != 0)) {
2178 gen_set_Rc0(ctx, t_ra);
2179 }
2180 }
2181 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2182 #endif
2183
2184 /*** Integer shift ***/
2185
2186 /* slw & slw. */
2187 static void gen_slw(DisasContext *ctx)
2188 {
2189 TCGv t0, t1;
2190
2191 t0 = tcg_temp_new();
2192 /* AND rS with a mask that is 0 when rB >= 0x20 */
2193 #if defined(TARGET_PPC64)
2194 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2195 tcg_gen_sari_tl(t0, t0, 0x3f);
2196 #else
2197 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2198 tcg_gen_sari_tl(t0, t0, 0x1f);
2199 #endif
2200 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2201 t1 = tcg_temp_new();
2202 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2203 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2204 tcg_temp_free(t1);
2205 tcg_temp_free(t0);
2206 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2207 if (unlikely(Rc(ctx->opcode) != 0))
2208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2209 }
2210
2211 /* sraw & sraw. */
2212 static void gen_sraw(DisasContext *ctx)
2213 {
2214 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2215 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2216 if (unlikely(Rc(ctx->opcode) != 0))
2217 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2218 }
2219
2220 /* srawi & srawi. */
2221 static void gen_srawi(DisasContext *ctx)
2222 {
2223 int sh = SH(ctx->opcode);
2224 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2225 TCGv src = cpu_gpr[rS(ctx->opcode)];
2226 if (sh == 0) {
2227 tcg_gen_ext32s_tl(dst, src);
2228 tcg_gen_movi_tl(cpu_ca, 0);
2229 } else {
2230 TCGv t0;
2231 tcg_gen_ext32s_tl(dst, src);
2232 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2233 t0 = tcg_temp_new();
2234 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2235 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2236 tcg_temp_free(t0);
2237 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2238 tcg_gen_sari_tl(dst, dst, sh);
2239 }
2240 if (unlikely(Rc(ctx->opcode) != 0)) {
2241 gen_set_Rc0(ctx, dst);
2242 }
2243 }
2244
2245 /* srw & srw. */
2246 static void gen_srw(DisasContext *ctx)
2247 {
2248 TCGv t0, t1;
2249
2250 t0 = tcg_temp_new();
2251 /* AND rS with a mask that is 0 when rB >= 0x20 */
2252 #if defined(TARGET_PPC64)
2253 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2254 tcg_gen_sari_tl(t0, t0, 0x3f);
2255 #else
2256 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2257 tcg_gen_sari_tl(t0, t0, 0x1f);
2258 #endif
2259 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2260 tcg_gen_ext32u_tl(t0, t0);
2261 t1 = tcg_temp_new();
2262 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2263 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2264 tcg_temp_free(t1);
2265 tcg_temp_free(t0);
2266 if (unlikely(Rc(ctx->opcode) != 0))
2267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2268 }
2269
2270 #if defined(TARGET_PPC64)
2271 /* sld & sld. */
2272 static void gen_sld(DisasContext *ctx)
2273 {
2274 TCGv t0, t1;
2275
2276 t0 = tcg_temp_new();
2277 /* AND rS with a mask that is 0 when rB >= 0x40 */
2278 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2279 tcg_gen_sari_tl(t0, t0, 0x3f);
2280 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2281 t1 = tcg_temp_new();
2282 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2283 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2284 tcg_temp_free(t1);
2285 tcg_temp_free(t0);
2286 if (unlikely(Rc(ctx->opcode) != 0))
2287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2288 }
2289
2290 /* srad & srad. */
2291 static void gen_srad(DisasContext *ctx)
2292 {
2293 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2294 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2295 if (unlikely(Rc(ctx->opcode) != 0))
2296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2297 }
2298 /* sradi & sradi. */
2299 static inline void gen_sradi(DisasContext *ctx, int n)
2300 {
2301 int sh = SH(ctx->opcode) + (n << 5);
2302 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2303 TCGv src = cpu_gpr[rS(ctx->opcode)];
2304 if (sh == 0) {
2305 tcg_gen_mov_tl(dst, src);
2306 tcg_gen_movi_tl(cpu_ca, 0);
2307 } else {
2308 TCGv t0;
2309 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2310 t0 = tcg_temp_new();
2311 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2312 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2313 tcg_temp_free(t0);
2314 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2315 tcg_gen_sari_tl(dst, src, sh);
2316 }
2317 if (unlikely(Rc(ctx->opcode) != 0)) {
2318 gen_set_Rc0(ctx, dst);
2319 }
2320 }
2321
2322 static void gen_sradi0(DisasContext *ctx)
2323 {
2324 gen_sradi(ctx, 0);
2325 }
2326
2327 static void gen_sradi1(DisasContext *ctx)
2328 {
2329 gen_sradi(ctx, 1);
2330 }
2331
2332 /* srd & srd. */
2333 static void gen_srd(DisasContext *ctx)
2334 {
2335 TCGv t0, t1;
2336
2337 t0 = tcg_temp_new();
2338 /* AND rS with a mask that is 0 when rB >= 0x40 */
2339 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2340 tcg_gen_sari_tl(t0, t0, 0x3f);
2341 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2342 t1 = tcg_temp_new();
2343 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2344 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2345 tcg_temp_free(t1);
2346 tcg_temp_free(t0);
2347 if (unlikely(Rc(ctx->opcode) != 0))
2348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2349 }
2350 #endif
2351
2352 /*** Addressing modes ***/
2353 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2354 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2355 target_long maskl)
2356 {
2357 target_long simm = SIMM(ctx->opcode);
2358
2359 simm &= ~maskl;
2360 if (rA(ctx->opcode) == 0) {
2361 if (NARROW_MODE(ctx)) {
2362 simm = (uint32_t)simm;
2363 }
2364 tcg_gen_movi_tl(EA, simm);
2365 } else if (likely(simm != 0)) {
2366 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2367 if (NARROW_MODE(ctx)) {
2368 tcg_gen_ext32u_tl(EA, EA);
2369 }
2370 } else {
2371 if (NARROW_MODE(ctx)) {
2372 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2373 } else {
2374 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2375 }
2376 }
2377 }
2378
2379 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2380 {
2381 if (rA(ctx->opcode) == 0) {
2382 if (NARROW_MODE(ctx)) {
2383 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2384 } else {
2385 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2386 }
2387 } else {
2388 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2389 if (NARROW_MODE(ctx)) {
2390 tcg_gen_ext32u_tl(EA, EA);
2391 }
2392 }
2393 }
2394
2395 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2396 {
2397 if (rA(ctx->opcode) == 0) {
2398 tcg_gen_movi_tl(EA, 0);
2399 } else if (NARROW_MODE(ctx)) {
2400 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2401 } else {
2402 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2403 }
2404 }
2405
2406 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2407 target_long val)
2408 {
2409 tcg_gen_addi_tl(ret, arg1, val);
2410 if (NARROW_MODE(ctx)) {
2411 tcg_gen_ext32u_tl(ret, ret);
2412 }
2413 }
2414
2415 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2416 {
2417 TCGLabel *l1 = gen_new_label();
2418 TCGv t0 = tcg_temp_new();
2419 TCGv_i32 t1, t2;
2420 tcg_gen_andi_tl(t0, EA, mask);
2421 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2422 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2423 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2424 gen_update_nip(ctx, ctx->nip - 4);
2425 gen_helper_raise_exception_err(cpu_env, t1, t2);
2426 tcg_temp_free_i32(t1);
2427 tcg_temp_free_i32(t2);
2428 gen_set_label(l1);
2429 tcg_temp_free(t0);
2430 }
2431
2432 static inline void gen_align_no_le(DisasContext *ctx)
2433 {
2434 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2435 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2436 }
2437
2438 /*** Integer load ***/
2439 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2440 {
2441 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2442 }
2443
2444 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2445 {
2446 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2447 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2448 }
2449
2450 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2451 {
2452 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2453 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2454 }
2455
2456 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2457 {
2458 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2459 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2460 }
2461
2462 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2463 {
2464 TCGv tmp = tcg_temp_new();
2465 gen_qemu_ld32u(ctx, tmp, addr);
2466 tcg_gen_extu_tl_i64(val, tmp);
2467 tcg_temp_free(tmp);
2468 }
2469
2470 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2471 {
2472 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2473 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2474 }
2475
2476 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2477 {
2478 TCGv tmp = tcg_temp_new();
2479 gen_qemu_ld32s(ctx, tmp, addr);
2480 tcg_gen_ext_tl_i64(val, tmp);
2481 tcg_temp_free(tmp);
2482 }
2483
2484 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2485 {
2486 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2487 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2488 }
2489
2490 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2491 {
2492 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2493 }
2494
2495 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2496 {
2497 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2498 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2499 }
2500
2501 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2502 {
2503 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2504 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2505 }
2506
2507 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2508 {
2509 TCGv tmp = tcg_temp_new();
2510 tcg_gen_trunc_i64_tl(tmp, val);
2511 gen_qemu_st32(ctx, tmp, addr);
2512 tcg_temp_free(tmp);
2513 }
2514
2515 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2516 {
2517 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2518 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2519 }
2520
2521 #define GEN_LD(name, ldop, opc, type) \
2522 static void glue(gen_, name)(DisasContext *ctx) \
2523 { \
2524 TCGv EA; \
2525 gen_set_access_type(ctx, ACCESS_INT); \
2526 EA = tcg_temp_new(); \
2527 gen_addr_imm_index(ctx, EA, 0); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_temp_free(EA); \
2530 }
2531
2532 #define GEN_LDU(name, ldop, opc, type) \
2533 static void glue(gen_, name##u)(DisasContext *ctx) \
2534 { \
2535 TCGv EA; \
2536 if (unlikely(rA(ctx->opcode) == 0 || \
2537 rA(ctx->opcode) == rD(ctx->opcode))) { \
2538 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2539 return; \
2540 } \
2541 gen_set_access_type(ctx, ACCESS_INT); \
2542 EA = tcg_temp_new(); \
2543 if (type == PPC_64B) \
2544 gen_addr_imm_index(ctx, EA, 0x03); \
2545 else \
2546 gen_addr_imm_index(ctx, EA, 0); \
2547 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2548 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2549 tcg_temp_free(EA); \
2550 }
2551
2552 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2553 static void glue(gen_, name##ux)(DisasContext *ctx) \
2554 { \
2555 TCGv EA; \
2556 if (unlikely(rA(ctx->opcode) == 0 || \
2557 rA(ctx->opcode) == rD(ctx->opcode))) { \
2558 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2559 return; \
2560 } \
2561 gen_set_access_type(ctx, ACCESS_INT); \
2562 EA = tcg_temp_new(); \
2563 gen_addr_reg_index(ctx, EA); \
2564 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2565 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2566 tcg_temp_free(EA); \
2567 }
2568
2569 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2570 static void glue(gen_, name##x)(DisasContext *ctx) \
2571 { \
2572 TCGv EA; \
2573 chk; \
2574 gen_set_access_type(ctx, ACCESS_INT); \
2575 EA = tcg_temp_new(); \
2576 gen_addr_reg_index(ctx, EA); \
2577 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2578 tcg_temp_free(EA); \
2579 }
2580
2581 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2582 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2583
2584 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2585 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2586
2587 #define GEN_LDS(name, ldop, op, type) \
2588 GEN_LD(name, ldop, op | 0x20, type); \
2589 GEN_LDU(name, ldop, op | 0x21, type); \
2590 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2591 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2592
2593 /* lbz lbzu lbzux lbzx */
2594 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2595 /* lha lhau lhaux lhax */
2596 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2597 /* lhz lhzu lhzux lhzx */
2598 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2599 /* lwz lwzu lwzux lwzx */
2600 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2601 #if defined(TARGET_PPC64)
2602 /* lwaux */
2603 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2604 /* lwax */
2605 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2606 /* ldux */
2607 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2608 /* ldx */
2609 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2610
2611 /* CI load/store variants */
2612 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2613 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2614 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2615 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2616
2617 static void gen_ld(DisasContext *ctx)
2618 {
2619 TCGv EA;
2620 if (Rc(ctx->opcode)) {
2621 if (unlikely(rA(ctx->opcode) == 0 ||
2622 rA(ctx->opcode) == rD(ctx->opcode))) {
2623 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2624 return;
2625 }
2626 }
2627 gen_set_access_type(ctx, ACCESS_INT);
2628 EA = tcg_temp_new();
2629 gen_addr_imm_index(ctx, EA, 0x03);
2630 if (ctx->opcode & 0x02) {
2631 /* lwa (lwau is undefined) */
2632 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2633 } else {
2634 /* ld - ldu */
2635 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2636 }
2637 if (Rc(ctx->opcode))
2638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2639 tcg_temp_free(EA);
2640 }
2641
2642 /* lq */
2643 static void gen_lq(DisasContext *ctx)
2644 {
2645 int ra, rd;
2646 TCGv EA;
2647
2648 /* lq is a legal user mode instruction starting in ISA 2.07 */
2649 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2650 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2651
2652 if (!legal_in_user_mode && ctx->pr) {
2653 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2654 return;
2655 }
2656
2657 if (!le_is_supported && ctx->le_mode) {
2658 gen_align_no_le(ctx);
2659 return;
2660 }
2661 ra = rA(ctx->opcode);
2662 rd = rD(ctx->opcode);
2663 if (unlikely((rd & 1) || rd == ra)) {
2664 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2665 return;
2666 }
2667
2668 gen_set_access_type(ctx, ACCESS_INT);
2669 EA = tcg_temp_new();
2670 gen_addr_imm_index(ctx, EA, 0x0F);
2671
2672 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2673 64-bit byteswap already. */
2674 if (unlikely(ctx->le_mode)) {
2675 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2676 gen_addr_add(ctx, EA, EA, 8);
2677 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2678 } else {
2679 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2680 gen_addr_add(ctx, EA, EA, 8);
2681 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2682 }
2683 tcg_temp_free(EA);
2684 }
2685 #endif
2686
2687 /*** Integer store ***/
2688 #define GEN_ST(name, stop, opc, type) \
2689 static void glue(gen_, name)(DisasContext *ctx) \
2690 { \
2691 TCGv EA; \
2692 gen_set_access_type(ctx, ACCESS_INT); \
2693 EA = tcg_temp_new(); \
2694 gen_addr_imm_index(ctx, EA, 0); \
2695 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2696 tcg_temp_free(EA); \
2697 }
2698
2699 #define GEN_STU(name, stop, opc, type) \
2700 static void glue(gen_, stop##u)(DisasContext *ctx) \
2701 { \
2702 TCGv EA; \
2703 if (unlikely(rA(ctx->opcode) == 0)) { \
2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2705 return; \
2706 } \
2707 gen_set_access_type(ctx, ACCESS_INT); \
2708 EA = tcg_temp_new(); \
2709 if (type == PPC_64B) \
2710 gen_addr_imm_index(ctx, EA, 0x03); \
2711 else \
2712 gen_addr_imm_index(ctx, EA, 0); \
2713 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2714 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2715 tcg_temp_free(EA); \
2716 }
2717
2718 #define GEN_STUX(name, stop, opc2, opc3, type) \
2719 static void glue(gen_, name##ux)(DisasContext *ctx) \
2720 { \
2721 TCGv EA; \
2722 if (unlikely(rA(ctx->opcode) == 0)) { \
2723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2724 return; \
2725 } \
2726 gen_set_access_type(ctx, ACCESS_INT); \
2727 EA = tcg_temp_new(); \
2728 gen_addr_reg_index(ctx, EA); \
2729 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2730 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2731 tcg_temp_free(EA); \
2732 }
2733
2734 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2735 static void glue(gen_, name##x)(DisasContext *ctx) \
2736 { \
2737 TCGv EA; \
2738 chk; \
2739 gen_set_access_type(ctx, ACCESS_INT); \
2740 EA = tcg_temp_new(); \
2741 gen_addr_reg_index(ctx, EA); \
2742 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2743 tcg_temp_free(EA); \
2744 }
2745 #define GEN_STX(name, stop, opc2, opc3, type) \
2746 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2747
2748 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2749 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2750
2751 #define GEN_STS(name, stop, op, type) \
2752 GEN_ST(name, stop, op | 0x20, type); \
2753 GEN_STU(name, stop, op | 0x21, type); \
2754 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2755 GEN_STX(name, stop, 0x17, op | 0x00, type)
2756
2757 /* stb stbu stbux stbx */
2758 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2759 /* sth sthu sthux sthx */
2760 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2761 /* stw stwu stwux stwx */
2762 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2763 #if defined(TARGET_PPC64)
2764 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2765 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2766 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2767 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2768 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2769 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2770
2771 static void gen_std(DisasContext *ctx)
2772 {
2773 int rs;
2774 TCGv EA;
2775
2776 rs = rS(ctx->opcode);
2777 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2778 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2779 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2780
2781 if (!(ctx->insns_flags & PPC_64BX)) {
2782 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2783 }
2784
2785 if (!legal_in_user_mode && ctx->pr) {
2786 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2787 return;
2788 }
2789
2790 if (!le_is_supported && ctx->le_mode) {
2791 gen_align_no_le(ctx);
2792 return;
2793 }
2794
2795 if (unlikely(rs & 1)) {
2796 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2797 return;
2798 }
2799 gen_set_access_type(ctx, ACCESS_INT);
2800 EA = tcg_temp_new();
2801 gen_addr_imm_index(ctx, EA, 0x03);
2802
2803 /* We only need to swap high and low halves. gen_qemu_st64 does
2804 necessary 64-bit byteswap already. */
2805 if (unlikely(ctx->le_mode)) {
2806 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2807 gen_addr_add(ctx, EA, EA, 8);
2808 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2809 } else {
2810 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2811 gen_addr_add(ctx, EA, EA, 8);
2812 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2813 }
2814 tcg_temp_free(EA);
2815 } else {
2816 /* std / stdu*/
2817 if (Rc(ctx->opcode)) {
2818 if (unlikely(rA(ctx->opcode) == 0)) {
2819 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2820 return;
2821 }
2822 }
2823 gen_set_access_type(ctx, ACCESS_INT);
2824 EA = tcg_temp_new();
2825 gen_addr_imm_index(ctx, EA, 0x03);
2826 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2827 if (Rc(ctx->opcode))
2828 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2829 tcg_temp_free(EA);
2830 }
2831 }
2832 #endif
2833 /*** Integer load and store with byte reverse ***/
2834
2835 /* lhbrx */
2836 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2837 {
2838 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2839 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2840 }
2841 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2842
2843 /* lwbrx */
2844 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2845 {
2846 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2847 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2848 }
2849 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2850
2851 #if defined(TARGET_PPC64)
2852 /* ldbrx */
2853 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2854 {
2855 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2856 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2857 }
2858 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2859 #endif /* TARGET_PPC64 */
2860
2861 /* sthbrx */
2862 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2863 {
2864 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2865 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2866 }
2867 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2868
2869 /* stwbrx */
2870 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2871 {
2872 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2873 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2874 }
2875 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2876
2877 #if defined(TARGET_PPC64)
2878 /* stdbrx */
2879 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2880 {
2881 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2882 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2883 }
2884 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2885 #endif /* TARGET_PPC64 */
2886
2887 /*** Integer load and store multiple ***/
2888
2889 /* lmw */
2890 static void gen_lmw(DisasContext *ctx)
2891 {
2892 TCGv t0;
2893 TCGv_i32 t1;
2894
2895 if (ctx->le_mode) {
2896 gen_align_no_le(ctx);
2897 return;
2898 }
2899 gen_set_access_type(ctx, ACCESS_INT);
2900 t0 = tcg_temp_new();
2901 t1 = tcg_const_i32(rD(ctx->opcode));
2902 gen_addr_imm_index(ctx, t0, 0);
2903 gen_helper_lmw(cpu_env, t0, t1);
2904 tcg_temp_free(t0);
2905 tcg_temp_free_i32(t1);
2906 }
2907
2908 /* stmw */
2909 static void gen_stmw(DisasContext *ctx)
2910 {
2911 TCGv t0;
2912 TCGv_i32 t1;
2913
2914 if (ctx->le_mode) {
2915 gen_align_no_le(ctx);
2916 return;
2917 }
2918 gen_set_access_type(ctx, ACCESS_INT);
2919 t0 = tcg_temp_new();
2920 t1 = tcg_const_i32(rS(ctx->opcode));
2921 gen_addr_imm_index(ctx, t0, 0);
2922 gen_helper_stmw(cpu_env, t0, t1);
2923 tcg_temp_free(t0);
2924 tcg_temp_free_i32(t1);
2925 }
2926
2927 /*** Integer load and store strings ***/
2928
2929 /* lswi */
2930 /* PowerPC32 specification says we must generate an exception if
2931 * rA is in the range of registers to be loaded.
2932 * In an other hand, IBM says this is valid, but rA won't be loaded.
2933 * For now, I'll follow the spec...
2934 */
2935 static void gen_lswi(DisasContext *ctx)
2936 {
2937 TCGv t0;
2938 TCGv_i32 t1, t2;
2939 int nb = NB(ctx->opcode);
2940 int start = rD(ctx->opcode);
2941 int ra = rA(ctx->opcode);
2942 int nr;
2943
2944 if (ctx->le_mode) {
2945 gen_align_no_le(ctx);
2946 return;
2947 }
2948 if (nb == 0)
2949 nb = 32;
2950 nr = (nb + 3) / 4;
2951 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2952 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2953 return;
2954 }
2955 gen_set_access_type(ctx, ACCESS_INT);
2956 t0 = tcg_temp_new();
2957 gen_addr_register(ctx, t0);
2958 t1 = tcg_const_i32(nb);
2959 t2 = tcg_const_i32(start);
2960 gen_helper_lsw(cpu_env, t0, t1, t2);
2961 tcg_temp_free(t0);
2962 tcg_temp_free_i32(t1);
2963 tcg_temp_free_i32(t2);
2964 }
2965
2966 /* lswx */
2967 static void gen_lswx(DisasContext *ctx)
2968 {
2969 TCGv t0;
2970 TCGv_i32 t1, t2, t3;
2971
2972 if (ctx->le_mode) {
2973 gen_align_no_le(ctx);
2974 return;
2975 }
2976 gen_set_access_type(ctx, ACCESS_INT);
2977 t0 = tcg_temp_new();
2978 gen_addr_reg_index(ctx, t0);
2979 t1 = tcg_const_i32(rD(ctx->opcode));
2980 t2 = tcg_const_i32(rA(ctx->opcode));
2981 t3 = tcg_const_i32(rB(ctx->opcode));
2982 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2983 tcg_temp_free(t0);
2984 tcg_temp_free_i32(t1);
2985 tcg_temp_free_i32(t2);
2986 tcg_temp_free_i32(t3);
2987 }
2988
2989 /* stswi */
2990 static void gen_stswi(DisasContext *ctx)
2991 {
2992 TCGv t0;
2993 TCGv_i32 t1, t2;
2994 int nb = NB(ctx->opcode);
2995
2996 if (ctx->le_mode) {
2997 gen_align_no_le(ctx);
2998 return;
2999 }
3000 gen_set_access_type(ctx, ACCESS_INT);
3001 t0 = tcg_temp_new();
3002 gen_addr_register(ctx, t0);
3003 if (nb == 0)
3004 nb = 32;
3005 t1 = tcg_const_i32(nb);
3006 t2 = tcg_const_i32(rS(ctx->opcode));
3007 gen_helper_stsw(cpu_env, t0, t1, t2);
3008 tcg_temp_free(t0);
3009 tcg_temp_free_i32(t1);
3010 tcg_temp_free_i32(t2);
3011 }
3012
3013 /* stswx */
3014 static void gen_stswx(DisasContext *ctx)
3015 {
3016 TCGv t0;
3017 TCGv_i32 t1, t2;
3018
3019 if (ctx->le_mode) {
3020 gen_align_no_le(ctx);
3021 return;
3022 }
3023 gen_set_access_type(ctx, ACCESS_INT);
3024 t0 = tcg_temp_new();
3025 gen_addr_reg_index(ctx, t0);
3026 t1 = tcg_temp_new_i32();
3027 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3028 tcg_gen_andi_i32(t1, t1, 0x7F);
3029 t2 = tcg_const_i32(rS(ctx->opcode));
3030 gen_helper_stsw(cpu_env, t0, t1, t2);
3031 tcg_temp_free(t0);
3032 tcg_temp_free_i32(t1);
3033 tcg_temp_free_i32(t2);
3034 }
3035
3036 /*** Memory synchronisation ***/
3037 /* eieio */
3038 static void gen_eieio(DisasContext *ctx)
3039 {
3040 }
3041
3042 #if !defined(CONFIG_USER_ONLY)
3043 static inline void gen_check_tlb_flush(DisasContext *ctx)
3044 {
3045 TCGv_i32 t;
3046 TCGLabel *l;
3047
3048 if (!ctx->lazy_tlb_flush) {
3049 return;
3050 }
3051 l = gen_new_label();
3052 t = tcg_temp_new_i32();
3053 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3054 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3055 gen_helper_check_tlb_flush(cpu_env);
3056 gen_set_label(l);
3057 tcg_temp_free_i32(t);
3058 }
3059 #else
3060 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3061 #endif
3062
3063 /* isync */
3064 static void gen_isync(DisasContext *ctx)
3065 {
3066 /*
3067 * We need to check for a pending TLB flush. This can only happen in
3068 * kernel mode however so check MSR_PR
3069 */
3070 if (!ctx->pr) {
3071 gen_check_tlb_flush(ctx);
3072 }
3073 gen_stop_exception(ctx);
3074 }
3075
3076 #define LARX(name, len, loadop) \
3077 static void gen_##name(DisasContext *ctx) \
3078 { \
3079 TCGv t0; \
3080 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3081 gen_set_access_type(ctx, ACCESS_RES); \
3082 t0 = tcg_temp_local_new(); \
3083 gen_addr_reg_index(ctx, t0); \
3084 if ((len) > 1) { \
3085 gen_check_align(ctx, t0, (len)-1); \
3086 } \
3087 gen_qemu_##loadop(ctx, gpr, t0); \
3088 tcg_gen_mov_tl(cpu_reserve, t0); \
3089 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3090 tcg_temp_free(t0); \
3091 }
3092
3093 /* lwarx */
3094 LARX(lbarx, 1, ld8u);
3095 LARX(lharx, 2, ld16u);
3096 LARX(lwarx, 4, ld32u);
3097
3098
3099 #if defined(CONFIG_USER_ONLY)
3100 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3101 int reg, int size)
3102 {
3103 TCGv t0 = tcg_temp_new();
3104
3105 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3106 tcg_gen_movi_tl(t0, (size << 5) | reg);
3107 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3108 tcg_temp_free(t0);
3109 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3110 }
3111 #else
3112 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3113 int reg, int size)
3114 {
3115 TCGLabel *l1;
3116
3117 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3118 l1 = gen_new_label();
3119 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3120 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3121 #if defined(TARGET_PPC64)
3122 if (size == 8) {
3123 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3124 } else
3125 #endif
3126 if (size == 4) {
3127 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3128 } else if (size == 2) {
3129 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3130 #if defined(TARGET_PPC64)
3131 } else if (size == 16) {
3132 TCGv gpr1, gpr2 , EA8;
3133 if (unlikely(ctx->le_mode)) {
3134 gpr1 = cpu_gpr[reg+1];
3135 gpr2 = cpu_gpr[reg];
3136 } else {
3137 gpr1 = cpu_gpr[reg];
3138 gpr2 = cpu_gpr[reg+1];
3139 }
3140 gen_qemu_st64(ctx, gpr1, EA);
3141 EA8 = tcg_temp_local_new();
3142 gen_addr_add(ctx, EA8, EA, 8);
3143 gen_qemu_st64(ctx, gpr2, EA8);
3144 tcg_temp_free(EA8);
3145 #endif
3146 } else {
3147 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3148 }
3149 gen_set_label(l1);
3150 tcg_gen_movi_tl(cpu_reserve, -1);
3151 }
3152 #endif
3153
3154 #define STCX(name, len) \
3155 static void gen_##name(DisasContext *ctx) \
3156 { \
3157 TCGv t0; \
3158 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3159 gen_inval_exception(ctx, \
3160 POWERPC_EXCP_INVAL_INVAL); \
3161 return; \
3162 } \
3163 gen_set_access_type(ctx, ACCESS_RES); \
3164 t0 = tcg_temp_local_new(); \
3165 gen_addr_reg_index(ctx, t0); \
3166 if (len > 1) { \
3167 gen_check_align(ctx, t0, (len)-1); \
3168 } \
3169 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3170 tcg_temp_free(t0); \
3171 }
3172
3173 STCX(stbcx_, 1);
3174 STCX(sthcx_, 2);
3175 STCX(stwcx_, 4);
3176
3177 #if defined(TARGET_PPC64)
3178 /* ldarx */
3179 LARX(ldarx, 8, ld64);
3180
3181 /* lqarx */
3182 static void gen_lqarx(DisasContext *ctx)
3183 {
3184 TCGv EA;
3185 int rd = rD(ctx->opcode);
3186 TCGv gpr1, gpr2;
3187
3188 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3189 (rd == rB(ctx->opcode)))) {
3190 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3191 return;
3192 }
3193
3194 gen_set_access_type(ctx, ACCESS_RES);
3195 EA = tcg_temp_local_new();
3196 gen_addr_reg_index(ctx, EA);
3197 gen_check_align(ctx, EA, 15);
3198 if (unlikely(ctx->le_mode)) {
3199 gpr1 = cpu_gpr[rd+1];
3200 gpr2 = cpu_gpr[rd];
3201 } else {
3202 gpr1 = cpu_gpr[rd];
3203 gpr2 = cpu_gpr[rd+1];
3204 }
3205 gen_qemu_ld64(ctx, gpr1, EA);
3206 tcg_gen_mov_tl(cpu_reserve, EA);
3207
3208 gen_addr_add(ctx, EA, EA, 8);
3209 gen_qemu_ld64(ctx, gpr2, EA);
3210
3211 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3212 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3213
3214 tcg_temp_free(EA);
3215 }
3216
3217 /* stdcx. */
3218 STCX(stdcx_, 8);
3219 STCX(stqcx_, 16);
3220 #endif /* defined(TARGET_PPC64) */
3221
3222 /* sync */
3223 static void gen_sync(DisasContext *ctx)
3224 {
3225 uint32_t l = (ctx->opcode >> 21) & 3;
3226
3227 /*
3228 * We may need to check for a pending TLB flush.
3229 *
3230 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3231 *
3232 * Additionally, this can only happen in kernel mode however so
3233 * check MSR_PR as well.
3234 */
3235 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3236 gen_check_tlb_flush(ctx);
3237 }
3238 }
3239
3240 /* wait */
3241 static void gen_wait(DisasContext *ctx)
3242 {
3243 TCGv_i32 t0 = tcg_const_i32(1);
3244 tcg_gen_st_i32(t0, cpu_env,
3245 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3246 tcg_temp_free_i32(t0);
3247 /* Stop translation, as the CPU is supposed to sleep from now */
3248 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3249 }
3250
3251 #if defined(TARGET_PPC64)
3252 static void gen_doze(DisasContext *ctx)
3253 {
3254 #if defined(CONFIG_USER_ONLY)
3255 GEN_PRIV;
3256 #else
3257 TCGv_i32 t;
3258
3259 CHK_HV;
3260 t = tcg_const_i32(PPC_PM_DOZE);
3261 gen_helper_pminsn(cpu_env, t);
3262 tcg_temp_free_i32(t);
3263 gen_stop_exception(ctx);
3264 #endif /* defined(CONFIG_USER_ONLY) */
3265 }
3266
3267 static void gen_nap(DisasContext *ctx)
3268 {
3269 #if defined(CONFIG_USER_ONLY)
3270 GEN_PRIV;
3271 #else
3272 TCGv_i32 t;
3273
3274 CHK_HV;
3275 t = tcg_const_i32(PPC_PM_NAP);
3276 gen_helper_pminsn(cpu_env, t);
3277 tcg_temp_free_i32(t);
3278 gen_stop_exception(ctx);
3279 #endif /* defined(CONFIG_USER_ONLY) */
3280 }
3281
3282 static void gen_sleep(DisasContext *ctx)
3283 {
3284 #if defined(CONFIG_USER_ONLY)
3285 GEN_PRIV;
3286 #else
3287 TCGv_i32 t;
3288
3289 CHK_HV;
3290 t = tcg_const_i32(PPC_PM_SLEEP);
3291 gen_helper_pminsn(cpu_env, t);
3292 tcg_temp_free_i32(t);
3293 gen_stop_exception(ctx);
3294 #endif /* defined(CONFIG_USER_ONLY) */
3295 }
3296
3297 static void gen_rvwinkle(DisasContext *ctx)
3298 {
3299 #if defined(CONFIG_USER_ONLY)
3300 GEN_PRIV;
3301 #else
3302 TCGv_i32 t;
3303
3304 CHK_HV;
3305 t = tcg_const_i32(PPC_PM_RVWINKLE);
3306 gen_helper_pminsn(cpu_env, t);
3307 tcg_temp_free_i32(t);
3308 gen_stop_exception(ctx);
3309 #endif /* defined(CONFIG_USER_ONLY) */
3310 }
3311 #endif /* #if defined(TARGET_PPC64) */
3312
3313 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3314 {
3315 #if defined(TARGET_PPC64)
3316 if (ctx->has_cfar)
3317 tcg_gen_movi_tl(cpu_cfar, nip);
3318 #endif
3319 }
3320
3321 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3322 {
3323 if (unlikely(ctx->singlestep_enabled)) {
3324 return false;
3325 }
3326
3327 #ifndef CONFIG_USER_ONLY
3328 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3329 #else
3330 return true;
3331 #endif
3332 }
3333
3334 /*** Branch ***/
3335 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3336 {
3337 if (NARROW_MODE(ctx)) {
3338 dest = (uint32_t) dest;
3339 }
3340 if (use_goto_tb(ctx, dest)) {
3341 tcg_gen_goto_tb(n);
3342 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3343 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3344 } else {
3345 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3346 if (unlikely(ctx->singlestep_enabled)) {
3347 if ((ctx->singlestep_enabled &
3348 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3349 (ctx->exception == POWERPC_EXCP_BRANCH ||
3350 ctx->exception == POWERPC_EXCP_TRACE)) {
3351 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3352 }
3353 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3354 gen_debug_exception(ctx);
3355 }
3356 }
3357 tcg_gen_exit_tb(0);
3358 }
3359 }
3360
3361 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3362 {
3363 if (NARROW_MODE(ctx)) {
3364 nip = (uint32_t)nip;
3365 }
3366 tcg_gen_movi_tl(cpu_lr, nip);
3367 }
3368
3369 /* b ba bl bla */
3370 static void gen_b(DisasContext *ctx)
3371 {
3372 target_ulong li, target;
3373
3374 ctx->exception = POWERPC_EXCP_BRANCH;
3375 /* sign extend LI */
3376 li = LI(ctx->opcode);
3377 li = (li ^ 0x02000000) - 0x02000000;
3378 if (likely(AA(ctx->opcode) == 0)) {
3379 target = ctx->nip + li - 4;
3380 } else {
3381 target = li;
3382 }
3383 if (LK(ctx->opcode)) {
3384 gen_setlr(ctx, ctx->nip);
3385 }
3386 gen_update_cfar(ctx, ctx->nip - 4);
3387 gen_goto_tb(ctx, 0, target);
3388 }
3389
3390 #define BCOND_IM 0
3391 #define BCOND_LR 1
3392 #define BCOND_CTR 2
3393 #define BCOND_TAR 3
3394
3395 static inline void gen_bcond(DisasContext *ctx, int type)
3396 {
3397 uint32_t bo = BO(ctx->opcode);
3398 TCGLabel *l1;
3399 TCGv target;
3400
3401 ctx->exception = POWERPC_EXCP_BRANCH;
3402 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3403 target = tcg_temp_local_new();
3404 if (type == BCOND_CTR)
3405 tcg_gen_mov_tl(target, cpu_ctr);
3406 else if (type == BCOND_TAR)
3407 gen_load_spr(target, SPR_TAR);
3408 else
3409 tcg_gen_mov_tl(target, cpu_lr);
3410 } else {
3411 TCGV_UNUSED(target);
3412 }
3413 if (LK(ctx->opcode))
3414 gen_setlr(ctx, ctx->nip);
3415 l1 = gen_new_label();
3416 if ((bo & 0x4) == 0) {
3417 /* Decrement and test CTR */
3418 TCGv temp = tcg_temp_new();
3419 if (unlikely(type == BCOND_CTR)) {
3420 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3421 return;
3422 }
3423 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3424 if (NARROW_MODE(ctx)) {
3425 tcg_gen_ext32u_tl(temp, cpu_ctr);
3426 } else {
3427 tcg_gen_mov_tl(temp, cpu_ctr);
3428 }
3429 if (bo & 0x2) {
3430 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3431 } else {
3432 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3433 }
3434 tcg_temp_free(temp);
3435 }
3436 if ((bo & 0x10) == 0) {
3437 /* Test CR */
3438 uint32_t bi = BI(ctx->opcode);
3439 uint32_t mask = 0x08 >> (bi & 0x03);
3440 TCGv_i32 temp = tcg_temp_new_i32();
3441
3442 if (bo & 0x8) {
3443 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3444 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3445 } else {
3446 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3447 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3448 }
3449 tcg_temp_free_i32(temp);
3450 }
3451 gen_update_cfar(ctx, ctx->nip - 4);
3452 if (type == BCOND_IM) {
3453 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3454 if (likely(AA(ctx->opcode) == 0)) {
3455 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3456 } else {
3457 gen_goto_tb(ctx, 0, li);
3458 }
3459 gen_set_label(l1);
3460 gen_goto_tb(ctx, 1, ctx->nip);
3461 } else {
3462 if (NARROW_MODE(ctx)) {
3463 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3464 } else {
3465 tcg_gen_andi_tl(cpu_nip, target, ~3);
3466 }
3467 tcg_gen_exit_tb(0);
3468 gen_set_label(l1);
3469 gen_update_nip(ctx, ctx->nip);
3470 tcg_gen_exit_tb(0);
3471 }
3472 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3473 tcg_temp_free(target);
3474 }
3475 }
3476
3477 static void gen_bc(DisasContext *ctx)
3478 {
3479 gen_bcond(ctx, BCOND_IM);
3480 }
3481
3482 static void gen_bcctr(DisasContext *ctx)
3483 {
3484 gen_bcond(ctx, BCOND_CTR);
3485 }
3486
3487 static void gen_bclr(DisasContext *ctx)
3488 {
3489 gen_bcond(ctx, BCOND_LR);
3490 }
3491
3492 static void gen_bctar(DisasContext *ctx)
3493 {
3494 gen_bcond(ctx, BCOND_TAR);
3495 }
3496
3497 /*** Condition register logical ***/
3498 #define GEN_CRLOGIC(name, tcg_op, opc) \
3499 static void glue(gen_, name)(DisasContext *ctx) \
3500 { \
3501 uint8_t bitmask; \
3502 int sh; \
3503 TCGv_i32 t0, t1; \
3504 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3505 t0 = tcg_temp_new_i32(); \
3506 if (sh > 0) \
3507 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3508 else if (sh < 0) \
3509 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3510 else \
3511 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3512 t1 = tcg_temp_new_i32(); \
3513 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3514 if (sh > 0) \
3515 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3516 else if (sh < 0) \
3517 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3518 else \
3519 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3520 tcg_op(t0, t0, t1); \
3521 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3522 tcg_gen_andi_i32(t0, t0, bitmask); \
3523 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3524 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3525 tcg_temp_free_i32(t0); \
3526 tcg_temp_free_i32(t1); \
3527 }
3528
3529 /* crand */
3530 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3531 /* crandc */
3532 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3533 /* creqv */
3534 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3535 /* crnand */
3536 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3537 /* crnor */
3538 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3539 /* cror */
3540 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3541 /* crorc */
3542 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3543 /* crxor */
3544 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3545
3546 /* mcrf */
3547 static void gen_mcrf(DisasContext *ctx)
3548 {
3549 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3550 }
3551
3552 /*** System linkage ***/
3553
3554 /* rfi (supervisor only) */
3555 static void gen_rfi(DisasContext *ctx)
3556 {
3557 #if defined(CONFIG_USER_ONLY)
3558 GEN_PRIV;
3559 #else
3560 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3561 * processors compliant with arch 2.x, we should remove it there,
3562 * but we need to fix OpenBIOS not to use it on 970 first
3563 */
3564 /* Restore CPU state */
3565 CHK_SV;
3566 gen_update_cfar(ctx, ctx->nip - 4);
3567 gen_helper_rfi(cpu_env);
3568 gen_sync_exception(ctx);
3569 #endif
3570 }
3571
3572 #if defined(TARGET_PPC64)
3573 static void gen_rfid(DisasContext *ctx)
3574 {
3575 #if defined(CONFIG_USER_ONLY)
3576 GEN_PRIV;
3577 #else
3578 /* Restore CPU state */
3579 CHK_SV;
3580 gen_update_cfar(ctx, ctx->nip - 4);
3581 gen_helper_rfid(cpu_env);
3582 gen_sync_exception(ctx);
3583 #endif
3584 }
3585
3586 static void gen_hrfid(DisasContext *ctx)
3587 {
3588 #if defined(CONFIG_USER_ONLY)
3589 GEN_PRIV;
3590 #else
3591 /* Restore CPU state */
3592 CHK_HV;
3593 gen_helper_hrfid(cpu_env);
3594 gen_sync_exception(ctx);
3595 #endif
3596 }
3597 #endif
3598
3599 /* sc */
3600 #if defined(CONFIG_USER_ONLY)
3601 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3602 #else
3603 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3604 #endif
3605 static void gen_sc(DisasContext *ctx)
3606 {
3607 uint32_t lev;
3608
3609 lev = (ctx->opcode >> 5) & 0x7F;
3610 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3611 }
3612
3613 /*** Trap ***/
3614
3615 /* Check for unconditional traps (always or never) */
3616 static bool check_unconditional_trap(DisasContext *ctx)
3617 {
3618 /* Trap never */
3619 if (TO(ctx->opcode) == 0) {
3620 return true;
3621 }
3622 /* Trap always */
3623 if (TO(ctx->opcode) == 31) {
3624 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3625 return true;
3626 }
3627 return false;
3628 }
3629
3630 /* tw */
3631 static void gen_tw(DisasContext *ctx)
3632 {
3633 TCGv_i32 t0;
3634
3635 if (check_unconditional_trap(ctx)) {
3636 return;
3637 }
3638 t0 = tcg_const_i32(TO(ctx->opcode));
3639 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3640 t0);
3641 tcg_temp_free_i32(t0);
3642 }
3643
3644 /* twi */
3645 static void gen_twi(DisasContext *ctx)
3646 {
3647 TCGv t0;
3648 TCGv_i32 t1;
3649
3650 if (check_unconditional_trap(ctx)) {
3651 return;
3652 }
3653 t0 = tcg_const_tl(SIMM(ctx->opcode));
3654 t1 = tcg_const_i32(TO(ctx->opcode));
3655 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3656 tcg_temp_free(t0);
3657 tcg_temp_free_i32(t1);
3658 }
3659
3660 #if defined(TARGET_PPC64)
3661 /* td */
3662 static void gen_td(DisasContext *ctx)
3663 {
3664 TCGv_i32 t0;
3665
3666 if (check_unconditional_trap(ctx)) {
3667 return;
3668 }
3669 t0 = tcg_const_i32(TO(ctx->opcode));
3670 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3671 t0);
3672 tcg_temp_free_i32(t0);
3673 }
3674
3675 /* tdi */
3676 static void gen_tdi(DisasContext *ctx)
3677 {
3678 TCGv t0;
3679 TCGv_i32 t1;
3680
3681 if (check_unconditional_trap(ctx)) {
3682 return;
3683 }
3684 t0 = tcg_const_tl(SIMM(ctx->opcode));
3685 t1 = tcg_const_i32(TO(ctx->opcode));
3686 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3687 tcg_temp_free(t0);
3688 tcg_temp_free_i32(t1);
3689 }
3690 #endif
3691
3692 /*** Processor control ***/
3693
3694 static void gen_read_xer(TCGv dst)
3695 {
3696 TCGv t0 = tcg_temp_new();
3697 TCGv t1 = tcg_temp_new();
3698 TCGv t2 = tcg_temp_new();
3699 tcg_gen_mov_tl(dst, cpu_xer);
3700 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3701 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3702 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3703 tcg_gen_or_tl(t0, t0, t1);
3704 tcg_gen_or_tl(dst, dst, t2);
3705 tcg_gen_or_tl(dst, dst, t0);
3706 tcg_temp_free(t0);
3707 tcg_temp_free(t1);
3708 tcg_temp_free(t2);
3709 }
3710
3711 static void gen_write_xer(TCGv src)
3712 {
3713 tcg_gen_andi_tl(cpu_xer, src,
3714 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3715 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3716 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3717 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3718 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3719 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3720 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3721 }
3722
3723 /* mcrxr */
3724 static void gen_mcrxr(DisasContext *ctx)
3725 {
3726 TCGv_i32 t0 = tcg_temp_new_i32();
3727 TCGv_i32 t1 = tcg_temp_new_i32();
3728 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3729
3730 tcg_gen_trunc_tl_i32(t0, cpu_so);
3731 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3732 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3733 tcg_gen_shli_i32(t0, t0, 3);
3734 tcg_gen_shli_i32(t1, t1, 2);
3735 tcg_gen_shli_i32(dst, dst, 1);
3736 tcg_gen_or_i32(dst, dst, t0);
3737 tcg_gen_or_i32(dst, dst, t1);
3738 tcg_temp_free_i32(t0);
3739 tcg_temp_free_i32(t1);
3740
3741 tcg_gen_movi_tl(cpu_so, 0);
3742 tcg_gen_movi_tl(cpu_ov, 0);
3743 tcg_gen_movi_tl(cpu_ca, 0);
3744 }
3745
3746 /* mfcr mfocrf */
3747 static void gen_mfcr(DisasContext *ctx)
3748 {
3749 uint32_t crm, crn;
3750
3751 if (likely(ctx->opcode & 0x00100000)) {
3752 crm = CRM(ctx->opcode);
3753 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3754 crn = ctz32 (crm);
3755 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3756 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3757 cpu_gpr[rD(ctx->opcode)], crn * 4);
3758 }
3759 } else {
3760 TCGv_i32 t0 = tcg_temp_new_i32();
3761 tcg_gen_mov_i32(t0, cpu_crf[0]);
3762 tcg_gen_shli_i32(t0, t0, 4);
3763 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3764 tcg_gen_shli_i32(t0, t0, 4);
3765 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3766 tcg_gen_shli_i32(t0, t0, 4);
3767 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3768 tcg_gen_shli_i32(t0, t0, 4);
3769 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3770 tcg_gen_shli_i32(t0, t0, 4);
3771 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3772 tcg_gen_shli_i32(t0, t0, 4);
3773 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3774 tcg_gen_shli_i32(t0, t0, 4);
3775 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3776 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3777 tcg_temp_free_i32(t0);
3778 }
3779 }
3780
3781 /* mfmsr */
3782 static void gen_mfmsr(DisasContext *ctx)
3783 {
3784 CHK_SV;
3785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3786 }
3787
3788 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3789 {
3790 #if 0
3791 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3792 printf("ERROR: try to access SPR %d !\n", sprn);
3793 #endif
3794 }
3795 #define SPR_NOACCESS (&spr_noaccess)
3796
3797 /* mfspr */
3798 static inline void gen_op_mfspr(DisasContext *ctx)
3799 {
3800 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3801 uint32_t sprn = SPR(ctx->opcode);
3802
3803 #if defined(CONFIG_USER_ONLY)
3804 read_cb = ctx->spr_cb[sprn].uea_read;
3805 #else
3806 if (ctx->pr) {
3807 read_cb = ctx->spr_cb[sprn].uea_read;
3808 } else if (ctx->hv) {
3809 read_cb = ctx->spr_cb[sprn].hea_read;
3810 } else {
3811 read_cb = ctx->spr_cb[sprn].oea_read;
3812 }
3813 #endif
3814 if (likely(read_cb != NULL)) {
3815 if (likely(read_cb != SPR_NOACCESS)) {
3816 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3817 } else {
3818 /* Privilege exception */
3819 /* This is a hack to avoid warnings when running Linux:
3820 * this OS breaks the PowerPC virtualisation model,
3821 * allowing userland application to read the PVR
3822 */
3823 if (sprn != SPR_PVR) {
3824 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3825 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3826 if (qemu_log_separate()) {
3827 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3828 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3829 }
3830 }
3831 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3832 }
3833 } else {
3834 /* ISA 2.07 defines these as no-ops */
3835 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3836 (sprn >= 808 && sprn <= 811)) {
3837 /* This is a nop */
3838 return;
3839 }
3840 /* Not defined */
3841 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3842 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3843 if (qemu_log_separate()) {
3844 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3845 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3846 }
3847
3848 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3849 * it can generate a priv, a hv emu or a no-op
3850 */
3851 if (sprn & 0x10) {
3852 if (ctx->pr) {
3853 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3854 }
3855 } else {
3856 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3857 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3858 }
3859 }
3860 }
3861 }
3862
3863 static void gen_mfspr(DisasContext *ctx)
3864 {
3865 gen_op_mfspr(ctx);
3866 }
3867
3868 /* mftb */
3869 static void gen_mftb(DisasContext *ctx)
3870 {
3871 gen_op_mfspr(ctx);
3872 }
3873
3874 /* mtcrf mtocrf*/
3875 static void gen_mtcrf(DisasContext *ctx)
3876 {
3877 uint32_t crm, crn;
3878
3879 crm = CRM(ctx->opcode);
3880 if (likely((ctx->opcode & 0x00100000))) {
3881 if (crm && ((crm & (crm - 1)) == 0)) {
3882 TCGv_i32 temp = tcg_temp_new_i32();
3883 crn = ctz32 (crm);
3884 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3885 tcg_gen_shri_i32(temp, temp, crn * 4);
3886 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3887 tcg_temp_free_i32(temp);
3888 }
3889 } else {
3890 TCGv_i32 temp = tcg_temp_new_i32();
3891 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3892 for (crn = 0 ; crn < 8 ; crn++) {
3893 if (crm & (1 << crn)) {
3894 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3895 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3896 }
3897 }
3898 tcg_temp_free_i32(temp);
3899 }
3900 }
3901
3902 /* mtmsr */
3903 #if defined(TARGET_PPC64)
3904 static void gen_mtmsrd(DisasContext *ctx)
3905 {
3906 CHK_SV;
3907
3908 #if !defined(CONFIG_USER_ONLY)
3909 if (ctx->opcode & 0x00010000) {
3910 /* Special form that does not need any synchronisation */
3911 TCGv t0 = tcg_temp_new();
3912 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3913 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3914 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3915 tcg_temp_free(t0);
3916 } else {
3917 /* XXX: we need to update nip before the store
3918 * if we enter power saving mode, we will exit the loop
3919 * directly from ppc_store_msr
3920 */
3921 gen_update_nip(ctx, ctx->nip);
3922 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3923 /* Must stop the translation as machine state (may have) changed */
3924 /* Note that mtmsr is not always defined as context-synchronizing */
3925 gen_stop_exception(ctx);
3926 }
3927 #endif /* !defined(CONFIG_USER_ONLY) */
3928 }
3929 #endif /* defined(TARGET_PPC64) */
3930
3931 static void gen_mtmsr(DisasContext *ctx)
3932 {
3933 CHK_SV;
3934
3935 #if !defined(CONFIG_USER_ONLY)
3936 if (ctx->opcode & 0x00010000) {
3937 /* Special form that does not need any synchronisation */
3938 TCGv t0 = tcg_temp_new();
3939 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3940 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3941 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3942 tcg_temp_free(t0);
3943 } else {
3944 TCGv msr = tcg_temp_new();
3945
3946 /* XXX: we need to update nip before the store
3947 * if we enter power saving mode, we will exit the loop
3948 * directly from ppc_store_msr
3949 */
3950 gen_update_nip(ctx, ctx->nip);
3951 #if defined(TARGET_PPC64)
3952 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3953 #else
3954 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3955 #endif
3956 gen_helper_store_msr(cpu_env, msr);
3957 tcg_temp_free(msr);
3958 /* Must stop the translation as machine state (may have) changed */
3959 /* Note that mtmsr is not always defined as context-synchronizing */
3960 gen_stop_exception(ctx);
3961 }
3962 #endif
3963 }
3964
3965 /* mtspr */
3966 static void gen_mtspr(DisasContext *ctx)
3967 {
3968 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3969 uint32_t sprn = SPR(ctx->opcode);
3970
3971 #if defined(CONFIG_USER_ONLY)
3972 write_cb = ctx->spr_cb[sprn].uea_write;
3973 #else
3974 if (ctx->pr) {
3975 write_cb = ctx->spr_cb[sprn].uea_write;
3976 } else if (ctx->hv) {
3977 write_cb = ctx->spr_cb[sprn].hea_write;
3978 } else {
3979 write_cb = ctx->spr_cb[sprn].oea_write;
3980 }
3981 #endif
3982 if (likely(write_cb != NULL)) {
3983 if (likely(write_cb != SPR_NOACCESS)) {
3984 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3985 } else {
3986 /* Privilege exception */
3987 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3988 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3989 if (qemu_log_separate()) {
3990 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3991 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3992 }
3993 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3994 }
3995 } else {
3996 /* ISA 2.07 defines these as no-ops */
3997 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3998 (sprn >= 808 && sprn <= 811)) {
3999 /* This is a nop */
4000 return;
4001 }
4002
4003 /* Not defined */
4004 if (qemu_log_separate()) {
4005 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4006 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4007 }
4008 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4009 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4010
4011
4012 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4013 * it can generate a priv, a hv emu or a no-op
4014 */
4015 if (sprn & 0x10) {
4016 if (ctx->pr) {
4017 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4018 }
4019 } else {
4020 if (ctx->pr || sprn == 0) {
4021 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4022 }
4023 }
4024 }
4025 }
4026
4027 #if defined(TARGET_PPC64)
4028 /* setb */
4029 static void gen_setb(DisasContext *ctx)
4030 {
4031 TCGv_i32 t0 = tcg_temp_new_i32();
4032 TCGv_i32 t8 = tcg_temp_new_i32();
4033 TCGv_i32 tm1 = tcg_temp_new_i32();
4034 int crf = crfS(ctx->opcode);
4035
4036 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4037 tcg_gen_movi_i32(t8, 8);
4038 tcg_gen_movi_i32(tm1, -1);
4039 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4040 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4041
4042 tcg_temp_free_i32(t0);
4043 tcg_temp_free_i32(t8);
4044 tcg_temp_free_i32(tm1);
4045 }
4046 #endif
4047
4048 /*** Cache management ***/
4049
4050 /* dcbf */
4051 static void gen_dcbf(DisasContext *ctx)
4052 {
4053 /* XXX: specification says this is treated as a load by the MMU */
4054 TCGv t0;
4055 gen_set_access_type(ctx, ACCESS_CACHE);
4056 t0 = tcg_temp_new();
4057 gen_addr_reg_index(ctx, t0);
4058 gen_qemu_ld8u(ctx, t0, t0);
4059 tcg_temp_free(t0);
4060 }
4061
4062 /* dcbi (Supervisor only) */
4063 static void gen_dcbi(DisasContext *ctx)
4064 {
4065 #if defined(CONFIG_USER_ONLY)
4066 GEN_PRIV;
4067 #else
4068 TCGv EA, val;
4069
4070 CHK_SV;
4071 EA = tcg_temp_new();
4072 gen_set_access_type(ctx, ACCESS_CACHE);
4073 gen_addr_reg_index(ctx, EA);
4074 val = tcg_temp_new();
4075 /* XXX: specification says this should be treated as a store by the MMU */
4076 gen_qemu_ld8u(ctx, val, EA);
4077 gen_qemu_st8(ctx, val, EA);
4078 tcg_temp_free(val);
4079 tcg_temp_free(EA);
4080 #endif /* defined(CONFIG_USER_ONLY) */
4081 }
4082
4083 /* dcdst */
4084 static void gen_dcbst(DisasContext *ctx)
4085 {
4086 /* XXX: specification say this is treated as a load by the MMU */
4087 TCGv t0;
4088 gen_set_access_type(ctx, ACCESS_CACHE);
4089 t0 = tcg_temp_new();
4090 gen_addr_reg_index(ctx, t0);
4091 gen_qemu_ld8u(ctx, t0, t0);
4092 tcg_temp_free(t0);
4093 }
4094
4095 /* dcbt */
4096 static void gen_dcbt(DisasContext *ctx)
4097 {
4098 /* interpreted as no-op */
4099 /* XXX: specification say this is treated as a load by the MMU
4100 * but does not generate any exception
4101 */
4102 }
4103
4104 /* dcbtst */
4105 static void gen_dcbtst(DisasContext *ctx)
4106 {
4107 /* interpreted as no-op */
4108 /* XXX: specification say this is treated as a load by the MMU
4109 * but does not generate any exception
4110 */
4111 }
4112
4113 /* dcbtls */
4114 static void gen_dcbtls(DisasContext *ctx)
4115 {
4116 /* Always fails locking the cache */
4117 TCGv t0 = tcg_temp_new();
4118 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4119 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4120 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4121 tcg_temp_free(t0);
4122 }
4123
4124 /* dcbz */
4125 static void gen_dcbz(DisasContext *ctx)
4126 {
4127 TCGv tcgv_addr;
4128 TCGv_i32 tcgv_op;
4129
4130 gen_set_access_type(ctx, ACCESS_CACHE);
4131 tcgv_addr = tcg_temp_new();
4132 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4133 gen_addr_reg_index(ctx, tcgv_addr);
4134 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4135 tcg_temp_free(tcgv_addr);
4136 tcg_temp_free_i32(tcgv_op);
4137 }
4138
4139 /* dst / dstt */
4140 static void gen_dst(DisasContext *ctx)
4141 {
4142 if (rA(ctx->opcode) == 0) {
4143 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4144 } else {
4145 /* interpreted as no-op */
4146 }
4147 }
4148
4149 /* dstst /dststt */
4150 static void gen_dstst(DisasContext *ctx)
4151 {
4152 if (rA(ctx->opcode) == 0) {
4153 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4154 } else {
4155 /* interpreted as no-op */
4156 }
4157
4158 }
4159
4160 /* dss / dssall */
4161 static void gen_dss(DisasContext *ctx)
4162 {
4163 /* interpreted as no-op */
4164 }
4165
4166 /* icbi */
4167 static void gen_icbi(DisasContext *ctx)
4168 {
4169 TCGv t0;
4170 gen_set_access_type(ctx, ACCESS_CACHE);
4171 t0 = tcg_temp_new();
4172 gen_addr_reg_index(ctx, t0);
4173 gen_helper_icbi(cpu_env, t0);
4174 tcg_temp_free(t0);
4175 }
4176
4177 /* Optional: */
4178 /* dcba */
4179 static void gen_dcba(DisasContext *ctx)
4180 {
4181 /* interpreted as no-op */
4182 /* XXX: specification say this is treated as a store by the MMU
4183 * but does not generate any exception
4184 */
4185 }
4186
4187 /*** Segment register manipulation ***/
4188 /* Supervisor only: */
4189
4190 /* mfsr */
4191 static void gen_mfsr(DisasContext *ctx)
4192 {
4193 #if defined(CONFIG_USER_ONLY)
4194 GEN_PRIV;
4195 #else
4196 TCGv t0;
4197
4198 CHK_SV;
4199 t0 = tcg_const_tl(SR(ctx->opcode));
4200 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4201 tcg_temp_free(t0);
4202 #endif /* defined(CONFIG_USER_ONLY) */
4203 }
4204
4205 /* mfsrin */
4206 static void gen_mfsrin(DisasContext *ctx)
4207 {
4208 #if defined(CONFIG_USER_ONLY)
4209 GEN_PRIV;
4210 #else
4211 TCGv t0;
4212
4213 CHK_SV;
4214 t0 = tcg_temp_new();
4215 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4216 tcg_gen_andi_tl(t0, t0, 0xF);
4217 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4218 tcg_temp_free(t0);
4219 #endif /* defined(CONFIG_USER_ONLY) */
4220 }
4221
4222 /* mtsr */
4223 static void gen_mtsr(DisasContext *ctx)
4224 {
4225 #if defined(CONFIG_USER_ONLY)
4226 GEN_PRIV;
4227 #else
4228 TCGv t0;
4229
4230 CHK_SV;
4231 t0 = tcg_const_tl(SR(ctx->opcode));
4232 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4233 tcg_temp_free(t0);
4234 #endif /* defined(CONFIG_USER_ONLY) */
4235 }
4236
4237 /* mtsrin */
4238 static void gen_mtsrin(DisasContext *ctx)
4239 {
4240 #if defined(CONFIG_USER_ONLY)
4241 GEN_PRIV;
4242 #else
4243 TCGv t0;
4244 CHK_SV;
4245
4246 t0 = tcg_temp_new();
4247 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4248 tcg_gen_andi_tl(t0, t0, 0xF);
4249 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4250 tcg_temp_free(t0);
4251 #endif /* defined(CONFIG_USER_ONLY) */
4252 }
4253
4254 #if defined(TARGET_PPC64)
4255 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4256
4257 /* mfsr */
4258 static void gen_mfsr_64b(DisasContext *ctx)
4259 {
4260 #if defined(CONFIG_USER_ONLY)
4261 GEN_PRIV;
4262 #else
4263 TCGv t0;
4264
4265 CHK_SV;
4266 t0 = tcg_const_tl(SR(ctx->opcode));
4267 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4268 tcg_temp_free(t0);
4269 #endif /* defined(CONFIG_USER_ONLY) */
4270 }
4271
4272 /* mfsrin */
4273 static void gen_mfsrin_64b(DisasContext *ctx)
4274 {
4275 #if defined(CONFIG_USER_ONLY)
4276 GEN_PRIV;
4277 #else
4278 TCGv t0;
4279
4280 CHK_SV;
4281 t0 = tcg_temp_new();
4282 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4283 tcg_gen_andi_tl(t0, t0, 0xF);
4284 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4285 tcg_temp_free(t0);
4286 #endif /* defined(CONFIG_USER_ONLY) */
4287 }
4288
4289 /* mtsr */
4290 static void gen_mtsr_64b(DisasContext *ctx)
4291 {
4292 #if defined(CONFIG_USER_ONLY)
4293 GEN_PRIV;
4294 #else
4295 TCGv t0;
4296
4297 CHK_SV;
4298 t0 = tcg_const_tl(SR(ctx->opcode));
4299 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4300 tcg_temp_free(t0);
4301 #endif /* defined(CONFIG_USER_ONLY) */
4302 }
4303
4304 /* mtsrin */
4305 static void gen_mtsrin_64b(DisasContext *ctx)
4306 {
4307 #if defined(CONFIG_USER_ONLY)
4308 GEN_PRIV;
4309 #else
4310 TCGv t0;
4311
4312 CHK_SV;
4313 t0 = tcg_temp_new();
4314 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4315 tcg_gen_andi_tl(t0, t0, 0xF);
4316 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4317 tcg_temp_free(t0);
4318 #endif /* defined(CONFIG_USER_ONLY) */
4319 }
4320
4321 /* slbmte */
4322 static void gen_slbmte(DisasContext *ctx)
4323 {
4324 #if defined(CONFIG_USER_ONLY)
4325 GEN_PRIV;
4326 #else
4327 CHK_SV;
4328
4329 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4330 cpu_gpr[rS(ctx->opcode)]);
4331 #endif /* defined(CONFIG_USER_ONLY) */
4332 }
4333
4334 static void gen_slbmfee(DisasContext *ctx)
4335 {
4336 #if defined(CONFIG_USER_ONLY)
4337 GEN_PRIV;
4338 #else
4339 CHK_SV;
4340
4341 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4342 cpu_gpr[rB(ctx->opcode)]);
4343 #endif /* defined(CONFIG_USER_ONLY) */
4344 }
4345
4346 static void gen_slbmfev(DisasContext *ctx)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 GEN_PRIV;
4350 #else
4351 CHK_SV;
4352
4353 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4354 cpu_gpr[rB(ctx->opcode)]);
4355 #endif /* defined(CONFIG_USER_ONLY) */
4356 }
4357
4358 static void gen_slbfee_(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4362 #else
4363 TCGLabel *l1, *l2;
4364
4365 if (unlikely(ctx->pr)) {
4366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4367 return;
4368 }
4369 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4370 cpu_gpr[rB(ctx->opcode)]);
4371 l1 = gen_new_label();
4372 l2 = gen_new_label();
4373 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4374 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4375 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4376 tcg_gen_br(l2);
4377 gen_set_label(l1);
4378 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4379 gen_set_label(l2);
4380 #endif
4381 }
4382 #endif /* defined(TARGET_PPC64) */
4383
4384 /*** Lookaside buffer management ***/
4385 /* Optional & supervisor only: */
4386
4387 /* tlbia */
4388 static void gen_tlbia(DisasContext *ctx)
4389 {
4390 #if defined(CONFIG_USER_ONLY)
4391 GEN_PRIV;
4392 #else
4393 CHK_HV;
4394
4395 gen_helper_tlbia(cpu_env);
4396 #endif /* defined(CONFIG_USER_ONLY) */
4397 }
4398
4399 /* tlbiel */
4400 static void gen_tlbiel(DisasContext *ctx)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 GEN_PRIV;
4404 #else
4405 CHK_SV;
4406
4407 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4408 #endif /* defined(CONFIG_USER_ONLY) */
4409 }
4410
4411 /* tlbie */
4412 static void gen_tlbie(DisasContext *ctx)
4413 {
4414 #if defined(CONFIG_USER_ONLY)
4415 GEN_PRIV;
4416 #else
4417 CHK_HV;
4418
4419 if (NARROW_MODE(ctx)) {
4420 TCGv t0 = tcg_temp_new();
4421 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4422 gen_helper_tlbie(cpu_env, t0);
4423 tcg_temp_free(t0);
4424 } else {
4425 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4426 }
4427 #endif /* defined(CONFIG_USER_ONLY) */
4428 }
4429
4430 /* tlbsync */
4431 static void gen_tlbsync(DisasContext *ctx)
4432 {
4433 #if defined(CONFIG_USER_ONLY)
4434 GEN_PRIV;
4435 #else
4436 CHK_HV;
4437
4438 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4439 * embedded however needs to deal with tlbsync. We don't try to be
4440 * fancy and swallow the overhead of checking for both.
4441 */
4442 gen_check_tlb_flush(ctx);
4443 #endif /* defined(CONFIG_USER_ONLY) */
4444 }
4445
4446 #if defined(TARGET_PPC64)
4447 /* slbia */
4448 static void gen_slbia(DisasContext *ctx)
4449 {
4450 #if defined(CONFIG_USER_ONLY)
4451 GEN_PRIV;
4452 #else
4453 CHK_SV;
4454
4455 gen_helper_slbia(cpu_env);
4456 #endif /* defined(CONFIG_USER_ONLY) */
4457 }
4458
4459 /* slbie */
4460 static void gen_slbie(DisasContext *ctx)
4461 {
4462 #if defined(CONFIG_USER_ONLY)
4463 GEN_PRIV;
4464 #else
4465 CHK_SV;
4466
4467 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4468 #endif /* defined(CONFIG_USER_ONLY) */
4469 }
4470 #endif /* defined(TARGET_PPC64) */
4471
4472 /*** External control ***/
4473 /* Optional: */
4474
4475 /* eciwx */
4476 static void gen_eciwx(DisasContext *ctx)
4477 {
4478 TCGv t0;
4479 /* Should check EAR[E] ! */
4480 gen_set_access_type(ctx, ACCESS_EXT);
4481 t0 = tcg_temp_new();
4482 gen_addr_reg_index(ctx, t0);
4483 gen_check_align(ctx, t0, 0x03);
4484 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4485 tcg_temp_free(t0);
4486 }
4487
4488 /* ecowx */
4489 static void gen_ecowx(DisasContext *ctx)
4490 {
4491 TCGv t0;
4492 /* Should check EAR[E] ! */
4493 gen_set_access_type(ctx, ACCESS_EXT);
4494 t0 = tcg_temp_new();
4495 gen_addr_reg_index(ctx, t0);
4496 gen_check_align(ctx, t0, 0x03);
4497 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4498 tcg_temp_free(t0);
4499 }
4500
4501 /* PowerPC 601 specific instructions */
4502
4503 /* abs - abs. */
4504 static void gen_abs(DisasContext *ctx)
4505 {
4506 TCGLabel *l1 = gen_new_label();
4507 TCGLabel *l2 = gen_new_label();
4508 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4509 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4510 tcg_gen_br(l2);
4511 gen_set_label(l1);
4512 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4513 gen_set_label(l2);
4514 if (unlikely(Rc(ctx->opcode) != 0))
4515 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4516 }
4517
4518 /* abso - abso. */
4519 static void gen_abso(DisasContext *ctx)
4520 {
4521 TCGLabel *l1 = gen_new_label();
4522 TCGLabel *l2 = gen_new_label();
4523 TCGLabel *l3 = gen_new_label();
4524 /* Start with XER OV disabled, the most likely case */
4525 tcg_gen_movi_tl(cpu_ov, 0);
4526 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4527 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4528 tcg_gen_movi_tl(cpu_ov, 1);
4529 tcg_gen_movi_tl(cpu_so, 1);
4530 tcg_gen_br(l2);
4531 gen_set_label(l1);
4532 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4533 tcg_gen_br(l3);
4534 gen_set_label(l2);
4535 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4536 gen_set_label(l3);
4537 if (unlikely(Rc(ctx->opcode) != 0))
4538 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4539 }
4540
4541 /* clcs */
4542 static void gen_clcs(DisasContext *ctx)
4543 {
4544 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4545 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4546 tcg_temp_free_i32(t0);
4547 /* Rc=1 sets CR0 to an undefined state */
4548 }
4549
4550 /* div - div. */
4551 static void gen_div(DisasContext *ctx)
4552 {
4553 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4554 cpu_gpr[rB(ctx->opcode)]);
4555 if (unlikely(Rc(ctx->opcode) != 0))
4556 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4557 }
4558
4559 /* divo - divo. */
4560 static void gen_divo(DisasContext *ctx)
4561 {
4562 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4563 cpu_gpr[rB(ctx->opcode)]);
4564 if (unlikely(Rc(ctx->opcode) != 0))
4565 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4566 }
4567
4568 /* divs - divs. */
4569 static void gen_divs(DisasContext *ctx)
4570 {
4571 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4572 cpu_gpr[rB(ctx->opcode)]);
4573 if (unlikely(Rc(ctx->opcode) != 0))
4574 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4575 }
4576
4577 /* divso - divso. */
4578 static void gen_divso(DisasContext *ctx)
4579 {
4580 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4581 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4582 if (unlikely(Rc(ctx->opcode) != 0))
4583 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4584 }
4585
4586 /* doz - doz. */
4587 static void gen_doz(DisasContext *ctx)
4588 {
4589 TCGLabel *l1 = gen_new_label();
4590 TCGLabel *l2 = gen_new_label();
4591 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4592 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4593 tcg_gen_br(l2);
4594 gen_set_label(l1);
4595 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4596 gen_set_label(l2);
4597 if (unlikely(Rc(ctx->opcode) != 0))
4598 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4599 }
4600
4601 /* dozo - dozo. */
4602 static void gen_dozo(DisasContext *ctx)
4603 {
4604 TCGLabel *l1 = gen_new_label();
4605 TCGLabel *l2 = gen_new_label();
4606 TCGv t0 = tcg_temp_new();
4607 TCGv t1 = tcg_temp_new();
4608 TCGv t2 = tcg_temp_new();
4609 /* Start with XER OV disabled, the most likely case */
4610 tcg_gen_movi_tl(cpu_ov, 0);
4611 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4612 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4613 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4614 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4615 tcg_gen_andc_tl(t1, t1, t2);
4616 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4617 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4618 tcg_gen_movi_tl(cpu_ov, 1);
4619 tcg_gen_movi_tl(cpu_so, 1);
4620 tcg_gen_br(l2);
4621 gen_set_label(l1);
4622 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4623 gen_set_label(l2);
4624 tcg_temp_free(t0);
4625 tcg_temp_free(t1);
4626 tcg_temp_free(t2);
4627 if (unlikely(Rc(ctx->opcode) != 0))
4628 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4629 }
4630
4631 /* dozi */
4632 static void gen_dozi(DisasContext *ctx)
4633 {
4634 target_long simm = SIMM(ctx->opcode);
4635 TCGLabel *l1 = gen_new_label();
4636 TCGLabel *l2 = gen_new_label();
4637 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4638 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4639 tcg_gen_br(l2);
4640 gen_set_label(l1);
4641 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4642 gen_set_label(l2);
4643 if (unlikely(Rc(ctx->opcode) != 0))
4644 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4645 }
4646
4647 /* lscbx - lscbx. */
4648 static void gen_lscbx(DisasContext *ctx)
4649 {
4650 TCGv t0 = tcg_temp_new();
4651 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4652 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4653 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4654
4655 gen_addr_reg_index(ctx, t0);
4656 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4657 tcg_temp_free_i32(t1);
4658 tcg_temp_free_i32(t2);
4659 tcg_temp_free_i32(t3);
4660 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4661 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4662 if (unlikely(Rc(ctx->opcode) != 0))
4663 gen_set_Rc0(ctx, t0);
4664 tcg_temp_free(t0);
4665 }
4666
4667 /* maskg - maskg. */
4668 static void gen_maskg(DisasContext *ctx)
4669 {
4670 TCGLabel *l1 = gen_new_label();
4671 TCGv t0 = tcg_temp_new();
4672 TCGv t1 = tcg_temp_new();
4673 TCGv t2 = tcg_temp_new();
4674 TCGv t3 = tcg_temp_new();
4675 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4676 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4677 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4678 tcg_gen_addi_tl(t2, t0, 1);
4679 tcg_gen_shr_tl(t2, t3, t2);
4680 tcg_gen_shr_tl(t3, t3, t1);
4681 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4682 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4683 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4684 gen_set_label(l1);
4685 tcg_temp_free(t0);
4686 tcg_temp_free(t1);
4687 tcg_temp_free(t2);
4688 tcg_temp_free(t3);
4689 if (unlikely(Rc(ctx->opcode) != 0))
4690 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4691 }
4692
4693 /* maskir - maskir. */
4694 static void gen_maskir(DisasContext *ctx)
4695 {
4696 TCGv t0 = tcg_temp_new();
4697 TCGv t1 = tcg_temp_new();
4698 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4699 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4700 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4701 tcg_temp_free(t0);
4702 tcg_temp_free(t1);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4705 }
4706
4707 /* mul - mul. */
4708 static void gen_mul(DisasContext *ctx)
4709 {
4710 TCGv_i64 t0 = tcg_temp_new_i64();
4711 TCGv_i64 t1 = tcg_temp_new_i64();
4712 TCGv t2 = tcg_temp_new();
4713 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4714 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4715 tcg_gen_mul_i64(t0, t0, t1);
4716 tcg_gen_trunc_i64_tl(t2, t0);
4717 gen_store_spr(SPR_MQ, t2);
4718 tcg_gen_shri_i64(t1, t0, 32);
4719 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4720 tcg_temp_free_i64(t0);
4721 tcg_temp_free_i64(t1);
4722 tcg_temp_free(t2);
4723 if (unlikely(Rc(ctx->opcode) != 0))
4724 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4725 }
4726
4727 /* mulo - mulo. */
4728 static void gen_mulo(DisasContext *ctx)
4729 {
4730 TCGLabel *l1 = gen_new_label();
4731 TCGv_i64 t0 = tcg_temp_new_i64();
4732 TCGv_i64 t1 = tcg_temp_new_i64();
4733 TCGv t2 = tcg_temp_new();
4734 /* Start with XER OV disabled, the most likely case */
4735 tcg_gen_movi_tl(cpu_ov, 0);
4736 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4737 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4738 tcg_gen_mul_i64(t0, t0, t1);
4739 tcg_gen_trunc_i64_tl(t2, t0);
4740 gen_store_spr(SPR_MQ, t2);
4741 tcg_gen_shri_i64(t1, t0, 32);
4742 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4743 tcg_gen_ext32s_i64(t1, t0);
4744 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4745 tcg_gen_movi_tl(cpu_ov, 1);
4746 tcg_gen_movi_tl(cpu_so, 1);
4747 gen_set_label(l1);
4748 tcg_temp_free_i64(t0);
4749 tcg_temp_free_i64(t1);
4750 tcg_temp_free(t2);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4753 }
4754
4755 /* nabs - nabs. */
4756 static void gen_nabs(DisasContext *ctx)
4757 {
4758 TCGLabel *l1 = gen_new_label();
4759 TCGLabel *l2 = gen_new_label();
4760 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4761 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4762 tcg_gen_br(l2);
4763 gen_set_label(l1);
4764 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4765 gen_set_label(l2);
4766 if (unlikely(Rc(ctx->opcode) != 0))
4767 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4768 }
4769
4770 /* nabso - nabso. */
4771 static void gen_nabso(DisasContext *ctx)
4772 {
4773 TCGLabel *l1 = gen_new_label();
4774 TCGLabel *l2 = gen_new_label();
4775 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4777 tcg_gen_br(l2);
4778 gen_set_label(l1);
4779 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4780 gen_set_label(l2);
4781 /* nabs never overflows */
4782 tcg_gen_movi_tl(cpu_ov, 0);
4783 if (unlikely(Rc(ctx->opcode) != 0))
4784 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4785 }
4786
4787 /* rlmi - rlmi. */
4788 static void gen_rlmi(DisasContext *ctx)
4789 {
4790 uint32_t mb = MB(ctx->opcode);
4791 uint32_t me = ME(ctx->opcode);
4792 TCGv t0 = tcg_temp_new();
4793 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4794 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4795 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4796 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4797 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4798 tcg_temp_free(t0);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4801 }
4802
4803 /* rrib - rrib. */
4804 static void gen_rrib(DisasContext *ctx)
4805 {
4806 TCGv t0 = tcg_temp_new();
4807 TCGv t1 = tcg_temp_new();
4808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4809 tcg_gen_movi_tl(t1, 0x80000000);
4810 tcg_gen_shr_tl(t1, t1, t0);
4811 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4812 tcg_gen_and_tl(t0, t0, t1);
4813 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4814 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4815 tcg_temp_free(t0);
4816 tcg_temp_free(t1);
4817 if (unlikely(Rc(ctx->opcode) != 0))
4818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4819 }
4820
4821 /* sle - sle. */
4822 static void gen_sle(DisasContext *ctx)
4823 {
4824 TCGv t0 = tcg_temp_new();
4825 TCGv t1 = tcg_temp_new();
4826 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4827 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4828 tcg_gen_subfi_tl(t1, 32, t1);
4829 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4830 tcg_gen_or_tl(t1, t0, t1);
4831 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4832 gen_store_spr(SPR_MQ, t1);
4833 tcg_temp_free(t0);
4834 tcg_temp_free(t1);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4837 }
4838
4839 /* sleq - sleq. */
4840 static void gen_sleq(DisasContext *ctx)
4841 {
4842 TCGv t0 = tcg_temp_new();
4843 TCGv t1 = tcg_temp_new();
4844 TCGv t2 = tcg_temp_new();
4845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4846 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4847 tcg_gen_shl_tl(t2, t2, t0);
4848 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4849 gen_load_spr(t1, SPR_MQ);
4850 gen_store_spr(SPR_MQ, t0);
4851 tcg_gen_and_tl(t0, t0, t2);
4852 tcg_gen_andc_tl(t1, t1, t2);
4853 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4854 tcg_temp_free(t0);
4855 tcg_temp_free(t1);
4856 tcg_temp_free(t2);
4857 if (unlikely(Rc(ctx->opcode) != 0))
4858 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4859 }
4860
4861 /* sliq - sliq. */
4862 static void gen_sliq(DisasContext *ctx)
4863 {
4864 int sh = SH(ctx->opcode);
4865 TCGv t0 = tcg_temp_new();
4866 TCGv t1 = tcg_temp_new();
4867 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4868 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4869 tcg_gen_or_tl(t1, t0, t1);
4870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4871 gen_store_spr(SPR_MQ, t1);
4872 tcg_temp_free(t0);
4873 tcg_temp_free(t1);
4874 if (unlikely(Rc(ctx->opcode) != 0))
4875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4876 }
4877
4878 /* slliq - slliq. */
4879 static void gen_slliq(DisasContext *ctx)
4880 {
4881 int sh = SH(ctx->opcode);
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4885 gen_load_spr(t1, SPR_MQ);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4888 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4889 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4890 tcg_temp_free(t0);
4891 tcg_temp_free(t1);
4892 if (unlikely(Rc(ctx->opcode) != 0))
4893 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4894 }
4895
4896 /* sllq - sllq. */
4897 static void gen_sllq(DisasContext *ctx)
4898 {
4899 TCGLabel *l1 = gen_new_label();
4900 TCGLabel *l2 = gen_new_label();
4901 TCGv t0 = tcg_temp_local_new();
4902 TCGv t1 = tcg_temp_local_new();
4903 TCGv t2 = tcg_temp_local_new();
4904 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4905 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4906 tcg_gen_shl_tl(t1, t1, t2);
4907 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4908 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4909 gen_load_spr(t0, SPR_MQ);
4910 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4911 tcg_gen_br(l2);
4912 gen_set_label(l1);
4913 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4914 gen_load_spr(t2, SPR_MQ);
4915 tcg_gen_andc_tl(t1, t2, t1);
4916 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4917 gen_set_label(l2);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 tcg_temp_free(t2);
4921 if (unlikely(Rc(ctx->opcode) != 0))
4922 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4923 }
4924
4925 /* slq - slq. */
4926 static void gen_slq(DisasContext *ctx)
4927 {
4928 TCGLabel *l1 = gen_new_label();
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_new();
4931 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4932 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4933 tcg_gen_subfi_tl(t1, 32, t1);
4934 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4935 tcg_gen_or_tl(t1, t0, t1);
4936 gen_store_spr(SPR_MQ, t1);
4937 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4939 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4940 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4941 gen_set_label(l1);
4942 tcg_temp_free(t0);
4943 tcg_temp_free(t1);
4944 if (unlikely(Rc(ctx->opcode) != 0))
4945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4946 }
4947
4948 /* sraiq - sraiq. */
4949 static void gen_sraiq(DisasContext *ctx)
4950 {
4951 int sh = SH(ctx->opcode);
4952 TCGLabel *l1 = gen_new_label();
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4956 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4957 tcg_gen_or_tl(t0, t0, t1);
4958 gen_store_spr(SPR_MQ, t0);
4959 tcg_gen_movi_tl(cpu_ca, 0);
4960 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4961 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4962 tcg_gen_movi_tl(cpu_ca, 1);
4963 gen_set_label(l1);
4964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4965 tcg_temp_free(t0);
4966 tcg_temp_free(t1);
4967 if (unlikely(Rc(ctx->opcode) != 0))
4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4969 }
4970
4971 /* sraq - sraq. */
4972 static void gen_sraq(DisasContext *ctx)
4973 {
4974 TCGLabel *l1 = gen_new_label();
4975 TCGLabel *l2 = gen_new_label();
4976 TCGv t0 = tcg_temp_new();
4977 TCGv t1 = tcg_temp_local_new();
4978 TCGv t2 = tcg_temp_local_new();
4979 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4980 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4981 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4982 tcg_gen_subfi_tl(t2, 32, t2);
4983 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4984 tcg_gen_or_tl(t0, t0, t2);
4985 gen_store_spr(SPR_MQ, t0);
4986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4987 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4988 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4989 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4990 gen_set_label(l1);
4991 tcg_temp_free(t0);
4992 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4993 tcg_gen_movi_tl(cpu_ca, 0);
4994 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4995 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4996 tcg_gen_movi_tl(cpu_ca, 1);
4997 gen_set_label(l2);
4998 tcg_temp_free(t1);
4999 tcg_temp_free(t2);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* sre - sre. */
5005 static void gen_sre(DisasContext *ctx)
5006 {
5007 TCGv t0 = tcg_temp_new();
5008 TCGv t1 = tcg_temp_new();
5009 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5010 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5011 tcg_gen_subfi_tl(t1, 32, t1);
5012 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5013 tcg_gen_or_tl(t1, t0, t1);
5014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5015 gen_store_spr(SPR_MQ, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* srea - srea. */
5023 static void gen_srea(DisasContext *ctx)
5024 {
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5029 gen_store_spr(SPR_MQ, t0);
5030 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5031 tcg_temp_free(t0);
5032 tcg_temp_free(t1);
5033 if (unlikely(Rc(ctx->opcode) != 0))
5034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5035 }
5036
5037 /* sreq */
5038 static void gen_sreq(DisasContext *ctx)
5039 {
5040 TCGv t0 = tcg_temp_new();
5041 TCGv t1 = tcg_temp_new();
5042 TCGv t2 = tcg_temp_new();
5043 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5044 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5045 tcg_gen_shr_tl(t1, t1, t0);
5046 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5047 gen_load_spr(t2, SPR_MQ);
5048 gen_store_spr(SPR_MQ, t0);
5049 tcg_gen_and_tl(t0, t0, t1);
5050 tcg_gen_andc_tl(t2, t2, t1);
5051 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 tcg_temp_free(t2);
5055 if (unlikely(Rc(ctx->opcode) != 0))
5056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5057 }
5058
5059 /* sriq */
5060 static void gen_sriq(DisasContext *ctx)
5061 {
5062 int sh = SH(ctx->opcode);
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5066 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5067 tcg_gen_or_tl(t1, t0, t1);
5068 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5069 gen_store_spr(SPR_MQ, t1);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 if (unlikely(Rc(ctx->opcode) != 0))
5073 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5074 }
5075
5076 /* srliq */
5077 static void gen_srliq(DisasContext *ctx)
5078 {
5079 int sh = SH(ctx->opcode);
5080 TCGv t0 = tcg_temp_new();
5081 TCGv t1 = tcg_temp_new();
5082 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5083 gen_load_spr(t1, SPR_MQ);
5084 gen_store_spr(SPR_MQ, t0);
5085 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5086 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5087 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5088 tcg_temp_free(t0);
5089 tcg_temp_free(t1);
5090 if (unlikely(Rc(ctx->opcode) != 0))
5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5092 }
5093
5094 /* srlq */
5095 static void gen_srlq(DisasContext *ctx)
5096 {
5097 TCGLabel *l1 = gen_new_label();
5098 TCGLabel *l2 = gen_new_label();
5099 TCGv t0 = tcg_temp_local_new();
5100 TCGv t1 = tcg_temp_local_new();
5101 TCGv t2 = tcg_temp_local_new();
5102 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5103 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5104 tcg_gen_shr_tl(t2, t1, t2);
5105 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5106 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5107 gen_load_spr(t0, SPR_MQ);
5108 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5109 tcg_gen_br(l2);
5110 gen_set_label(l1);
5111 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5112 tcg_gen_and_tl(t0, t0, t2);
5113 gen_load_spr(t1, SPR_MQ);
5114 tcg_gen_andc_tl(t1, t1, t2);
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 gen_set_label(l2);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
5119 tcg_temp_free(t2);
5120 if (unlikely(Rc(ctx->opcode) != 0))
5121 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5122 }
5123
5124 /* srq */
5125 static void gen_srq(DisasContext *ctx)
5126 {
5127 TCGLabel *l1 = gen_new_label();
5128 TCGv t0 = tcg_temp_new();
5129 TCGv t1 = tcg_temp_new();
5130 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5132 tcg_gen_subfi_tl(t1, 32, t1);
5133 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5134 tcg_gen_or_tl(t1, t0, t1);
5135 gen_store_spr(SPR_MQ, t1);
5136 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5137 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5138 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5139 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5140 gen_set_label(l1);
5141 tcg_temp_free(t0);
5142 tcg_temp_free(t1);
5143 if (unlikely(Rc(ctx->opcode) != 0))
5144 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5145 }
5146
5147 /* PowerPC 602 specific instructions */
5148
5149 /* dsa */
5150 static void gen_dsa(DisasContext *ctx)
5151 {
5152 /* XXX: TODO */
5153 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5154 }
5155
5156 /* esa */
5157 static void gen_esa(DisasContext *ctx)
5158 {
5159 /* XXX: TODO */
5160 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5161 }
5162
5163 /* mfrom */
5164 static void gen_mfrom(DisasContext *ctx)
5165 {
5166 #if defined(CONFIG_USER_ONLY)
5167 GEN_PRIV;
5168 #else
5169 CHK_SV;
5170 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5171 #endif /* defined(CONFIG_USER_ONLY) */
5172 }
5173
5174 /* 602 - 603 - G2 TLB management */
5175
5176 /* tlbld */
5177 static void gen_tlbld_6xx(DisasContext *ctx)
5178 {
5179 #if defined(CONFIG_USER_ONLY)
5180 GEN_PRIV;
5181 #else
5182 CHK_SV;
5183 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5184 #endif /* defined(CONFIG_USER_ONLY) */
5185 }
5186
5187 /* tlbli */
5188 static void gen_tlbli_6xx(DisasContext *ctx)
5189 {
5190 #if defined(CONFIG_USER_ONLY)
5191 GEN_PRIV;
5192 #else
5193 CHK_SV;
5194 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5195 #endif /* defined(CONFIG_USER_ONLY) */
5196 }
5197
5198 /* 74xx TLB management */
5199
5200 /* tlbld */
5201 static void gen_tlbld_74xx(DisasContext *ctx)
5202 {
5203 #if defined(CONFIG_USER_ONLY)
5204 GEN_PRIV;
5205 #else
5206 CHK_SV;
5207 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5208 #endif /* defined(CONFIG_USER_ONLY) */
5209 }
5210
5211 /* tlbli */
5212 static void gen_tlbli_74xx(DisasContext *ctx)
5213 {
5214 #if defined(CONFIG_USER_ONLY)
5215 GEN_PRIV;
5216 #else
5217 CHK_SV;
5218 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5219 #endif /* defined(CONFIG_USER_ONLY) */
5220 }
5221
5222 /* POWER instructions not in PowerPC 601 */
5223
5224 /* clf */
5225 static void gen_clf(DisasContext *ctx)
5226 {
5227 /* Cache line flush: implemented as no-op */
5228 }
5229
5230 /* cli */
5231 static void gen_cli(DisasContext *ctx)
5232 {
5233 #if defined(CONFIG_USER_ONLY)
5234 GEN_PRIV;
5235 #else
5236 /* Cache line invalidate: privileged and treated as no-op */
5237 CHK_SV;
5238 #endif /* defined(CONFIG_USER_ONLY) */
5239 }
5240
5241 /* dclst */
5242 static void gen_dclst(DisasContext *ctx)
5243 {
5244 /* Data cache line store: treated as no-op */
5245 }
5246
5247 static void gen_mfsri(DisasContext *ctx)
5248 {
5249 #if defined(CONFIG_USER_ONLY)
5250 GEN_PRIV;
5251 #else
5252 int ra = rA(ctx->opcode);
5253 int rd = rD(ctx->opcode);
5254 TCGv t0;
5255
5256 CHK_SV;
5257 t0 = tcg_temp_new();
5258 gen_addr_reg_index(ctx, t0);
5259 tcg_gen_shri_tl(t0, t0, 28);
5260 tcg_gen_andi_tl(t0, t0, 0xF);
5261 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5262 tcg_temp_free(t0);
5263 if (ra != 0 && ra != rd)
5264 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5265 #endif /* defined(CONFIG_USER_ONLY) */
5266 }
5267
5268 static void gen_rac(DisasContext *ctx)
5269 {
5270 #if defined(CONFIG_USER_ONLY)
5271 GEN_PRIV;
5272 #else
5273 TCGv t0;
5274
5275 CHK_SV;
5276 t0 = tcg_temp_new();
5277 gen_addr_reg_index(ctx, t0);
5278 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5279 tcg_temp_free(t0);
5280 #endif /* defined(CONFIG_USER_ONLY) */
5281 }
5282
5283 static void gen_rfsvc(DisasContext *ctx)
5284 {
5285 #if defined(CONFIG_USER_ONLY)
5286 GEN_PRIV;
5287 #else
5288 CHK_SV;
5289
5290 gen_helper_rfsvc(cpu_env);
5291 gen_sync_exception(ctx);
5292 #endif /* defined(CONFIG_USER_ONLY) */
5293 }
5294
5295 #include "translate/fp-impl.c"
5296
5297 #include "translate/vmx-impl.c"
5298
5299 #include "translate/vsx-impl.c"
5300
5301 /* svc is not implemented for now */
5302
5303 /* BookE specific instructions */
5304
5305 /* XXX: not implemented on 440 ? */
5306 static void gen_mfapidi(DisasContext *ctx)
5307 {
5308 /* XXX: TODO */
5309 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5310 }
5311
5312 /* XXX: not implemented on 440 ? */
5313 static void gen_tlbiva(DisasContext *ctx)
5314 {
5315 #if defined(CONFIG_USER_ONLY)
5316 GEN_PRIV;
5317 #else
5318 TCGv t0;
5319
5320 CHK_SV;
5321 t0 = tcg_temp_new();
5322 gen_addr_reg_index(ctx, t0);
5323 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5324 tcg_temp_free(t0);
5325 #endif /* defined(CONFIG_USER_ONLY) */
5326 }
5327
5328 /* All 405 MAC instructions are translated here */
5329 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5330 int ra, int rb, int rt, int Rc)
5331 {
5332 TCGv t0, t1;
5333
5334 t0 = tcg_temp_local_new();
5335 t1 = tcg_temp_local_new();
5336
5337 switch (opc3 & 0x0D) {
5338 case 0x05:
5339 /* macchw - macchw. - macchwo - macchwo. */
5340 /* macchws - macchws. - macchwso - macchwso. */
5341 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5342 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5343 /* mulchw - mulchw. */
5344 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5345 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5346 tcg_gen_ext16s_tl(t1, t1);
5347 break;
5348 case 0x04:
5349 /* macchwu - macchwu. - macchwuo - macchwuo. */
5350 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5351 /* mulchwu - mulchwu. */
5352 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5353 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5354 tcg_gen_ext16u_tl(t1, t1);
5355 break;
5356 case 0x01:
5357 /* machhw - machhw. - machhwo - machhwo. */
5358 /* machhws - machhws. - machhwso - machhwso. */
5359 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5360 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5361 /* mulhhw - mulhhw. */
5362 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5363 tcg_gen_ext16s_tl(t0, t0);
5364 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5365 tcg_gen_ext16s_tl(t1, t1);
5366 break;
5367 case 0x00:
5368 /* machhwu - machhwu. - machhwuo - machhwuo. */
5369 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5370 /* mulhhwu - mulhhwu. */
5371 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5372 tcg_gen_ext16u_tl(t0, t0);
5373 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5374 tcg_gen_ext16u_tl(t1, t1);
5375 break;
5376 case 0x0D:
5377 /* maclhw - maclhw. - maclhwo - maclhwo. */
5378 /* maclhws - maclhws. - maclhwso - maclhwso. */
5379 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5380 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5381 /* mullhw - mullhw. */
5382 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5383 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5384 break;
5385 case 0x0C:
5386 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5387 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5388 /* mullhwu - mullhwu. */
5389 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5390 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5391 break;
5392 }
5393 if (opc2 & 0x04) {
5394 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5395 tcg_gen_mul_tl(t1, t0, t1);
5396 if (opc2 & 0x02) {
5397 /* nmultiply-and-accumulate (0x0E) */
5398 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5399 } else {
5400 /* multiply-and-accumulate (0x0C) */
5401 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5402 }
5403
5404 if (opc3 & 0x12) {
5405 /* Check overflow and/or saturate */
5406 TCGLabel *l1 = gen_new_label();
5407
5408 if (opc3 & 0x10) {
5409 /* Start with XER OV disabled, the most likely case */
5410 tcg_gen_movi_tl(cpu_ov, 0);
5411 }
5412 if (opc3 & 0x01) {
5413 /* Signed */
5414 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5415 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5416 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5417 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5418 if (opc3 & 0x02) {
5419 /* Saturate */
5420 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5421 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5422 }
5423 } else {
5424 /* Unsigned */
5425 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5426 if (opc3 & 0x02) {
5427 /* Saturate */
5428 tcg_gen_movi_tl(t0, UINT32_MAX);
5429 }
5430 }
5431 if (opc3 & 0x10) {
5432 /* Check overflow */
5433 tcg_gen_movi_tl(cpu_ov, 1);
5434 tcg_gen_movi_tl(cpu_so, 1);
5435 }
5436 gen_set_label(l1);
5437 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5438 }
5439 } else {
5440 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5441 }
5442 tcg_temp_free(t0);
5443 tcg_temp_free(t1);
5444 if (unlikely(Rc) != 0) {
5445 /* Update Rc0 */
5446 gen_set_Rc0(ctx, cpu_gpr[rt]);
5447 }
5448 }
5449
5450 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5451 static void glue(gen_, name)(DisasContext *ctx) \
5452 { \
5453 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5454 rD(ctx->opcode), Rc(ctx->opcode)); \
5455 }
5456
5457 /* macchw - macchw. */
5458 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5459 /* macchwo - macchwo. */
5460 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5461 /* macchws - macchws. */
5462 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5463 /* macchwso - macchwso. */
5464 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5465 /* macchwsu - macchwsu. */
5466 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5467 /* macchwsuo - macchwsuo. */
5468 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5469 /* macchwu - macchwu. */
5470 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5471 /* macchwuo - macchwuo. */
5472 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5473 /* machhw - machhw. */
5474 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5475 /* machhwo - machhwo. */
5476 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5477 /* machhws - machhws. */
5478 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5479 /* machhwso - machhwso. */
5480 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5481 /* machhwsu - machhwsu. */
5482 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5483 /* machhwsuo - machhwsuo. */
5484 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5485 /* machhwu - machhwu. */
5486 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5487 /* machhwuo - machhwuo. */
5488 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5489 /* maclhw - maclhw. */
5490 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5491 /* maclhwo - maclhwo. */
5492 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5493 /* maclhws - maclhws. */
5494 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5495 /* maclhwso - maclhwso. */
5496 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5497 /* maclhwu - maclhwu. */
5498 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5499 /* maclhwuo - maclhwuo. */
5500 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5501 /* maclhwsu - maclhwsu. */
5502 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5503 /* maclhwsuo - maclhwsuo. */
5504 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5505 /* nmacchw - nmacchw. */
5506 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5507 /* nmacchwo - nmacchwo. */
5508 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5509 /* nmacchws - nmacchws. */
5510 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5511 /* nmacchwso - nmacchwso. */
5512 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5513 /* nmachhw - nmachhw. */
5514 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5515 /* nmachhwo - nmachhwo. */
5516 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5517 /* nmachhws - nmachhws. */
5518 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5519 /* nmachhwso - nmachhwso. */
5520 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5521 /* nmaclhw - nmaclhw. */
5522 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5523 /* nmaclhwo - nmaclhwo. */
5524 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5525 /* nmaclhws - nmaclhws. */
5526 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5527 /* nmaclhwso - nmaclhwso. */
5528 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5529
5530 /* mulchw - mulchw. */
5531 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5532 /* mulchwu - mulchwu. */
5533 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5534 /* mulhhw - mulhhw. */
5535 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5536 /* mulhhwu - mulhhwu. */
5537 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5538 /* mullhw - mullhw. */
5539 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5540 /* mullhwu - mullhwu. */
5541 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5542
5543 /* mfdcr */
5544 static void gen_mfdcr(DisasContext *ctx)
5545 {
5546 #if defined(CONFIG_USER_ONLY)
5547 GEN_PRIV;
5548 #else
5549 TCGv dcrn;
5550
5551 CHK_SV;
5552 dcrn = tcg_const_tl(SPR(ctx->opcode));
5553 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5554 tcg_temp_free(dcrn);
5555 #endif /* defined(CONFIG_USER_ONLY) */
5556 }
5557
5558 /* mtdcr */
5559 static void gen_mtdcr(DisasContext *ctx)
5560 {
5561 #if defined(CONFIG_USER_ONLY)
5562 GEN_PRIV;
5563 #else
5564 TCGv dcrn;
5565
5566 CHK_SV;
5567 dcrn = tcg_const_tl(SPR(ctx->opcode));
5568 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5569 tcg_temp_free(dcrn);
5570 #endif /* defined(CONFIG_USER_ONLY) */
5571 }
5572
5573 /* mfdcrx */
5574 /* XXX: not implemented on 440 ? */
5575 static void gen_mfdcrx(DisasContext *ctx)
5576 {
5577 #if defined(CONFIG_USER_ONLY)
5578 GEN_PRIV;
5579 #else
5580 CHK_SV;
5581 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5582 cpu_gpr[rA(ctx->opcode)]);
5583 /* Note: Rc update flag set leads to undefined state of Rc0 */
5584 #endif /* defined(CONFIG_USER_ONLY) */
5585 }
5586
5587 /* mtdcrx */
5588 /* XXX: not implemented on 440 ? */
5589 static void gen_mtdcrx(DisasContext *ctx)
5590 {
5591 #if defined(CONFIG_USER_ONLY)
5592 GEN_PRIV;
5593 #else
5594 CHK_SV;
5595 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5596 cpu_gpr[rS(ctx->opcode)]);
5597 /* Note: Rc update flag set leads to undefined state of Rc0 */
5598 #endif /* defined(CONFIG_USER_ONLY) */
5599 }
5600
5601 /* mfdcrux (PPC 460) : user-mode access to DCR */
5602 static void gen_mfdcrux(DisasContext *ctx)
5603 {
5604 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5605 cpu_gpr[rA(ctx->opcode)]);
5606 /* Note: Rc update flag set leads to undefined state of Rc0 */
5607 }
5608
5609 /* mtdcrux (PPC 460) : user-mode access to DCR */
5610 static void gen_mtdcrux(DisasContext *ctx)
5611 {
5612 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5613 cpu_gpr[rS(ctx->opcode)]);
5614 /* Note: Rc update flag set leads to undefined state of Rc0 */
5615 }
5616
5617 /* dccci */
5618 static void gen_dccci(DisasContext *ctx)
5619 {
5620 CHK_SV;
5621 /* interpreted as no-op */
5622 }
5623
5624 /* dcread */
5625 static void gen_dcread(DisasContext *ctx)
5626 {
5627 #if defined(CONFIG_USER_ONLY)
5628 GEN_PRIV;
5629 #else
5630 TCGv EA, val;
5631
5632 CHK_SV;
5633 gen_set_access_type(ctx, ACCESS_CACHE);
5634 EA = tcg_temp_new();
5635 gen_addr_reg_index(ctx, EA);
5636 val = tcg_temp_new();
5637 gen_qemu_ld32u(ctx, val, EA);
5638 tcg_temp_free(val);
5639 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5640 tcg_temp_free(EA);
5641 #endif /* defined(CONFIG_USER_ONLY) */
5642 }
5643
5644 /* icbt */
5645 static void gen_icbt_40x(DisasContext *ctx)
5646 {
5647 /* interpreted as no-op */
5648 /* XXX: specification say this is treated as a load by the MMU
5649 * but does not generate any exception
5650 */
5651 }
5652
5653 /* iccci */
5654 static void gen_iccci(DisasContext *ctx)
5655 {
5656 CHK_SV;
5657 /* interpreted as no-op */
5658 }
5659
5660 /* icread */
5661 static void gen_icread(DisasContext *ctx)
5662 {
5663 CHK_SV;
5664 /* interpreted as no-op */
5665 }
5666
5667 /* rfci (supervisor only) */
5668 static void gen_rfci_40x(DisasContext *ctx)
5669 {
5670 #if defined(CONFIG_USER_ONLY)
5671 GEN_PRIV;
5672 #else
5673 CHK_SV;
5674 /* Restore CPU state */
5675 gen_helper_40x_rfci(cpu_env);
5676 gen_sync_exception(ctx);
5677 #endif /* defined(CONFIG_USER_ONLY) */
5678 }
5679
5680 static void gen_rfci(DisasContext *ctx)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 GEN_PRIV;
5684 #else
5685 CHK_SV;
5686 /* Restore CPU state */
5687 gen_helper_rfci(cpu_env);
5688 gen_sync_exception(ctx);
5689 #endif /* defined(CONFIG_USER_ONLY) */
5690 }
5691
5692 /* BookE specific */
5693
5694 /* XXX: not implemented on 440 ? */
5695 static void gen_rfdi(DisasContext *ctx)
5696 {
5697 #if defined(CONFIG_USER_ONLY)
5698 GEN_PRIV;
5699 #else
5700 CHK_SV;
5701 /* Restore CPU state */
5702 gen_helper_rfdi(cpu_env);
5703 gen_sync_exception(ctx);
5704 #endif /* defined(CONFIG_USER_ONLY) */
5705 }
5706
5707 /* XXX: not implemented on 440 ? */
5708 static void gen_rfmci(DisasContext *ctx)
5709 {
5710 #if defined(CONFIG_USER_ONLY)
5711 GEN_PRIV;
5712 #else
5713 CHK_SV;
5714 /* Restore CPU state */
5715 gen_helper_rfmci(cpu_env);
5716 gen_sync_exception(ctx);
5717 #endif /* defined(CONFIG_USER_ONLY) */
5718 }
5719
5720 /* TLB management - PowerPC 405 implementation */
5721
5722 /* tlbre */
5723 static void gen_tlbre_40x(DisasContext *ctx)
5724 {
5725 #if defined(CONFIG_USER_ONLY)
5726 GEN_PRIV;
5727 #else
5728 CHK_SV;
5729 switch (rB(ctx->opcode)) {
5730 case 0:
5731 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5732 cpu_gpr[rA(ctx->opcode)]);
5733 break;
5734 case 1:
5735 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5736 cpu_gpr[rA(ctx->opcode)]);
5737 break;
5738 default:
5739 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5740 break;
5741 }
5742 #endif /* defined(CONFIG_USER_ONLY) */
5743 }
5744
5745 /* tlbsx - tlbsx. */
5746 static void gen_tlbsx_40x(DisasContext *ctx)
5747 {
5748 #if defined(CONFIG_USER_ONLY)
5749 GEN_PRIV;
5750 #else
5751 TCGv t0;
5752
5753 CHK_SV;
5754 t0 = tcg_temp_new();
5755 gen_addr_reg_index(ctx, t0);
5756 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5757 tcg_temp_free(t0);
5758 if (Rc(ctx->opcode)) {
5759 TCGLabel *l1 = gen_new_label();
5760 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5761 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5762 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5763 gen_set_label(l1);
5764 }
5765 #endif /* defined(CONFIG_USER_ONLY) */
5766 }
5767
5768 /* tlbwe */
5769 static void gen_tlbwe_40x(DisasContext *ctx)
5770 {
5771 #if defined(CONFIG_USER_ONLY)
5772 GEN_PRIV;
5773 #else
5774 CHK_SV;
5775
5776 switch (rB(ctx->opcode)) {
5777 case 0:
5778 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5779 cpu_gpr[rS(ctx->opcode)]);
5780 break;
5781 case 1:
5782 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5783 cpu_gpr[rS(ctx->opcode)]);
5784 break;
5785 default:
5786 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5787 break;
5788 }
5789 #endif /* defined(CONFIG_USER_ONLY) */
5790 }
5791
5792 /* TLB management - PowerPC 440 implementation */
5793
5794 /* tlbre */
5795 static void gen_tlbre_440(DisasContext *ctx)
5796 {
5797 #if defined(CONFIG_USER_ONLY)
5798 GEN_PRIV;
5799 #else
5800 CHK_SV;
5801
5802 switch (rB(ctx->opcode)) {
5803 case 0:
5804 case 1:
5805 case 2:
5806 {
5807 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5808 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5809 t0, cpu_gpr[rA(ctx->opcode)]);
5810 tcg_temp_free_i32(t0);
5811 }
5812 break;
5813 default:
5814 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5815 break;
5816 }
5817 #endif /* defined(CONFIG_USER_ONLY) */
5818 }
5819
5820 /* tlbsx - tlbsx. */
5821 static void gen_tlbsx_440(DisasContext *ctx)
5822 {
5823 #if defined(CONFIG_USER_ONLY)
5824 GEN_PRIV;
5825 #else
5826 TCGv t0;
5827
5828 CHK_SV;
5829 t0 = tcg_temp_new();
5830 gen_addr_reg_index(ctx, t0);
5831 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5832 tcg_temp_free(t0);
5833 if (Rc(ctx->opcode)) {
5834 TCGLabel *l1 = gen_new_label();
5835 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5836 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5837 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5838 gen_set_label(l1);
5839 }
5840 #endif /* defined(CONFIG_USER_ONLY) */
5841 }
5842
5843 /* tlbwe */
5844 static void gen_tlbwe_440(DisasContext *ctx)
5845 {
5846 #if defined(CONFIG_USER_ONLY)
5847 GEN_PRIV;
5848 #else
5849 CHK_SV;
5850 switch (rB(ctx->opcode)) {
5851 case 0:
5852 case 1:
5853 case 2:
5854 {
5855 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5856 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5857 cpu_gpr[rS(ctx->opcode)]);
5858 tcg_temp_free_i32(t0);
5859 }
5860 break;
5861 default:
5862 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5863 break;
5864 }
5865 #endif /* defined(CONFIG_USER_ONLY) */
5866 }
5867
5868 /* TLB management - PowerPC BookE 2.06 implementation */
5869
5870 /* tlbre */
5871 static void gen_tlbre_booke206(DisasContext *ctx)
5872 {
5873 #if defined(CONFIG_USER_ONLY)
5874 GEN_PRIV;
5875 #else
5876 CHK_SV;
5877 gen_helper_booke206_tlbre(cpu_env);
5878 #endif /* defined(CONFIG_USER_ONLY) */
5879 }
5880
5881 /* tlbsx - tlbsx. */
5882 static void gen_tlbsx_booke206(DisasContext *ctx)
5883 {
5884 #if defined(CONFIG_USER_ONLY)
5885 GEN_PRIV;
5886 #else
5887 TCGv t0;
5888
5889 CHK_SV;
5890 if (rA(ctx->opcode)) {
5891 t0 = tcg_temp_new();
5892 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5893 } else {
5894 t0 = tcg_const_tl(0);
5895 }
5896
5897 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5898 gen_helper_booke206_tlbsx(cpu_env, t0);
5899 tcg_temp_free(t0);
5900 #endif /* defined(CONFIG_USER_ONLY) */
5901 }
5902
5903 /* tlbwe */
5904 static void gen_tlbwe_booke206(DisasContext *ctx)
5905 {
5906 #if defined(CONFIG_USER_ONLY)
5907 GEN_PRIV;
5908 #else
5909 CHK_SV;
5910 gen_helper_booke206_tlbwe(cpu_env);
5911 #endif /* defined(CONFIG_USER_ONLY) */
5912 }
5913
5914 static void gen_tlbivax_booke206(DisasContext *ctx)
5915 {
5916 #if defined(CONFIG_USER_ONLY)
5917 GEN_PRIV;
5918 #else
5919 TCGv t0;
5920
5921 CHK_SV;
5922 t0 = tcg_temp_new();
5923 gen_addr_reg_index(ctx, t0);
5924 gen_helper_booke206_tlbivax(cpu_env, t0);
5925 tcg_temp_free(t0);
5926 #endif /* defined(CONFIG_USER_ONLY) */
5927 }
5928
5929 static void gen_tlbilx_booke206(DisasContext *ctx)
5930 {
5931 #if defined(CONFIG_USER_ONLY)
5932 GEN_PRIV;
5933 #else
5934 TCGv t0;
5935
5936 CHK_SV;
5937 t0 = tcg_temp_new();
5938 gen_addr_reg_index(ctx, t0);
5939
5940 switch((ctx->opcode >> 21) & 0x3) {
5941 case 0:
5942 gen_helper_booke206_tlbilx0(cpu_env, t0);
5943 break;
5944 case 1:
5945 gen_helper_booke206_tlbilx1(cpu_env, t0);
5946 break;
5947 case 3:
5948 gen_helper_booke206_tlbilx3(cpu_env, t0);
5949 break;
5950 default:
5951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5952 break;
5953 }
5954
5955 tcg_temp_free(t0);
5956 #endif /* defined(CONFIG_USER_ONLY) */
5957 }
5958
5959
5960 /* wrtee */
5961 static void gen_wrtee(DisasContext *ctx)
5962 {
5963 #if defined(CONFIG_USER_ONLY)
5964 GEN_PRIV;
5965 #else
5966 TCGv t0;
5967
5968 CHK_SV;
5969 t0 = tcg_temp_new();
5970 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5971 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5972 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5973 tcg_temp_free(t0);
5974 /* Stop translation to have a chance to raise an exception
5975 * if we just set msr_ee to 1
5976 */
5977 gen_stop_exception(ctx);
5978 #endif /* defined(CONFIG_USER_ONLY) */
5979 }
5980
5981 /* wrteei */
5982 static void gen_wrteei(DisasContext *ctx)
5983 {
5984 #if defined(CONFIG_USER_ONLY)
5985 GEN_PRIV;
5986 #else
5987 CHK_SV;
5988 if (ctx->opcode & 0x00008000) {
5989 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5990 /* Stop translation to have a chance to raise an exception */
5991 gen_stop_exception(ctx);
5992 } else {
5993 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5994 }
5995 #endif /* defined(CONFIG_USER_ONLY) */
5996 }
5997
5998 /* PowerPC 440 specific instructions */
5999
6000 /* dlmzb */
6001 static void gen_dlmzb(DisasContext *ctx)
6002 {
6003 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6004 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6005 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6006 tcg_temp_free_i32(t0);
6007 }
6008
6009 /* mbar replaces eieio on 440 */
6010 static void gen_mbar(DisasContext *ctx)
6011 {
6012 /* interpreted as no-op */
6013 }
6014
6015 /* msync replaces sync on 440 */
6016 static void gen_msync_4xx(DisasContext *ctx)
6017 {
6018 /* interpreted as no-op */
6019 }
6020
6021 /* icbt */
6022 static void gen_icbt_440(DisasContext *ctx)
6023 {
6024 /* interpreted as no-op */
6025 /* XXX: specification say this is treated as a load by the MMU
6026 * but does not generate any exception
6027 */
6028 }
6029
6030 /* Embedded.Processor Control */
6031
6032 static void gen_msgclr(DisasContext *ctx)
6033 {
6034 #if defined(CONFIG_USER_ONLY)
6035 GEN_PRIV;
6036 #else
6037 CHK_SV;
6038 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6039 #endif /* defined(CONFIG_USER_ONLY) */
6040 }
6041
6042 static void gen_msgsnd(DisasContext *ctx)
6043 {
6044 #if defined(CONFIG_USER_ONLY)
6045 GEN_PRIV;
6046 #else
6047 CHK_SV;
6048 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6049 #endif /* defined(CONFIG_USER_ONLY) */
6050 }
6051
6052
6053 #if defined(TARGET_PPC64)
6054 static void gen_maddld(DisasContext *ctx)
6055 {
6056 TCGv_i64 t1 = tcg_temp_new_i64();
6057
6058 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6059 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6060 tcg_temp_free_i64(t1);
6061 }
6062
6063 /* maddhd maddhdu */
6064 static void gen_maddhd_maddhdu(DisasContext *ctx)
6065 {
6066 TCGv_i64 lo = tcg_temp_new_i64();
6067 TCGv_i64 hi = tcg_temp_new_i64();
6068 TCGv_i64 t1 = tcg_temp_new_i64();
6069
6070 if (Rc(ctx->opcode)) {
6071 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6072 cpu_gpr[rB(ctx->opcode)]);
6073 tcg_gen_movi_i64(t1, 0);
6074 } else {
6075 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6076 cpu_gpr[rB(ctx->opcode)]);
6077 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6078 }
6079 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6080 cpu_gpr[rC(ctx->opcode)], t1);
6081 tcg_temp_free_i64(lo);
6082 tcg_temp_free_i64(hi);
6083 tcg_temp_free_i64(t1);
6084 }
6085 #endif /* defined(TARGET_PPC64) */
6086
6087 #include "translate/dfp-impl.c"
6088
6089 #include "translate/spe-impl.c"
6090
6091 static void gen_tbegin(DisasContext *ctx)
6092 {
6093 if (unlikely(!ctx->tm_enabled)) {
6094 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6095 return;
6096 }
6097 gen_helper_tbegin(cpu_env);
6098 }
6099
6100 #define GEN_TM_NOOP(name) \
6101 static inline void gen_##name(DisasContext *ctx) \
6102 { \
6103 if (unlikely(!ctx->tm_enabled)) { \
6104 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6105 return; \
6106 } \
6107 /* Because tbegin always fails in QEMU, these user \
6108 * space instructions all have a simple implementation: \
6109 * \
6110 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6111 * = 0b0 || 0b00 || 0b0 \
6112 */ \
6113 tcg_gen_movi_i32(cpu_crf[0], 0); \
6114 }
6115
6116 GEN_TM_NOOP(tend);
6117 GEN_TM_NOOP(tabort);
6118 GEN_TM_NOOP(tabortwc);
6119 GEN_TM_NOOP(tabortwci);
6120 GEN_TM_NOOP(tabortdc);
6121 GEN_TM_NOOP(tabortdci);
6122 GEN_TM_NOOP(tsr);
6123
6124 static void gen_tcheck(DisasContext *ctx)
6125 {
6126 if (unlikely(!ctx->tm_enabled)) {
6127 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6128 return;
6129 }
6130 /* Because tbegin always fails, the tcheck implementation
6131 * is simple:
6132 *
6133 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6134 * = 0b1 || 0b00 || 0b0
6135 */
6136 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6137 }
6138
6139 #if defined(CONFIG_USER_ONLY)
6140 #define GEN_TM_PRIV_NOOP(name) \
6141 static inline void gen_##name(DisasContext *ctx) \
6142 { \
6143 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6144 }
6145
6146 #else
6147
6148 #define GEN_TM_PRIV_NOOP(name) \
6149 static inline void gen_##name(DisasContext *ctx) \
6150 { \
6151 CHK_SV; \
6152 if (unlikely(!ctx->tm_enabled)) { \
6153 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6154 return; \
6155 } \
6156 /* Because tbegin always fails, the implementation is \
6157 * simple: \
6158 * \
6159 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6160 * = 0b0 || 0b00 | 0b0 \
6161 */ \
6162 tcg_gen_movi_i32(cpu_crf[0], 0); \
6163 }
6164
6165 #endif
6166
6167 GEN_TM_PRIV_NOOP(treclaim);
6168 GEN_TM_PRIV_NOOP(trechkpt);
6169
6170 static opcode_t opcodes[] = {
6171 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6172 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6173 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6174 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6175 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6176 #if defined(TARGET_PPC64)
6177 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6178 #endif
6179 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6180 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6181 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6182 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6183 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6184 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6185 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6186 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6187 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6188 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6189 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6190 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6191 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6192 #if defined(TARGET_PPC64)
6193 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6194 #endif
6195 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6196 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6197 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6198 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6199 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6200 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6201 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6202 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6203 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6204 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6205 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6206 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6207 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6208 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6209 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6210 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6211 #if defined(TARGET_PPC64)
6212 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6213 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6214 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6215 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6216 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6217 #endif
6218 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6219 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6220 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6221 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6222 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6223 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6224 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6225 #if defined(TARGET_PPC64)
6226 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6227 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6228 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6229 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6230 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6231 #endif
6232 #if defined(TARGET_PPC64)
6233 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6234 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6235 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6236 #endif
6237 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6238 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6239 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6240 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6241 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6242 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6243 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6244 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6245 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6246 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6247 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6248 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6249 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6250 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6251 #if defined(TARGET_PPC64)
6252 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6253 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6254 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6255 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6256 #endif
6257 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6258 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6259 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6260 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6261 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6262 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6263 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6264 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6265 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6266 #if defined(TARGET_PPC64)
6267 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6268 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6269 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6270 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6271 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6272 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6273 #endif
6274 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6275 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6276 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6277 #if defined(TARGET_PPC64)
6278 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6279 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6280 #endif
6281 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6282 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6283 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6284 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6285 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6286 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6287 #if defined(TARGET_PPC64)
6288 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6289 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6290 #endif
6291 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6292 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6293 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6294 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6295 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6296 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6297 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6298 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6299 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6300 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6301 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6302 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6303 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6304 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6305 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6306 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6307 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6308 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6309 #if defined(TARGET_PPC64)
6310 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6311 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6312 PPC_SEGMENT_64B),
6313 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6314 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6315 PPC_SEGMENT_64B),
6316 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6317 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6318 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6319 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6320 #endif
6321 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6322 /* XXX Those instructions will need to be handled differently for
6323 * different ISA versions */
6324 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6325 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6326 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6327 #if defined(TARGET_PPC64)
6328 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6329 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6330 #endif
6331 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6332 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6333 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6334 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6335 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6336 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6337 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6338 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6339 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6340 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6341 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6342 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6343 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6344 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6345 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6346 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6347 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6348 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6349 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6350 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6351 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6352 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6353 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6354 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6355 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6356 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6357 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6358 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6359 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6360 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6361 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6362 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6363 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6364 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6365 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6366 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6367 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6368 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6369 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6370 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6371 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6372 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6373 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6374 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6375 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6376 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6377 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6378 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6379 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6380 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6381 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6382 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6383 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6384 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6385 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6386 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6387 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6388 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6389 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6390 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6391 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6392 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6393 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6394 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6395 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6396 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6397 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6398 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6399 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6400 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6401 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6402 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6403 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6404 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6405 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6406 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6407 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6408 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6409 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6410 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6411 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6412 PPC_NONE, PPC2_BOOKE206),
6413 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6414 PPC_NONE, PPC2_BOOKE206),
6415 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6416 PPC_NONE, PPC2_BOOKE206),
6417 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6418 PPC_NONE, PPC2_BOOKE206),
6419 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6420 PPC_NONE, PPC2_BOOKE206),
6421 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6422 PPC_NONE, PPC2_PRCNTL),
6423 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6424 PPC_NONE, PPC2_PRCNTL),
6425 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6426 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6427 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6428 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6429 PPC_BOOKE, PPC2_BOOKE206),
6430 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6431 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6432 PPC_BOOKE, PPC2_BOOKE206),
6433 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6434 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6435 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6436 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6437 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6438 #if defined(TARGET_PPC64)
6439 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6440 PPC2_ISA300),
6441 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6442 #endif
6443
6444 #undef GEN_INT_ARITH_ADD
6445 #undef GEN_INT_ARITH_ADD_CONST
6446 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6447 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6448 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6449 add_ca, compute_ca, compute_ov) \
6450 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6451 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6452 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6453 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6454 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6455 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6456 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6457 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6458 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6459 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6460 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6461
6462 #undef GEN_INT_ARITH_DIVW
6463 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6464 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6465 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6466 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6467 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6468 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6469 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6470 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6471 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6472 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6473 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6474 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6475
6476 #if defined(TARGET_PPC64)
6477 #undef GEN_INT_ARITH_DIVD
6478 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6479 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6480 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6481 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6482 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6483 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6484
6485 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6486 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6487 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6488 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6489 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6490 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6491
6492 #undef GEN_INT_ARITH_MUL_HELPER
6493 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6494 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6495 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6496 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6497 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6498 #endif
6499
6500 #undef GEN_INT_ARITH_SUBF
6501 #undef GEN_INT_ARITH_SUBF_CONST
6502 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6503 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6504 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6505 add_ca, compute_ca, compute_ov) \
6506 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6507 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6508 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6509 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6510 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6511 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6512 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6513 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6514 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6515 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6516 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6517
6518 #undef GEN_LOGICAL1
6519 #undef GEN_LOGICAL2
6520 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6521 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6522 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6523 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6524 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6525 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6526 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6527 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6528 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6529 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6530 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6531 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6532 #if defined(TARGET_PPC64)
6533 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6534 #endif
6535
6536 #if defined(TARGET_PPC64)
6537 #undef GEN_PPC64_R2
6538 #undef GEN_PPC64_R4
6539 #define GEN_PPC64_R2(name, opc1, opc2) \
6540 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6541 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6542 PPC_64B)
6543 #define GEN_PPC64_R4(name, opc1, opc2) \
6544 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6545 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6546 PPC_64B), \
6547 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6548 PPC_64B), \
6549 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6550 PPC_64B)
6551 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6552 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6553 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6554 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6555 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6556 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6557 #endif
6558
6559 #undef GEN_LD
6560 #undef GEN_LDU
6561 #undef GEN_LDUX
6562 #undef GEN_LDX_E
6563 #undef GEN_LDS
6564 #define GEN_LD(name, ldop, opc, type) \
6565 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6566 #define GEN_LDU(name, ldop, opc, type) \
6567 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6568 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6569 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6570 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6571 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6572 #define GEN_LDS(name, ldop, op, type) \
6573 GEN_LD(name, ldop, op | 0x20, type) \
6574 GEN_LDU(name, ldop, op | 0x21, type) \
6575 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6576 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6577
6578 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6579 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6580 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6581 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6582 #if defined(TARGET_PPC64)
6583 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6584 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6585 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6586 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6587 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6588
6589 /* HV/P7 and later only */
6590 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6591 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6592 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6593 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6594 #endif
6595 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6596 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6597
6598 #undef GEN_ST
6599 #undef GEN_STU
6600 #undef GEN_STUX
6601 #undef GEN_STX_E
6602 #undef GEN_STS
6603 #define GEN_ST(name, stop, opc, type) \
6604 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6605 #define GEN_STU(name, stop, opc, type) \
6606 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6607 #define GEN_STUX(name, stop, opc2, opc3, type) \
6608 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6609 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6610 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6611 #define GEN_STS(name, stop, op, type) \
6612 GEN_ST(name, stop, op | 0x20, type) \
6613 GEN_STU(name, stop, op | 0x21, type) \
6614 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6615 GEN_STX(name, stop, 0x17, op | 0x00, type)
6616
6617 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6618 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6619 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6620 #if defined(TARGET_PPC64)
6621 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6622 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6623 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6624 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6625 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6626 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6627 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6628 #endif
6629 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6630 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6631
6632 #undef GEN_CRLOGIC
6633 #define GEN_CRLOGIC(name, tcg_op, opc) \
6634 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6635 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6636 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6637 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6638 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6639 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6640 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6641 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6642 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6643
6644 #undef GEN_MAC_HANDLER
6645 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6646 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6647 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6648 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6649 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6650 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6651 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6652 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6653 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6654 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6655 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6656 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6657 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6658 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6659 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6660 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6661 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6662 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6663 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6664 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6665 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6666 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6667 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6668 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6669 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6670 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6671 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6672 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6673 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6674 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6675 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6676 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6677 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6678 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6679 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6680 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6681 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6682 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6683 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6684 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6685 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6686 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6687 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6688 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6689
6690 #include "translate/fp-ops.c"
6691
6692 #include "translate/vmx-ops.c"
6693
6694 #include "translate/vsx-ops.c"
6695
6696 #include "translate/dfp-ops.c"
6697
6698 #include "translate/spe-ops.c"
6699
6700 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6701 PPC_NONE, PPC2_TM),
6702 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6703 PPC_NONE, PPC2_TM),
6704 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6705 PPC_NONE, PPC2_TM),
6706 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6707 PPC_NONE, PPC2_TM),
6708 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6709 PPC_NONE, PPC2_TM),
6710 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6711 PPC_NONE, PPC2_TM),
6712 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6713 PPC_NONE, PPC2_TM),
6714 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6715 PPC_NONE, PPC2_TM),
6716 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6717 PPC_NONE, PPC2_TM),
6718 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6719 PPC_NONE, PPC2_TM),
6720 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6721 PPC_NONE, PPC2_TM),
6722 };
6723
6724 #include "helper_regs.h"
6725 #include "translate_init.c"
6726
6727 /*****************************************************************************/
6728 /* Misc PowerPC helpers */
6729 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6730 int flags)
6731 {
6732 #define RGPL 4
6733 #define RFPL 4
6734
6735 PowerPCCPU *cpu = POWERPC_CPU(cs);
6736 CPUPPCState *env = &cpu->env;
6737 int i;
6738
6739 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6740 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6741 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6742 cs->cpu_index);
6743 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6744 TARGET_FMT_lx " iidx %d didx %d\n",
6745 env->msr, env->spr[SPR_HID0],
6746 env->hflags, env->immu_idx, env->dmmu_idx);
6747 #if !defined(NO_TIMER_DUMP)
6748 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6749 #if !defined(CONFIG_USER_ONLY)
6750 " DECR %08" PRIu32
6751 #endif
6752 "\n",
6753 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6754 #if !defined(CONFIG_USER_ONLY)
6755 , cpu_ppc_load_decr(env)
6756 #endif
6757 );
6758 #endif
6759 for (i = 0; i < 32; i++) {
6760 if ((i & (RGPL - 1)) == 0)
6761 cpu_fprintf(f, "GPR%02d", i);
6762 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6763 if ((i & (RGPL - 1)) == (RGPL - 1))
6764 cpu_fprintf(f, "\n");
6765 }
6766 cpu_fprintf(f, "CR ");
6767 for (i = 0; i < 8; i++)
6768 cpu_fprintf(f, "%01x", env->crf[i]);
6769 cpu_fprintf(f, " [");
6770 for (i = 0; i < 8; i++) {
6771 char a = '-';
6772 if (env->crf[i] & 0x08)
6773 a = 'L';
6774 else if (env->crf[i] & 0x04)
6775 a = 'G';
6776 else if (env->crf[i] & 0x02)
6777 a = 'E';
6778 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6779 }
6780 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6781 env->reserve_addr);
6782 for (i = 0; i < 32; i++) {
6783 if ((i & (RFPL - 1)) == 0)
6784 cpu_fprintf(f, "FPR%02d", i);
6785 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6786 if ((i & (RFPL - 1)) == (RFPL - 1))
6787 cpu_fprintf(f, "\n");
6788 }
6789 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6790 #if !defined(CONFIG_USER_ONLY)
6791 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6792 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6793 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6794 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6795
6796 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6797 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6798 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6799 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6800
6801 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6802 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6803 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6804 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6805
6806 #if defined(TARGET_PPC64)
6807 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6808 env->excp_model == POWERPC_EXCP_POWER8) {
6809 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6810 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6811 }
6812 #endif
6813 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6814 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6815 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6816 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6817 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6818
6819 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6820 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6821 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6822 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6823
6824 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6825 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6826 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6827 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6828
6829 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6830 " EPR " TARGET_FMT_lx "\n",
6831 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6832 env->spr[SPR_BOOKE_EPR]);
6833
6834 /* FSL-specific */
6835 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6836 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6837 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6838 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6839
6840 /*
6841 * IVORs are left out as they are large and do not change often --
6842 * they can be read with "p $ivor0", "p $ivor1", etc.
6843 */
6844 }
6845
6846 #if defined(TARGET_PPC64)
6847 if (env->flags & POWERPC_FLAG_CFAR) {
6848 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6849 }
6850 #endif
6851
6852 switch (env->mmu_model) {
6853 case POWERPC_MMU_32B:
6854 case POWERPC_MMU_601:
6855 case POWERPC_MMU_SOFT_6xx:
6856 case POWERPC_MMU_SOFT_74xx:
6857 #if defined(TARGET_PPC64)
6858 case POWERPC_MMU_64B:
6859 case POWERPC_MMU_2_03:
6860 case POWERPC_MMU_2_06:
6861 case POWERPC_MMU_2_06a:
6862 case POWERPC_MMU_2_07:
6863 case POWERPC_MMU_2_07a:
6864 #endif
6865 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6866 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6867 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6868 break;
6869 case POWERPC_MMU_BOOKE206:
6870 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6871 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6872 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6873 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6874
6875 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6876 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6877 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6878 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6879
6880 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6881 " TLB1CFG " TARGET_FMT_lx "\n",
6882 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6883 env->spr[SPR_BOOKE_TLB1CFG]);
6884 break;
6885 default:
6886 break;
6887 }
6888 #endif
6889
6890 #undef RGPL
6891 #undef RFPL
6892 }
6893
6894 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6895 fprintf_function cpu_fprintf, int flags)
6896 {
6897 #if defined(DO_PPC_STATISTICS)
6898 PowerPCCPU *cpu = POWERPC_CPU(cs);
6899 opc_handler_t **t1, **t2, **t3, *handler;
6900 int op1, op2, op3;
6901
6902 t1 = cpu->env.opcodes;
6903 for (op1 = 0; op1 < 64; op1++) {
6904 handler = t1[op1];
6905 if (is_indirect_opcode(handler)) {
6906 t2 = ind_table(handler);
6907 for (op2 = 0; op2 < 32; op2++) {
6908 handler = t2[op2];
6909 if (is_indirect_opcode(handler)) {
6910 t3 = ind_table(handler);
6911 for (op3 = 0; op3 < 32; op3++) {
6912 handler = t3[op3];
6913 if (handler->count == 0)
6914 continue;
6915 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6916 "%016" PRIx64 " %" PRId64 "\n",
6917 op1, op2, op3, op1, (op3 << 5) | op2,
6918 handler->oname,
6919 handler->count, handler->count);
6920 }
6921 } else {
6922 if (handler->count == 0)
6923 continue;
6924 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6925 "%016" PRIx64 " %" PRId64 "\n",
6926 op1, op2, op1, op2, handler->oname,
6927 handler->count, handler->count);
6928 }
6929 }
6930 } else {
6931 if (handler->count == 0)
6932 continue;
6933 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6934 " %" PRId64 "\n",
6935 op1, op1, handler->oname,
6936 handler->count, handler->count);
6937 }
6938 }
6939 #endif
6940 }
6941
6942 /*****************************************************************************/
6943 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6944 {
6945 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6946 CPUState *cs = CPU(cpu);
6947 DisasContext ctx, *ctxp = &ctx;
6948 opc_handler_t **table, *handler;
6949 target_ulong pc_start;
6950 int num_insns;
6951 int max_insns;
6952
6953 pc_start = tb->pc;
6954 ctx.nip = pc_start;
6955 ctx.tb = tb;
6956 ctx.exception = POWERPC_EXCP_NONE;
6957 ctx.spr_cb = env->spr_cb;
6958 ctx.pr = msr_pr;
6959 ctx.mem_idx = env->dmmu_idx;
6960 ctx.dr = msr_dr;
6961 #if !defined(CONFIG_USER_ONLY)
6962 ctx.hv = msr_hv || !env->has_hv_mode;
6963 #endif
6964 ctx.insns_flags = env->insns_flags;
6965 ctx.insns_flags2 = env->insns_flags2;
6966 ctx.access_type = -1;
6967 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
6968 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6969 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6970 #if defined(TARGET_PPC64)
6971 ctx.sf_mode = msr_is_64bit(env, env->msr);
6972 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6973 #endif
6974 if (env->mmu_model == POWERPC_MMU_32B ||
6975 env->mmu_model == POWERPC_MMU_601 ||
6976 (env->mmu_model & POWERPC_MMU_64B))
6977 ctx.lazy_tlb_flush = true;
6978
6979 ctx.fpu_enabled = !!msr_fp;
6980 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6981 ctx.spe_enabled = !!msr_spe;
6982 else
6983 ctx.spe_enabled = false;
6984 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6985 ctx.altivec_enabled = !!msr_vr;
6986 else
6987 ctx.altivec_enabled = false;
6988 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6989 ctx.vsx_enabled = !!msr_vsx;
6990 } else {
6991 ctx.vsx_enabled = false;
6992 }
6993 #if defined(TARGET_PPC64)
6994 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6995 ctx.tm_enabled = !!msr_tm;
6996 } else {
6997 ctx.tm_enabled = false;
6998 }
6999 #endif
7000 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7001 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7002 else
7003 ctx.singlestep_enabled = 0;
7004 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7005 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7006 if (unlikely(cs->singlestep_enabled)) {
7007 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7008 }
7009 #if defined (DO_SINGLE_STEP) && 0
7010 /* Single step trace mode */
7011 msr_se = 1;
7012 #endif
7013 num_insns = 0;
7014 max_insns = tb->cflags & CF_COUNT_MASK;
7015 if (max_insns == 0) {
7016 max_insns = CF_COUNT_MASK;
7017 }
7018 if (max_insns > TCG_MAX_INSNS) {
7019 max_insns = TCG_MAX_INSNS;
7020 }
7021
7022 gen_tb_start(tb);
7023 tcg_clear_temp_count();
7024 /* Set env in case of segfault during code fetch */
7025 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7026 tcg_gen_insn_start(ctx.nip);
7027 num_insns++;
7028
7029 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7030 gen_debug_exception(ctxp);
7031 /* The address covered by the breakpoint must be included in
7032 [tb->pc, tb->pc + tb->size) in order to for it to be
7033 properly cleared -- thus we increment the PC here so that
7034 the logic setting tb->size below does the right thing. */
7035 ctx.nip += 4;
7036 break;
7037 }
7038
7039 LOG_DISAS("----------------\n");
7040 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7041 ctx.nip, ctx.mem_idx, (int)msr_ir);
7042 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7043 gen_io_start();
7044 if (unlikely(need_byteswap(&ctx))) {
7045 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7046 } else {
7047 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7048 }
7049 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7050 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7051 opc3(ctx.opcode), opc4(ctx.opcode),
7052 ctx.le_mode ? "little" : "big");
7053 ctx.nip += 4;
7054 table = env->opcodes;
7055 handler = table[opc1(ctx.opcode)];
7056 if (is_indirect_opcode(handler)) {
7057 table = ind_table(handler);
7058 handler = table[opc2(ctx.opcode)];
7059 if (is_indirect_opcode(handler)) {
7060 table = ind_table(handler);
7061 handler = table[opc3(ctx.opcode)];
7062 if (is_indirect_opcode(handler)) {
7063 table = ind_table(handler);
7064 handler = table[opc4(ctx.opcode)];
7065 }
7066 }
7067 }
7068 /* Is opcode *REALLY* valid ? */
7069 if (unlikely(handler->handler == &gen_invalid)) {
7070 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7071 "%02x - %02x - %02x - %02x (%08x) "
7072 TARGET_FMT_lx " %d\n",
7073 opc1(ctx.opcode), opc2(ctx.opcode),
7074 opc3(ctx.opcode), opc4(ctx.opcode),
7075 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7076 } else {
7077 uint32_t inval;
7078
7079 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7080 inval = handler->inval2;
7081 } else {
7082 inval = handler->inval1;
7083 }
7084
7085 if (unlikely((ctx.opcode & inval) != 0)) {
7086 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7087 "%02x - %02x - %02x - %02x (%08x) "
7088 TARGET_FMT_lx "\n", ctx.opcode & inval,
7089 opc1(ctx.opcode), opc2(ctx.opcode),
7090 opc3(ctx.opcode), opc4(ctx.opcode),
7091 ctx.opcode, ctx.nip - 4);
7092 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7093 break;
7094 }
7095 }
7096 (*(handler->handler))(&ctx);
7097 #if defined(DO_PPC_STATISTICS)
7098 handler->count++;
7099 #endif
7100 /* Check trace mode exceptions */
7101 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7102 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7103 ctx.exception != POWERPC_SYSCALL &&
7104 ctx.exception != POWERPC_EXCP_TRAP &&
7105 ctx.exception != POWERPC_EXCP_BRANCH)) {
7106 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7107 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7108 (cs->singlestep_enabled) ||
7109 singlestep ||
7110 num_insns >= max_insns)) {
7111 /* if we reach a page boundary or are single stepping, stop
7112 * generation
7113 */
7114 break;
7115 }
7116 if (tcg_check_temp_count()) {
7117 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7118 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7119 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7120 exit(1);
7121 }
7122 }
7123 if (tb->cflags & CF_LAST_IO)
7124 gen_io_end();
7125 if (ctx.exception == POWERPC_EXCP_NONE) {
7126 gen_goto_tb(&ctx, 0, ctx.nip);
7127 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7128 if (unlikely(cs->singlestep_enabled)) {
7129 gen_debug_exception(ctxp);
7130 }
7131 /* Generate the return instruction */
7132 tcg_gen_exit_tb(0);
7133 }
7134 gen_tb_end(tb, num_insns);
7135
7136 tb->size = ctx.nip - pc_start;
7137 tb->icount = num_insns;
7138
7139 #if defined(DEBUG_DISAS)
7140 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7141 && qemu_log_in_addr_range(pc_start)) {
7142 int flags;
7143 flags = env->bfd_mach;
7144 flags |= ctx.le_mode << 16;
7145 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7146 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7147 qemu_log("\n");
7148 }
7149 #endif
7150 }
7151
7152 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7153 target_ulong *data)
7154 {
7155 env->nip = data[0];
7156 }
AR7 emulation for QEMU