3 * TI X3130 pci express downstream port switch
5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "hw/pci/pci_ids.h"
23 #include "hw/pci/msi.h"
24 #include "hw/pci/pcie.h"
25 #include "xio3130_downstream.h"
27 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
28 #define XIO3130_REVISION 0x1
29 #define XIO3130_MSI_OFFSET 0x70
30 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
31 #define XIO3130_MSI_NR_VECTOR 1
32 #define XIO3130_SSVID_OFFSET 0x80
33 #define XIO3130_SSVID_SVID 0
34 #define XIO3130_SSVID_SSID 0
35 #define XIO3130_EXP_OFFSET 0x90
36 #define XIO3130_AER_OFFSET 0x100
38 static void xio3130_downstream_write_config(PCIDevice
*d
, uint32_t address
,
39 uint32_t val
, int len
)
41 pci_bridge_write_config(d
, address
, val
, len
);
42 pcie_cap_flr_write_config(d
, address
, val
, len
);
43 pcie_cap_slot_write_config(d
, address
, val
, len
);
44 pcie_aer_write_config(d
, address
, val
, len
);
47 static void xio3130_downstream_reset(DeviceState
*qdev
)
49 PCIDevice
*d
= PCI_DEVICE(qdev
);
51 pcie_cap_deverr_reset(d
);
52 pcie_cap_slot_reset(d
);
53 pcie_cap_ari_reset(d
);
54 pci_bridge_reset(qdev
);
57 static int xio3130_downstream_initfn(PCIDevice
*d
)
59 PCIEPort
*p
= PCIE_PORT(d
);
60 PCIESlot
*s
= PCIE_SLOT(d
);
63 rc
= pci_bridge_initfn(d
, TYPE_PCIE_BUS
);
68 pcie_port_init_reg(d
);
70 rc
= msi_init(d
, XIO3130_MSI_OFFSET
, XIO3130_MSI_NR_VECTOR
,
71 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_64BIT
,
72 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_MASKBIT
);
76 rc
= pci_bridge_ssvid_init(d
, XIO3130_SSVID_OFFSET
,
77 XIO3130_SSVID_SVID
, XIO3130_SSVID_SSID
);
81 rc
= pcie_cap_init(d
, XIO3130_EXP_OFFSET
, PCI_EXP_TYPE_DOWNSTREAM
,
87 pcie_cap_deverr_init(d
);
88 pcie_cap_slot_init(d
, s
->slot
);
89 pcie_chassis_create(s
->chassis
);
90 rc
= pcie_chassis_add_slot(s
);
95 rc
= pcie_aer_init(d
, XIO3130_AER_OFFSET
);
103 pcie_chassis_del_slot(s
);
109 pci_bridge_exitfn(d
);
113 static void xio3130_downstream_exitfn(PCIDevice
*d
)
115 PCIESlot
*s
= PCIE_SLOT(d
);
118 pcie_chassis_del_slot(s
);
121 pci_bridge_exitfn(d
);
124 PCIESlot
*xio3130_downstream_init(PCIBus
*bus
, int devfn
, bool multifunction
,
125 const char *bus_name
, pci_map_irq_fn map_irq
,
126 uint8_t port
, uint8_t chassis
,
133 d
= pci_create_multifunction(bus
, devfn
, multifunction
,
134 "xio3130-downstream");
141 pci_bridge_map_irq(br
, bus_name
, map_irq
);
142 qdev_prop_set_uint8(qdev
, "port", port
);
143 qdev_prop_set_uint8(qdev
, "chassis", chassis
);
144 qdev_prop_set_uint16(qdev
, "slot", slot
);
145 qdev_init_nofail(qdev
);
150 static const VMStateDescription vmstate_xio3130_downstream
= {
151 .name
= "xio3130-express-downstream-port",
153 .minimum_version_id
= 1,
154 .minimum_version_id_old
= 1,
155 .post_load
= pcie_cap_slot_post_load
,
156 .fields
= (VMStateField
[]) {
157 VMSTATE_PCIE_DEVICE(parent_obj
.parent_obj
.parent_obj
, PCIESlot
),
158 VMSTATE_STRUCT(parent_obj
.parent_obj
.parent_obj
.exp
.aer_log
,
159 PCIESlot
, 0, vmstate_pcie_aer_log
, PCIEAERLog
),
160 VMSTATE_END_OF_LIST()
164 static void xio3130_downstream_class_init(ObjectClass
*klass
, void *data
)
166 DeviceClass
*dc
= DEVICE_CLASS(klass
);
167 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
171 k
->config_write
= xio3130_downstream_write_config
;
172 k
->init
= xio3130_downstream_initfn
;
173 k
->exit
= xio3130_downstream_exitfn
;
174 k
->vendor_id
= PCI_VENDOR_ID_TI
;
175 k
->device_id
= PCI_DEVICE_ID_TI_XIO3130D
;
176 k
->revision
= XIO3130_REVISION
;
177 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
178 dc
->desc
= "TI X3130 Downstream Port of PCI Express Switch";
179 dc
->reset
= xio3130_downstream_reset
;
180 dc
->vmsd
= &vmstate_xio3130_downstream
;
183 static const TypeInfo xio3130_downstream_info
= {
184 .name
= "xio3130-downstream",
185 .parent
= TYPE_PCIE_SLOT
,
186 .class_init
= xio3130_downstream_class_init
,
189 static void xio3130_downstream_register_types(void)
191 type_register_static(&xio3130_downstream_info
);
194 type_init(xio3130_downstream_register_types
)
201 * indent-tab-mode: nil