2 * ARM implementation of KVM hooks, 64 bit specific code
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
5 * Copyright Alex Bennée 2014, Linaro
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
14 #include <sys/ptrace.h>
16 #include <linux/elf.h>
17 #include <linux/kvm.h>
19 #include "qapi/error.h"
21 #include "qemu/timer.h"
22 #include "qemu/error-report.h"
23 #include "qemu/host-utils.h"
24 #include "qemu/main-loop.h"
25 #include "exec/gdbstub.h"
26 #include "sysemu/runstate.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/kvm_int.h"
30 #include "internals.h"
31 #include "hw/acpi/acpi.h"
32 #include "hw/acpi/ghes.h"
33 #include "hw/arm/virt.h"
35 static bool have_guest_debug
;
37 void kvm_arm_init_debug(KVMState
*s
)
39 have_guest_debug
= kvm_check_extension(s
,
40 KVM_CAP_SET_GUEST_DEBUG
);
42 max_hw_wps
= kvm_check_extension(s
, KVM_CAP_GUEST_DEBUG_HW_WPS
);
43 hw_watchpoints
= g_array_sized_new(true, true,
44 sizeof(HWWatchpoint
), max_hw_wps
);
46 max_hw_bps
= kvm_check_extension(s
, KVM_CAP_GUEST_DEBUG_HW_BPS
);
47 hw_breakpoints
= g_array_sized_new(true, true,
48 sizeof(HWBreakpoint
), max_hw_bps
);
52 int kvm_arch_insert_hw_breakpoint(vaddr addr
, vaddr len
, int type
)
55 case GDB_BREAKPOINT_HW
:
56 return insert_hw_breakpoint(addr
);
58 case GDB_WATCHPOINT_READ
:
59 case GDB_WATCHPOINT_WRITE
:
60 case GDB_WATCHPOINT_ACCESS
:
61 return insert_hw_watchpoint(addr
, len
, type
);
67 int kvm_arch_remove_hw_breakpoint(vaddr addr
, vaddr len
, int type
)
70 case GDB_BREAKPOINT_HW
:
71 return delete_hw_breakpoint(addr
);
72 case GDB_WATCHPOINT_READ
:
73 case GDB_WATCHPOINT_WRITE
:
74 case GDB_WATCHPOINT_ACCESS
:
75 return delete_hw_watchpoint(addr
, len
, type
);
82 void kvm_arch_remove_all_hw_breakpoints(void)
85 g_array_remove_range(hw_watchpoints
, 0, cur_hw_wps
);
88 g_array_remove_range(hw_breakpoints
, 0, cur_hw_bps
);
92 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch
*ptr
)
95 memset(ptr
, 0, sizeof(struct kvm_guest_debug_arch
));
97 for (i
= 0; i
< max_hw_wps
; i
++) {
98 HWWatchpoint
*wp
= get_hw_wp(i
);
99 ptr
->dbg_wcr
[i
] = wp
->wcr
;
100 ptr
->dbg_wvr
[i
] = wp
->wvr
;
102 for (i
= 0; i
< max_hw_bps
; i
++) {
103 HWBreakpoint
*bp
= get_hw_bp(i
);
104 ptr
->dbg_bcr
[i
] = bp
->bcr
;
105 ptr
->dbg_bvr
[i
] = bp
->bvr
;
109 bool kvm_arm_hw_debug_active(CPUState
*cs
)
111 return ((cur_hw_wps
> 0) || (cur_hw_bps
> 0));
114 static bool kvm_arm_set_device_attr(CPUState
*cs
, struct kvm_device_attr
*attr
,
119 err
= kvm_vcpu_ioctl(cs
, KVM_HAS_DEVICE_ATTR
, attr
);
121 error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name
, strerror(-err
));
125 err
= kvm_vcpu_ioctl(cs
, KVM_SET_DEVICE_ATTR
, attr
);
127 error_report("%s: KVM_SET_DEVICE_ATTR: %s", name
, strerror(-err
));
134 void kvm_arm_pmu_init(CPUState
*cs
)
136 struct kvm_device_attr attr
= {
137 .group
= KVM_ARM_VCPU_PMU_V3_CTRL
,
138 .attr
= KVM_ARM_VCPU_PMU_V3_INIT
,
141 if (!ARM_CPU(cs
)->has_pmu
) {
144 if (!kvm_arm_set_device_attr(cs
, &attr
, "PMU")) {
145 error_report("failed to init PMU");
150 void kvm_arm_pmu_set_irq(CPUState
*cs
, int irq
)
152 struct kvm_device_attr attr
= {
153 .group
= KVM_ARM_VCPU_PMU_V3_CTRL
,
154 .addr
= (intptr_t)&irq
,
155 .attr
= KVM_ARM_VCPU_PMU_V3_IRQ
,
158 if (!ARM_CPU(cs
)->has_pmu
) {
161 if (!kvm_arm_set_device_attr(cs
, &attr
, "PMU")) {
162 error_report("failed to set irq for PMU");
167 void kvm_arm_pvtime_init(CPUState
*cs
, uint64_t ipa
)
169 struct kvm_device_attr attr
= {
170 .group
= KVM_ARM_VCPU_PVTIME_CTRL
,
171 .attr
= KVM_ARM_VCPU_PVTIME_IPA
,
172 .addr
= (uint64_t)&ipa
,
175 if (ARM_CPU(cs
)->kvm_steal_time
== ON_OFF_AUTO_OFF
) {
178 if (!kvm_arm_set_device_attr(cs
, &attr
, "PVTIME IPA")) {
179 error_report("failed to init PVTIME IPA");
184 static int read_sys_reg32(int fd
, uint32_t *pret
, uint64_t id
)
187 struct kvm_one_reg idreg
= { .id
= id
, .addr
= (uintptr_t)&ret
};
190 assert((id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
);
191 err
= ioctl(fd
, KVM_GET_ONE_REG
, &idreg
);
199 static int read_sys_reg64(int fd
, uint64_t *pret
, uint64_t id
)
201 struct kvm_one_reg idreg
= { .id
= id
, .addr
= (uintptr_t)pret
};
203 assert((id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
);
204 return ioctl(fd
, KVM_GET_ONE_REG
, &idreg
);
207 static bool kvm_arm_pauth_supported(void)
209 return (kvm_check_extension(kvm_state
, KVM_CAP_ARM_PTRAUTH_ADDRESS
) &&
210 kvm_check_extension(kvm_state
, KVM_CAP_ARM_PTRAUTH_GENERIC
));
213 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf
)
215 /* Identify the feature bits corresponding to the host CPU, and
216 * fill out the ARMHostCPUClass fields accordingly. To do this
217 * we have to create a scratch VM, create a single CPU inside it,
218 * and then query that CPU for the relevant ID registers.
222 bool pmu_supported
= false;
223 uint64_t features
= 0;
226 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
227 * we know these will only support creating one kind of guest CPU,
228 * which is its preferred CPU type. Fortunately these old kernels
229 * support only a very limited number of CPUs.
231 static const uint32_t cpus_to_try
[] = {
232 KVM_ARM_TARGET_AEM_V8
,
233 KVM_ARM_TARGET_FOUNDATION_V8
,
234 KVM_ARM_TARGET_CORTEX_A57
,
235 QEMU_KVM_ARM_TARGET_NONE
238 * target = -1 informs kvm_arm_create_scratch_host_vcpu()
239 * to use the preferred target
241 struct kvm_vcpu_init init
= { .target
= -1, };
244 * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
245 * which is otherwise RAZ.
247 sve_supported
= kvm_arm_sve_supported();
249 init
.features
[0] |= 1 << KVM_ARM_VCPU_SVE
;
253 * Ask for Pointer Authentication if supported, so that we get
254 * the unsanitized field values for AA64ISAR1_EL1.
256 if (kvm_arm_pauth_supported()) {
257 init
.features
[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS
|
258 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC
);
261 if (kvm_arm_pmu_supported()) {
262 init
.features
[0] |= 1 << KVM_ARM_VCPU_PMU_V3
;
263 pmu_supported
= true;
266 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try
, fdarray
, &init
)) {
270 ahcf
->target
= init
.target
;
271 ahcf
->dtb_compatible
= "arm,arm-v8";
273 err
= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64pfr0
,
274 ARM64_SYS_REG(3, 0, 0, 4, 0));
275 if (unlikely(err
< 0)) {
277 * Before v4.15, the kernel only exposed a limited number of system
278 * registers, not including any of the interesting AArch64 ID regs.
279 * For the most part we could leave these fields as zero with minimal
280 * effect, since this does not affect the values seen by the guest.
282 * However, it could cause problems down the line for QEMU,
283 * so provide a minimal v8.0 default.
285 * ??? Could read MIDR and use knowledge from cpu64.c.
286 * ??? Could map a page of memory into our temp guest and
287 * run the tiniest of hand-crafted kernels to extract
288 * the values seen by the guest.
289 * ??? Either of these sounds like too much effort just
290 * to work around running a modern host kernel.
292 ahcf
->isar
.id_aa64pfr0
= 0x00000011; /* EL1&0, AArch64 only */
295 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64pfr1
,
296 ARM64_SYS_REG(3, 0, 0, 4, 1));
297 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64smfr0
,
298 ARM64_SYS_REG(3, 0, 0, 4, 5));
299 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64dfr0
,
300 ARM64_SYS_REG(3, 0, 0, 5, 0));
301 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64dfr1
,
302 ARM64_SYS_REG(3, 0, 0, 5, 1));
303 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64isar0
,
304 ARM64_SYS_REG(3, 0, 0, 6, 0));
305 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64isar1
,
306 ARM64_SYS_REG(3, 0, 0, 6, 1));
307 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64isar2
,
308 ARM64_SYS_REG(3, 0, 0, 6, 2));
309 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64mmfr0
,
310 ARM64_SYS_REG(3, 0, 0, 7, 0));
311 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64mmfr1
,
312 ARM64_SYS_REG(3, 0, 0, 7, 1));
313 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64mmfr2
,
314 ARM64_SYS_REG(3, 0, 0, 7, 2));
317 * Note that if AArch32 support is not present in the host,
318 * the AArch32 sysregs are present to be read, but will
319 * return UNKNOWN values. This is neither better nor worse
320 * than skipping the reads and leaving 0, as we must avoid
321 * considering the values in every case.
323 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_pfr0
,
324 ARM64_SYS_REG(3, 0, 0, 1, 0));
325 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_pfr1
,
326 ARM64_SYS_REG(3, 0, 0, 1, 1));
327 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_dfr0
,
328 ARM64_SYS_REG(3, 0, 0, 1, 2));
329 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_mmfr0
,
330 ARM64_SYS_REG(3, 0, 0, 1, 4));
331 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_mmfr1
,
332 ARM64_SYS_REG(3, 0, 0, 1, 5));
333 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_mmfr2
,
334 ARM64_SYS_REG(3, 0, 0, 1, 6));
335 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_mmfr3
,
336 ARM64_SYS_REG(3, 0, 0, 1, 7));
337 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar0
,
338 ARM64_SYS_REG(3, 0, 0, 2, 0));
339 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar1
,
340 ARM64_SYS_REG(3, 0, 0, 2, 1));
341 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar2
,
342 ARM64_SYS_REG(3, 0, 0, 2, 2));
343 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar3
,
344 ARM64_SYS_REG(3, 0, 0, 2, 3));
345 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar4
,
346 ARM64_SYS_REG(3, 0, 0, 2, 4));
347 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar5
,
348 ARM64_SYS_REG(3, 0, 0, 2, 5));
349 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_mmfr4
,
350 ARM64_SYS_REG(3, 0, 0, 2, 6));
351 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar6
,
352 ARM64_SYS_REG(3, 0, 0, 2, 7));
354 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr0
,
355 ARM64_SYS_REG(3, 0, 0, 3, 0));
356 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr1
,
357 ARM64_SYS_REG(3, 0, 0, 3, 1));
358 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr2
,
359 ARM64_SYS_REG(3, 0, 0, 3, 2));
360 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_pfr2
,
361 ARM64_SYS_REG(3, 0, 0, 3, 4));
362 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_dfr1
,
363 ARM64_SYS_REG(3, 0, 0, 3, 5));
364 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_mmfr5
,
365 ARM64_SYS_REG(3, 0, 0, 3, 6));
368 * DBGDIDR is a bit complicated because the kernel doesn't
369 * provide an accessor for it in 64-bit mode, which is what this
370 * scratch VM is in, and there's no architected "64-bit sysreg
371 * which reads the same as the 32-bit register" the way there is
372 * for other ID registers. Instead we synthesize a value from the
373 * AArch64 ID_AA64DFR0, the same way the kernel code in
374 * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
375 * We only do this if the CPU supports AArch32 at EL1.
377 if (FIELD_EX32(ahcf
->isar
.id_aa64pfr0
, ID_AA64PFR0
, EL1
) >= 2) {
378 int wrps
= FIELD_EX64(ahcf
->isar
.id_aa64dfr0
, ID_AA64DFR0
, WRPS
);
379 int brps
= FIELD_EX64(ahcf
->isar
.id_aa64dfr0
, ID_AA64DFR0
, BRPS
);
381 FIELD_EX64(ahcf
->isar
.id_aa64dfr0
, ID_AA64DFR0
, CTX_CMPS
);
382 int version
= 6; /* ARMv8 debug architecture */
384 !!FIELD_EX32(ahcf
->isar
.id_aa64pfr0
, ID_AA64PFR0
, EL3
);
385 uint32_t dbgdidr
= 0;
387 dbgdidr
= FIELD_DP32(dbgdidr
, DBGDIDR
, WRPS
, wrps
);
388 dbgdidr
= FIELD_DP32(dbgdidr
, DBGDIDR
, BRPS
, brps
);
389 dbgdidr
= FIELD_DP32(dbgdidr
, DBGDIDR
, CTX_CMPS
, ctx_cmps
);
390 dbgdidr
= FIELD_DP32(dbgdidr
, DBGDIDR
, VERSION
, version
);
391 dbgdidr
= FIELD_DP32(dbgdidr
, DBGDIDR
, NSUHD_IMP
, has_el3
);
392 dbgdidr
= FIELD_DP32(dbgdidr
, DBGDIDR
, SE_IMP
, has_el3
);
393 dbgdidr
|= (1 << 15); /* RES1 bit */
394 ahcf
->isar
.dbgdidr
= dbgdidr
;
398 /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */
399 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.reset_pmcr_el0
,
400 ARM64_SYS_REG(3, 3, 9, 12, 0));
405 * There is a range of kernels between kernel commit 73433762fcae
406 * and f81cb2c3ad41 which have a bug where the kernel doesn't
407 * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
408 * enabled SVE support, which resulted in an error rather than RAZ.
409 * So only read the register if we set KVM_ARM_VCPU_SVE above.
411 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64zfr0
,
412 ARM64_SYS_REG(3, 0, 0, 4, 4));
416 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
423 * We can assume any KVM supporting CPU is at least a v8
424 * with VFPv4+Neon; this in turn implies most of the other
427 features
|= 1ULL << ARM_FEATURE_V8
;
428 features
|= 1ULL << ARM_FEATURE_NEON
;
429 features
|= 1ULL << ARM_FEATURE_AARCH64
;
430 features
|= 1ULL << ARM_FEATURE_PMU
;
431 features
|= 1ULL << ARM_FEATURE_GENERIC_TIMER
;
433 ahcf
->features
= features
;
438 void kvm_arm_steal_time_finalize(ARMCPU
*cpu
, Error
**errp
)
440 bool has_steal_time
= kvm_arm_steal_time_supported();
442 if (cpu
->kvm_steal_time
== ON_OFF_AUTO_AUTO
) {
443 if (!has_steal_time
|| !arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
444 cpu
->kvm_steal_time
= ON_OFF_AUTO_OFF
;
446 cpu
->kvm_steal_time
= ON_OFF_AUTO_ON
;
448 } else if (cpu
->kvm_steal_time
== ON_OFF_AUTO_ON
) {
449 if (!has_steal_time
) {
450 error_setg(errp
, "'kvm-steal-time' cannot be enabled "
453 } else if (!arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
455 * DEN0057A chapter 2 says "This specification only covers
456 * systems in which the Execution state of the hypervisor
457 * as well as EL1 of virtual machines is AArch64.". And,
458 * to ensure that, the smc/hvc calls are only specified as
461 error_setg(errp
, "'kvm-steal-time' cannot be enabled "
462 "for AArch32 guests");
468 bool kvm_arm_aarch32_supported(void)
470 return kvm_check_extension(kvm_state
, KVM_CAP_ARM_EL1_32BIT
);
473 bool kvm_arm_sve_supported(void)
475 return kvm_check_extension(kvm_state
, KVM_CAP_ARM_SVE
);
478 bool kvm_arm_steal_time_supported(void)
480 return kvm_check_extension(kvm_state
, KVM_CAP_STEAL_TIME
);
483 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN
!= 1);
485 uint32_t kvm_arm_sve_get_vls(CPUState
*cs
)
487 /* Only call this function if kvm_arm_sve_supported() returns true. */
488 static uint64_t vls
[KVM_ARM64_SVE_VLS_WORDS
];
494 * KVM ensures all host CPUs support the same set of vector lengths.
495 * So we only need to create the scratch VCPUs once and then cache
499 struct kvm_vcpu_init init
= {
501 .features
[0] = (1 << KVM_ARM_VCPU_SVE
),
503 struct kvm_one_reg reg
= {
504 .id
= KVM_REG_ARM64_SVE_VLS
,
505 .addr
= (uint64_t)&vls
[0],
511 if (!kvm_arm_create_scratch_host_vcpu(NULL
, fdarray
, &init
)) {
512 error_report("failed to create scratch VCPU with SVE enabled");
515 ret
= ioctl(fdarray
[2], KVM_GET_ONE_REG
, ®
);
516 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
518 error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
523 for (i
= KVM_ARM64_SVE_VLS_WORDS
- 1; i
>= 0; --i
) {
525 vq
= 64 - clz64(vls
[i
]) + i
* 64;
529 if (vq
> ARM_MAX_VQ
) {
530 warn_report("KVM supports vector lengths larger than "
532 vls
[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ
);
539 static int kvm_arm_sve_set_vls(CPUState
*cs
)
541 ARMCPU
*cpu
= ARM_CPU(cs
);
542 uint64_t vls
[KVM_ARM64_SVE_VLS_WORDS
] = { cpu
->sve_vq
.map
};
544 assert(cpu
->sve_max_vq
<= KVM_ARM64_SVE_VQ_MAX
);
546 return kvm_set_one_reg(cs
, KVM_REG_ARM64_SVE_VLS
, &vls
[0]);
549 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
551 int kvm_arch_init_vcpu(CPUState
*cs
)
555 ARMCPU
*cpu
= ARM_CPU(cs
);
556 CPUARMState
*env
= &cpu
->env
;
559 if (cpu
->kvm_target
== QEMU_KVM_ARM_TARGET_NONE
||
560 !object_dynamic_cast(OBJECT(cpu
), TYPE_AARCH64_CPU
)) {
561 error_report("KVM is not supported for this guest CPU type");
565 qemu_add_vm_change_state_handler(kvm_arm_vm_state_change
, cs
);
567 /* Determine init features for this CPU */
568 memset(cpu
->kvm_init_features
, 0, sizeof(cpu
->kvm_init_features
));
569 if (cs
->start_powered_off
) {
570 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_POWER_OFF
;
572 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PSCI_0_2
)) {
573 cpu
->psci_version
= QEMU_PSCI_VERSION_0_2
;
574 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2
;
576 if (!arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
577 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT
;
579 if (!kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PMU_V3
)) {
580 cpu
->has_pmu
= false;
583 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PMU_V3
;
585 env
->features
&= ~(1ULL << ARM_FEATURE_PMU
);
587 if (cpu_isar_feature(aa64_sve
, cpu
)) {
588 assert(kvm_arm_sve_supported());
589 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_SVE
;
591 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
592 cpu
->kvm_init_features
[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS
|
593 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC
);
596 /* Do KVM_ARM_VCPU_INIT ioctl */
597 ret
= kvm_arm_vcpu_init(cs
);
602 if (cpu_isar_feature(aa64_sve
, cpu
)) {
603 ret
= kvm_arm_sve_set_vls(cs
);
607 ret
= kvm_arm_vcpu_finalize(cs
, KVM_ARM_VCPU_SVE
);
614 * KVM reports the exact PSCI version it is implementing via a
615 * special sysreg. If it is present, use its contents to determine
616 * what to report to the guest in the dtb (it is the PSCI version,
617 * in the same 15-bits major 16-bits minor format that PSCI_VERSION
620 if (!kvm_get_one_reg(cs
, KVM_REG_ARM_PSCI_VERSION
, &psciver
)) {
621 cpu
->psci_version
= psciver
;
625 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
626 * Currently KVM has its own idea about MPIDR assignment, so we
627 * override our defaults with what we get from KVM.
629 ret
= kvm_get_one_reg(cs
, ARM64_SYS_REG(ARM_CPU_ID_MPIDR
), &mpidr
);
633 cpu
->mp_affinity
= mpidr
& ARM64_AFFINITY_MASK
;
635 /* Check whether user space can specify guest syndrome value */
636 kvm_arm_init_serror_injection(cs
);
638 return kvm_arm_init_cpreg_list(cpu
);
641 int kvm_arch_destroy_vcpu(CPUState
*cs
)
646 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx
)
648 /* Return true if the regidx is a register we should synchronize
649 * via the cpreg_tuples array (ie is not a core or sve reg that
650 * we sync by hand in kvm_arch_get/put_registers())
652 switch (regidx
& KVM_REG_ARM_COPROC_MASK
) {
653 case KVM_REG_ARM_CORE
:
654 case KVM_REG_ARM64_SVE
:
661 typedef struct CPRegStateLevel
{
666 /* All system registers not listed in the following table are assumed to be
667 * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
668 * often, you must add it to this table with a state of either
669 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
671 static const CPRegStateLevel non_runtime_cpregs
[] = {
672 { KVM_REG_ARM_TIMER_CNT
, KVM_PUT_FULL_STATE
},
673 { KVM_REG_ARM_PTIMER_CNT
, KVM_PUT_FULL_STATE
},
676 int kvm_arm_cpreg_level(uint64_t regidx
)
680 for (i
= 0; i
< ARRAY_SIZE(non_runtime_cpregs
); i
++) {
681 const CPRegStateLevel
*l
= &non_runtime_cpregs
[i
];
682 if (l
->regidx
== regidx
) {
687 return KVM_PUT_RUNTIME_STATE
;
690 /* Callers must hold the iothread mutex lock */
691 static void kvm_inject_arm_sea(CPUState
*c
)
693 ARMCPU
*cpu
= ARM_CPU(c
);
694 CPUARMState
*env
= &cpu
->env
;
698 c
->exception_index
= EXCP_DATA_ABORT
;
699 env
->exception
.target_el
= 1;
702 * Set the DFSC to synchronous external abort and set FnV to not valid,
703 * this will tell guest the FAR_ELx is UNKNOWN for this abort.
705 same_el
= arm_current_el(env
) == env
->exception
.target_el
;
706 esr
= syn_data_abort_no_iss(same_el
, 1, 0, 0, 0, 0, 0x10);
708 env
->exception
.syndrome
= esr
;
710 arm_cpu_do_interrupt(c
);
713 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
714 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
716 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
717 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
719 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
720 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
722 static int kvm_arch_put_fpsimd(CPUState
*cs
)
724 CPUARMState
*env
= &ARM_CPU(cs
)->env
;
727 for (i
= 0; i
< 32; i
++) {
728 uint64_t *q
= aa64_vfp_qreg(env
, i
);
730 uint64_t fp_val
[2] = { q
[1], q
[0] };
731 ret
= kvm_set_one_reg(cs
, AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]),
734 ret
= kvm_set_one_reg(cs
, AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]), q
);
745 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
746 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
747 * code the slice index to zero for now as it's unlikely we'll need more than
748 * one slice for quite some time.
750 static int kvm_arch_put_sve(CPUState
*cs
)
752 ARMCPU
*cpu
= ARM_CPU(cs
);
753 CPUARMState
*env
= &cpu
->env
;
754 uint64_t tmp
[ARM_MAX_VQ
* 2];
758 for (n
= 0; n
< KVM_ARM64_SVE_NUM_ZREGS
; ++n
) {
759 r
= sve_bswap64(tmp
, &env
->vfp
.zregs
[n
].d
[0], cpu
->sve_max_vq
* 2);
760 ret
= kvm_set_one_reg(cs
, KVM_REG_ARM64_SVE_ZREG(n
, 0), r
);
766 for (n
= 0; n
< KVM_ARM64_SVE_NUM_PREGS
; ++n
) {
767 r
= sve_bswap64(tmp
, r
= &env
->vfp
.pregs
[n
].p
[0],
768 DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
769 ret
= kvm_set_one_reg(cs
, KVM_REG_ARM64_SVE_PREG(n
, 0), r
);
775 r
= sve_bswap64(tmp
, &env
->vfp
.pregs
[FFR_PRED_NUM
].p
[0],
776 DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
777 ret
= kvm_set_one_reg(cs
, KVM_REG_ARM64_SVE_FFR(0), r
);
785 int kvm_arch_put_registers(CPUState
*cs
, int level
)
792 ARMCPU
*cpu
= ARM_CPU(cs
);
793 CPUARMState
*env
= &cpu
->env
;
795 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
796 * AArch64 registers before pushing them out to 64-bit KVM.
799 aarch64_sync_32_to_64(env
);
802 for (i
= 0; i
< 31; i
++) {
803 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(regs
.regs
[i
]),
810 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
811 * QEMU side we keep the current SP in xregs[31] as well.
813 aarch64_save_sp(env
, 1);
815 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(regs
.sp
), &env
->sp_el
[0]);
820 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(sp_el1
), &env
->sp_el
[1]);
825 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
827 val
= pstate_read(env
);
829 val
= cpsr_read(env
);
831 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(regs
.pstate
), &val
);
836 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(regs
.pc
), &env
->pc
);
841 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(elr_el1
), &env
->elr_el
[1]);
846 /* Saved Program State Registers
848 * Before we restore from the banked_spsr[] array we need to
849 * ensure that any modifications to env->spsr are correctly
850 * reflected in the banks.
852 el
= arm_current_el(env
);
853 if (el
> 0 && !is_a64(env
)) {
854 i
= bank_number(env
->uncached_cpsr
& CPSR_M
);
855 env
->banked_spsr
[i
] = env
->spsr
;
858 /* KVM 0-4 map to QEMU banks 1-5 */
859 for (i
= 0; i
< KVM_NR_SPSR
; i
++) {
860 ret
= kvm_set_one_reg(cs
, AARCH64_CORE_REG(spsr
[i
]),
861 &env
->banked_spsr
[i
+ 1]);
867 if (cpu_isar_feature(aa64_sve
, cpu
)) {
868 ret
= kvm_arch_put_sve(cs
);
870 ret
= kvm_arch_put_fpsimd(cs
);
876 fpr
= vfp_get_fpsr(env
);
877 ret
= kvm_set_one_reg(cs
, AARCH64_SIMD_CTRL_REG(fp_regs
.fpsr
), &fpr
);
882 fpr
= vfp_get_fpcr(env
);
883 ret
= kvm_set_one_reg(cs
, AARCH64_SIMD_CTRL_REG(fp_regs
.fpcr
), &fpr
);
888 write_cpustate_to_list(cpu
, true);
890 if (!write_list_to_kvmstate(cpu
, level
)) {
895 * Setting VCPU events should be triggered after syncing the registers
896 * to avoid overwriting potential changes made by KVM upon calling
897 * KVM_SET_VCPU_EVENTS ioctl
899 ret
= kvm_put_vcpu_events(cpu
);
904 kvm_arm_sync_mpstate_to_kvm(cpu
);
909 static int kvm_arch_get_fpsimd(CPUState
*cs
)
911 CPUARMState
*env
= &ARM_CPU(cs
)->env
;
914 for (i
= 0; i
< 32; i
++) {
915 uint64_t *q
= aa64_vfp_qreg(env
, i
);
916 ret
= kvm_get_one_reg(cs
, AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]), q
);
922 t
= q
[0], q
[0] = q
[1], q
[1] = t
;
931 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
932 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
933 * code the slice index to zero for now as it's unlikely we'll need more than
934 * one slice for quite some time.
936 static int kvm_arch_get_sve(CPUState
*cs
)
938 ARMCPU
*cpu
= ARM_CPU(cs
);
939 CPUARMState
*env
= &cpu
->env
;
943 for (n
= 0; n
< KVM_ARM64_SVE_NUM_ZREGS
; ++n
) {
944 r
= &env
->vfp
.zregs
[n
].d
[0];
945 ret
= kvm_get_one_reg(cs
, KVM_REG_ARM64_SVE_ZREG(n
, 0), r
);
949 sve_bswap64(r
, r
, cpu
->sve_max_vq
* 2);
952 for (n
= 0; n
< KVM_ARM64_SVE_NUM_PREGS
; ++n
) {
953 r
= &env
->vfp
.pregs
[n
].p
[0];
954 ret
= kvm_get_one_reg(cs
, KVM_REG_ARM64_SVE_PREG(n
, 0), r
);
958 sve_bswap64(r
, r
, DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
961 r
= &env
->vfp
.pregs
[FFR_PRED_NUM
].p
[0];
962 ret
= kvm_get_one_reg(cs
, KVM_REG_ARM64_SVE_FFR(0), r
);
966 sve_bswap64(r
, r
, DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
971 int kvm_arch_get_registers(CPUState
*cs
)
978 ARMCPU
*cpu
= ARM_CPU(cs
);
979 CPUARMState
*env
= &cpu
->env
;
981 for (i
= 0; i
< 31; i
++) {
982 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(regs
.regs
[i
]),
989 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(regs
.sp
), &env
->sp_el
[0]);
994 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(sp_el1
), &env
->sp_el
[1]);
999 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(regs
.pstate
), &val
);
1004 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
1006 pstate_write(env
, val
);
1008 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
1011 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
1012 * QEMU side we keep the current SP in xregs[31] as well.
1014 aarch64_restore_sp(env
, 1);
1016 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(regs
.pc
), &env
->pc
);
1021 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
1022 * incoming AArch64 regs received from 64-bit KVM.
1023 * We must perform this after all of the registers have been acquired from
1027 aarch64_sync_64_to_32(env
);
1030 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(elr_el1
), &env
->elr_el
[1]);
1035 /* Fetch the SPSR registers
1037 * KVM SPSRs 0-4 map to QEMU banks 1-5
1039 for (i
= 0; i
< KVM_NR_SPSR
; i
++) {
1040 ret
= kvm_get_one_reg(cs
, AARCH64_CORE_REG(spsr
[i
]),
1041 &env
->banked_spsr
[i
+ 1]);
1047 el
= arm_current_el(env
);
1048 if (el
> 0 && !is_a64(env
)) {
1049 i
= bank_number(env
->uncached_cpsr
& CPSR_M
);
1050 env
->spsr
= env
->banked_spsr
[i
];
1053 if (cpu_isar_feature(aa64_sve
, cpu
)) {
1054 ret
= kvm_arch_get_sve(cs
);
1056 ret
= kvm_arch_get_fpsimd(cs
);
1062 ret
= kvm_get_one_reg(cs
, AARCH64_SIMD_CTRL_REG(fp_regs
.fpsr
), &fpr
);
1066 vfp_set_fpsr(env
, fpr
);
1068 ret
= kvm_get_one_reg(cs
, AARCH64_SIMD_CTRL_REG(fp_regs
.fpcr
), &fpr
);
1072 vfp_set_fpcr(env
, fpr
);
1074 ret
= kvm_get_vcpu_events(cpu
);
1079 if (!write_kvmstate_to_list(cpu
)) {
1082 /* Note that it's OK to have registers which aren't in CPUState,
1083 * so we can ignore a failure return here.
1085 write_list_to_cpustate(cpu
);
1087 kvm_arm_sync_mpstate_to_qemu(cpu
);
1089 /* TODO: other registers */
1093 void kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
1095 ram_addr_t ram_addr
;
1098 assert(code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
);
1100 if (acpi_ghes_present() && addr
) {
1101 ram_addr
= qemu_ram_addr_from_host(addr
);
1102 if (ram_addr
!= RAM_ADDR_INVALID
&&
1103 kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
1104 kvm_hwpoison_page_add(ram_addr
);
1106 * If this is a BUS_MCEERR_AR, we know we have been called
1107 * synchronously from the vCPU thread, so we can easily
1108 * synchronize the state and inject an error.
1110 * TODO: we currently don't tell the guest at all about
1111 * BUS_MCEERR_AO. In that case we might either be being
1112 * called synchronously from the vCPU thread, or a bit
1113 * later from the main thread, so doing the injection of
1114 * the error would be more complicated.
1116 if (code
== BUS_MCEERR_AR
) {
1117 kvm_cpu_synchronize_state(c
);
1118 if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA
, paddr
)) {
1119 kvm_inject_arm_sea(c
);
1121 error_report("failed to record the error");
1127 if (code
== BUS_MCEERR_AO
) {
1128 error_report("Hardware memory error at addr %p for memory used by "
1129 "QEMU itself instead of guest system!", addr
);
1133 if (code
== BUS_MCEERR_AR
) {
1134 error_report("Hardware memory error!");
1139 /* C6.6.29 BRK instruction */
1140 static const uint32_t brk_insn
= 0xd4200000;
1142 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1144 if (have_guest_debug
) {
1145 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 4, 0) ||
1146 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&brk_insn
, 4, 1)) {
1151 error_report("guest debug not supported on this kernel");
1156 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1158 static uint32_t brk
;
1160 if (have_guest_debug
) {
1161 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&brk
, 4, 0) ||
1163 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 4, 1)) {
1168 error_report("guest debug not supported on this kernel");
1173 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
1175 * To minimise translating between kernel and user-space the kernel
1176 * ABI just provides user-space with the full exception syndrome
1177 * register value to be decoded in QEMU.
1180 bool kvm_arm_handle_debug(CPUState
*cs
, struct kvm_debug_exit_arch
*debug_exit
)
1182 int hsr_ec
= syn_get_ec(debug_exit
->hsr
);
1183 ARMCPU
*cpu
= ARM_CPU(cs
);
1184 CPUARMState
*env
= &cpu
->env
;
1186 /* Ensure PC is synchronised */
1187 kvm_cpu_synchronize_state(cs
);
1190 case EC_SOFTWARESTEP
:
1191 if (cs
->singlestep_enabled
) {
1195 * The kernel should have suppressed the guest's ability to
1196 * single step at this point so something has gone wrong.
1198 error_report("%s: guest single-step while debugging unsupported"
1199 " (%"PRIx64
", %"PRIx32
")",
1200 __func__
, env
->pc
, debug_exit
->hsr
);
1205 if (kvm_find_sw_breakpoint(cs
, env
->pc
)) {
1210 if (find_hw_breakpoint(cs
, env
->pc
)) {
1216 CPUWatchpoint
*wp
= find_hw_watchpoint(cs
, debug_exit
->far
);
1218 cs
->watchpoint_hit
= wp
;
1224 error_report("%s: unhandled debug exit (%"PRIx32
", %"PRIx64
")",
1225 __func__
, debug_exit
->hsr
, env
->pc
);
1228 /* If we are not handling the debug exception it must belong to
1229 * the guest. Let's re-use the existing TCG interrupt code to set
1230 * everything up properly.
1232 cs
->exception_index
= EXCP_BKPT
;
1233 env
->exception
.syndrome
= debug_exit
->hsr
;
1234 env
->exception
.vaddress
= debug_exit
->far
;
1235 env
->exception
.target_el
= 1;
1236 qemu_mutex_lock_iothread();
1237 arm_cpu_do_interrupt(cs
);
1238 qemu_mutex_unlock_iothread();
1243 #define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
1244 #define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
1249 * AARCH64: DFSC, bits [5:0]
1253 * FS[3:0] - DFSR[3:0]
1257 #define ESR_DFSC(aarch64, lpae, v) \
1258 ((aarch64 || (lpae)) ? ((v) & 0x3F) \
1259 : (((v) >> 6) | ((v) & 0x1F)))
1261 #define ESR_DFSC_EXTABT(aarch64, lpae) \
1262 ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
1264 bool kvm_arm_verify_ext_dabt_pending(CPUState
*cs
)
1268 if (!kvm_get_one_reg(cs
, ARM64_REG_ESR_EL1
, &dfsr_val
)) {
1269 ARMCPU
*cpu
= ARM_CPU(cs
);
1270 CPUARMState
*env
= &cpu
->env
;
1271 int aarch64_mode
= arm_feature(env
, ARM_FEATURE_AARCH64
);
1274 if (!aarch64_mode
) {
1277 if (!kvm_get_one_reg(cs
, ARM64_REG_TCR_EL1
, &ttbcr
)) {
1278 lpae
= arm_feature(env
, ARM_FEATURE_LPAE
)
1279 && (ttbcr
& TTBCR_EAE
);
1283 * The verification here is based on the DFSC bits
1284 * of the ESR_EL1 reg only
1286 return (ESR_DFSC(aarch64_mode
, lpae
, dfsr_val
) ==
1287 ESR_DFSC_EXTABT(aarch64_mode
, lpae
));