2 * Arm SSE (Subsystems for Embedded): IoTKit
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qemu/module.h"
15 #include "qemu/bitops.h"
16 #include "qapi/error.h"
18 #include "hw/sysbus.h"
19 #include "migration/vmstate.h"
20 #include "hw/registerfields.h"
21 #include "hw/arm/armsse.h"
22 #include "hw/arm/armsse-version.h"
23 #include "hw/arm/boot.h"
25 #include "hw/qdev-clock.h"
27 /* Format of the System Information block SYS_CONFIG register */
28 typedef enum SysConfigFormat
{
40 SysConfigFormat sys_config_format
;
49 static Property iotkit_properties
[] = {
50 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
52 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
53 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
54 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
55 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], true),
56 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], true),
57 DEFINE_PROP_END_OF_LIST()
60 static Property armsse_properties
[] = {
61 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
63 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
64 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
65 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
66 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], false),
67 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], false),
68 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE
, cpu_fpu
[1], true),
69 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE
, cpu_dsp
[1], true),
70 DEFINE_PROP_END_OF_LIST()
73 static const ARMSSEInfo armsse_variants
[] = {
76 .sse_version
= ARMSSE_IOTKIT
,
79 .sys_version
= 0x41743,
81 .sys_config_format
= IoTKitFormat
,
84 .has_cachectrl
= false,
85 .has_cpusecctrl
= false,
87 .props
= iotkit_properties
,
91 .sse_version
= ARMSSE_SSE200
,
94 .sys_version
= 0x22041743,
96 .sys_config_format
= SSE200Format
,
99 .has_cachectrl
= true,
100 .has_cpusecctrl
= true,
102 .props
= armsse_properties
,
106 static uint32_t armsse_sys_config_value(ARMSSE
*s
, const ARMSSEInfo
*info
)
108 /* Return the SYS_CONFIG value for this SSE */
111 switch (info
->sys_config_format
) {
114 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
115 sys_config
= deposit32(sys_config
, 4, 4, s
->sram_addr_width
- 12);
119 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
120 sys_config
= deposit32(sys_config
, 4, 5, s
->sram_addr_width
);
121 sys_config
= deposit32(sys_config
, 24, 4, 2);
122 if (info
->num_cpus
> 1) {
123 sys_config
= deposit32(sys_config
, 10, 1, 1);
124 sys_config
= deposit32(sys_config
, 20, 4, info
->sram_banks
- 1);
125 sys_config
= deposit32(sys_config
, 28, 4, 2);
129 g_assert_not_reached();
134 /* Clock frequency in HZ of the 32KHz "slow clock" */
135 #define S32KCLK (32 * 1000)
137 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
138 static bool irq_is_common
[32] = {
140 /* 6, 7: per-CPU MHU interrupts */
142 /* 13: per-CPU icache interrupt */
148 /* 28, 29: per-CPU CTI interrupts */
149 /* 30, 31: reserved */
153 * Create an alias region in @container of @size bytes starting at @base
154 * which mirrors the memory starting at @orig.
156 static void make_alias(ARMSSE
*s
, MemoryRegion
*mr
, MemoryRegion
*container
,
157 const char *name
, hwaddr base
, hwaddr size
, hwaddr orig
)
159 memory_region_init_alias(mr
, NULL
, name
, container
, orig
, size
);
160 /* The alias is even lower priority than unimplemented_device regions */
161 memory_region_add_subregion_overlap(container
, base
, mr
, -1500);
164 static void irq_status_forwarder(void *opaque
, int n
, int level
)
166 qemu_irq destirq
= opaque
;
168 qemu_set_irq(destirq
, level
);
171 static void nsccfg_handler(void *opaque
, int n
, int level
)
173 ARMSSE
*s
= ARM_SSE(opaque
);
178 static void armsse_forward_ppc(ARMSSE
*s
, const char *ppcname
, int ppcnum
)
180 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
181 * system using the ARMSSE has a collection of control lines which
182 * are provided by the security controller and which we want to
183 * expose as control lines on the ARMSSE device itself, so the
184 * code using the ARMSSE can wire them up to the PPCs.
186 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[ppcnum
];
187 DeviceState
*armssedev
= DEVICE(s
);
188 DeviceState
*dev_secctl
= DEVICE(&s
->secctl
);
189 DeviceState
*dev_splitter
= DEVICE(splitter
);
192 name
= g_strdup_printf("%s_nonsec", ppcname
);
193 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
195 name
= g_strdup_printf("%s_ap", ppcname
);
196 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
198 name
= g_strdup_printf("%s_irq_enable", ppcname
);
199 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
201 name
= g_strdup_printf("%s_irq_clear", ppcname
);
202 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
205 /* irq_status is a little more tricky, because we need to
206 * split it so we can send it both to the security controller
207 * and to our OR gate for the NVIC interrupt line.
208 * Connect up the splitter's outputs, and create a GPIO input
209 * which will pass the line state to the input splitter.
211 name
= g_strdup_printf("%s_irq_status", ppcname
);
212 qdev_connect_gpio_out(dev_splitter
, 0,
213 qdev_get_gpio_in_named(dev_secctl
,
215 qdev_connect_gpio_out(dev_splitter
, 1,
216 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), ppcnum
));
217 s
->irq_status_in
[ppcnum
] = qdev_get_gpio_in(dev_splitter
, 0);
218 qdev_init_gpio_in_named_with_opaque(armssedev
, irq_status_forwarder
,
219 s
->irq_status_in
[ppcnum
], name
, 1);
223 static void armsse_forward_sec_resp_cfg(ARMSSE
*s
)
225 /* Forward the 3rd output from the splitter device as a
226 * named GPIO output of the armsse object.
228 DeviceState
*dev
= DEVICE(s
);
229 DeviceState
*dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
231 qdev_init_gpio_out_named(dev
, &s
->sec_resp_cfg
, "sec_resp_cfg", 1);
232 s
->sec_resp_cfg_in
= qemu_allocate_irq(irq_status_forwarder
,
234 qdev_connect_gpio_out(dev_splitter
, 2, s
->sec_resp_cfg_in
);
237 static void armsse_mainclk_update(void *opaque
, ClockEvent event
)
239 ARMSSE
*s
= ARM_SSE(opaque
);
242 * Set system_clock_scale from our Clock input; this is what
243 * controls the tick rate of the CPU SysTick timer.
245 system_clock_scale
= clock_ticks_to_ns(s
->mainclk
, 1);
248 static void armsse_init(Object
*obj
)
250 ARMSSE
*s
= ARM_SSE(obj
);
251 ARMSSEClass
*asc
= ARM_SSE_GET_CLASS(obj
);
252 const ARMSSEInfo
*info
= asc
->info
;
255 assert(info
->sram_banks
<= MAX_SRAM_BANKS
);
256 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
258 s
->mainclk
= qdev_init_clock_in(DEVICE(s
), "MAINCLK",
259 armsse_mainclk_update
, s
, ClockUpdate
);
260 s
->s32kclk
= qdev_init_clock_in(DEVICE(s
), "S32KCLK", NULL
, NULL
, 0);
262 memory_region_init(&s
->container
, obj
, "armsse-container", UINT64_MAX
);
264 for (i
= 0; i
< info
->num_cpus
; i
++) {
266 * We put each CPU in its own cluster as they are logically
267 * distinct and may be configured differently.
271 name
= g_strdup_printf("cluster%d", i
);
272 object_initialize_child(obj
, name
, &s
->cluster
[i
], TYPE_CPU_CLUSTER
);
273 qdev_prop_set_uint32(DEVICE(&s
->cluster
[i
]), "cluster-id", i
);
276 name
= g_strdup_printf("armv7m%d", i
);
277 object_initialize_child(OBJECT(&s
->cluster
[i
]), name
, &s
->armv7m
[i
],
279 qdev_prop_set_string(DEVICE(&s
->armv7m
[i
]), "cpu-type",
280 ARM_CPU_TYPE_NAME("cortex-m33"));
282 name
= g_strdup_printf("arm-sse-cpu-container%d", i
);
283 memory_region_init(&s
->cpu_container
[i
], obj
, name
, UINT64_MAX
);
286 name
= g_strdup_printf("arm-sse-container-alias%d", i
);
287 memory_region_init_alias(&s
->container_alias
[i
- 1], obj
,
288 name
, &s
->container
, 0, UINT64_MAX
);
293 object_initialize_child(obj
, "secctl", &s
->secctl
, TYPE_IOTKIT_SECCTL
);
294 object_initialize_child(obj
, "apb-ppc0", &s
->apb_ppc0
, TYPE_TZ_PPC
);
295 object_initialize_child(obj
, "apb-ppc1", &s
->apb_ppc1
, TYPE_TZ_PPC
);
296 for (i
= 0; i
< info
->sram_banks
; i
++) {
297 char *name
= g_strdup_printf("mpc%d", i
);
298 object_initialize_child(obj
, name
, &s
->mpc
[i
], TYPE_TZ_MPC
);
301 object_initialize_child(obj
, "mpc-irq-orgate", &s
->mpc_irq_orgate
,
304 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
305 char *name
= g_strdup_printf("mpc-irq-splitter-%d", i
);
306 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
308 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
311 object_initialize_child(obj
, "timer0", &s
->timer0
, TYPE_CMSDK_APB_TIMER
);
312 object_initialize_child(obj
, "timer1", &s
->timer1
, TYPE_CMSDK_APB_TIMER
);
313 object_initialize_child(obj
, "s32ktimer", &s
->s32ktimer
,
314 TYPE_CMSDK_APB_TIMER
);
315 object_initialize_child(obj
, "dualtimer", &s
->dualtimer
,
316 TYPE_CMSDK_APB_DUALTIMER
);
317 object_initialize_child(obj
, "s32kwatchdog", &s
->s32kwatchdog
,
318 TYPE_CMSDK_APB_WATCHDOG
);
319 object_initialize_child(obj
, "nswatchdog", &s
->nswatchdog
,
320 TYPE_CMSDK_APB_WATCHDOG
);
321 object_initialize_child(obj
, "swatchdog", &s
->swatchdog
,
322 TYPE_CMSDK_APB_WATCHDOG
);
323 object_initialize_child(obj
, "armsse-sysctl", &s
->sysctl
,
325 object_initialize_child(obj
, "armsse-sysinfo", &s
->sysinfo
,
326 TYPE_IOTKIT_SYSINFO
);
327 if (info
->has_mhus
) {
328 object_initialize_child(obj
, "mhu0", &s
->mhu
[0], TYPE_ARMSSE_MHU
);
329 object_initialize_child(obj
, "mhu1", &s
->mhu
[1], TYPE_ARMSSE_MHU
);
331 if (info
->has_ppus
) {
332 for (i
= 0; i
< info
->num_cpus
; i
++) {
333 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
334 int ppuidx
= CPU0CORE_PPU
+ i
;
336 object_initialize_child(obj
, name
, &s
->ppu
[ppuidx
],
337 TYPE_UNIMPLEMENTED_DEVICE
);
340 object_initialize_child(obj
, "DBG_PPU", &s
->ppu
[DBG_PPU
],
341 TYPE_UNIMPLEMENTED_DEVICE
);
342 for (i
= 0; i
< info
->sram_banks
; i
++) {
343 char *name
= g_strdup_printf("RAM%d_PPU", i
);
344 int ppuidx
= RAM0_PPU
+ i
;
346 object_initialize_child(obj
, name
, &s
->ppu
[ppuidx
],
347 TYPE_UNIMPLEMENTED_DEVICE
);
351 if (info
->has_cachectrl
) {
352 for (i
= 0; i
< info
->num_cpus
; i
++) {
353 char *name
= g_strdup_printf("cachectrl%d", i
);
355 object_initialize_child(obj
, name
, &s
->cachectrl
[i
],
356 TYPE_UNIMPLEMENTED_DEVICE
);
360 if (info
->has_cpusecctrl
) {
361 for (i
= 0; i
< info
->num_cpus
; i
++) {
362 char *name
= g_strdup_printf("cpusecctrl%d", i
);
364 object_initialize_child(obj
, name
, &s
->cpusecctrl
[i
],
365 TYPE_UNIMPLEMENTED_DEVICE
);
369 if (info
->has_cpuid
) {
370 for (i
= 0; i
< info
->num_cpus
; i
++) {
371 char *name
= g_strdup_printf("cpuid%d", i
);
373 object_initialize_child(obj
, name
, &s
->cpuid
[i
],
378 object_initialize_child(obj
, "nmi-orgate", &s
->nmi_orgate
, TYPE_OR_IRQ
);
379 object_initialize_child(obj
, "ppc-irq-orgate", &s
->ppc_irq_orgate
,
381 object_initialize_child(obj
, "sec-resp-splitter", &s
->sec_resp_splitter
,
383 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
384 char *name
= g_strdup_printf("ppc-irq-splitter-%d", i
);
385 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[i
];
387 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
390 if (info
->num_cpus
> 1) {
391 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
392 if (irq_is_common
[i
]) {
393 char *name
= g_strdup_printf("cpu-irq-splitter%d", i
);
394 SplitIRQ
*splitter
= &s
->cpu_irq_splitter
[i
];
396 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
403 static void armsse_exp_irq(void *opaque
, int n
, int level
)
405 qemu_irq
*irqarray
= opaque
;
407 qemu_set_irq(irqarray
[n
], level
);
410 static void armsse_mpcexp_status(void *opaque
, int n
, int level
)
412 ARMSSE
*s
= ARM_SSE(opaque
);
413 qemu_set_irq(s
->mpcexp_status_in
[n
], level
);
416 static qemu_irq
armsse_get_common_irq_in(ARMSSE
*s
, int irqno
)
419 * Return a qemu_irq which can be used to signal IRQ n to
420 * all CPUs in the SSE.
422 ARMSSEClass
*asc
= ARM_SSE_GET_CLASS(s
);
423 const ARMSSEInfo
*info
= asc
->info
;
425 assert(irq_is_common
[irqno
]);
427 if (info
->num_cpus
== 1) {
428 /* Only one CPU -- just connect directly to it */
429 return qdev_get_gpio_in(DEVICE(&s
->armv7m
[0]), irqno
);
431 /* Connect to the splitter which feeds all CPUs */
432 return qdev_get_gpio_in(DEVICE(&s
->cpu_irq_splitter
[irqno
]), 0);
436 static void map_ppu(ARMSSE
*s
, int ppuidx
, const char *name
, hwaddr addr
)
438 /* Map a PPU unimplemented device stub */
439 DeviceState
*dev
= DEVICE(&s
->ppu
[ppuidx
]);
441 qdev_prop_set_string(dev
, "name", name
);
442 qdev_prop_set_uint64(dev
, "size", 0x1000);
443 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
444 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ppu
[ppuidx
]), 0, addr
);
447 static void armsse_realize(DeviceState
*dev
, Error
**errp
)
449 ARMSSE
*s
= ARM_SSE(dev
);
450 ARMSSEClass
*asc
= ARM_SSE_GET_CLASS(dev
);
451 const ARMSSEInfo
*info
= asc
->info
;
455 SysBusDevice
*sbd_apb_ppc0
;
456 SysBusDevice
*sbd_secctl
;
457 DeviceState
*dev_apb_ppc0
;
458 DeviceState
*dev_apb_ppc1
;
459 DeviceState
*dev_secctl
;
460 DeviceState
*dev_splitter
;
461 uint32_t addr_width_max
;
463 if (!s
->board_memory
) {
464 error_setg(errp
, "memory property was not set");
468 if (!clock_has_source(s
->mainclk
)) {
469 error_setg(errp
, "MAINCLK clock was not connected");
471 if (!clock_has_source(s
->s32kclk
)) {
472 error_setg(errp
, "S32KCLK clock was not connected");
475 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
477 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
478 assert(is_power_of_2(info
->sram_banks
));
479 addr_width_max
= 24 - ctz32(info
->sram_banks
);
480 if (s
->sram_addr_width
< 1 || s
->sram_addr_width
> addr_width_max
) {
481 error_setg(errp
, "SRAM_ADDR_WIDTH must be between 1 and %d",
486 /* Handling of which devices should be available only to secure
487 * code is usually done differently for M profile than for A profile.
488 * Instead of putting some devices only into the secure address space,
489 * devices exist in both address spaces but with hard-wired security
490 * permissions that will cause the CPU to fault for non-secure accesses.
492 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
493 * which specifies hard-wired security permissions for different
494 * areas of the physical address space. For the ARMSSE IDAU, the
495 * top 4 bits of the physical address are the IDAU region ID, and
496 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
497 * region, otherwise it is an S region.
499 * The various devices and RAMs are generally all mapped twice,
500 * once into a region that the IDAU defines as secure and once
501 * into a non-secure region. They sit behind either a Memory
502 * Protection Controller (for RAM) or a Peripheral Protection
503 * Controller (for devices), which allow a more fine grained
504 * configuration of whether non-secure accesses are permitted.
506 * (The other place that guest software can configure security
507 * permissions is in the architected SAU (Security Attribution
508 * Unit), which is entirely inside the CPU. The IDAU can upgrade
509 * the security attributes for a region to more restrictive than
510 * the SAU specifies, but cannot downgrade them.)
512 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
513 * 0x20000000..0x2007ffff 32KB FPGA block RAM
514 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
515 * 0x40000000..0x4000ffff base peripheral region 1
516 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
517 * 0x40020000..0x4002ffff system control element peripherals
518 * 0x40080000..0x400fffff base peripheral region 2
519 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
522 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -2);
524 for (i
= 0; i
< info
->num_cpus
; i
++) {
525 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[i
]);
526 Object
*cpuobj
= OBJECT(&s
->armv7m
[i
]);
530 qdev_prop_set_uint32(cpudev
, "num-irq", s
->exp_numirq
+ 32);
532 * In real hardware the initial Secure VTOR is set from the INITSVTOR*
533 * registers in the IoT Kit System Control Register block. In QEMU
534 * we set the initial value here, and also the reset value of the
535 * sysctl register, from this object's QOM init-svtor property.
536 * If the guest changes the INITSVTOR* registers at runtime then the
537 * code in iotkit-sysctl.c will update the CPU init-svtor property
538 * (which will then take effect on the next CPU warm-reset).
540 * Note that typically a board using the SSE-200 will have a system
541 * control processor whose boot firmware initializes the INITSVTOR*
542 * registers before powering up the CPUs. QEMU doesn't emulate
543 * the control processor, so instead we behave in the way that the
544 * firmware does: the initial value should be set by the board code
545 * (using the init-svtor property on the ARMSSE object) to match
546 * whatever its firmware does.
548 qdev_prop_set_uint32(cpudev
, "init-svtor", s
->init_svtor
);
550 * CPUs start powered down if the corresponding bit in the CPUWAIT
551 * register is 1. In real hardware the CPUWAIT register reset value is
552 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
553 * CPUWAIT1_RST parameters), but since all the boards we care about
554 * start CPU0 and leave CPU1 powered off, we hard-code that in
555 * info->cpuwait_rst for now. We can add QOM properties for this
556 * later if necessary.
558 if (extract32(info
->cpuwait_rst
, i
, 1)) {
559 if (!object_property_set_bool(cpuobj
, "start-powered-off", true,
564 if (!s
->cpu_fpu
[i
]) {
565 if (!object_property_set_bool(cpuobj
, "vfp", false, errp
)) {
569 if (!s
->cpu_dsp
[i
]) {
570 if (!object_property_set_bool(cpuobj
, "dsp", false, errp
)) {
576 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
577 &s
->container_alias
[i
- 1], -1);
579 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
582 object_property_set_link(cpuobj
, "memory",
583 OBJECT(&s
->cpu_container
[i
]), &error_abort
);
584 object_property_set_link(cpuobj
, "idau", OBJECT(s
), &error_abort
);
585 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj
), errp
)) {
589 * The cluster must be realized after the armv7m container, as
590 * the container's CPU object is only created on realize, and the
591 * CPU must exist and have been parented into the cluster before
592 * the cluster is realized.
594 if (!qdev_realize(DEVICE(&s
->cluster
[i
]), NULL
, errp
)) {
598 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
599 s
->exp_irqs
[i
] = g_new(qemu_irq
, s
->exp_numirq
);
600 for (j
= 0; j
< s
->exp_numirq
; j
++) {
601 s
->exp_irqs
[i
][j
] = qdev_get_gpio_in(cpudev
, j
+ 32);
604 gpioname
= g_strdup("EXP_IRQ");
606 gpioname
= g_strdup_printf("EXP_CPU%d_IRQ", i
);
608 qdev_init_gpio_in_named_with_opaque(dev
, armsse_exp_irq
,
610 gpioname
, s
->exp_numirq
);
614 /* Wire up the splitters that connect common IRQs to all CPUs */
615 if (info
->num_cpus
> 1) {
616 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
617 if (irq_is_common
[i
]) {
618 Object
*splitter
= OBJECT(&s
->cpu_irq_splitter
[i
]);
619 DeviceState
*devs
= DEVICE(splitter
);
622 if (!object_property_set_int(splitter
, "num-lines",
623 info
->num_cpus
, errp
)) {
626 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
629 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
630 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
632 qdev_connect_gpio_out(devs
, cpunum
,
633 qdev_get_gpio_in(cpudev
, i
));
639 /* Set up the big aliases first */
640 make_alias(s
, &s
->alias1
, &s
->container
, "alias 1",
641 0x10000000, 0x10000000, 0x00000000);
642 make_alias(s
, &s
->alias2
, &s
->container
,
643 "alias 2", 0x30000000, 0x10000000, 0x20000000);
644 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
645 * a few extra devices that only appear there (generally the
646 * control interfaces for the protection controllers).
647 * We implement this by mapping those devices over the top of this
648 * alias MR at a higher priority. Some of the devices in this range
649 * are per-CPU, so we must put this alias in the per-cpu containers.
651 for (i
= 0; i
< info
->num_cpus
; i
++) {
652 make_alias(s
, &s
->alias3
[i
], &s
->cpu_container
[i
],
653 "alias 3", 0x50000000, 0x10000000, 0x40000000);
656 /* Security controller */
657 object_property_set_int(OBJECT(&s
->secctl
), "sse-version",
658 info
->sse_version
, &error_abort
);
659 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->secctl
), errp
)) {
662 sbd_secctl
= SYS_BUS_DEVICE(&s
->secctl
);
663 dev_secctl
= DEVICE(&s
->secctl
);
664 sysbus_mmio_map(sbd_secctl
, 0, 0x50080000);
665 sysbus_mmio_map(sbd_secctl
, 1, 0x40080000);
667 s
->nsc_cfg_in
= qemu_allocate_irq(nsccfg_handler
, s
, 1);
668 qdev_connect_gpio_out_named(dev_secctl
, "nsc_cfg", 0, s
->nsc_cfg_in
);
670 /* The sec_resp_cfg output from the security controller must be split into
671 * multiple lines, one for each of the PPCs within the ARMSSE and one
672 * that will be an output from the ARMSSE to the system.
674 if (!object_property_set_int(OBJECT(&s
->sec_resp_splitter
),
675 "num-lines", 3, errp
)) {
678 if (!qdev_realize(DEVICE(&s
->sec_resp_splitter
), NULL
, errp
)) {
681 dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
682 qdev_connect_gpio_out_named(dev_secctl
, "sec_resp_cfg", 0,
683 qdev_get_gpio_in(dev_splitter
, 0));
685 /* Each SRAM bank lives behind its own Memory Protection Controller */
686 for (i
= 0; i
< info
->sram_banks
; i
++) {
687 char *ramname
= g_strdup_printf("armsse.sram%d", i
);
688 SysBusDevice
*sbd_mpc
;
689 uint32_t sram_bank_size
= 1 << s
->sram_addr_width
;
691 memory_region_init_ram(&s
->sram
[i
], NULL
, ramname
,
692 sram_bank_size
, &err
);
695 error_propagate(errp
, err
);
698 object_property_set_link(OBJECT(&s
->mpc
[i
]), "downstream",
699 OBJECT(&s
->sram
[i
]), &error_abort
);
700 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mpc
[i
]), errp
)) {
703 /* Map the upstream end of the MPC into the right place... */
704 sbd_mpc
= SYS_BUS_DEVICE(&s
->mpc
[i
]);
705 memory_region_add_subregion(&s
->container
,
706 0x20000000 + i
* sram_bank_size
,
707 sysbus_mmio_get_region(sbd_mpc
, 1));
708 /* ...and its register interface */
709 memory_region_add_subregion(&s
->container
, 0x50083000 + i
* 0x1000,
710 sysbus_mmio_get_region(sbd_mpc
, 0));
713 /* We must OR together lines from the MPC splitters to go to the NVIC */
714 if (!object_property_set_int(OBJECT(&s
->mpc_irq_orgate
), "num-lines",
715 IOTS_NUM_EXP_MPC
+ info
->sram_banks
,
719 if (!qdev_realize(DEVICE(&s
->mpc_irq_orgate
), NULL
, errp
)) {
722 qdev_connect_gpio_out(DEVICE(&s
->mpc_irq_orgate
), 0,
723 armsse_get_common_irq_in(s
, 9));
725 /* Devices behind APB PPC0:
728 * 0x40002000: dual timer
729 * 0x40003000: MHU0 (SSE-200 only)
730 * 0x40004000: MHU1 (SSE-200 only)
731 * We must configure and realize each downstream device and connect
732 * it to the appropriate PPC port; then we can realize the PPC and
733 * map its upstream ends to the right place in the container.
735 qdev_connect_clock_in(DEVICE(&s
->timer0
), "pclk", s
->mainclk
);
736 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer0
), errp
)) {
739 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer0
), 0,
740 armsse_get_common_irq_in(s
, 3));
741 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer0
), 0);
742 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[0]", OBJECT(mr
),
745 qdev_connect_clock_in(DEVICE(&s
->timer1
), "pclk", s
->mainclk
);
746 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer1
), errp
)) {
749 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer1
), 0,
750 armsse_get_common_irq_in(s
, 4));
751 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer1
), 0);
752 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[1]", OBJECT(mr
),
755 qdev_connect_clock_in(DEVICE(&s
->dualtimer
), "TIMCLK", s
->mainclk
);
756 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dualtimer
), errp
)) {
759 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dualtimer
), 0,
760 armsse_get_common_irq_in(s
, 5));
761 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->dualtimer
), 0);
762 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[2]", OBJECT(mr
),
765 if (info
->has_mhus
) {
767 * An SSE-200 with only one CPU should have only one MHU created,
768 * with the region where the second MHU usually is being RAZ/WI.
769 * We don't implement that SSE-200 config; if we want to support
770 * it then this code needs to be enhanced to handle creating the
771 * RAZ/WI region instead of the second MHU.
773 assert(info
->num_cpus
== ARRAY_SIZE(s
->mhu
));
775 for (i
= 0; i
< ARRAY_SIZE(s
->mhu
); i
++) {
778 SysBusDevice
*mhu_sbd
= SYS_BUS_DEVICE(&s
->mhu
[i
]);
780 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mhu
[i
]), errp
)) {
783 port
= g_strdup_printf("port[%d]", i
+ 3);
784 mr
= sysbus_mmio_get_region(mhu_sbd
, 0);
785 object_property_set_link(OBJECT(&s
->apb_ppc0
), port
, OBJECT(mr
),
790 * Each MHU has an irq line for each CPU:
791 * MHU 0 irq line 0 -> CPU 0 IRQ 6
792 * MHU 0 irq line 1 -> CPU 1 IRQ 6
793 * MHU 1 irq line 0 -> CPU 0 IRQ 7
794 * MHU 1 irq line 1 -> CPU 1 IRQ 7
796 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
797 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
799 sysbus_connect_irq(mhu_sbd
, cpunum
,
800 qdev_get_gpio_in(cpudev
, 6 + i
));
805 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc0
), errp
)) {
809 sbd_apb_ppc0
= SYS_BUS_DEVICE(&s
->apb_ppc0
);
810 dev_apb_ppc0
= DEVICE(&s
->apb_ppc0
);
812 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 0);
813 memory_region_add_subregion(&s
->container
, 0x40000000, mr
);
814 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 1);
815 memory_region_add_subregion(&s
->container
, 0x40001000, mr
);
816 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 2);
817 memory_region_add_subregion(&s
->container
, 0x40002000, mr
);
818 if (info
->has_mhus
) {
819 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 3);
820 memory_region_add_subregion(&s
->container
, 0x40003000, mr
);
821 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 4);
822 memory_region_add_subregion(&s
->container
, 0x40004000, mr
);
824 for (i
= 0; i
< IOTS_APB_PPC0_NUM_PORTS
; i
++) {
825 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_nonsec", i
,
826 qdev_get_gpio_in_named(dev_apb_ppc0
,
828 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_ap", i
,
829 qdev_get_gpio_in_named(dev_apb_ppc0
,
832 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_enable", 0,
833 qdev_get_gpio_in_named(dev_apb_ppc0
,
835 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_clear", 0,
836 qdev_get_gpio_in_named(dev_apb_ppc0
,
838 qdev_connect_gpio_out(dev_splitter
, 0,
839 qdev_get_gpio_in_named(dev_apb_ppc0
,
842 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
843 * ones) are sent individually to the security controller, and also
844 * ORed together to give a single combined PPC interrupt to the NVIC.
846 if (!object_property_set_int(OBJECT(&s
->ppc_irq_orgate
),
847 "num-lines", NUM_PPCS
, errp
)) {
850 if (!qdev_realize(DEVICE(&s
->ppc_irq_orgate
), NULL
, errp
)) {
853 qdev_connect_gpio_out(DEVICE(&s
->ppc_irq_orgate
), 0,
854 armsse_get_common_irq_in(s
, 10));
857 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
858 * private per-CPU region (all these devices are SSE-200 only):
859 * 0x50010000: L1 icache control registers
860 * 0x50011000: CPUSECCTRL (CPU local security control registers)
861 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
863 if (info
->has_cachectrl
) {
864 for (i
= 0; i
< info
->num_cpus
; i
++) {
865 char *name
= g_strdup_printf("cachectrl%d", i
);
868 qdev_prop_set_string(DEVICE(&s
->cachectrl
[i
]), "name", name
);
870 qdev_prop_set_uint64(DEVICE(&s
->cachectrl
[i
]), "size", 0x1000);
871 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), errp
)) {
875 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), 0);
876 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50010000, mr
);
879 if (info
->has_cpusecctrl
) {
880 for (i
= 0; i
< info
->num_cpus
; i
++) {
881 char *name
= g_strdup_printf("CPUSECCTRL%d", i
);
884 qdev_prop_set_string(DEVICE(&s
->cpusecctrl
[i
]), "name", name
);
886 qdev_prop_set_uint64(DEVICE(&s
->cpusecctrl
[i
]), "size", 0x1000);
887 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), errp
)) {
891 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), 0);
892 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50011000, mr
);
895 if (info
->has_cpuid
) {
896 for (i
= 0; i
< info
->num_cpus
; i
++) {
899 qdev_prop_set_uint32(DEVICE(&s
->cpuid
[i
]), "CPUID", i
);
900 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cpuid
[i
]), errp
)) {
904 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpuid
[i
]), 0);
905 memory_region_add_subregion(&s
->cpu_container
[i
], 0x4001F000, mr
);
909 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
910 /* Devices behind APB PPC1:
911 * 0x4002f000: S32K timer
913 qdev_connect_clock_in(DEVICE(&s
->s32ktimer
), "pclk", s
->s32kclk
);
914 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->s32ktimer
), errp
)) {
917 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32ktimer
), 0,
918 armsse_get_common_irq_in(s
, 2));
919 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->s32ktimer
), 0);
920 object_property_set_link(OBJECT(&s
->apb_ppc1
), "port[0]", OBJECT(mr
),
923 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc1
), errp
)) {
926 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->apb_ppc1
), 0);
927 memory_region_add_subregion(&s
->container
, 0x4002f000, mr
);
929 dev_apb_ppc1
= DEVICE(&s
->apb_ppc1
);
930 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_nonsec", 0,
931 qdev_get_gpio_in_named(dev_apb_ppc1
,
933 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_ap", 0,
934 qdev_get_gpio_in_named(dev_apb_ppc1
,
936 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_enable", 0,
937 qdev_get_gpio_in_named(dev_apb_ppc1
,
939 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_clear", 0,
940 qdev_get_gpio_in_named(dev_apb_ppc1
,
942 qdev_connect_gpio_out(dev_splitter
, 1,
943 qdev_get_gpio_in_named(dev_apb_ppc1
,
946 if (!object_property_set_int(OBJECT(&s
->sysinfo
), "SYS_VERSION",
947 info
->sys_version
, errp
)) {
950 if (!object_property_set_int(OBJECT(&s
->sysinfo
), "SYS_CONFIG",
951 armsse_sys_config_value(s
, info
), errp
)) {
954 object_property_set_int(OBJECT(&s
->sysinfo
), "sse-version",
955 info
->sse_version
, &error_abort
);
956 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sysinfo
), errp
)) {
959 /* System information registers */
960 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysinfo
), 0, 0x40020000);
961 /* System control registers */
962 object_property_set_int(OBJECT(&s
->sysctl
), "sse-version",
963 info
->sse_version
, &error_abort
);
964 object_property_set_int(OBJECT(&s
->sysctl
), "CPUWAIT_RST",
965 info
->cpuwait_rst
, &error_abort
);
966 object_property_set_int(OBJECT(&s
->sysctl
), "INITSVTOR0_RST",
967 s
->init_svtor
, &error_abort
);
968 object_property_set_int(OBJECT(&s
->sysctl
), "INITSVTOR1_RST",
969 s
->init_svtor
, &error_abort
);
970 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sysctl
), errp
)) {
973 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysctl
), 0, 0x50021000);
975 if (info
->has_ppus
) {
976 /* CPUnCORE_PPU for each CPU */
977 for (i
= 0; i
< info
->num_cpus
; i
++) {
978 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
980 map_ppu(s
, CPU0CORE_PPU
+ i
, name
, 0x50023000 + i
* 0x2000);
982 * We don't support CPU debug so don't create the
983 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000.
987 map_ppu(s
, DBG_PPU
, "DBG_PPU", 0x50029000);
989 for (i
= 0; i
< info
->sram_banks
; i
++) {
990 char *name
= g_strdup_printf("RAM%d_PPU", i
);
992 map_ppu(s
, RAM0_PPU
+ i
, name
, 0x5002a000 + i
* 0x1000);
997 /* This OR gate wires together outputs from the secure watchdogs to NMI */
998 if (!object_property_set_int(OBJECT(&s
->nmi_orgate
), "num-lines", 2,
1002 if (!qdev_realize(DEVICE(&s
->nmi_orgate
), NULL
, errp
)) {
1005 qdev_connect_gpio_out(DEVICE(&s
->nmi_orgate
), 0,
1006 qdev_get_gpio_in_named(DEVICE(&s
->armv7m
), "NMI", 0));
1008 qdev_connect_clock_in(DEVICE(&s
->s32kwatchdog
), "WDOGCLK", s
->s32kclk
);
1009 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->s32kwatchdog
), errp
)) {
1012 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0,
1013 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 0));
1014 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0, 0x5002e000);
1016 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
1018 qdev_connect_clock_in(DEVICE(&s
->nswatchdog
), "WDOGCLK", s
->mainclk
);
1019 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->nswatchdog
), errp
)) {
1022 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->nswatchdog
), 0,
1023 armsse_get_common_irq_in(s
, 1));
1024 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->nswatchdog
), 0, 0x40081000);
1026 qdev_connect_clock_in(DEVICE(&s
->swatchdog
), "WDOGCLK", s
->mainclk
);
1027 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->swatchdog
), errp
)) {
1030 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->swatchdog
), 0,
1031 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 1));
1032 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->swatchdog
), 0, 0x50081000);
1034 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
1035 Object
*splitter
= OBJECT(&s
->ppc_irq_splitter
[i
]);
1037 if (!object_property_set_int(splitter
, "num-lines", 2, errp
)) {
1040 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
1045 for (i
= 0; i
< IOTS_NUM_AHB_EXP_PPC
; i
++) {
1046 char *ppcname
= g_strdup_printf("ahb_ppcexp%d", i
);
1048 armsse_forward_ppc(s
, ppcname
, i
);
1052 for (i
= 0; i
< IOTS_NUM_APB_EXP_PPC
; i
++) {
1053 char *ppcname
= g_strdup_printf("apb_ppcexp%d", i
);
1055 armsse_forward_ppc(s
, ppcname
, i
+ IOTS_NUM_AHB_EXP_PPC
);
1059 for (i
= NUM_EXTERNAL_PPCS
; i
< NUM_PPCS
; i
++) {
1060 /* Wire up IRQ splitter for internal PPCs */
1061 DeviceState
*devs
= DEVICE(&s
->ppc_irq_splitter
[i
]);
1062 char *gpioname
= g_strdup_printf("apb_ppc%d_irq_status",
1063 i
- NUM_EXTERNAL_PPCS
);
1064 TZPPC
*ppc
= (i
== NUM_EXTERNAL_PPCS
) ? &s
->apb_ppc0
: &s
->apb_ppc1
;
1066 qdev_connect_gpio_out(devs
, 0,
1067 qdev_get_gpio_in_named(dev_secctl
, gpioname
, 0));
1068 qdev_connect_gpio_out(devs
, 1,
1069 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), i
));
1070 qdev_connect_gpio_out_named(DEVICE(ppc
), "irq", 0,
1071 qdev_get_gpio_in(devs
, 0));
1075 /* Wire up the splitters for the MPC IRQs */
1076 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
1077 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
1078 DeviceState
*dev_splitter
= DEVICE(splitter
);
1080 if (!object_property_set_int(OBJECT(splitter
), "num-lines", 2,
1084 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
1088 if (i
< IOTS_NUM_EXP_MPC
) {
1089 /* Splitter input is from GPIO input line */
1090 s
->mpcexp_status_in
[i
] = qdev_get_gpio_in(dev_splitter
, 0);
1091 qdev_connect_gpio_out(dev_splitter
, 0,
1092 qdev_get_gpio_in_named(dev_secctl
,
1093 "mpcexp_status", i
));
1095 /* Splitter input is from our own MPC */
1096 qdev_connect_gpio_out_named(DEVICE(&s
->mpc
[i
- IOTS_NUM_EXP_MPC
]),
1098 qdev_get_gpio_in(dev_splitter
, 0));
1099 qdev_connect_gpio_out(dev_splitter
, 0,
1100 qdev_get_gpio_in_named(dev_secctl
,
1102 i
- IOTS_NUM_EXP_MPC
));
1105 qdev_connect_gpio_out(dev_splitter
, 1,
1106 qdev_get_gpio_in(DEVICE(&s
->mpc_irq_orgate
), i
));
1108 /* Create GPIO inputs which will pass the line state for our
1109 * mpcexp_irq inputs to the correct splitter devices.
1111 qdev_init_gpio_in_named(dev
, armsse_mpcexp_status
, "mpcexp_status",
1114 armsse_forward_sec_resp_cfg(s
);
1116 /* Forward the MSC related signals */
1117 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_status");
1118 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_clear");
1119 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_ns");
1120 qdev_connect_gpio_out_named(dev_secctl
, "msc_irq", 0,
1121 armsse_get_common_irq_in(s
, 11));
1124 * Expose our container region to the board model; this corresponds
1125 * to the AHB Slave Expansion ports which allow bus master devices
1126 * (eg DMA controllers) in the board model to make transactions into
1127 * devices in the ARMSSE.
1129 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->container
);
1131 /* Set initial system_clock_scale from MAINCLK */
1132 armsse_mainclk_update(s
, ClockUpdate
);
1135 static void armsse_idau_check(IDAUInterface
*ii
, uint32_t address
,
1136 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1139 * For ARMSSE systems the IDAU responses are simple logical functions
1140 * of the address bits. The NSC attribute is guest-adjustable via the
1141 * NSCCFG register in the security controller.
1143 ARMSSE
*s
= ARM_SSE(ii
);
1144 int region
= extract32(address
, 28, 4);
1146 *ns
= !(region
& 1);
1147 *nsc
= (region
== 1 && (s
->nsccfg
& 1)) || (region
== 3 && (s
->nsccfg
& 2));
1148 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1149 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1153 static const VMStateDescription armsse_vmstate
= {
1156 .minimum_version_id
= 2,
1157 .fields
= (VMStateField
[]) {
1158 VMSTATE_CLOCK(mainclk
, ARMSSE
),
1159 VMSTATE_CLOCK(s32kclk
, ARMSSE
),
1160 VMSTATE_UINT32(nsccfg
, ARMSSE
),
1161 VMSTATE_END_OF_LIST()
1165 static void armsse_reset(DeviceState
*dev
)
1167 ARMSSE
*s
= ARM_SSE(dev
);
1172 static void armsse_class_init(ObjectClass
*klass
, void *data
)
1174 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1175 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(klass
);
1176 ARMSSEClass
*asc
= ARM_SSE_CLASS(klass
);
1177 const ARMSSEInfo
*info
= data
;
1179 dc
->realize
= armsse_realize
;
1180 dc
->vmsd
= &armsse_vmstate
;
1181 device_class_set_props(dc
, info
->props
);
1182 dc
->reset
= armsse_reset
;
1183 iic
->check
= armsse_idau_check
;
1187 static const TypeInfo armsse_info
= {
1188 .name
= TYPE_ARM_SSE
,
1189 .parent
= TYPE_SYS_BUS_DEVICE
,
1190 .instance_size
= sizeof(ARMSSE
),
1191 .class_size
= sizeof(ARMSSEClass
),
1192 .instance_init
= armsse_init
,
1194 .interfaces
= (InterfaceInfo
[]) {
1195 { TYPE_IDAU_INTERFACE
},
1200 static void armsse_register_types(void)
1204 type_register_static(&armsse_info
);
1206 for (i
= 0; i
< ARRAY_SIZE(armsse_variants
); i
++) {
1208 .name
= armsse_variants
[i
].name
,
1209 .parent
= TYPE_ARM_SSE
,
1210 .class_init
= armsse_class_init
,
1211 .class_data
= (void *)&armsse_variants
[i
],
1217 type_init(armsse_register_types
);