exec/memory_ldst_cached: Use correct type size
[qemu/ar7.git] / tcg / ppc / tcg-target-con-set.h
bloba1a345883d88d76b7c8b5cf7ee8d494f774b8b18
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define PowerPC target-specific constraint sets.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
9 * Each operand should be a sequence of constraint letters as defined by
10 * tcg-target-con-str.h; the constraint combination is inclusive or.
12 C_O0_I1(r)
13 C_O0_I2(r, r)
14 C_O0_I2(r, ri)
15 C_O0_I2(S, S)
16 C_O0_I2(v, r)
17 C_O0_I3(S, S, S)
18 C_O0_I4(r, r, ri, ri)
19 C_O0_I4(S, S, S, S)
20 C_O1_I1(r, L)
21 C_O1_I1(r, r)
22 C_O1_I1(v, r)
23 C_O1_I1(v, v)
24 C_O1_I1(v, vr)
25 C_O1_I2(r, 0, rZ)
26 C_O1_I2(r, L, L)
27 C_O1_I2(r, rI, ri)
28 C_O1_I2(r, rI, rT)
29 C_O1_I2(r, r, r)
30 C_O1_I2(r, r, ri)
31 C_O1_I2(r, r, rI)
32 C_O1_I2(r, r, rT)
33 C_O1_I2(r, r, rU)
34 C_O1_I2(r, r, rZW)
35 C_O1_I2(v, v, v)
36 C_O1_I3(v, v, v, v)
37 C_O1_I4(r, r, ri, rZ, rZ)
38 C_O1_I4(r, r, r, ri, ri)
39 C_O2_I1(L, L, L)
40 C_O2_I2(L, L, L, L)
41 C_O2_I4(r, r, rI, rZM, r, r)
42 C_O2_I4(r, r, r, r, rI, rZM)