tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35 #include "qemu/int128.h"
  36
  37 /* XXX: make safe guess about sizes */
  38 #define MAX_OP_PER_INSTR 266
  39
  40 #if HOST_LONG_BITS == 32
  41 #define MAX_OPC_PARAM_PER_ARG 2
  42 #else
  43 #define MAX_OPC_PARAM_PER_ARG 1
  44 #endif
  45 #define MAX_OPC_PARAM_IARGS 6
  46 #define MAX_OPC_PARAM_OARGS 1
  47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  48
  49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50  * and up to 4 + N parameters on 64-bit archs
  51  * (N = number of input arguments + output arguments).  */
  52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53
  54 #define CPU_TEMP_BUF_NLONGS 128
  55
  56 /* Default target word size to pointer size.  */
  57 #ifndef TCG_TARGET_REG_BITS
  58 # if UINTPTR_MAX == UINT32_MAX
  59 #  define TCG_TARGET_REG_BITS 32
  60 # elif UINTPTR_MAX == UINT64_MAX
  61 #  define TCG_TARGET_REG_BITS 64
  62 # else
  63 #  error Unknown pointer size for tcg target
  64 # endif
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 typedef int32_t tcg_target_long;
  69 typedef uint32_t tcg_target_ulong;
  70 #define TCG_PRIlx PRIx32
  71 #define TCG_PRIld PRId32
  72 #elif TCG_TARGET_REG_BITS == 64
  73 typedef int64_t tcg_target_long;
  74 typedef uint64_t tcg_target_ulong;
  75 #define TCG_PRIlx PRIx64
  76 #define TCG_PRIld PRId64
  77 #else
  78 #error unsupported
  79 #endif
  80
  81 /* Oversized TCG guests make things like MTTCG hard
  82  * as we can't use atomics for cputlb updates.
  83  */
  84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  85 #define TCG_OVERSIZED_GUEST 1
  86 #else
  87 #define TCG_OVERSIZED_GUEST 0
  88 #endif
  89
  90 #if TCG_TARGET_NB_REGS <= 32
  91 typedef uint32_t TCGRegSet;
  92 #elif TCG_TARGET_NB_REGS <= 64
  93 typedef uint64_t TCGRegSet;
  94 #else
  95 #error unsupported
  96 #endif
  97
  98 #if TCG_TARGET_REG_BITS == 32
  99 /* Turn some undef macros into false macros.  */
 100 #define TCG_TARGET_HAS_extrl_i64_i32    0
 101 #define TCG_TARGET_HAS_extrh_i64_i32    0
 102 #define TCG_TARGET_HAS_div_i64          0
 103 #define TCG_TARGET_HAS_rem_i64          0
 104 #define TCG_TARGET_HAS_div2_i64         0
 105 #define TCG_TARGET_HAS_rot_i64          0
 106 #define TCG_TARGET_HAS_ext8s_i64        0
 107 #define TCG_TARGET_HAS_ext16s_i64       0
 108 #define TCG_TARGET_HAS_ext32s_i64       0
 109 #define TCG_TARGET_HAS_ext8u_i64        0
 110 #define TCG_TARGET_HAS_ext16u_i64       0
 111 #define TCG_TARGET_HAS_ext32u_i64       0
 112 #define TCG_TARGET_HAS_bswap16_i64      0
 113 #define TCG_TARGET_HAS_bswap32_i64      0
 114 #define TCG_TARGET_HAS_bswap64_i64      0
 115 #define TCG_TARGET_HAS_neg_i64          0
 116 #define TCG_TARGET_HAS_not_i64          0
 117 #define TCG_TARGET_HAS_andc_i64         0
 118 #define TCG_TARGET_HAS_orc_i64          0
 119 #define TCG_TARGET_HAS_eqv_i64          0
 120 #define TCG_TARGET_HAS_nand_i64         0
 121 #define TCG_TARGET_HAS_nor_i64          0
 122 #define TCG_TARGET_HAS_clz_i64          0
 123 #define TCG_TARGET_HAS_ctz_i64          0
 124 #define TCG_TARGET_HAS_ctpop_i64        0
 125 #define TCG_TARGET_HAS_deposit_i64      0
 126 #define TCG_TARGET_HAS_extract_i64      0
 127 #define TCG_TARGET_HAS_sextract_i64     0
 128 #define TCG_TARGET_HAS_extract2_i64     0
 129 #define TCG_TARGET_HAS_movcond_i64      0
 130 #define TCG_TARGET_HAS_add2_i64         0
 131 #define TCG_TARGET_HAS_sub2_i64         0
 132 #define TCG_TARGET_HAS_mulu2_i64        0
 133 #define TCG_TARGET_HAS_muls2_i64        0
 134 #define TCG_TARGET_HAS_muluh_i64        0
 135 #define TCG_TARGET_HAS_mulsh_i64        0
 136 /* Turn some undef macros into true macros.  */
 137 #define TCG_TARGET_HAS_add2_i32         1
 138 #define TCG_TARGET_HAS_sub2_i32         1
 139 #endif
 140
 141 #ifndef TCG_TARGET_deposit_i32_valid
 142 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 143 #endif
 144 #ifndef TCG_TARGET_deposit_i64_valid
 145 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 146 #endif
 147 #ifndef TCG_TARGET_extract_i32_valid
 148 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 149 #endif
 150 #ifndef TCG_TARGET_extract_i64_valid
 151 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 152 #endif
 153
 154 /* Only one of DIV or DIV2 should be defined.  */
 155 #if defined(TCG_TARGET_HAS_div_i32)
 156 #define TCG_TARGET_HAS_div2_i32         0
 157 #elif defined(TCG_TARGET_HAS_div2_i32)
 158 #define TCG_TARGET_HAS_div_i32          0
 159 #define TCG_TARGET_HAS_rem_i32          0
 160 #endif
 161 #if defined(TCG_TARGET_HAS_div_i64)
 162 #define TCG_TARGET_HAS_div2_i64         0
 163 #elif defined(TCG_TARGET_HAS_div2_i64)
 164 #define TCG_TARGET_HAS_div_i64          0
 165 #define TCG_TARGET_HAS_rem_i64          0
 166 #endif
 167
 168 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 169 #if TCG_TARGET_REG_BITS == 32 \
 170     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 171          || defined(TCG_TARGET_HAS_muluh_i32))
 172 # error "Missing unsigned widening multiply"
 173 #endif
 174
 175 #if !defined(TCG_TARGET_HAS_v64) \
 176     && !defined(TCG_TARGET_HAS_v128) \
 177     && !defined(TCG_TARGET_HAS_v256)
 178 #define TCG_TARGET_MAYBE_vec            0
 179 #define TCG_TARGET_HAS_abs_vec          0
 180 #define TCG_TARGET_HAS_neg_vec          0
 181 #define TCG_TARGET_HAS_not_vec          0
 182 #define TCG_TARGET_HAS_andc_vec         0
 183 #define TCG_TARGET_HAS_orc_vec          0
 184 #define TCG_TARGET_HAS_shi_vec          0
 185 #define TCG_TARGET_HAS_shs_vec          0
 186 #define TCG_TARGET_HAS_shv_vec          0
 187 #define TCG_TARGET_HAS_mul_vec          0
 188 #define TCG_TARGET_HAS_sat_vec          0
 189 #define TCG_TARGET_HAS_minmax_vec       0
 190 #define TCG_TARGET_HAS_bitsel_vec       0
 191 #define TCG_TARGET_HAS_cmpsel_vec       0
 192 #else
 193 #define TCG_TARGET_MAYBE_vec            1
 194 #endif
 195 #ifndef TCG_TARGET_HAS_v64
 196 #define TCG_TARGET_HAS_v64              0
 197 #endif
 198 #ifndef TCG_TARGET_HAS_v128
 199 #define TCG_TARGET_HAS_v128             0
 200 #endif
 201 #ifndef TCG_TARGET_HAS_v256
 202 #define TCG_TARGET_HAS_v256             0
 203 #endif
 204
 205 #ifndef TARGET_INSN_START_EXTRA_WORDS
 206 # define TARGET_INSN_START_WORDS 1
 207 #else
 208 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 209 #endif
 210
 211 typedef enum TCGOpcode {
 212 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 213 #include "tcg-opc.h"
 214 #undef DEF
 215     NB_OPS,
 216 } TCGOpcode;
 217
 218 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 219 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 220 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 221
 222 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 223 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 225 typedef uint8_t tcg_insn_unit;
 226 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 227 typedef uint16_t tcg_insn_unit;
 228 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 229 typedef uint32_t tcg_insn_unit;
 230 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 231 typedef uint64_t tcg_insn_unit;
 232 #else
 233 /* The port better have done this.  */
 234 #endif
 235
 236
 237 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 238 # define tcg_debug_assert(X) do { assert(X); } while (0)
 239 #else
 240 # define tcg_debug_assert(X) \
 241     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 242 #endif
 243
 244 typedef struct TCGRelocation TCGRelocation;
 245 struct TCGRelocation {
 246     QSIMPLEQ_ENTRY(TCGRelocation) next;
 247     tcg_insn_unit *ptr;
 248     intptr_t addend;
 249     int type;
 250 };
 251
 252 typedef struct TCGLabel TCGLabel;
 253 struct TCGLabel {
 254     unsigned present : 1;
 255     unsigned has_value : 1;
 256     unsigned id : 14;
 257     unsigned refs : 16;
 258     union {
 259         uintptr_t value;
 260         tcg_insn_unit *value_ptr;
 261     } u;
 262     QSIMPLEQ_HEAD(, TCGRelocation) relocs;
 263     QSIMPLEQ_ENTRY(TCGLabel) next;
 264 };
 265
 266 typedef struct TCGPool {
 267     struct TCGPool *next;
 268     int size;
 269     uint8_t data[0] __attribute__ ((aligned));
 270 } TCGPool;
 271
 272 #define TCG_POOL_CHUNK_SIZE 32768
 273
 274 #define TCG_MAX_TEMPS 512
 275 #define TCG_MAX_INSNS 512
 276
 277 /* when the size of the arguments of a called function is smaller than
 278    this value, they are statically allocated in the TB stack frame */
 279 #define TCG_STATIC_CALL_ARGS_SIZE 128
 280
 281 typedef enum TCGType {
 282     TCG_TYPE_I32,
 283     TCG_TYPE_I64,
 284
 285     TCG_TYPE_V64,
 286     TCG_TYPE_V128,
 287     TCG_TYPE_V256,
 288
 289     TCG_TYPE_COUNT, /* number of different types */
 290
 291     /* An alias for the size of the host register.  */
 292 #if TCG_TARGET_REG_BITS == 32
 293     TCG_TYPE_REG = TCG_TYPE_I32,
 294 #else
 295     TCG_TYPE_REG = TCG_TYPE_I64,
 296 #endif
 297
 298     /* An alias for the size of the native pointer.  */
 299 #if UINTPTR_MAX == UINT32_MAX
 300     TCG_TYPE_PTR = TCG_TYPE_I32,
 301 #else
 302     TCG_TYPE_PTR = TCG_TYPE_I64,
 303 #endif
 304
 305     /* An alias for the size of the target "long", aka register.  */
 306 #if TARGET_LONG_BITS == 64
 307     TCG_TYPE_TL = TCG_TYPE_I64,
 308 #else
 309     TCG_TYPE_TL = TCG_TYPE_I32,
 310 #endif
 311 } TCGType;
 312
 313 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 314 typedef enum TCGMemOp {
 315     MO_8     = 0,
 316     MO_16    = 1,
 317     MO_32    = 2,
 318     MO_64    = 3,
 319     MO_SIZE  = 3,   /* Mask for the above.  */
 320
 321     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 322
 323     MO_BSWAP = 8,   /* Host reverse endian.  */
 324 #ifdef HOST_WORDS_BIGENDIAN
 325     MO_LE    = MO_BSWAP,
 326     MO_BE    = 0,
 327 #else
 328     MO_LE    = 0,
 329     MO_BE    = MO_BSWAP,
 330 #endif
 331 #ifdef TARGET_WORDS_BIGENDIAN
 332     MO_TE    = MO_BE,
 333 #else
 334     MO_TE    = MO_LE,
 335 #endif
 336
 337     /* MO_UNALN accesses are never checked for alignment.
 338      * MO_ALIGN accesses will result in a call to the CPU's
 339      * do_unaligned_access hook if the guest address is not aligned.
 340      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 341      *
 342      * Some architectures (e.g. ARMv8) need the address which is aligned
 343      * to a size more than the size of the memory access.
 344      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 345      * but less strictly than the natural alignment.
 346      *
 347      * MO_ALIGN supposes the alignment size is the size of a memory access.
 348      *
 349      * There are three options:
 350      * - unaligned access permitted (MO_UNALN).
 351      * - an alignment to the size of an access (MO_ALIGN);
 352      * - an alignment to a specified size, which may be more or less than
 353      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 354      */
 355     MO_ASHIFT = 4,
 356     MO_AMASK = 7 << MO_ASHIFT,
 357 #ifdef ALIGNED_ONLY
 358     MO_ALIGN = 0,
 359     MO_UNALN = MO_AMASK,
 360 #else
 361     MO_ALIGN = MO_AMASK,
 362     MO_UNALN = 0,
 363 #endif
 364     MO_ALIGN_2  = 1 << MO_ASHIFT,
 365     MO_ALIGN_4  = 2 << MO_ASHIFT,
 366     MO_ALIGN_8  = 3 << MO_ASHIFT,
 367     MO_ALIGN_16 = 4 << MO_ASHIFT,
 368     MO_ALIGN_32 = 5 << MO_ASHIFT,
 369     MO_ALIGN_64 = 6 << MO_ASHIFT,
 370
 371     /* Combinations of the above, for ease of use.  */
 372     MO_UB    = MO_8,
 373     MO_UW    = MO_16,
 374     MO_UL    = MO_32,
 375     MO_SB    = MO_SIGN | MO_8,
 376     MO_SW    = MO_SIGN | MO_16,
 377     MO_SL    = MO_SIGN | MO_32,
 378     MO_Q     = MO_64,
 379
 380     MO_LEUW  = MO_LE | MO_UW,
 381     MO_LEUL  = MO_LE | MO_UL,
 382     MO_LESW  = MO_LE | MO_SW,
 383     MO_LESL  = MO_LE | MO_SL,
 384     MO_LEQ   = MO_LE | MO_Q,
 385
 386     MO_BEUW  = MO_BE | MO_UW,
 387     MO_BEUL  = MO_BE | MO_UL,
 388     MO_BESW  = MO_BE | MO_SW,
 389     MO_BESL  = MO_BE | MO_SL,
 390     MO_BEQ   = MO_BE | MO_Q,
 391
 392     MO_TEUW  = MO_TE | MO_UW,
 393     MO_TEUL  = MO_TE | MO_UL,
 394     MO_TESW  = MO_TE | MO_SW,
 395     MO_TESL  = MO_TE | MO_SL,
 396     MO_TEQ   = MO_TE | MO_Q,
 397
 398     MO_SSIZE = MO_SIZE | MO_SIGN,
 399 } TCGMemOp;
 400
 401 /**
 402  * get_alignment_bits
 403  * @memop: TCGMemOp value
 404  *
 405  * Extract the alignment size from the memop.
 406  */
 407 static inline unsigned get_alignment_bits(TCGMemOp memop)
 408 {
 409     unsigned a = memop & MO_AMASK;
 410
 411     if (a == MO_UNALN) {
 412         /* No alignment required.  */
 413         a = 0;
 414     } else if (a == MO_ALIGN) {
 415         /* A natural alignment requirement.  */
 416         a = memop & MO_SIZE;
 417     } else {
 418         /* A specific alignment requirement.  */
 419         a = a >> MO_ASHIFT;
 420     }
 421 #if defined(CONFIG_SOFTMMU)
 422     /* The requested alignment cannot overlap the TLB flags.  */
 423     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 424 #endif
 425     return a;
 426 }
 427
 428 typedef tcg_target_ulong TCGArg;
 429
 430 /* Define type and accessor macros for TCG variables.
 431
 432    TCG variables are the inputs and outputs of TCG ops, as described
 433    in tcg/README. Target CPU front-end code uses these types to deal
 434    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 435    They come in several flavours:
 436     * TCGv_i32 : 32 bit integer type
 437     * TCGv_i64 : 64 bit integer type
 438     * TCGv_ptr : a host pointer type
 439     * TCGv_vec : a host vector type; the exact size is not exposed
 440                  to the CPU front-end code.
 441     * TCGv : an integer type the same size as target_ulong
 442              (an alias for either TCGv_i32 or TCGv_i64)
 443    The compiler's type checking will complain if you mix them
 444    up and pass the wrong sized TCGv to a function.
 445
 446    Users of tcg_gen_* don't need to know about any of the internal
 447    details of these, and should treat them as opaque types.
 448    You won't be able to look inside them in a debugger either.
 449
 450    Internal implementation details follow:
 451
 452    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 453    This is deliberate, because the values we store in variables of type
 454    TCGv_i32 are not really pointers-to-structures. They're just small
 455    integers, but keeping them in pointer types like this means that the
 456    compiler will complain if you accidentally pass a TCGv_i32 to a
 457    function which takes a TCGv_i64, and so on. Only the internals of
 458    TCG need to care about the actual contents of the types.  */
 459
 460 typedef struct TCGv_i32_d *TCGv_i32;
 461 typedef struct TCGv_i64_d *TCGv_i64;
 462 typedef struct TCGv_ptr_d *TCGv_ptr;
 463 typedef struct TCGv_vec_d *TCGv_vec;
 464 typedef TCGv_ptr TCGv_env;
 465 #if TARGET_LONG_BITS == 32
 466 #define TCGv TCGv_i32
 467 #elif TARGET_LONG_BITS == 64
 468 #define TCGv TCGv_i64
 469 #else
 470 #error Unhandled TARGET_LONG_BITS value
 471 #endif
 472
 473 /* call flags */
 474 /* Helper does not read globals (either directly or through an exception). It
 475    implies TCG_CALL_NO_WRITE_GLOBALS. */
 476 #define TCG_CALL_NO_READ_GLOBALS    0x0001
 477 /* Helper does not write globals */
 478 #define TCG_CALL_NO_WRITE_GLOBALS   0x0002
 479 /* Helper can be safely suppressed if the return value is not used. */
 480 #define TCG_CALL_NO_SIDE_EFFECTS    0x0004
 481 /* Helper is QEMU_NORETURN.  */
 482 #define TCG_CALL_NO_RETURN          0x0008
 483
 484 /* convenience version of most used call flags */
 485 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 486 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 487 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 488 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 489 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 490
 491 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 492 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 493
 494 /* Conditions.  Note that these are laid out for easy manipulation by
 495    the functions below:
 496      bit 0 is used for inverting;
 497      bit 1 is signed,
 498      bit 2 is unsigned,
 499      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 500 typedef enum {
 501     /* non-signed */
 502     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 503     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 504     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 505     TCG_COND_NE     = 8 | 0 | 0 | 1,
 506     /* signed */
 507     TCG_COND_LT     = 0 | 0 | 2 | 0,
 508     TCG_COND_GE     = 0 | 0 | 2 | 1,
 509     TCG_COND_LE     = 8 | 0 | 2 | 0,
 510     TCG_COND_GT     = 8 | 0 | 2 | 1,
 511     /* unsigned */
 512     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 513     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 514     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 515     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 516 } TCGCond;
 517
 518 /* Invert the sense of the comparison.  */
 519 static inline TCGCond tcg_invert_cond(TCGCond c)
 520 {
 521     return (TCGCond)(c ^ 1);
 522 }
 523
 524 /* Swap the operands in a comparison.  */
 525 static inline TCGCond tcg_swap_cond(TCGCond c)
 526 {
 527     return c & 6 ? (TCGCond)(c ^ 9) : c;
 528 }
 529
 530 /* Create an "unsigned" version of a "signed" comparison.  */
 531 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 532 {
 533     return c & 2 ? (TCGCond)(c ^ 6) : c;
 534 }
 535
 536 /* Create a "signed" version of an "unsigned" comparison.  */
 537 static inline TCGCond tcg_signed_cond(TCGCond c)
 538 {
 539     return c & 4 ? (TCGCond)(c ^ 6) : c;
 540 }
 541
 542 /* Must a comparison be considered unsigned?  */
 543 static inline bool is_unsigned_cond(TCGCond c)
 544 {
 545     return (c & 4) != 0;
 546 }
 547
 548 /* Create a "high" version of a double-word comparison.
 549    This removes equality from a LTE or GTE comparison.  */
 550 static inline TCGCond tcg_high_cond(TCGCond c)
 551 {
 552     switch (c) {
 553     case TCG_COND_GE:
 554     case TCG_COND_LE:
 555     case TCG_COND_GEU:
 556     case TCG_COND_LEU:
 557         return (TCGCond)(c ^ 8);
 558     default:
 559         return c;
 560     }
 561 }
 562
 563 typedef enum TCGTempVal {
 564     TEMP_VAL_DEAD,
 565     TEMP_VAL_REG,
 566     TEMP_VAL_MEM,
 567     TEMP_VAL_CONST,
 568 } TCGTempVal;
 569
 570 typedef struct TCGTemp {
 571     TCGReg reg:8;
 572     TCGTempVal val_type:8;
 573     TCGType base_type:8;
 574     TCGType type:8;
 575     unsigned int fixed_reg:1;
 576     unsigned int indirect_reg:1;
 577     unsigned int indirect_base:1;
 578     unsigned int mem_coherent:1;
 579     unsigned int mem_allocated:1;
 580     /* If true, the temp is saved across both basic blocks and
 581        translation blocks.  */
 582     unsigned int temp_global:1;
 583     /* If true, the temp is saved across basic blocks but dead
 584        at the end of translation blocks.  If false, the temp is
 585        dead at the end of basic blocks.  */
 586     unsigned int temp_local:1;
 587     unsigned int temp_allocated:1;
 588
 589     tcg_target_long val;
 590     struct TCGTemp *mem_base;
 591     intptr_t mem_offset;
 592     const char *name;
 593
 594     /* Pass-specific information that can be stored for a temporary.
 595        One word worth of integer data, and one pointer to data
 596        allocated separately.  */
 597     uintptr_t state;
 598     void *state_ptr;
 599 } TCGTemp;
 600
 601 typedef struct TCGContext TCGContext;
 602
 603 typedef struct TCGTempSet {
 604     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 605 } TCGTempSet;
 606
 607 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 608    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 609    There are never more than 2 outputs, which means that we can store all
 610    dead + sync data within 16 bits.  */
 611 #define DEAD_ARG  4
 612 #define SYNC_ARG  1
 613 typedef uint16_t TCGLifeData;
 614
 615 /* The layout here is designed to avoid a bitfield crossing of
 616    a 32-bit boundary, which would cause GCC to add extra padding.  */
 617 typedef struct TCGOp {
 618     TCGOpcode opc   : 8;        /*  8 */
 619
 620     /* Parameters for this opcode.  See below.  */
 621     unsigned param1 : 4;        /* 12 */
 622     unsigned param2 : 4;        /* 16 */
 623
 624     /* Lifetime data of the operands.  */
 625     unsigned life   : 16;       /* 32 */
 626
 627     /* Next and previous opcodes.  */
 628     QTAILQ_ENTRY(TCGOp) link;
 629
 630     /* Arguments for the opcode.  */
 631     TCGArg args[MAX_OPC_PARAM];
 632
 633     /* Register preferences for the output(s).  */
 634     TCGRegSet output_pref[2];
 635 } TCGOp;
 636
 637 #define TCGOP_CALLI(X)    (X)->param1
 638 #define TCGOP_CALLO(X)    (X)->param2
 639
 640 #define TCGOP_VECL(X)     (X)->param1
 641 #define TCGOP_VECE(X)     (X)->param2
 642
 643 /* Make sure operands fit in the bitfields above.  */
 644 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 645
 646 typedef struct TCGProfile {
 647     int64_t cpu_exec_time;
 648     int64_t tb_count1;
 649     int64_t tb_count;
 650     int64_t op_count; /* total insn count */
 651     int op_count_max; /* max insn per TB */
 652     int temp_count_max;
 653     int64_t temp_count;
 654     int64_t del_op_count;
 655     int64_t code_in_len;
 656     int64_t code_out_len;
 657     int64_t search_out_len;
 658     int64_t interm_time;
 659     int64_t code_time;
 660     int64_t la_time;
 661     int64_t opt_time;
 662     int64_t restore_count;
 663     int64_t restore_time;
 664     int64_t table_op_count[NB_OPS];
 665 } TCGProfile;
 666
 667 struct TCGContext {
 668     uint8_t *pool_cur, *pool_end;
 669     TCGPool *pool_first, *pool_current, *pool_first_large;
 670     int nb_labels;
 671     int nb_globals;
 672     int nb_temps;
 673     int nb_indirects;
 674     int nb_ops;
 675
 676     /* goto_tb support */
 677     tcg_insn_unit *code_buf;
 678     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 679     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 680     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 681
 682     TCGRegSet reserved_regs;
 683     uint32_t tb_cflags; /* cflags of the current TB */
 684     intptr_t current_frame_offset;
 685     intptr_t frame_start;
 686     intptr_t frame_end;
 687     TCGTemp *frame_temp;
 688
 689     tcg_insn_unit *code_ptr;
 690
 691 #ifdef CONFIG_PROFILER
 692     TCGProfile prof;
 693 #endif
 694
 695 #ifdef CONFIG_DEBUG_TCG
 696     int temps_in_use;
 697     int goto_tb_issue_mask;
 698     const TCGOpcode *vecop_list;
 699 #endif
 700
 701     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 702        here, because there's too much arithmetic throughout that relies
 703        on addition and subtraction working on bytes.  Rely on the GCC
 704        extension that allows arithmetic on void*.  */
 705     void *code_gen_prologue;
 706     void *code_gen_epilogue;
 707     void *code_gen_buffer;
 708     size_t code_gen_buffer_size;
 709     void *code_gen_ptr;
 710     void *data_gen_ptr;
 711
 712     /* Threshold to flush the translated code buffer.  */
 713     void *code_gen_highwater;
 714
 715     size_t tb_phys_invalidate_count;
 716
 717     /* Track which vCPU triggers events */
 718     CPUState *cpu;                      /* *_trans */
 719
 720     /* These structures are private to tcg-target.inc.c.  */
 721 #ifdef TCG_TARGET_NEED_LDST_LABELS
 722     QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
 723 #endif
 724 #ifdef TCG_TARGET_NEED_POOL_LABELS
 725     struct TCGLabelPoolData *pool_labels;
 726 #endif
 727
 728     TCGLabel *exitreq_label;
 729
 730     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 731     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 732
 733     QTAILQ_HEAD(, TCGOp) ops, free_ops;
 734     QSIMPLEQ_HEAD(, TCGLabel) labels;
 735
 736     /* Tells which temporary holds a given register.
 737        It does not take into account fixed registers */
 738     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 739
 740     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 741     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 742 };
 743
 744 extern TCGContext tcg_init_ctx;
 745 extern __thread TCGContext *tcg_ctx;
 746 extern TCGv_env cpu_env;
 747
 748 static inline size_t temp_idx(TCGTemp *ts)
 749 {
 750     ptrdiff_t n = ts - tcg_ctx->temps;
 751     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 752     return n;
 753 }
 754
 755 static inline TCGArg temp_arg(TCGTemp *ts)
 756 {
 757     return (uintptr_t)ts;
 758 }
 759
 760 static inline TCGTemp *arg_temp(TCGArg a)
 761 {
 762     return (TCGTemp *)(uintptr_t)a;
 763 }
 764
 765 /* Using the offset of a temporary, relative to TCGContext, rather than
 766    its index means that we don't use 0.  That leaves offset 0 free for
 767    a NULL representation without having to leave index 0 unused.  */
 768 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 769 {
 770     uintptr_t o = (uintptr_t)v;
 771     TCGTemp *t = (void *)tcg_ctx + o;
 772     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 773     return t;
 774 }
 775
 776 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 777 {
 778     return tcgv_i32_temp((TCGv_i32)v);
 779 }
 780
 781 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 782 {
 783     return tcgv_i32_temp((TCGv_i32)v);
 784 }
 785
 786 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 787 {
 788     return tcgv_i32_temp((TCGv_i32)v);
 789 }
 790
 791 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 792 {
 793     return temp_arg(tcgv_i32_temp(v));
 794 }
 795
 796 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 797 {
 798     return temp_arg(tcgv_i64_temp(v));
 799 }
 800
 801 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 802 {
 803     return temp_arg(tcgv_ptr_temp(v));
 804 }
 805
 806 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 807 {
 808     return temp_arg(tcgv_vec_temp(v));
 809 }
 810
 811 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 812 {
 813     (void)temp_idx(t); /* trigger embedded assert */
 814     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 815 }
 816
 817 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 818 {
 819     return (TCGv_i64)temp_tcgv_i32(t);
 820 }
 821
 822 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 823 {
 824     return (TCGv_ptr)temp_tcgv_i32(t);
 825 }
 826
 827 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 828 {
 829     return (TCGv_vec)temp_tcgv_i32(t);
 830 }
 831
 832 #if TCG_TARGET_REG_BITS == 32
 833 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 834 {
 835     return temp_tcgv_i32(tcgv_i64_temp(t));
 836 }
 837
 838 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 839 {
 840     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 841 }
 842 #endif
 843
 844 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 845 {
 846     op->args[arg] = v;
 847 }
 848
 849 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
 850 {
 851 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
 852     tcg_set_insn_param(op, arg, v);
 853 #else
 854     tcg_set_insn_param(op, arg * 2, v);
 855     tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
 856 #endif
 857 }
 858
 859 /* The last op that was emitted.  */
 860 static inline TCGOp *tcg_last_op(void)
 861 {
 862     return QTAILQ_LAST(&tcg_ctx->ops);
 863 }
 864
 865 /* Test for whether to terminate the TB for using too many opcodes.  */
 866 static inline bool tcg_op_buf_full(void)
 867 {
 868     /* This is not a hard limit, it merely stops translation when
 869      * we have produced "enough" opcodes.  We want to limit TB size
 870      * such that a RISC host can reasonably use a 16-bit signed
 871      * branch within the TB.  We also need to be mindful of the
 872      * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
 873      * and TCGContext.gen_insn_end_off[].
 874      */
 875     return tcg_ctx->nb_ops >= 4000;
 876 }
 877
 878 /* pool based memory allocation */
 879
 880 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
 881 void *tcg_malloc_internal(TCGContext *s, int size);
 882 void tcg_pool_reset(TCGContext *s);
 883 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 884
 885 void tcg_region_init(void);
 886 void tcg_region_reset_all(void);
 887
 888 size_t tcg_code_size(void);
 889 size_t tcg_code_capacity(void);
 890
 891 void tcg_tb_insert(TranslationBlock *tb);
 892 void tcg_tb_remove(TranslationBlock *tb);
 893 size_t tcg_tb_phys_invalidate_count(void);
 894 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
 895 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
 896 size_t tcg_nb_tbs(void);
 897
 898 /* user-mode: Called with mmap_lock held.  */
 899 static inline void *tcg_malloc(int size)
 900 {
 901     TCGContext *s = tcg_ctx;
 902     uint8_t *ptr, *ptr_end;
 903
 904     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 905     size = QEMU_ALIGN_UP(size, 8);
 906
 907     ptr = s->pool_cur;
 908     ptr_end = ptr + size;
 909     if (unlikely(ptr_end > s->pool_end)) {
 910         return tcg_malloc_internal(tcg_ctx, size);
 911     } else {
 912         s->pool_cur = ptr_end;
 913         return ptr;
 914     }
 915 }
 916
 917 void tcg_context_init(TCGContext *s);
 918 void tcg_register_thread(void);
 919 void tcg_prologue_init(TCGContext *s);
 920 void tcg_func_start(TCGContext *s);
 921
 922 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 923
 924 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 925
 926 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 927                                      intptr_t, const char *);
 928 TCGTemp *tcg_temp_new_internal(TCGType, bool);
 929 void tcg_temp_free_internal(TCGTemp *);
 930 TCGv_vec tcg_temp_new_vec(TCGType type);
 931 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 932
 933 static inline void tcg_temp_free_i32(TCGv_i32 arg)
 934 {
 935     tcg_temp_free_internal(tcgv_i32_temp(arg));
 936 }
 937
 938 static inline void tcg_temp_free_i64(TCGv_i64 arg)
 939 {
 940     tcg_temp_free_internal(tcgv_i64_temp(arg));
 941 }
 942
 943 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
 944 {
 945     tcg_temp_free_internal(tcgv_ptr_temp(arg));
 946 }
 947
 948 static inline void tcg_temp_free_vec(TCGv_vec arg)
 949 {
 950     tcg_temp_free_internal(tcgv_vec_temp(arg));
 951 }
 952
 953 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 954                                               const char *name)
 955 {
 956     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 957     return temp_tcgv_i32(t);
 958 }
 959
 960 static inline TCGv_i32 tcg_temp_new_i32(void)
 961 {
 962     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
 963     return temp_tcgv_i32(t);
 964 }
 965
 966 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 967 {
 968     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
 969     return temp_tcgv_i32(t);
 970 }
 971
 972 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 973                                               const char *name)
 974 {
 975     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 976     return temp_tcgv_i64(t);
 977 }
 978
 979 static inline TCGv_i64 tcg_temp_new_i64(void)
 980 {
 981     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
 982     return temp_tcgv_i64(t);
 983 }
 984
 985 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 986 {
 987     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
 988     return temp_tcgv_i64(t);
 989 }
 990
 991 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
 992                                               const char *name)
 993 {
 994     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
 995     return temp_tcgv_ptr(t);
 996 }
 997
 998 static inline TCGv_ptr tcg_temp_new_ptr(void)
 999 {
1000     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
1001     return temp_tcgv_ptr(t);
1002 }
1003
1004 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
1005 {
1006     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
1007     return temp_tcgv_ptr(t);
1008 }
1009
1010 #if defined(CONFIG_DEBUG_TCG)
1011 /* If you call tcg_clear_temp_count() at the start of a section of
1012  * code which is not supposed to leak any TCG temporaries, then
1013  * calling tcg_check_temp_count() at the end of the section will
1014  * return 1 if the section did in fact leak a temporary.
1015  */
1016 void tcg_clear_temp_count(void);
1017 int tcg_check_temp_count(void);
1018 #else
1019 #define tcg_clear_temp_count() do { } while (0)
1020 #define tcg_check_temp_count() 0
1021 #endif
1022
1023 int64_t tcg_cpu_exec_time(void);
1024 void tcg_dump_info(void);
1025 void tcg_dump_op_count(void);
1026
1027 #define TCG_CT_ALIAS  0x80
1028 #define TCG_CT_IALIAS 0x40
1029 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1030 #define TCG_CT_REG    0x01
1031 #define TCG_CT_CONST  0x02 /* any constant of register size */
1032
1033 typedef struct TCGArgConstraint {
1034     uint16_t ct;
1035     uint8_t alias_index;
1036     union {
1037         TCGRegSet regs;
1038     } u;
1039 } TCGArgConstraint;
1040
1041 #define TCG_MAX_OP_ARGS 16
1042
1043 /* Bits for TCGOpDef->flags, 8 bits available.  */
1044 enum {
1045     /* Instruction exits the translation block.  */
1046     TCG_OPF_BB_EXIT      = 0x01,
1047     /* Instruction defines the end of a basic block.  */
1048     TCG_OPF_BB_END       = 0x02,
1049     /* Instruction clobbers call registers and potentially update globals.  */
1050     TCG_OPF_CALL_CLOBBER = 0x04,
1051     /* Instruction has side effects: it cannot be removed if its outputs
1052        are not used, and might trigger exceptions.  */
1053     TCG_OPF_SIDE_EFFECTS = 0x08,
1054     /* Instruction operands are 64-bits (otherwise 32-bits).  */
1055     TCG_OPF_64BIT        = 0x10,
1056     /* Instruction is optional and not implemented by the host, or insn
1057        is generic and should not be implemened by the host.  */
1058     TCG_OPF_NOT_PRESENT  = 0x20,
1059     /* Instruction operands are vectors.  */
1060     TCG_OPF_VECTOR       = 0x40,
1061 };
1062
1063 typedef struct TCGOpDef {
1064     const char *name;
1065     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
1066     uint8_t flags;
1067     TCGArgConstraint *args_ct;
1068     int *sorted_args;
1069 #if defined(CONFIG_DEBUG_TCG)
1070     int used;
1071 #endif
1072 } TCGOpDef;
1073
1074 extern TCGOpDef tcg_op_defs[];
1075 extern const size_t tcg_op_defs_max;
1076
1077 typedef struct TCGTargetOpDef {
1078     TCGOpcode op;
1079     const char *args_ct_str[TCG_MAX_OP_ARGS];
1080 } TCGTargetOpDef;
1081
1082 #define tcg_abort() \
1083 do {\
1084     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1085     abort();\
1086 } while (0)
1087
1088 bool tcg_op_supported(TCGOpcode op);
1089
1090 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1091
1092 TCGOp *tcg_emit_op(TCGOpcode opc);
1093 void tcg_op_remove(TCGContext *s, TCGOp *op);
1094 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1095 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1096
1097 void tcg_optimize(TCGContext *s);
1098
1099 TCGv_i32 tcg_const_i32(int32_t val);
1100 TCGv_i64 tcg_const_i64(int64_t val);
1101 TCGv_i32 tcg_const_local_i32(int32_t val);
1102 TCGv_i64 tcg_const_local_i64(int64_t val);
1103 TCGv_vec tcg_const_zeros_vec(TCGType);
1104 TCGv_vec tcg_const_ones_vec(TCGType);
1105 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1106 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1107
1108 #if UINTPTR_MAX == UINT32_MAX
1109 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1110 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1111 #else
1112 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1113 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1114 #endif
1115
1116 TCGLabel *gen_new_label(void);
1117
1118 /**
1119  * label_arg
1120  * @l: label
1121  *
1122  * Encode a label for storage in the TCG opcode stream.
1123  */
1124
1125 static inline TCGArg label_arg(TCGLabel *l)
1126 {
1127     return (uintptr_t)l;
1128 }
1129
1130 /**
1131  * arg_label
1132  * @i: value
1133  *
1134  * The opposite of label_arg.  Retrieve a label from the
1135  * encoding of the TCG opcode stream.
1136  */
1137
1138 static inline TCGLabel *arg_label(TCGArg i)
1139 {
1140     return (TCGLabel *)(uintptr_t)i;
1141 }
1142
1143 /**
1144  * tcg_ptr_byte_diff
1145  * @a, @b: addresses to be differenced
1146  *
1147  * There are many places within the TCG backends where we need a byte
1148  * difference between two pointers.  While this can be accomplished
1149  * with local casting, it's easy to get wrong -- especially if one is
1150  * concerned with the signedness of the result.
1151  *
1152  * This version relies on GCC's void pointer arithmetic to get the
1153  * correct result.
1154  */
1155
1156 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1157 {
1158     return a - b;
1159 }
1160
1161 /**
1162  * tcg_pcrel_diff
1163  * @s: the tcg context
1164  * @target: address of the target
1165  *
1166  * Produce a pc-relative difference, from the current code_ptr
1167  * to the destination address.
1168  */
1169
1170 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1171 {
1172     return tcg_ptr_byte_diff(target, s->code_ptr);
1173 }
1174
1175 /**
1176  * tcg_current_code_size
1177  * @s: the tcg context
1178  *
1179  * Compute the current code size within the translation block.
1180  * This is used to fill in qemu's data structures for goto_tb.
1181  */
1182
1183 static inline size_t tcg_current_code_size(TCGContext *s)
1184 {
1185     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1186 }
1187
1188 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1189 typedef uint32_t TCGMemOpIdx;
1190
1191 /**
1192  * make_memop_idx
1193  * @op: memory operation
1194  * @idx: mmu index
1195  *
1196  * Encode these values into a single parameter.
1197  */
1198 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1199 {
1200     tcg_debug_assert(idx <= 15);
1201     return (op << 4) | idx;
1202 }
1203
1204 /**
1205  * get_memop
1206  * @oi: combined op/idx parameter
1207  *
1208  * Extract the memory operation from the combined value.
1209  */
1210 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1211 {
1212     return oi >> 4;
1213 }
1214
1215 /**
1216  * get_mmuidx
1217  * @oi: combined op/idx parameter
1218  *
1219  * Extract the mmu index from the combined value.
1220  */
1221 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1222 {
1223     return oi & 15;
1224 }
1225
1226 /**
1227  * tcg_qemu_tb_exec:
1228  * @env: pointer to CPUArchState for the CPU
1229  * @tb_ptr: address of generated code for the TB to execute
1230  *
1231  * Start executing code from a given translation block.
1232  * Where translation blocks have been linked, execution
1233  * may proceed from the given TB into successive ones.
1234  * Control eventually returns only when some action is needed
1235  * from the top-level loop: either control must pass to a TB
1236  * which has not yet been directly linked, or an asynchronous
1237  * event such as an interrupt needs handling.
1238  *
1239  * Return: The return value is the value passed to the corresponding
1240  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1241  * The value is either zero or a 4-byte aligned pointer to that TB combined
1242  * with additional information in its two least significant bits. The
1243  * additional information is encoded as follows:
1244  *  0, 1: the link between this TB and the next is via the specified
1245  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1246  *        of) "goto_tb <index>". The main loop uses this to determine
1247  *        how to link the TB just executed to the next.
1248  *  2:    we are using instruction counting code generation, and we
1249  *        did not start executing this TB because the instruction counter
1250  *        would hit zero midway through it. In this case the pointer
1251  *        returned is the TB we were about to execute, and the caller must
1252  *        arrange to execute the remaining count of instructions.
1253  *  3:    we stopped because the CPU's exit_request flag was set
1254  *        (usually meaning that there is an interrupt that needs to be
1255  *        handled). The pointer returned is the TB we were about to execute
1256  *        when we noticed the pending exit request.
1257  *
1258  * If the bottom two bits indicate an exit-via-index then the CPU
1259  * state is correctly synchronised and ready for execution of the next
1260  * TB (and in particular the guest PC is the address to execute next).
1261  * Otherwise, we gave up on execution of this TB before it started, and
1262  * the caller must fix up the CPU state by calling the CPU's
1263  * synchronize_from_tb() method with the TB pointer we return (falling
1264  * back to calling the CPU's set_pc method with tb->pb if no
1265  * synchronize_from_tb() method exists).
1266  *
1267  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1268  * to this default (which just calls the prologue.code emitted by
1269  * tcg_target_qemu_prologue()).
1270  */
1271 #define TB_EXIT_MASK      3
1272 #define TB_EXIT_IDX0      0
1273 #define TB_EXIT_IDX1      1
1274 #define TB_EXIT_IDXMAX    1
1275 #define TB_EXIT_REQUESTED 3
1276
1277 #ifdef HAVE_TCG_QEMU_TB_EXEC
1278 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1279 #else
1280 # define tcg_qemu_tb_exec(env, tb_ptr) \
1281     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1282 #endif
1283
1284 void tcg_register_jit(void *buf, size_t buf_size);
1285
1286 #if TCG_TARGET_MAYBE_vec
1287 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1288    return > 0 if it is directly supportable;
1289    return < 0 if we must call tcg_expand_vec_op.  */
1290 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1291 #else
1292 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1293 {
1294     return 0;
1295 }
1296 #endif
1297
1298 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1299 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1300
1301 /* Replicate a constant C accoring to the log2 of the element size.  */
1302 uint64_t dup_const(unsigned vece, uint64_t c);
1303
1304 #define dup_const(VECE, C)                                         \
1305     (__builtin_constant_p(VECE)                                    \
1306      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1307         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1308         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1309         : dup_const(VECE, C))                                      \
1310      : dup_const(VECE, C))
1311
1312
1313 /*
1314  * Memory helpers that will be used by TCG generated code.
1315  */
1316 #ifdef CONFIG_SOFTMMU
1317 /* Value zero-extended to tcg register size.  */
1318 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1319                                      TCGMemOpIdx oi, uintptr_t retaddr);
1320 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1321                                     TCGMemOpIdx oi, uintptr_t retaddr);
1322 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1323                                     TCGMemOpIdx oi, uintptr_t retaddr);
1324 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1325                            TCGMemOpIdx oi, uintptr_t retaddr);
1326 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1327                                     TCGMemOpIdx oi, uintptr_t retaddr);
1328 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1329                                     TCGMemOpIdx oi, uintptr_t retaddr);
1330 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1331                            TCGMemOpIdx oi, uintptr_t retaddr);
1332
1333 /* Value sign-extended to tcg register size.  */
1334 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1335                                      TCGMemOpIdx oi, uintptr_t retaddr);
1336 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1337                                     TCGMemOpIdx oi, uintptr_t retaddr);
1338 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1339                                     TCGMemOpIdx oi, uintptr_t retaddr);
1340 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1341                                     TCGMemOpIdx oi, uintptr_t retaddr);
1342 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1343                                     TCGMemOpIdx oi, uintptr_t retaddr);
1344
1345 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1346                         TCGMemOpIdx oi, uintptr_t retaddr);
1347 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1348                        TCGMemOpIdx oi, uintptr_t retaddr);
1349 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1350                        TCGMemOpIdx oi, uintptr_t retaddr);
1351 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1352                        TCGMemOpIdx oi, uintptr_t retaddr);
1353 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1354                        TCGMemOpIdx oi, uintptr_t retaddr);
1355 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1356                        TCGMemOpIdx oi, uintptr_t retaddr);
1357 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1358                        TCGMemOpIdx oi, uintptr_t retaddr);
1359
1360 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1361                             TCGMemOpIdx oi, uintptr_t retaddr);
1362 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1363                             TCGMemOpIdx oi, uintptr_t retaddr);
1364 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1365                             TCGMemOpIdx oi, uintptr_t retaddr);
1366 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1367                             TCGMemOpIdx oi, uintptr_t retaddr);
1368 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1369                             TCGMemOpIdx oi, uintptr_t retaddr);
1370 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1371                             TCGMemOpIdx oi, uintptr_t retaddr);
1372 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1373                             TCGMemOpIdx oi, uintptr_t retaddr);
1374
1375 /* Temporary aliases until backends are converted.  */
1376 #ifdef TARGET_WORDS_BIGENDIAN
1377 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1378 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1379 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1380 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1381 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1382 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1383 # define helper_ret_stw_mmu   helper_be_stw_mmu
1384 # define helper_ret_stl_mmu   helper_be_stl_mmu
1385 # define helper_ret_stq_mmu   helper_be_stq_mmu
1386 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1387 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1388 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1389 #else
1390 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1391 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1392 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1393 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1394 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1395 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1396 # define helper_ret_stw_mmu   helper_le_stw_mmu
1397 # define helper_ret_stl_mmu   helper_le_stl_mmu
1398 # define helper_ret_stq_mmu   helper_le_stq_mmu
1399 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1400 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1401 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1402 #endif
1403
1404 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1405                                     uint32_t cmpv, uint32_t newv,
1406                                     TCGMemOpIdx oi, uintptr_t retaddr);
1407 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1408                                        uint32_t cmpv, uint32_t newv,
1409                                        TCGMemOpIdx oi, uintptr_t retaddr);
1410 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1411                                        uint32_t cmpv, uint32_t newv,
1412                                        TCGMemOpIdx oi, uintptr_t retaddr);
1413 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1414                                        uint64_t cmpv, uint64_t newv,
1415                                        TCGMemOpIdx oi, uintptr_t retaddr);
1416 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1417                                        uint32_t cmpv, uint32_t newv,
1418                                        TCGMemOpIdx oi, uintptr_t retaddr);
1419 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1420                                        uint32_t cmpv, uint32_t newv,
1421                                        TCGMemOpIdx oi, uintptr_t retaddr);
1422 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1423                                        uint64_t cmpv, uint64_t newv,
1424                                        TCGMemOpIdx oi, uintptr_t retaddr);
1425
1426 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1427 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1428     (CPUArchState *env, target_ulong addr, TYPE val,  \
1429      TCGMemOpIdx oi, uintptr_t retaddr);
1430
1431 #ifdef CONFIG_ATOMIC64
1432 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1433     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1434     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1435     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1436     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1437     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1438     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1439     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1440 #else
1441 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1442     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1443     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1444     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1445     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1446     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1447 #endif
1448
1449 GEN_ATOMIC_HELPER_ALL(fetch_add)
1450 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1451 GEN_ATOMIC_HELPER_ALL(fetch_and)
1452 GEN_ATOMIC_HELPER_ALL(fetch_or)
1453 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1454 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1455 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1456 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1457 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1458
1459 GEN_ATOMIC_HELPER_ALL(add_fetch)
1460 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1461 GEN_ATOMIC_HELPER_ALL(and_fetch)
1462 GEN_ATOMIC_HELPER_ALL(or_fetch)
1463 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1464 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1465 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1466 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1467 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1468
1469 GEN_ATOMIC_HELPER_ALL(xchg)
1470
1471 #undef GEN_ATOMIC_HELPER_ALL
1472 #undef GEN_ATOMIC_HELPER
1473 #endif /* CONFIG_SOFTMMU */
1474
1475 /*
1476  * These aren't really a "proper" helpers because TCG cannot manage Int128.
1477  * However, use the same format as the others, for use by the backends.
1478  *
1479  * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1480  * the ld/st functions are only defined if HAVE_ATOMIC128,
1481  * as defined by <qemu/atomic128.h>.
1482  */
1483 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1484                                      Int128 cmpv, Int128 newv,
1485                                      TCGMemOpIdx oi, uintptr_t retaddr);
1486 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1487                                      Int128 cmpv, Int128 newv,
1488                                      TCGMemOpIdx oi, uintptr_t retaddr);
1489
1490 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1491                                 TCGMemOpIdx oi, uintptr_t retaddr);
1492 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1493                                 TCGMemOpIdx oi, uintptr_t retaddr);
1494 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1495                               TCGMemOpIdx oi, uintptr_t retaddr);
1496 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1497                               TCGMemOpIdx oi, uintptr_t retaddr);
1498
1499 #ifdef CONFIG_DEBUG_TCG
1500 void tcg_assert_listed_vecop(TCGOpcode);
1501 #else
1502 static inline void tcg_assert_listed_vecop(TCGOpcode op) { }
1503 #endif
1504
1505 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n)
1506 {
1507 #ifdef CONFIG_DEBUG_TCG
1508     const TCGOpcode *o = tcg_ctx->vecop_list;
1509     tcg_ctx->vecop_list = n;
1510     return o;
1511 #else
1512     return NULL;
1513 #endif
1514 }
1515
1516 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned);
1517
1518 #endif /* TCG_H */