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target-sparc: Use QT0 to return results from ldda
[qemu/ar7.git] / target-sparc / ldst_helper.c
blobba48687b19bfe2a481c907b29b3bcea7dd8fd72b
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "asi.h"
26
27 //#define DEBUG_MMU
28 //#define DEBUG_MXCC
29 //#define DEBUG_UNALIGNED
30 //#define DEBUG_UNASSIGNED
31 //#define DEBUG_ASI
32 //#define DEBUG_CACHE_CONTROL
33
34 #ifdef DEBUG_MMU
35 #define DPRINTF_MMU(fmt, ...) \
36 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
37 #else
38 #define DPRINTF_MMU(fmt, ...) do {} while (0)
39 #endif
40
41 #ifdef DEBUG_MXCC
42 #define DPRINTF_MXCC(fmt, ...) \
43 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
44 #else
45 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
46 #endif
47
48 #ifdef DEBUG_ASI
49 #define DPRINTF_ASI(fmt, ...) \
50 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
51 #endif
52
53 #ifdef DEBUG_CACHE_CONTROL
54 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
55 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
58 #endif
59
60 #ifdef TARGET_SPARC64
61 #ifndef TARGET_ABI32
62 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
63 #else
64 #define AM_CHECK(env1) (1)
65 #endif
66 #endif
67
68 #define QT0 (env->qt0)
69 #define QT1 (env->qt1)
70
71 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
72 /* Calculates TSB pointer value for fault page size 8k or 64k */
73 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
74 uint64_t tag_access_register,
75 int page_size)
76 {
77 uint64_t tsb_base = tsb_register & ~0x1fffULL;
78 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
79 int tsb_size = tsb_register & 0xf;
80
81 /* discard lower 13 bits which hold tag access context */
82 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
83
84 /* now reorder bits */
85 uint64_t tsb_base_mask = ~0x1fffULL;
86 uint64_t va = tag_access_va;
87
88 /* move va bits to correct position */
89 if (page_size == 8*1024) {
90 va >>= 9;
91 } else if (page_size == 64*1024) {
92 va >>= 12;
93 }
94
95 if (tsb_size) {
96 tsb_base_mask <<= tsb_size;
97 }
98
99 /* calculate tsb_base mask and adjust va if split is in use */
100 if (tsb_split) {
101 if (page_size == 8*1024) {
102 va &= ~(1ULL << (13 + tsb_size));
103 } else if (page_size == 64*1024) {
104 va |= (1ULL << (13 + tsb_size));
105 }
106 tsb_base_mask <<= 1;
107 }
108
109 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
110 }
111
112 /* Calculates tag target register value by reordering bits
113 in tag access register */
114 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
115 {
116 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
117 }
118
119 static void replace_tlb_entry(SparcTLBEntry *tlb,
120 uint64_t tlb_tag, uint64_t tlb_tte,
121 CPUSPARCState *env1)
122 {
123 target_ulong mask, size, va, offset;
124
125 /* flush page range if translation is valid */
126 if (TTE_IS_VALID(tlb->tte)) {
127 CPUState *cs = CPU(sparc_env_get_cpu(env1));
128
129 mask = 0xffffffffffffe000ULL;
130 mask <<= 3 * ((tlb->tte >> 61) & 3);
131 size = ~mask + 1;
132
133 va = tlb->tag & mask;
134
135 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
136 tlb_flush_page(cs, va + offset);
137 }
138 }
139
140 tlb->tag = tlb_tag;
141 tlb->tte = tlb_tte;
142 }
143
144 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
145 const char *strmmu, CPUSPARCState *env1)
146 {
147 unsigned int i;
148 target_ulong mask;
149 uint64_t context;
150
151 int is_demap_context = (demap_addr >> 6) & 1;
152
153 /* demap context */
154 switch ((demap_addr >> 4) & 3) {
155 case 0: /* primary */
156 context = env1->dmmu.mmu_primary_context;
157 break;
158 case 1: /* secondary */
159 context = env1->dmmu.mmu_secondary_context;
160 break;
161 case 2: /* nucleus */
162 context = 0;
163 break;
164 case 3: /* reserved */
165 default:
166 return;
167 }
168
169 for (i = 0; i < 64; i++) {
170 if (TTE_IS_VALID(tlb[i].tte)) {
171
172 if (is_demap_context) {
173 /* will remove non-global entries matching context value */
174 if (TTE_IS_GLOBAL(tlb[i].tte) ||
175 !tlb_compare_context(&tlb[i], context)) {
176 continue;
177 }
178 } else {
179 /* demap page
180 will remove any entry matching VA */
181 mask = 0xffffffffffffe000ULL;
182 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
183
184 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
185 continue;
186 }
187
188 /* entry should be global or matching context value */
189 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
190 !tlb_compare_context(&tlb[i], context)) {
191 continue;
192 }
193 }
194
195 replace_tlb_entry(&tlb[i], 0, 0, env1);
196 #ifdef DEBUG_MMU
197 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
198 dump_mmu(stdout, fprintf, env1);
199 #endif
200 }
201 }
202 }
203
204 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
205 uint64_t tlb_tag, uint64_t tlb_tte,
206 const char *strmmu, CPUSPARCState *env1)
207 {
208 unsigned int i, replace_used;
209
210 /* Try replacing invalid entry */
211 for (i = 0; i < 64; i++) {
212 if (!TTE_IS_VALID(tlb[i].tte)) {
213 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
214 #ifdef DEBUG_MMU
215 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
216 dump_mmu(stdout, fprintf, env1);
217 #endif
218 return;
219 }
220 }
221
222 /* All entries are valid, try replacing unlocked entry */
223
224 for (replace_used = 0; replace_used < 2; ++replace_used) {
225
226 /* Used entries are not replaced on first pass */
227
228 for (i = 0; i < 64; i++) {
229 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
230
231 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
232 #ifdef DEBUG_MMU
233 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
234 strmmu, (replace_used ? "used" : "unused"), i);
235 dump_mmu(stdout, fprintf, env1);
236 #endif
237 return;
238 }
239 }
240
241 /* Now reset used bit and search for unused entries again */
242
243 for (i = 0; i < 64; i++) {
244 TTE_SET_UNUSED(tlb[i].tte);
245 }
246 }
247
248 #ifdef DEBUG_MMU
249 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
250 #endif
251 /* error state? */
252 }
253
254 #endif
255
256 #if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)
257 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
258 {
259 #ifdef TARGET_SPARC64
260 if (AM_CHECK(env1)) {
261 addr &= 0xffffffffULL;
262 }
263 #endif
264 return addr;
265 }
266 #endif
267
268 #ifdef TARGET_SPARC64
269 /* returns true if access using this ASI is to have address translated by MMU
270 otherwise access is to raw physical address */
271 /* TODO: check sparc32 bits */
272 static inline int is_translating_asi(int asi)
273 {
274 /* Ultrasparc IIi translating asi
275 - note this list is defined by cpu implementation
276 */
277 switch (asi) {
278 case 0x04 ... 0x11:
279 case 0x16 ... 0x19:
280 case 0x1E ... 0x1F:
281 case 0x24 ... 0x2C:
282 case 0x70 ... 0x73:
283 case 0x78 ... 0x79:
284 case 0x80 ... 0xFF:
285 return 1;
286
287 default:
288 return 0;
289 }
290 }
291
292 static inline target_ulong asi_address_mask(CPUSPARCState *env,
293 int asi, target_ulong addr)
294 {
295 if (is_translating_asi(asi)) {
296 return address_mask(env, addr);
297 } else {
298 return addr;
299 }
300 }
301 #endif
302
303 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
304 {
305 if (addr & align) {
306 #ifdef DEBUG_UNALIGNED
307 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
308 "\n", addr, env->pc);
309 #endif
310 helper_raise_exception(env, TT_UNALIGNED);
311 }
312 }
313
314 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
315 defined(DEBUG_MXCC)
316 static void dump_mxcc(CPUSPARCState *env)
317 {
318 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
319 "\n",
320 env->mxccdata[0], env->mxccdata[1],
321 env->mxccdata[2], env->mxccdata[3]);
322 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
323 "\n"
324 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
325 "\n",
326 env->mxccregs[0], env->mxccregs[1],
327 env->mxccregs[2], env->mxccregs[3],
328 env->mxccregs[4], env->mxccregs[5],
329 env->mxccregs[6], env->mxccregs[7]);
330 }
331 #endif
332
333 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
334 && defined(DEBUG_ASI)
335 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
336 uint64_t r1)
337 {
338 switch (size) {
339 case 1:
340 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
341 addr, asi, r1 & 0xff);
342 break;
343 case 2:
344 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
345 addr, asi, r1 & 0xffff);
346 break;
347 case 4:
348 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
349 addr, asi, r1 & 0xffffffff);
350 break;
351 case 8:
352 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
353 addr, asi, r1);
354 break;
355 }
356 }
357 #endif
358
359 #ifndef TARGET_SPARC64
360 #ifndef CONFIG_USER_ONLY
361
362
363 /* Leon3 cache control */
364
365 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
366 uint64_t val, int size)
367 {
368 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
369 addr, val, size);
370
371 if (size != 4) {
372 DPRINTF_CACHE_CONTROL("32bits only\n");
373 return;
374 }
375
376 switch (addr) {
377 case 0x00: /* Cache control */
378
379 /* These values must always be read as zeros */
380 val &= ~CACHE_CTRL_FD;
381 val &= ~CACHE_CTRL_FI;
382 val &= ~CACHE_CTRL_IB;
383 val &= ~CACHE_CTRL_IP;
384 val &= ~CACHE_CTRL_DP;
385
386 env->cache_control = val;
387 break;
388 case 0x04: /* Instruction cache configuration */
389 case 0x08: /* Data cache configuration */
390 /* Read Only */
391 break;
392 default:
393 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
394 break;
395 };
396 }
397
398 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
399 int size)
400 {
401 uint64_t ret = 0;
402
403 if (size != 4) {
404 DPRINTF_CACHE_CONTROL("32bits only\n");
405 return 0;
406 }
407
408 switch (addr) {
409 case 0x00: /* Cache control */
410 ret = env->cache_control;
411 break;
412
413 /* Configuration registers are read and only always keep those
414 predefined values */
415
416 case 0x04: /* Instruction cache configuration */
417 ret = 0x10220000;
418 break;
419 case 0x08: /* Data cache configuration */
420 ret = 0x18220000;
421 break;
422 default:
423 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
424 break;
425 };
426 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
427 addr, ret, size);
428 return ret;
429 }
430
431 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
432 int sign)
433 {
434 CPUState *cs = CPU(sparc_env_get_cpu(env));
435 uint64_t ret = 0;
436 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
437 uint32_t last_addr = addr;
438 #endif
439
440 helper_check_align(env, addr, size - 1);
441 switch (asi) {
442 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
443 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
444 switch (addr) {
445 case 0x00: /* Leon3 Cache Control */
446 case 0x08: /* Leon3 Instruction Cache config */
447 case 0x0C: /* Leon3 Date Cache config */
448 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
449 ret = leon3_cache_control_ld(env, addr, size);
450 }
451 break;
452 case 0x01c00a00: /* MXCC control register */
453 if (size == 8) {
454 ret = env->mxccregs[3];
455 } else {
456 qemu_log_mask(LOG_UNIMP,
457 "%08x: unimplemented access size: %d\n", addr,
458 size);
459 }
460 break;
461 case 0x01c00a04: /* MXCC control register */
462 if (size == 4) {
463 ret = env->mxccregs[3];
464 } else {
465 qemu_log_mask(LOG_UNIMP,
466 "%08x: unimplemented access size: %d\n", addr,
467 size);
468 }
469 break;
470 case 0x01c00c00: /* Module reset register */
471 if (size == 8) {
472 ret = env->mxccregs[5];
473 /* should we do something here? */
474 } else {
475 qemu_log_mask(LOG_UNIMP,
476 "%08x: unimplemented access size: %d\n", addr,
477 size);
478 }
479 break;
480 case 0x01c00f00: /* MBus port address register */
481 if (size == 8) {
482 ret = env->mxccregs[7];
483 } else {
484 qemu_log_mask(LOG_UNIMP,
485 "%08x: unimplemented access size: %d\n", addr,
486 size);
487 }
488 break;
489 default:
490 qemu_log_mask(LOG_UNIMP,
491 "%08x: unimplemented address, size: %d\n", addr,
492 size);
493 break;
494 }
495 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
496 "addr = %08x -> ret = %" PRIx64 ","
497 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
498 #ifdef DEBUG_MXCC
499 dump_mxcc(env);
500 #endif
501 break;
502 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */
503 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */
504 {
505 int mmulev;
506
507 mmulev = (addr >> 8) & 15;
508 if (mmulev > 4) {
509 ret = 0;
510 } else {
511 ret = mmu_probe(env, addr, mmulev);
512 }
513 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
514 addr, mmulev, ret);
515 }
516 break;
517 case ASI_M_MMUREGS: /* SuperSparc MMU regs */
518 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */
519 {
520 int reg = (addr >> 8) & 0x1f;
521
522 ret = env->mmuregs[reg];
523 if (reg == 3) { /* Fault status cleared on read */
524 env->mmuregs[3] = 0;
525 } else if (reg == 0x13) { /* Fault status read */
526 ret = env->mmuregs[3];
527 } else if (reg == 0x14) { /* Fault address read */
528 ret = env->mmuregs[4];
529 }
530 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
531 }
532 break;
533 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
534 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
535 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
536 break;
537 case ASI_KERNELTXT: /* Supervisor code access */
538 switch (size) {
539 case 1:
540 ret = cpu_ldub_code(env, addr);
541 break;
542 case 2:
543 ret = cpu_lduw_code(env, addr);
544 break;
545 default:
546 case 4:
547 ret = cpu_ldl_code(env, addr);
548 break;
549 case 8:
550 ret = cpu_ldq_code(env, addr);
551 break;
552 }
553 break;
554 case ASI_USERDATA: /* User data access */
555 switch (size) {
556 case 1:
557 ret = cpu_ldub_user(env, addr);
558 break;
559 case 2:
560 ret = cpu_lduw_user(env, addr);
561 break;
562 default:
563 case 4:
564 ret = cpu_ldl_user(env, addr);
565 break;
566 case 8:
567 ret = cpu_ldq_user(env, addr);
568 break;
569 }
570 break;
571 case ASI_KERNELDATA: /* Supervisor data access */
572 case ASI_P: /* Implicit primary context data access (v9 only?) */
573 switch (size) {
574 case 1:
575 ret = cpu_ldub_kernel(env, addr);
576 break;
577 case 2:
578 ret = cpu_lduw_kernel(env, addr);
579 break;
580 default:
581 case 4:
582 ret = cpu_ldl_kernel(env, addr);
583 break;
584 case 8:
585 ret = cpu_ldq_kernel(env, addr);
586 break;
587 }
588 break;
589 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */
590 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */
591 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */
592 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */
593 break;
594 case ASI_M_BYPASS: /* MMU passthrough */
595 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
596 switch (size) {
597 case 1:
598 ret = ldub_phys(cs->as, addr);
599 break;
600 case 2:
601 ret = lduw_phys(cs->as, addr);
602 break;
603 default:
604 case 4:
605 ret = ldl_phys(cs->as, addr);
606 break;
607 case 8:
608 ret = ldq_phys(cs->as, addr);
609 break;
610 }
611 break;
612 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
613 switch (size) {
614 case 1:
615 ret = ldub_phys(cs->as, (hwaddr)addr
616 | ((hwaddr)(asi & 0xf) << 32));
617 break;
618 case 2:
619 ret = lduw_phys(cs->as, (hwaddr)addr
620 | ((hwaddr)(asi & 0xf) << 32));
621 break;
622 default:
623 case 4:
624 ret = ldl_phys(cs->as, (hwaddr)addr
625 | ((hwaddr)(asi & 0xf) << 32));
626 break;
627 case 8:
628 ret = ldq_phys(cs->as, (hwaddr)addr
629 | ((hwaddr)(asi & 0xf) << 32));
630 break;
631 }
632 break;
633 case 0x30: /* Turbosparc secondary cache diagnostic */
634 case 0x31: /* Turbosparc RAM snoop */
635 case 0x32: /* Turbosparc page table descriptor diagnostic */
636 case 0x39: /* data cache diagnostic register */
637 ret = 0;
638 break;
639 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
640 {
641 int reg = (addr >> 8) & 3;
642
643 switch (reg) {
644 case 0: /* Breakpoint Value (Addr) */
645 ret = env->mmubpregs[reg];
646 break;
647 case 1: /* Breakpoint Mask */
648 ret = env->mmubpregs[reg];
649 break;
650 case 2: /* Breakpoint Control */
651 ret = env->mmubpregs[reg];
652 break;
653 case 3: /* Breakpoint Status */
654 ret = env->mmubpregs[reg];
655 env->mmubpregs[reg] = 0ULL;
656 break;
657 }
658 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
659 ret);
660 }
661 break;
662 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
663 ret = env->mmubpctrv;
664 break;
665 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
666 ret = env->mmubpctrc;
667 break;
668 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
669 ret = env->mmubpctrs;
670 break;
671 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
672 ret = env->mmubpaction;
673 break;
674 case ASI_USERTXT: /* User code access, XXX */
675 default:
676 cpu_unassigned_access(cs, addr, false, false, asi, size);
677 ret = 0;
678 break;
679 }
680 if (sign) {
681 switch (size) {
682 case 1:
683 ret = (int8_t) ret;
684 break;
685 case 2:
686 ret = (int16_t) ret;
687 break;
688 case 4:
689 ret = (int32_t) ret;
690 break;
691 default:
692 break;
693 }
694 }
695 #ifdef DEBUG_ASI
696 dump_asi("read ", last_addr, asi, size, ret);
697 #endif
698 return ret;
699 }
700
701 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
702 int size)
703 {
704 SPARCCPU *cpu = sparc_env_get_cpu(env);
705 CPUState *cs = CPU(cpu);
706
707 helper_check_align(env, addr, size - 1);
708 switch (asi) {
709 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
710 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
711 switch (addr) {
712 case 0x00: /* Leon3 Cache Control */
713 case 0x08: /* Leon3 Instruction Cache config */
714 case 0x0C: /* Leon3 Date Cache config */
715 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
716 leon3_cache_control_st(env, addr, val, size);
717 }
718 break;
719
720 case 0x01c00000: /* MXCC stream data register 0 */
721 if (size == 8) {
722 env->mxccdata[0] = val;
723 } else {
724 qemu_log_mask(LOG_UNIMP,
725 "%08x: unimplemented access size: %d\n", addr,
726 size);
727 }
728 break;
729 case 0x01c00008: /* MXCC stream data register 1 */
730 if (size == 8) {
731 env->mxccdata[1] = val;
732 } else {
733 qemu_log_mask(LOG_UNIMP,
734 "%08x: unimplemented access size: %d\n", addr,
735 size);
736 }
737 break;
738 case 0x01c00010: /* MXCC stream data register 2 */
739 if (size == 8) {
740 env->mxccdata[2] = val;
741 } else {
742 qemu_log_mask(LOG_UNIMP,
743 "%08x: unimplemented access size: %d\n", addr,
744 size);
745 }
746 break;
747 case 0x01c00018: /* MXCC stream data register 3 */
748 if (size == 8) {
749 env->mxccdata[3] = val;
750 } else {
751 qemu_log_mask(LOG_UNIMP,
752 "%08x: unimplemented access size: %d\n", addr,
753 size);
754 }
755 break;
756 case 0x01c00100: /* MXCC stream source */
757 if (size == 8) {
758 env->mxccregs[0] = val;
759 } else {
760 qemu_log_mask(LOG_UNIMP,
761 "%08x: unimplemented access size: %d\n", addr,
762 size);
763 }
764 env->mxccdata[0] = ldq_phys(cs->as,
765 (env->mxccregs[0] & 0xffffffffULL) +
766 0);
767 env->mxccdata[1] = ldq_phys(cs->as,
768 (env->mxccregs[0] & 0xffffffffULL) +
769 8);
770 env->mxccdata[2] = ldq_phys(cs->as,
771 (env->mxccregs[0] & 0xffffffffULL) +
772 16);
773 env->mxccdata[3] = ldq_phys(cs->as,
774 (env->mxccregs[0] & 0xffffffffULL) +
775 24);
776 break;
777 case 0x01c00200: /* MXCC stream destination */
778 if (size == 8) {
779 env->mxccregs[1] = val;
780 } else {
781 qemu_log_mask(LOG_UNIMP,
782 "%08x: unimplemented access size: %d\n", addr,
783 size);
784 }
785 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
786 env->mxccdata[0]);
787 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
788 env->mxccdata[1]);
789 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
790 env->mxccdata[2]);
791 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
792 env->mxccdata[3]);
793 break;
794 case 0x01c00a00: /* MXCC control register */
795 if (size == 8) {
796 env->mxccregs[3] = val;
797 } else {
798 qemu_log_mask(LOG_UNIMP,
799 "%08x: unimplemented access size: %d\n", addr,
800 size);
801 }
802 break;
803 case 0x01c00a04: /* MXCC control register */
804 if (size == 4) {
805 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
806 | val;
807 } else {
808 qemu_log_mask(LOG_UNIMP,
809 "%08x: unimplemented access size: %d\n", addr,
810 size);
811 }
812 break;
813 case 0x01c00e00: /* MXCC error register */
814 /* writing a 1 bit clears the error */
815 if (size == 8) {
816 env->mxccregs[6] &= ~val;
817 } else {
818 qemu_log_mask(LOG_UNIMP,
819 "%08x: unimplemented access size: %d\n", addr,
820 size);
821 }
822 break;
823 case 0x01c00f00: /* MBus port address register */
824 if (size == 8) {
825 env->mxccregs[7] = val;
826 } else {
827 qemu_log_mask(LOG_UNIMP,
828 "%08x: unimplemented access size: %d\n", addr,
829 size);
830 }
831 break;
832 default:
833 qemu_log_mask(LOG_UNIMP,
834 "%08x: unimplemented address, size: %d\n", addr,
835 size);
836 break;
837 }
838 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
839 asi, size, addr, val);
840 #ifdef DEBUG_MXCC
841 dump_mxcc(env);
842 #endif
843 break;
844 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */
845 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */
846 {
847 int mmulev;
848
849 mmulev = (addr >> 8) & 15;
850 DPRINTF_MMU("mmu flush level %d\n", mmulev);
851 switch (mmulev) {
852 case 0: /* flush page */
853 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
854 break;
855 case 1: /* flush segment (256k) */
856 case 2: /* flush region (16M) */
857 case 3: /* flush context (4G) */
858 case 4: /* flush entire */
859 tlb_flush(CPU(cpu), 1);
860 break;
861 default:
862 break;
863 }
864 #ifdef DEBUG_MMU
865 dump_mmu(stdout, fprintf, env);
866 #endif
867 }
868 break;
869 case ASI_M_MMUREGS: /* write MMU regs */
870 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */
871 {
872 int reg = (addr >> 8) & 0x1f;
873 uint32_t oldreg;
874
875 oldreg = env->mmuregs[reg];
876 switch (reg) {
877 case 0: /* Control Register */
878 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
879 (val & 0x00ffffff);
880 /* Mappings generated during no-fault mode or MMU
881 disabled mode are invalid in normal mode */
882 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
883 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
884 tlb_flush(CPU(cpu), 1);
885 }
886 break;
887 case 1: /* Context Table Pointer Register */
888 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
889 break;
890 case 2: /* Context Register */
891 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
892 if (oldreg != env->mmuregs[reg]) {
893 /* we flush when the MMU context changes because
894 QEMU has no MMU context support */
895 tlb_flush(CPU(cpu), 1);
896 }
897 break;
898 case 3: /* Synchronous Fault Status Register with Clear */
899 case 4: /* Synchronous Fault Address Register */
900 break;
901 case 0x10: /* TLB Replacement Control Register */
902 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
903 break;
904 case 0x13: /* Synchronous Fault Status Register with Read
905 and Clear */
906 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
907 break;
908 case 0x14: /* Synchronous Fault Address Register */
909 env->mmuregs[4] = val;
910 break;
911 default:
912 env->mmuregs[reg] = val;
913 break;
914 }
915 if (oldreg != env->mmuregs[reg]) {
916 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
917 reg, oldreg, env->mmuregs[reg]);
918 }
919 #ifdef DEBUG_MMU
920 dump_mmu(stdout, fprintf, env);
921 #endif
922 }
923 break;
924 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
925 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
926 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
927 break;
928 case ASI_USERDATA: /* User data access */
929 switch (size) {
930 case 1:
931 cpu_stb_user(env, addr, val);
932 break;
933 case 2:
934 cpu_stw_user(env, addr, val);
935 break;
936 default:
937 case 4:
938 cpu_stl_user(env, addr, val);
939 break;
940 case 8:
941 cpu_stq_user(env, addr, val);
942 break;
943 }
944 break;
945 case ASI_KERNELDATA: /* Supervisor data access */
946 case ASI_P:
947 switch (size) {
948 case 1:
949 cpu_stb_kernel(env, addr, val);
950 break;
951 case 2:
952 cpu_stw_kernel(env, addr, val);
953 break;
954 default:
955 case 4:
956 cpu_stl_kernel(env, addr, val);
957 break;
958 case 8:
959 cpu_stq_kernel(env, addr, val);
960 break;
961 }
962 break;
963 case ASI_M_TXTC_TAG: /* I-cache tag */
964 case ASI_M_TXTC_DATA: /* I-cache data */
965 case ASI_M_DATAC_TAG: /* D-cache tag */
966 case ASI_M_DATAC_DATA: /* D-cache data */
967 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */
968 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */
969 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */
970 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */
971 case ASI_M_FLUSH_USER: /* I/D-cache flush user */
972 break;
973 case ASI_M_BCOPY: /* Block copy, sta access */
974 {
975 /* val = src
976 addr = dst
977 copy 32 bytes */
978 unsigned int i;
979 uint32_t src = val & ~3, dst = addr & ~3, temp;
980
981 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
982 temp = cpu_ldl_kernel(env, src);
983 cpu_stl_kernel(env, dst, temp);
984 }
985 }
986 break;
987 case ASI_M_BFILL: /* Block fill, stda access */
988 {
989 /* addr = dst
990 fill 32 bytes with val */
991 unsigned int i;
992 uint32_t dst = addr & 7;
993
994 for (i = 0; i < 32; i += 8, dst += 8) {
995 cpu_stq_kernel(env, dst, val);
996 }
997 }
998 break;
999 case ASI_M_BYPASS: /* MMU passthrough */
1000 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1001 {
1002 switch (size) {
1003 case 1:
1004 stb_phys(cs->as, addr, val);
1005 break;
1006 case 2:
1007 stw_phys(cs->as, addr, val);
1008 break;
1009 case 4:
1010 default:
1011 stl_phys(cs->as, addr, val);
1012 break;
1013 case 8:
1014 stq_phys(cs->as, addr, val);
1015 break;
1016 }
1017 }
1018 break;
1019 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1020 {
1021 switch (size) {
1022 case 1:
1023 stb_phys(cs->as, (hwaddr)addr
1024 | ((hwaddr)(asi & 0xf) << 32), val);
1025 break;
1026 case 2:
1027 stw_phys(cs->as, (hwaddr)addr
1028 | ((hwaddr)(asi & 0xf) << 32), val);
1029 break;
1030 case 4:
1031 default:
1032 stl_phys(cs->as, (hwaddr)addr
1033 | ((hwaddr)(asi & 0xf) << 32), val);
1034 break;
1035 case 8:
1036 stq_phys(cs->as, (hwaddr)addr
1037 | ((hwaddr)(asi & 0xf) << 32), val);
1038 break;
1039 }
1040 }
1041 break;
1042 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1043 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1044 Turbosparc snoop RAM */
1045 case 0x32: /* store buffer control or Turbosparc page table
1046 descriptor diagnostic */
1047 case 0x36: /* I-cache flash clear */
1048 case 0x37: /* D-cache flash clear */
1049 break;
1050 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1051 {
1052 int reg = (addr >> 8) & 3;
1053
1054 switch (reg) {
1055 case 0: /* Breakpoint Value (Addr) */
1056 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1057 break;
1058 case 1: /* Breakpoint Mask */
1059 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1060 break;
1061 case 2: /* Breakpoint Control */
1062 env->mmubpregs[reg] = (val & 0x7fULL);
1063 break;
1064 case 3: /* Breakpoint Status */
1065 env->mmubpregs[reg] = (val & 0xfULL);
1066 break;
1067 }
1068 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1069 env->mmuregs[reg]);
1070 }
1071 break;
1072 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1073 env->mmubpctrv = val & 0xffffffff;
1074 break;
1075 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1076 env->mmubpctrc = val & 0x3;
1077 break;
1078 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1079 env->mmubpctrs = val & 0x3;
1080 break;
1081 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1082 env->mmubpaction = val & 0x1fff;
1083 break;
1084 case ASI_USERTXT: /* User code access, XXX */
1085 case ASI_KERNELTXT: /* Supervisor code access, XXX */
1086 default:
1087 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1088 addr, true, false, asi, size);
1089 break;
1090 }
1091 #ifdef DEBUG_ASI
1092 dump_asi("write", addr, asi, size, val);
1093 #endif
1094 }
1095
1096 #endif /* CONFIG_USER_ONLY */
1097 #else /* TARGET_SPARC64 */
1098
1099 #ifdef CONFIG_USER_ONLY
1100 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1101 int sign)
1102 {
1103 uint64_t ret = 0;
1104 #if defined(DEBUG_ASI)
1105 target_ulong last_addr = addr;
1106 #endif
1107
1108 if (asi < 0x80) {
1109 helper_raise_exception(env, TT_PRIV_ACT);
1110 }
1111
1112 helper_check_align(env, addr, size - 1);
1113 addr = asi_address_mask(env, asi, addr);
1114
1115 switch (asi) {
1116 case ASI_PNF: /* Primary no-fault */
1117 case ASI_PNFL: /* Primary no-fault LE */
1118 if (page_check_range(addr, size, PAGE_READ) == -1) {
1119 #ifdef DEBUG_ASI
1120 dump_asi("read ", last_addr, asi, size, ret);
1121 #endif
1122 return 0;
1123 }
1124 /* Fall through */
1125 case ASI_P: /* Primary */
1126 case ASI_PL: /* Primary LE */
1127 {
1128 switch (size) {
1129 case 1:
1130 ret = cpu_ldub_data(env, addr);
1131 break;
1132 case 2:
1133 ret = cpu_lduw_data(env, addr);
1134 break;
1135 case 4:
1136 ret = cpu_ldl_data(env, addr);
1137 break;
1138 default:
1139 case 8:
1140 ret = cpu_ldq_data(env, addr);
1141 break;
1142 }
1143 }
1144 break;
1145 case ASI_SNF: /* Secondary no-fault */
1146 case ASI_SNFL: /* Secondary no-fault LE */
1147 if (page_check_range(addr, size, PAGE_READ) == -1) {
1148 #ifdef DEBUG_ASI
1149 dump_asi("read ", last_addr, asi, size, ret);
1150 #endif
1151 return 0;
1152 }
1153 /* Fall through */
1154 case ASI_S: /* Secondary */
1155 case ASI_SL: /* Secondary LE */
1156 /* XXX */
1157 break;
1158 default:
1159 break;
1160 }
1161
1162 /* Convert from little endian */
1163 switch (asi) {
1164 case ASI_PL: /* Primary LE */
1165 case ASI_SL: /* Secondary LE */
1166 case ASI_PNFL: /* Primary no-fault LE */
1167 case ASI_SNFL: /* Secondary no-fault LE */
1168 switch (size) {
1169 case 2:
1170 ret = bswap16(ret);
1171 break;
1172 case 4:
1173 ret = bswap32(ret);
1174 break;
1175 case 8:
1176 ret = bswap64(ret);
1177 break;
1178 default:
1179 break;
1180 }
1181 default:
1182 break;
1183 }
1184
1185 /* Convert to signed number */
1186 if (sign) {
1187 switch (size) {
1188 case 1:
1189 ret = (int8_t) ret;
1190 break;
1191 case 2:
1192 ret = (int16_t) ret;
1193 break;
1194 case 4:
1195 ret = (int32_t) ret;
1196 break;
1197 default:
1198 break;
1199 }
1200 }
1201 #ifdef DEBUG_ASI
1202 dump_asi("read ", last_addr, asi, size, ret);
1203 #endif
1204 return ret;
1205 }
1206
1207 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1208 int asi, int size)
1209 {
1210 #ifdef DEBUG_ASI
1211 dump_asi("write", addr, asi, size, val);
1212 #endif
1213 if (asi < 0x80) {
1214 helper_raise_exception(env, TT_PRIV_ACT);
1215 }
1216
1217 helper_check_align(env, addr, size - 1);
1218 addr = asi_address_mask(env, asi, addr);
1219
1220 /* Convert to little endian */
1221 switch (asi) {
1222 case ASI_PL: /* Primary LE */
1223 case ASI_SL: /* Secondary LE */
1224 switch (size) {
1225 case 2:
1226 val = bswap16(val);
1227 break;
1228 case 4:
1229 val = bswap32(val);
1230 break;
1231 case 8:
1232 val = bswap64(val);
1233 break;
1234 default:
1235 break;
1236 }
1237 default:
1238 break;
1239 }
1240
1241 switch (asi) {
1242 case ASI_P: /* Primary */
1243 case ASI_PL: /* Primary LE */
1244 {
1245 switch (size) {
1246 case 1:
1247 cpu_stb_data(env, addr, val);
1248 break;
1249 case 2:
1250 cpu_stw_data(env, addr, val);
1251 break;
1252 case 4:
1253 cpu_stl_data(env, addr, val);
1254 break;
1255 case 8:
1256 default:
1257 cpu_stq_data(env, addr, val);
1258 break;
1259 }
1260 }
1261 break;
1262 case ASI_S: /* Secondary */
1263 case ASI_SL: /* Secondary LE */
1264 /* XXX */
1265 return;
1266
1267 case ASI_PNF: /* Primary no-fault, RO */
1268 case ASI_SNF: /* Secondary no-fault, RO */
1269 case ASI_PNFL: /* Primary no-fault LE, RO */
1270 case ASI_SNFL: /* Secondary no-fault LE, RO */
1271 default:
1272 helper_raise_exception(env, TT_DATA_ACCESS);
1273 return;
1274 }
1275 }
1276
1277 #else /* CONFIG_USER_ONLY */
1278
1279 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1280 int sign)
1281 {
1282 CPUState *cs = CPU(sparc_env_get_cpu(env));
1283 uint64_t ret = 0;
1284 #if defined(DEBUG_ASI)
1285 target_ulong last_addr = addr;
1286 #endif
1287
1288 asi &= 0xff;
1289
1290 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1291 || (cpu_has_hypervisor(env)
1292 && asi >= 0x30 && asi < 0x80
1293 && !(env->hpstate & HS_PRIV))) {
1294 helper_raise_exception(env, TT_PRIV_ACT);
1295 }
1296
1297 helper_check_align(env, addr, size - 1);
1298 addr = asi_address_mask(env, asi, addr);
1299
1300 /* process nonfaulting loads first */
1301 if ((asi & 0xf6) == 0x82) {
1302 int mmu_idx;
1303
1304 /* secondary space access has lowest asi bit equal to 1 */
1305 if (env->pstate & PS_PRIV) {
1306 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1307 } else {
1308 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1309 }
1310
1311 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1312 #ifdef DEBUG_ASI
1313 dump_asi("read ", last_addr, asi, size, ret);
1314 #endif
1315 /* env->exception_index is set in get_physical_address_data(). */
1316 helper_raise_exception(env, cs->exception_index);
1317 }
1318
1319 /* convert nonfaulting load ASIs to normal load ASIs */
1320 asi &= ~0x02;
1321 }
1322
1323 switch (asi) {
1324 case ASI_AIUP: /* As if user primary */
1325 case ASI_AIUS: /* As if user secondary */
1326 case ASI_AIUPL: /* As if user primary LE */
1327 case ASI_AIUSL: /* As if user secondary LE */
1328 case ASI_P: /* Primary */
1329 case ASI_S: /* Secondary */
1330 case ASI_PL: /* Primary LE */
1331 case ASI_SL: /* Secondary LE */
1332 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1333 if (cpu_hypervisor_mode(env)) {
1334 switch (size) {
1335 case 1:
1336 ret = cpu_ldub_hypv(env, addr);
1337 break;
1338 case 2:
1339 ret = cpu_lduw_hypv(env, addr);
1340 break;
1341 case 4:
1342 ret = cpu_ldl_hypv(env, addr);
1343 break;
1344 default:
1345 case 8:
1346 ret = cpu_ldq_hypv(env, addr);
1347 break;
1348 }
1349 } else {
1350 /* secondary space access has lowest asi bit equal to 1 */
1351 if (asi & 1) {
1352 switch (size) {
1353 case 1:
1354 ret = cpu_ldub_kernel_secondary(env, addr);
1355 break;
1356 case 2:
1357 ret = cpu_lduw_kernel_secondary(env, addr);
1358 break;
1359 case 4:
1360 ret = cpu_ldl_kernel_secondary(env, addr);
1361 break;
1362 default:
1363 case 8:
1364 ret = cpu_ldq_kernel_secondary(env, addr);
1365 break;
1366 }
1367 } else {
1368 switch (size) {
1369 case 1:
1370 ret = cpu_ldub_kernel(env, addr);
1371 break;
1372 case 2:
1373 ret = cpu_lduw_kernel(env, addr);
1374 break;
1375 case 4:
1376 ret = cpu_ldl_kernel(env, addr);
1377 break;
1378 default:
1379 case 8:
1380 ret = cpu_ldq_kernel(env, addr);
1381 break;
1382 }
1383 }
1384 }
1385 } else {
1386 /* secondary space access has lowest asi bit equal to 1 */
1387 if (asi & 1) {
1388 switch (size) {
1389 case 1:
1390 ret = cpu_ldub_user_secondary(env, addr);
1391 break;
1392 case 2:
1393 ret = cpu_lduw_user_secondary(env, addr);
1394 break;
1395 case 4:
1396 ret = cpu_ldl_user_secondary(env, addr);
1397 break;
1398 default:
1399 case 8:
1400 ret = cpu_ldq_user_secondary(env, addr);
1401 break;
1402 }
1403 } else {
1404 switch (size) {
1405 case 1:
1406 ret = cpu_ldub_user(env, addr);
1407 break;
1408 case 2:
1409 ret = cpu_lduw_user(env, addr);
1410 break;
1411 case 4:
1412 ret = cpu_ldl_user(env, addr);
1413 break;
1414 default:
1415 case 8:
1416 ret = cpu_ldq_user(env, addr);
1417 break;
1418 }
1419 }
1420 }
1421 break;
1422 case ASI_REAL: /* Bypass */
1423 case ASI_REAL_IO: /* Bypass, non-cacheable */
1424 case ASI_REAL_L: /* Bypass LE */
1425 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1426 {
1427 switch (size) {
1428 case 1:
1429 ret = ldub_phys(cs->as, addr);
1430 break;
1431 case 2:
1432 ret = lduw_phys(cs->as, addr);
1433 break;
1434 case 4:
1435 ret = ldl_phys(cs->as, addr);
1436 break;
1437 default:
1438 case 8:
1439 ret = ldq_phys(cs->as, addr);
1440 break;
1441 }
1442 break;
1443 }
1444 case ASI_N: /* Nucleus */
1445 case ASI_NL: /* Nucleus Little Endian (LE) */
1446 {
1447 switch (size) {
1448 case 1:
1449 ret = cpu_ldub_nucleus(env, addr);
1450 break;
1451 case 2:
1452 ret = cpu_lduw_nucleus(env, addr);
1453 break;
1454 case 4:
1455 ret = cpu_ldl_nucleus(env, addr);
1456 break;
1457 default:
1458 case 8:
1459 ret = cpu_ldq_nucleus(env, addr);
1460 break;
1461 }
1462 break;
1463 }
1464 case ASI_UPA_CONFIG: /* UPA config */
1465 /* XXX */
1466 break;
1467 case ASI_LSU_CONTROL: /* LSU */
1468 ret = env->lsu;
1469 break;
1470 case ASI_IMMU: /* I-MMU regs */
1471 {
1472 int reg = (addr >> 3) & 0xf;
1473
1474 if (reg == 0) {
1475 /* I-TSB Tag Target register */
1476 ret = ultrasparc_tag_target(env->immu.tag_access);
1477 } else {
1478 ret = env->immuregs[reg];
1479 }
1480
1481 break;
1482 }
1483 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
1484 {
1485 /* env->immuregs[5] holds I-MMU TSB register value
1486 env->immuregs[6] holds I-MMU Tag Access register value */
1487 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1488 8*1024);
1489 break;
1490 }
1491 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
1492 {
1493 /* env->immuregs[5] holds I-MMU TSB register value
1494 env->immuregs[6] holds I-MMU Tag Access register value */
1495 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1496 64*1024);
1497 break;
1498 }
1499 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1500 {
1501 int reg = (addr >> 3) & 0x3f;
1502
1503 ret = env->itlb[reg].tte;
1504 break;
1505 }
1506 case ASI_ITLB_TAG_READ: /* I-MMU tag read */
1507 {
1508 int reg = (addr >> 3) & 0x3f;
1509
1510 ret = env->itlb[reg].tag;
1511 break;
1512 }
1513 case ASI_DMMU: /* D-MMU regs */
1514 {
1515 int reg = (addr >> 3) & 0xf;
1516
1517 if (reg == 0) {
1518 /* D-TSB Tag Target register */
1519 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1520 } else {
1521 ret = env->dmmuregs[reg];
1522 }
1523 break;
1524 }
1525 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
1526 {
1527 /* env->dmmuregs[5] holds D-MMU TSB register value
1528 env->dmmuregs[6] holds D-MMU Tag Access register value */
1529 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1530 8*1024);
1531 break;
1532 }
1533 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
1534 {
1535 /* env->dmmuregs[5] holds D-MMU TSB register value
1536 env->dmmuregs[6] holds D-MMU Tag Access register value */
1537 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1538 64*1024);
1539 break;
1540 }
1541 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1542 {
1543 int reg = (addr >> 3) & 0x3f;
1544
1545 ret = env->dtlb[reg].tte;
1546 break;
1547 }
1548 case ASI_DTLB_TAG_READ: /* D-MMU tag read */
1549 {
1550 int reg = (addr >> 3) & 0x3f;
1551
1552 ret = env->dtlb[reg].tag;
1553 break;
1554 }
1555 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1556 break;
1557 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1558 ret = env->ivec_status;
1559 break;
1560 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1561 {
1562 int reg = (addr >> 4) & 0x3;
1563 if (reg < 3) {
1564 ret = env->ivec_data[reg];
1565 }
1566 break;
1567 }
1568 case ASI_DCACHE_DATA: /* D-cache data */
1569 case ASI_DCACHE_TAG: /* D-cache tag access */
1570 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1571 case ASI_AFSR: /* E-cache asynchronous fault status */
1572 case ASI_AFAR: /* E-cache asynchronous fault address */
1573 case ASI_EC_TAG_DATA: /* E-cache tag data */
1574 case ASI_IC_INSTR: /* I-cache instruction access */
1575 case ASI_IC_TAG: /* I-cache tag access */
1576 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1577 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1578 case ASI_EC_W: /* E-cache tag */
1579 case ASI_EC_R: /* E-cache tag */
1580 break;
1581 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
1582 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
1583 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
1584 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
1585 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
1586 case ASI_INTR_W: /* Interrupt vector, WO */
1587 default:
1588 cpu_unassigned_access(cs, addr, false, false, 1, size);
1589 ret = 0;
1590 break;
1591
1592 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1593 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1594 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1595 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1596 case ASI_TWINX_REAL: /* Real address, twinx */
1597 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1598 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1599 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1600 case ASI_TWINX_N: /* Nucleus, twinx */
1601 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1602 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1603 case ASI_TWINX_P: /* Primary, twinx */
1604 case ASI_TWINX_PL: /* Primary, twinx, LE */
1605 case ASI_TWINX_S: /* Secondary, twinx */
1606 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1607 /* These are all 128-bit atomic; only ldda (now ldtxa) allowed */
1608 helper_raise_exception(env, TT_ILL_INSN);
1609 return 0;
1610 }
1611
1612 /* Convert from little endian */
1613 switch (asi) {
1614 case ASI_NL: /* Nucleus Little Endian (LE) */
1615 case ASI_AIUPL: /* As if user primary LE */
1616 case ASI_AIUSL: /* As if user secondary LE */
1617 case ASI_REAL_L: /* Bypass LE */
1618 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1619 case ASI_PL: /* Primary LE */
1620 case ASI_SL: /* Secondary LE */
1621 switch(size) {
1622 case 2:
1623 ret = bswap16(ret);
1624 break;
1625 case 4:
1626 ret = bswap32(ret);
1627 break;
1628 case 8:
1629 ret = bswap64(ret);
1630 break;
1631 default:
1632 break;
1633 }
1634 default:
1635 break;
1636 }
1637
1638 /* Convert to signed number */
1639 if (sign) {
1640 switch (size) {
1641 case 1:
1642 ret = (int8_t) ret;
1643 break;
1644 case 2:
1645 ret = (int16_t) ret;
1646 break;
1647 case 4:
1648 ret = (int32_t) ret;
1649 break;
1650 default:
1651 break;
1652 }
1653 }
1654 #ifdef DEBUG_ASI
1655 dump_asi("read ", last_addr, asi, size, ret);
1656 #endif
1657 return ret;
1658 }
1659
1660 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1661 int asi, int size)
1662 {
1663 SPARCCPU *cpu = sparc_env_get_cpu(env);
1664 CPUState *cs = CPU(cpu);
1665
1666 #ifdef DEBUG_ASI
1667 dump_asi("write", addr, asi, size, val);
1668 #endif
1669
1670 asi &= 0xff;
1671
1672 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1673 || (cpu_has_hypervisor(env)
1674 && asi >= 0x30 && asi < 0x80
1675 && !(env->hpstate & HS_PRIV))) {
1676 helper_raise_exception(env, TT_PRIV_ACT);
1677 }
1678
1679 helper_check_align(env, addr, size - 1);
1680 addr = asi_address_mask(env, asi, addr);
1681
1682 /* Convert to little endian */
1683 switch (asi) {
1684 case ASI_NL: /* Nucleus Little Endian (LE) */
1685 case ASI_AIUPL: /* As if user primary LE */
1686 case ASI_AIUSL: /* As if user secondary LE */
1687 case ASI_REAL_L: /* Bypass LE */
1688 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1689 case ASI_PL: /* Primary LE */
1690 case ASI_SL: /* Secondary LE */
1691 switch (size) {
1692 case 2:
1693 val = bswap16(val);
1694 break;
1695 case 4:
1696 val = bswap32(val);
1697 break;
1698 case 8:
1699 val = bswap64(val);
1700 break;
1701 default:
1702 break;
1703 }
1704 default:
1705 break;
1706 }
1707
1708 switch (asi) {
1709 case ASI_AIUP: /* As if user primary */
1710 case ASI_AIUS: /* As if user secondary */
1711 case ASI_AIUPL: /* As if user primary LE */
1712 case ASI_AIUSL: /* As if user secondary LE */
1713 case ASI_P: /* Primary */
1714 case ASI_S: /* Secondary */
1715 case ASI_PL: /* Primary LE */
1716 case ASI_SL: /* Secondary LE */
1717 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1718 if (cpu_hypervisor_mode(env)) {
1719 switch (size) {
1720 case 1:
1721 cpu_stb_hypv(env, addr, val);
1722 break;
1723 case 2:
1724 cpu_stw_hypv(env, addr, val);
1725 break;
1726 case 4:
1727 cpu_stl_hypv(env, addr, val);
1728 break;
1729 case 8:
1730 default:
1731 cpu_stq_hypv(env, addr, val);
1732 break;
1733 }
1734 } else {
1735 /* secondary space access has lowest asi bit equal to 1 */
1736 if (asi & 1) {
1737 switch (size) {
1738 case 1:
1739 cpu_stb_kernel_secondary(env, addr, val);
1740 break;
1741 case 2:
1742 cpu_stw_kernel_secondary(env, addr, val);
1743 break;
1744 case 4:
1745 cpu_stl_kernel_secondary(env, addr, val);
1746 break;
1747 case 8:
1748 default:
1749 cpu_stq_kernel_secondary(env, addr, val);
1750 break;
1751 }
1752 } else {
1753 switch (size) {
1754 case 1:
1755 cpu_stb_kernel(env, addr, val);
1756 break;
1757 case 2:
1758 cpu_stw_kernel(env, addr, val);
1759 break;
1760 case 4:
1761 cpu_stl_kernel(env, addr, val);
1762 break;
1763 case 8:
1764 default:
1765 cpu_stq_kernel(env, addr, val);
1766 break;
1767 }
1768 }
1769 }
1770 } else {
1771 /* secondary space access has lowest asi bit equal to 1 */
1772 if (asi & 1) {
1773 switch (size) {
1774 case 1:
1775 cpu_stb_user_secondary(env, addr, val);
1776 break;
1777 case 2:
1778 cpu_stw_user_secondary(env, addr, val);
1779 break;
1780 case 4:
1781 cpu_stl_user_secondary(env, addr, val);
1782 break;
1783 case 8:
1784 default:
1785 cpu_stq_user_secondary(env, addr, val);
1786 break;
1787 }
1788 } else {
1789 switch (size) {
1790 case 1:
1791 cpu_stb_user(env, addr, val);
1792 break;
1793 case 2:
1794 cpu_stw_user(env, addr, val);
1795 break;
1796 case 4:
1797 cpu_stl_user(env, addr, val);
1798 break;
1799 case 8:
1800 default:
1801 cpu_stq_user(env, addr, val);
1802 break;
1803 }
1804 }
1805 }
1806 break;
1807 case ASI_REAL: /* Bypass */
1808 case ASI_REAL_IO: /* Bypass, non-cacheable */
1809 case ASI_REAL_L: /* Bypass LE */
1810 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1811 {
1812 switch (size) {
1813 case 1:
1814 stb_phys(cs->as, addr, val);
1815 break;
1816 case 2:
1817 stw_phys(cs->as, addr, val);
1818 break;
1819 case 4:
1820 stl_phys(cs->as, addr, val);
1821 break;
1822 case 8:
1823 default:
1824 stq_phys(cs->as, addr, val);
1825 break;
1826 }
1827 }
1828 return;
1829 case ASI_N: /* Nucleus */
1830 case ASI_NL: /* Nucleus Little Endian (LE) */
1831 {
1832 switch (size) {
1833 case 1:
1834 cpu_stb_nucleus(env, addr, val);
1835 break;
1836 case 2:
1837 cpu_stw_nucleus(env, addr, val);
1838 break;
1839 case 4:
1840 cpu_stl_nucleus(env, addr, val);
1841 break;
1842 default:
1843 case 8:
1844 cpu_stq_nucleus(env, addr, val);
1845 break;
1846 }
1847 break;
1848 }
1849
1850 case ASI_UPA_CONFIG: /* UPA config */
1851 /* XXX */
1852 return;
1853 case ASI_LSU_CONTROL: /* LSU */
1854 {
1855 uint64_t oldreg;
1856
1857 oldreg = env->lsu;
1858 env->lsu = val & (DMMU_E | IMMU_E);
1859 /* Mappings generated during D/I MMU disabled mode are
1860 invalid in normal mode */
1861 if (oldreg != env->lsu) {
1862 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1863 oldreg, env->lsu);
1864 #ifdef DEBUG_MMU
1865 dump_mmu(stdout, fprintf, env);
1866 #endif
1867 tlb_flush(CPU(cpu), 1);
1868 }
1869 return;
1870 }
1871 case ASI_IMMU: /* I-MMU regs */
1872 {
1873 int reg = (addr >> 3) & 0xf;
1874 uint64_t oldreg;
1875
1876 oldreg = env->immuregs[reg];
1877 switch (reg) {
1878 case 0: /* RO */
1879 return;
1880 case 1: /* Not in I-MMU */
1881 case 2:
1882 return;
1883 case 3: /* SFSR */
1884 if ((val & 1) == 0) {
1885 val = 0; /* Clear SFSR */
1886 }
1887 env->immu.sfsr = val;
1888 break;
1889 case 4: /* RO */
1890 return;
1891 case 5: /* TSB access */
1892 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1893 PRIx64 "\n", env->immu.tsb, val);
1894 env->immu.tsb = val;
1895 break;
1896 case 6: /* Tag access */
1897 env->immu.tag_access = val;
1898 break;
1899 case 7:
1900 case 8:
1901 return;
1902 default:
1903 break;
1904 }
1905
1906 if (oldreg != env->immuregs[reg]) {
1907 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1908 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1909 }
1910 #ifdef DEBUG_MMU
1911 dump_mmu(stdout, fprintf, env);
1912 #endif
1913 return;
1914 }
1915 case ASI_ITLB_DATA_IN: /* I-MMU data in */
1916 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1917 return;
1918 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1919 {
1920 /* TODO: auto demap */
1921
1922 unsigned int i = (addr >> 3) & 0x3f;
1923
1924 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1925
1926 #ifdef DEBUG_MMU
1927 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1928 dump_mmu(stdout, fprintf, env);
1929 #endif
1930 return;
1931 }
1932 case ASI_IMMU_DEMAP: /* I-MMU demap */
1933 demap_tlb(env->itlb, addr, "immu", env);
1934 return;
1935 case ASI_DMMU: /* D-MMU regs */
1936 {
1937 int reg = (addr >> 3) & 0xf;
1938 uint64_t oldreg;
1939
1940 oldreg = env->dmmuregs[reg];
1941 switch (reg) {
1942 case 0: /* RO */
1943 case 4:
1944 return;
1945 case 3: /* SFSR */
1946 if ((val & 1) == 0) {
1947 val = 0; /* Clear SFSR, Fault address */
1948 env->dmmu.sfar = 0;
1949 }
1950 env->dmmu.sfsr = val;
1951 break;
1952 case 1: /* Primary context */
1953 env->dmmu.mmu_primary_context = val;
1954 /* can be optimized to only flush MMU_USER_IDX
1955 and MMU_KERNEL_IDX entries */
1956 tlb_flush(CPU(cpu), 1);
1957 break;
1958 case 2: /* Secondary context */
1959 env->dmmu.mmu_secondary_context = val;
1960 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1961 and MMU_KERNEL_SECONDARY_IDX entries */
1962 tlb_flush(CPU(cpu), 1);
1963 break;
1964 case 5: /* TSB access */
1965 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1966 PRIx64 "\n", env->dmmu.tsb, val);
1967 env->dmmu.tsb = val;
1968 break;
1969 case 6: /* Tag access */
1970 env->dmmu.tag_access = val;
1971 break;
1972 case 7: /* Virtual Watchpoint */
1973 case 8: /* Physical Watchpoint */
1974 default:
1975 env->dmmuregs[reg] = val;
1976 break;
1977 }
1978
1979 if (oldreg != env->dmmuregs[reg]) {
1980 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1981 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1982 }
1983 #ifdef DEBUG_MMU
1984 dump_mmu(stdout, fprintf, env);
1985 #endif
1986 return;
1987 }
1988 case ASI_DTLB_DATA_IN: /* D-MMU data in */
1989 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1990 return;
1991 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1992 {
1993 unsigned int i = (addr >> 3) & 0x3f;
1994
1995 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1996
1997 #ifdef DEBUG_MMU
1998 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1999 dump_mmu(stdout, fprintf, env);
2000 #endif
2001 return;
2002 }
2003 case ASI_DMMU_DEMAP: /* D-MMU demap */
2004 demap_tlb(env->dtlb, addr, "dmmu", env);
2005 return;
2006 case ASI_INTR_RECEIVE: /* Interrupt data receive */
2007 env->ivec_status = val & 0x20;
2008 return;
2009 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
2010 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
2011 case ASI_TWINX_AIUP: /* As if user primary, twinx */
2012 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
2013 case ASI_TWINX_REAL: /* Real address, twinx */
2014 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
2015 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
2016 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
2017 case ASI_TWINX_N: /* Nucleus, twinx */
2018 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
2019 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
2020 case ASI_TWINX_P: /* Primary, twinx */
2021 case ASI_TWINX_PL: /* Primary, twinx, LE */
2022 case ASI_TWINX_S: /* Secondary, twinx */
2023 case ASI_TWINX_SL: /* Secondary, twinx, LE */
2024 /* Only stda allowed */
2025 helper_raise_exception(env, TT_ILL_INSN);
2026 return;
2027 case ASI_DCACHE_DATA: /* D-cache data */
2028 case ASI_DCACHE_TAG: /* D-cache tag access */
2029 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
2030 case ASI_AFSR: /* E-cache asynchronous fault status */
2031 case ASI_AFAR: /* E-cache asynchronous fault address */
2032 case ASI_EC_TAG_DATA: /* E-cache tag data */
2033 case ASI_IC_INSTR: /* I-cache instruction access */
2034 case ASI_IC_TAG: /* I-cache tag access */
2035 case ASI_IC_PRE_DECODE: /* I-cache predecode */
2036 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
2037 case ASI_EC_W: /* E-cache tag */
2038 case ASI_EC_R: /* E-cache tag */
2039 return;
2040 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
2041 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
2042 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
2043 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
2044 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
2045 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
2046 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
2047 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
2048 case ASI_INTR_R: /* Incoming interrupt vector, RO */
2049 case ASI_PNF: /* Primary no-fault, RO */
2050 case ASI_SNF: /* Secondary no-fault, RO */
2051 case ASI_PNFL: /* Primary no-fault LE, RO */
2052 case ASI_SNFL: /* Secondary no-fault LE, RO */
2053 default:
2054 cpu_unassigned_access(cs, addr, true, false, 1, size);
2055 return;
2056 }
2057 }
2058 #endif /* CONFIG_USER_ONLY */
2059
2060 /* 128-bit LDDA; result returned in QT0. */
2061 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi)
2062 {
2063 uint64_t h, l;
2064
2065 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2066 || (cpu_has_hypervisor(env)
2067 && asi >= 0x30 && asi < 0x80
2068 && !(env->hpstate & HS_PRIV))) {
2069 helper_raise_exception(env, TT_PRIV_ACT);
2070 }
2071
2072 addr = asi_address_mask(env, asi, addr);
2073
2074 switch (asi) {
2075 #if !defined(CONFIG_USER_ONLY)
2076 case ASI_TWINX_AIUP: /* As if user primary, twinx */
2077 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
2078 helper_check_align(env, addr, 0xf);
2079 h = cpu_ldq_user(env, addr);
2080 l = cpu_ldq_user(env, addr + 8);
2081 break;
2082 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
2083 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
2084 helper_check_align(env, addr, 0xf);
2085 h = cpu_ldq_user_secondary(env, addr);
2086 l = cpu_ldq_user_secondary(env, addr + 8);
2087 break;
2088 case ASI_TWINX_REAL: /* Real address, twinx */
2089 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
2090 helper_check_align(env, addr, 0xf);
2091 {
2092 CPUState *cs = CPU(sparc_env_get_cpu(env));
2093 h = ldq_phys(cs->as, addr);
2094 l = ldq_phys(cs->as, addr + 8);
2095 }
2096 break;
2097 case ASI_NUCLEUS_QUAD_LDD:
2098 case ASI_NUCLEUS_QUAD_LDD_L:
2099 case ASI_TWINX_N: /* Nucleus, twinx */
2100 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
2101 helper_check_align(env, addr, 0xf);
2102 h = cpu_ldq_nucleus(env, addr);
2103 l = cpu_ldq_nucleus(env, addr + 8);
2104 break;
2105 case ASI_TWINX_S: /* Secondary, twinx */
2106 case ASI_TWINX_SL: /* Secondary, twinx, LE */
2107 if (!cpu_hypervisor_mode(env)) {
2108 helper_check_align(env, addr, 0xf);
2109 if (env->pstate & PS_PRIV) {
2110 h = cpu_ldq_kernel_secondary(env, addr);
2111 l = cpu_ldq_kernel_secondary(env, addr + 8);
2112 } else {
2113 h = cpu_ldq_user_secondary(env, addr);
2114 l = cpu_ldq_user_secondary(env, addr + 8);
2115 }
2116 break;
2117 }
2118 /* fallthru */
2119 case ASI_TWINX_P: /* Primary, twinx */
2120 case ASI_TWINX_PL: /* Primary, twinx, LE */
2121 helper_check_align(env, addr, 0xf);
2122 h = cpu_ldq_data(env, addr);
2123 l = cpu_ldq_data(env, addr + 8);
2124 break;
2125 #else
2126 case ASI_TWINX_P: /* Primary, twinx */
2127 case ASI_TWINX_PL: /* Primary, twinx, LE */
2128 case ASI_TWINX_S: /* Primary, twinx */
2129 case ASI_TWINX_SL: /* Primary, twinx, LE */
2130 /* ??? Should be available, but we need to implement
2131 an atomic 128-bit load. */
2132 helper_raise_exception(env, TT_PRIV_ACT);
2133 #endif
2134 default:
2135 /* Non-twinx asi, so this is the legacy ldda insn, which
2136 performs two word sized operations. */
2137 /* ??? The UA2011 manual recommends emulating this with
2138 a single 64-bit load. However, LE asis *are* treated
2139 as two 32-bit loads individually byte swapped. */
2140 helper_check_align(env, addr, 0x7);
2141 QT0.high = (uint32_t)helper_ld_asi(env, addr, asi, 4, 0);
2142 QT0.low = (uint32_t)helper_ld_asi(env, addr + 4, asi, 4, 0);
2143 return;
2144 }
2145
2146 if (asi & 8) {
2147 h = bswap64(h);
2148 l = bswap64(l);
2149 }
2150 QT0.high = h;
2151 QT0.low = l;
2152 }
2153
2154 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2155 int rd)
2156 {
2157 unsigned int i;
2158 target_ulong val;
2159
2160 helper_check_align(env, addr, 3);
2161 addr = asi_address_mask(env, asi, addr);
2162
2163 switch (asi) {
2164 case ASI_BLK_P: /* UA2007/JPS1 Block load primary */
2165 case ASI_BLK_S: /* UA2007/JPS1 Block load secondary */
2166 case ASI_BLK_PL: /* UA2007/JPS1 Block load primary LE */
2167 case ASI_BLK_SL: /* UA2007/JPS1 Block load secondary LE */
2168 if (rd & 7) {
2169 helper_raise_exception(env, TT_ILL_INSN);
2170 return;
2171 }
2172 helper_check_align(env, addr, 0x3f);
2173 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2174 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2175 }
2176 return;
2177
2178 case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
2179 case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
2180 case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
2181 case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
2182 case ASI_BLK_AIUP: /* JPS1 Block load primary, user privilege */
2183 case ASI_BLK_AIUS: /* JPS1 Block load secondary, user privilege */
2184 case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
2185 case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
2186 if (rd & 7) {
2187 helper_raise_exception(env, TT_ILL_INSN);
2188 return;
2189 }
2190 helper_check_align(env, addr, 0x3f);
2191 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2192 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2193 }
2194 return;
2195
2196 default:
2197 break;
2198 }
2199
2200 switch (size) {
2201 default:
2202 case 4:
2203 val = helper_ld_asi(env, addr, asi, size, 0);
2204 if (rd & 1) {
2205 env->fpr[rd / 2].l.lower = val;
2206 } else {
2207 env->fpr[rd / 2].l.upper = val;
2208 }
2209 break;
2210 case 8:
2211 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2212 break;
2213 case 16:
2214 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2215 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2216 break;
2217 }
2218 }
2219
2220 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2221 int rd)
2222 {
2223 unsigned int i;
2224 target_ulong val;
2225
2226 addr = asi_address_mask(env, asi, addr);
2227
2228 switch (asi) {
2229 case ASI_BLK_COMMIT_P: /* UA2007/JPS1 Block store primary (cache flush) */
2230 case ASI_BLK_COMMIT_S: /* UA2007/JPS1 Block store secondary (cache flush) */
2231 case ASI_BLK_P: /* UA2007/JPS1 Block store primary */
2232 case ASI_BLK_S: /* UA2007/JPS1 Block store secondary */
2233 case ASI_BLK_PL: /* UA2007/JPS1 Block store primary LE */
2234 case ASI_BLK_SL: /* UA2007/JPS1 Block store secondary LE */
2235 if (rd & 7) {
2236 helper_raise_exception(env, TT_ILL_INSN);
2237 return;
2238 }
2239 helper_check_align(env, addr, 0x3f);
2240 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2241 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2242 }
2243
2244 return;
2245 case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
2246 case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
2247 case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
2248 case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
2249 case ASI_BLK_AIUP: /* JPS1 Block store primary, user privilege */
2250 case ASI_BLK_AIUS: /* JPS1 Block store secondary, user privilege */
2251 case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
2252 case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
2253 if (rd & 7) {
2254 helper_raise_exception(env, TT_ILL_INSN);
2255 return;
2256 }
2257 helper_check_align(env, addr, 0x3f);
2258 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2259 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2260 }
2261
2262 return;
2263 case ASI_FL16_P: /* 16-bit floating point load primary */
2264 case ASI_FL16_S: /* 16-bit floating point load secondary */
2265 case ASI_FL16_PL: /* 16-bit floating point load primary, LE */
2266 case ASI_FL16_SL: /* 16-bit floating point load secondary, LE */
2267 helper_check_align(env, addr, 1);
2268 /* Fall through */
2269 case ASI_FL8_P: /* 8-bit floating point load primary */
2270 case ASI_FL8_S: /* 8-bit floating point load secondary */
2271 case ASI_FL8_PL: /* 8-bit floating point load primary, LE */
2272 case ASI_FL8_SL: /* 8-bit floating point load secondary, LE */
2273 val = env->fpr[rd / 2].l.lower;
2274 helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
2275 return;
2276 default:
2277 helper_check_align(env, addr, 3);
2278 break;
2279 }
2280
2281 switch (size) {
2282 default:
2283 case 4:
2284 if (rd & 1) {
2285 val = env->fpr[rd / 2].l.lower;
2286 } else {
2287 val = env->fpr[rd / 2].l.upper;
2288 }
2289 helper_st_asi(env, addr, val, asi, size);
2290 break;
2291 case 8:
2292 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2293 break;
2294 case 16:
2295 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2296 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2297 break;
2298 }
2299 }
2300
2301 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2302 target_ulong val1, target_ulong val2,
2303 uint32_t asi)
2304 {
2305 target_ulong ret;
2306
2307 ret = helper_ld_asi(env, addr, asi, 8, 0);
2308 if (val2 == ret) {
2309 helper_st_asi(env, addr, val1, asi, 8);
2310 }
2311 return ret;
2312 }
2313 #endif /* TARGET_SPARC64 */
2314
2315 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2316 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2317 target_ulong val1, target_ulong val2, uint32_t asi)
2318 {
2319 target_ulong ret;
2320
2321 val2 &= 0xffffffffUL;
2322 ret = helper_ld_asi(env, addr, asi, 4, 0);
2323 ret &= 0xffffffffUL;
2324 if (val2 == ret) {
2325 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2326 }
2327 return ret;
2328 }
2329 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2330
2331 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2332 {
2333 /* XXX add 128 bit load */
2334 CPU_QuadU u;
2335
2336 helper_check_align(env, addr, 7);
2337 #if !defined(CONFIG_USER_ONLY)
2338 switch (mem_idx) {
2339 case MMU_USER_IDX:
2340 u.ll.upper = cpu_ldq_user(env, addr);
2341 u.ll.lower = cpu_ldq_user(env, addr + 8);
2342 QT0 = u.q;
2343 break;
2344 case MMU_KERNEL_IDX:
2345 u.ll.upper = cpu_ldq_kernel(env, addr);
2346 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2347 QT0 = u.q;
2348 break;
2349 #ifdef TARGET_SPARC64
2350 case MMU_HYPV_IDX:
2351 u.ll.upper = cpu_ldq_hypv(env, addr);
2352 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2353 QT0 = u.q;
2354 break;
2355 #endif
2356 default:
2357 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2358 break;
2359 }
2360 #else
2361 u.ll.upper = cpu_ldq_data(env, address_mask(env, addr));
2362 u.ll.lower = cpu_ldq_data(env, address_mask(env, addr + 8));
2363 QT0 = u.q;
2364 #endif
2365 }
2366
2367 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2368 {
2369 /* XXX add 128 bit store */
2370 CPU_QuadU u;
2371
2372 helper_check_align(env, addr, 7);
2373 #if !defined(CONFIG_USER_ONLY)
2374 switch (mem_idx) {
2375 case MMU_USER_IDX:
2376 u.q = QT0;
2377 cpu_stq_user(env, addr, u.ll.upper);
2378 cpu_stq_user(env, addr + 8, u.ll.lower);
2379 break;
2380 case MMU_KERNEL_IDX:
2381 u.q = QT0;
2382 cpu_stq_kernel(env, addr, u.ll.upper);
2383 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2384 break;
2385 #ifdef TARGET_SPARC64
2386 case MMU_HYPV_IDX:
2387 u.q = QT0;
2388 cpu_stq_hypv(env, addr, u.ll.upper);
2389 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2390 break;
2391 #endif
2392 default:
2393 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2394 break;
2395 }
2396 #else
2397 u.q = QT0;
2398 cpu_stq_data(env, address_mask(env, addr), u.ll.upper);
2399 cpu_stq_data(env, address_mask(env, addr + 8), u.ll.lower);
2400 #endif
2401 }
2402
2403 #if !defined(CONFIG_USER_ONLY)
2404 #ifndef TARGET_SPARC64
2405 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2406 bool is_write, bool is_exec, int is_asi,
2407 unsigned size)
2408 {
2409 SPARCCPU *cpu = SPARC_CPU(cs);
2410 CPUSPARCState *env = &cpu->env;
2411 int fault_type;
2412
2413 #ifdef DEBUG_UNASSIGNED
2414 if (is_asi) {
2415 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2416 " asi 0x%02x from " TARGET_FMT_lx "\n",
2417 is_exec ? "exec" : is_write ? "write" : "read", size,
2418 size == 1 ? "" : "s", addr, is_asi, env->pc);
2419 } else {
2420 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2421 " from " TARGET_FMT_lx "\n",
2422 is_exec ? "exec" : is_write ? "write" : "read", size,
2423 size == 1 ? "" : "s", addr, env->pc);
2424 }
2425 #endif
2426 /* Don't overwrite translation and access faults */
2427 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2428 if ((fault_type > 4) || (fault_type == 0)) {
2429 env->mmuregs[3] = 0; /* Fault status register */
2430 if (is_asi) {
2431 env->mmuregs[3] |= 1 << 16;
2432 }
2433 if (env->psrs) {
2434 env->mmuregs[3] |= 1 << 5;
2435 }
2436 if (is_exec) {
2437 env->mmuregs[3] |= 1 << 6;
2438 }
2439 if (is_write) {
2440 env->mmuregs[3] |= 1 << 7;
2441 }
2442 env->mmuregs[3] |= (5 << 2) | 2;
2443 /* SuperSPARC will never place instruction fault addresses in the FAR */
2444 if (!is_exec) {
2445 env->mmuregs[4] = addr; /* Fault address register */
2446 }
2447 }
2448 /* overflow (same type fault was not read before another fault) */
2449 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2450 env->mmuregs[3] |= 1;
2451 }
2452
2453 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2454 if (is_exec) {
2455 helper_raise_exception(env, TT_CODE_ACCESS);
2456 } else {
2457 helper_raise_exception(env, TT_DATA_ACCESS);
2458 }
2459 }
2460
2461 /* flush neverland mappings created during no-fault mode,
2462 so the sequential MMU faults report proper fault types */
2463 if (env->mmuregs[0] & MMU_NF) {
2464 tlb_flush(cs, 1);
2465 }
2466 }
2467 #else
2468 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2469 bool is_write, bool is_exec, int is_asi,
2470 unsigned size)
2471 {
2472 SPARCCPU *cpu = SPARC_CPU(cs);
2473 CPUSPARCState *env = &cpu->env;
2474
2475 #ifdef DEBUG_UNASSIGNED
2476 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2477 "\n", addr, env->pc);
2478 #endif
2479
2480 if (is_exec) {
2481 helper_raise_exception(env, TT_CODE_ACCESS);
2482 } else {
2483 helper_raise_exception(env, TT_DATA_ACCESS);
2484 }
2485 }
2486 #endif
2487 #endif
2488
2489 #if !defined(CONFIG_USER_ONLY)
2490 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2491 MMUAccessType access_type,
2492 int mmu_idx,
2493 uintptr_t retaddr)
2494 {
2495 SPARCCPU *cpu = SPARC_CPU(cs);
2496 CPUSPARCState *env = &cpu->env;
2497
2498 #ifdef DEBUG_UNALIGNED
2499 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2500 "\n", addr, env->pc);
2501 #endif
2502 if (retaddr) {
2503 cpu_restore_state(CPU(cpu), retaddr);
2504 }
2505 helper_raise_exception(env, TT_UNALIGNED);
2506 }
2507
2508 /* try to fill the TLB and return an exception if error. If retaddr is
2509 NULL, it means that the function was called in C code (i.e. not
2510 from generated code or from helper.c) */
2511 /* XXX: fix it to restore all registers */
2512 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
2513 int mmu_idx, uintptr_t retaddr)
2514 {
2515 int ret;
2516
2517 ret = sparc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
2518 if (ret) {
2519 if (retaddr) {
2520 cpu_restore_state(cs, retaddr);
2521 }
2522 cpu_loop_exit(cs);
2523 }
2524 }
2525 #endif
AR7 emulation for QEMU