2 * Octeon-specific instructions translation routines
4 * Copyright (c) 2022 Pavel Dovgalyuk
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "translate.h"
11 #include "tcg/tcg-op-gvec.h"
13 /* Include the auto-generated decoder. */
14 #include "decode-octeon.c.inc"
16 static bool trans_BBIT(DisasContext
*ctx
, arg_BBIT
*a
)
20 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
21 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
22 TARGET_FMT_lx
"\n", ctx
->base
.pc_next
);
23 generate_exception_end(ctx
, EXCP_RI
);
27 /* Load needed operands */
28 TCGv t0
= tcg_temp_new();
29 gen_load_gpr(t0
, a
->rs
);
31 p
= tcg_constant_tl(1ULL << a
->p
);
33 tcg_gen_and_tl(bcond
, p
, t0
);
35 tcg_gen_andc_tl(bcond
, p
, t0
);
38 ctx
->hflags
|= MIPS_HFLAG_BC
;
39 ctx
->btarget
= ctx
->base
.pc_next
+ 4 + a
->offset
* 4;
40 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
44 static bool trans_BADDU(DisasContext
*ctx
, arg_BADDU
*a
)
55 gen_load_gpr(t0
, a
->rs
);
56 gen_load_gpr(t1
, a
->rt
);
58 tcg_gen_add_tl(t0
, t0
, t1
);
59 tcg_gen_andi_i64(cpu_gpr
[a
->rd
], t0
, 0xff);
63 static bool trans_DMUL(DisasContext
*ctx
, arg_DMUL
*a
)
74 gen_load_gpr(t0
, a
->rs
);
75 gen_load_gpr(t1
, a
->rt
);
77 tcg_gen_mul_i64(cpu_gpr
[a
->rd
], t0
, t1
);
81 static bool trans_EXTS(DisasContext
*ctx
, arg_EXTS
*a
)
91 gen_load_gpr(t0
, a
->rs
);
92 tcg_gen_sextract_tl(t0
, t0
, a
->p
, a
->lenm1
+ 1);
93 gen_store_gpr(t0
, a
->rt
);
97 static bool trans_CINS(DisasContext
*ctx
, arg_CINS
*a
)
107 gen_load_gpr(t0
, a
->rs
);
108 tcg_gen_deposit_z_tl(t0
, t0
, a
->p
, a
->lenm1
+ 1);
109 gen_store_gpr(t0
, a
->rt
);
113 static bool trans_POP(DisasContext
*ctx
, arg_POP
*a
)
123 gen_load_gpr(t0
, a
->rs
);
125 tcg_gen_andi_i64(t0
, t0
, 0xffffffff);
127 tcg_gen_ctpop_tl(t0
, t0
);
128 gen_store_gpr(t0
, a
->rd
);
132 static bool trans_SEQNE(DisasContext
*ctx
, arg_SEQNE
*a
)
144 gen_load_gpr(t0
, a
->rs
);
145 gen_load_gpr(t1
, a
->rt
);
148 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr
[a
->rd
], t1
, t0
);
150 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr
[a
->rd
], t1
, t0
);
155 static bool trans_SEQNEI(DisasContext
*ctx
, arg_SEQNEI
*a
)
166 gen_load_gpr(t0
, a
->rs
);
168 /* Sign-extend to 64 bit value */
169 target_ulong imm
= a
->imm
;
171 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr
[a
->rt
], t0
, imm
);
173 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr
[a
->rt
], t0
, imm
);