2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "qemu/cpu-float.h"
33 #include "exec/cpu-defs.h"
35 #include "xtensa-isa.h"
38 /* Additional instructions */
39 XTENSA_OPTION_CODE_DENSITY
,
41 XTENSA_OPTION_EXTENDED_L32R
,
42 XTENSA_OPTION_16_BIT_IMUL
,
43 XTENSA_OPTION_32_BIT_IMUL
,
44 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
45 XTENSA_OPTION_32_BIT_IDIV
,
47 XTENSA_OPTION_MISC_OP_NSA
,
48 XTENSA_OPTION_MISC_OP_MINMAX
,
49 XTENSA_OPTION_MISC_OP_SEXT
,
50 XTENSA_OPTION_MISC_OP_CLAMPS
,
51 XTENSA_OPTION_COPROCESSOR
,
52 XTENSA_OPTION_BOOLEAN
,
53 XTENSA_OPTION_FP_COPROCESSOR
,
54 XTENSA_OPTION_DFP_COPROCESSOR
,
55 XTENSA_OPTION_DFPU_SINGLE_ONLY
,
56 XTENSA_OPTION_MP_SYNCHRO
,
57 XTENSA_OPTION_CONDITIONAL_STORE
,
58 XTENSA_OPTION_ATOMCTL
,
59 XTENSA_OPTION_DEPBITS
,
61 /* Interrupts and exceptions */
62 XTENSA_OPTION_EXCEPTION
,
63 XTENSA_OPTION_RELOCATABLE_VECTOR
,
64 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
65 XTENSA_OPTION_INTERRUPT
,
66 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
67 XTENSA_OPTION_TIMER_INTERRUPT
,
71 XTENSA_OPTION_ICACHE_TEST
,
72 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
74 XTENSA_OPTION_DCACHE_TEST
,
75 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
81 XTENSA_OPTION_HW_ALIGNMENT
,
82 XTENSA_OPTION_MEMORY_ECC_PARITY
,
84 /* Memory protection and translation */
85 XTENSA_OPTION_REGION_PROTECTION
,
86 XTENSA_OPTION_REGION_TRANSLATION
,
89 XTENSA_OPTION_CACHEATTR
,
92 XTENSA_OPTION_WINDOWED_REGISTER
,
93 XTENSA_OPTION_PROCESSOR_INTERFACE
,
94 XTENSA_OPTION_MISC_SR
,
95 XTENSA_OPTION_THREAD_POINTER
,
96 XTENSA_OPTION_PROCESSOR_ID
,
98 XTENSA_OPTION_TRACE_PORT
,
99 XTENSA_OPTION_EXTERN_REGS
,
169 #define PS_INTLEVEL 0xf
170 #define PS_INTLEVEL_SHIFT 0
176 #define PS_RING_SHIFT 6
179 #define PS_OWB_SHIFT 8
182 #define PS_CALLINC 0x30000
183 #define PS_CALLINC_SHIFT 16
184 #define PS_CALLINC_LEN 2
186 #define PS_WOE 0x40000
188 #define DEBUGCAUSE_IC 0x1
189 #define DEBUGCAUSE_IB 0x2
190 #define DEBUGCAUSE_DB 0x4
191 #define DEBUGCAUSE_BI 0x8
192 #define DEBUGCAUSE_BN 0x10
193 #define DEBUGCAUSE_DI 0x20
194 #define DEBUGCAUSE_DBNUM 0xf00
195 #define DEBUGCAUSE_DBNUM_SHIFT 8
197 #define DBREAKC_SB 0x80000000
198 #define DBREAKC_LB 0x40000000
199 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
200 #define DBREAKC_MASK 0x3f
202 #define MEMCTL_INIT 0x00800000
203 #define MEMCTL_IUSEWAYS_SHIFT 18
204 #define MEMCTL_IUSEWAYS_LEN 5
205 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
206 #define MEMCTL_DALLOCWAYS_SHIFT 13
207 #define MEMCTL_DALLOCWAYS_LEN 5
208 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
209 #define MEMCTL_DUSEWAYS_SHIFT 8
210 #define MEMCTL_DUSEWAYS_LEN 5
211 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
212 #define MEMCTL_ISNP 0x4
213 #define MEMCTL_DSNP 0x2
214 #define MEMCTL_IL0EN 0x1
216 #define MAX_INSN_LENGTH 64
217 #define MAX_INSNBUF_LENGTH \
218 ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \
219 sizeof(xtensa_insnbuf_word))
220 #define MAX_INSN_SLOTS 32
221 #define MAX_OPCODE_ARGS 16
223 #define MAX_NINTERRUPT 32
226 #define MAX_NCCOMPARE 3
227 #define MAX_TLB_WAY_SIZE 8
228 #define MAX_NDBREAK 2
229 #define MAX_NIBREAK 2
230 #define MAX_NMEMORY 4
231 #define MAX_MPU_FOREGROUND_SEGMENTS 32
233 #define REGION_PAGE_MASK 0xe0000000
235 #define PAGE_CACHE_MASK 0x700
236 #define PAGE_CACHE_SHIFT 8
237 #define PAGE_CACHE_INVALID 0x000
238 #define PAGE_CACHE_BYPASS 0x100
239 #define PAGE_CACHE_WT 0x200
240 #define PAGE_CACHE_WB 0x400
241 #define PAGE_CACHE_ISOLATE 0x600
249 /* Dynamic vectors */
250 EXC_WINDOW_OVERFLOW4
,
251 EXC_WINDOW_UNDERFLOW4
,
252 EXC_WINDOW_OVERFLOW8
,
253 EXC_WINDOW_UNDERFLOW8
,
254 EXC_WINDOW_OVERFLOW12
,
255 EXC_WINDOW_UNDERFLOW12
,
265 ILLEGAL_INSTRUCTION_CAUSE
= 0,
267 INSTRUCTION_FETCH_ERROR_CAUSE
,
268 LOAD_STORE_ERROR_CAUSE
,
269 LEVEL1_INTERRUPT_CAUSE
,
271 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
272 PC_VALUE_ERROR_CAUSE
,
274 LOAD_STORE_ALIGNMENT_CAUSE
,
275 EXTERNAL_REG_PRIVILEGE_CAUSE
,
276 EXCLUSIVE_ERROR_CAUSE
,
277 INSTR_PIF_DATA_ERROR_CAUSE
,
278 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
279 INSTR_PIF_ADDR_ERROR_CAUSE
,
280 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
282 INST_TLB_MULTI_HIT_CAUSE
,
283 INST_FETCH_PRIVILEGE_CAUSE
,
284 INST_FETCH_PROHIBITED_CAUSE
= 20,
285 LOAD_STORE_TLB_MISS_CAUSE
= 24,
286 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
287 LOAD_STORE_PRIVILEGE_CAUSE
,
288 LOAD_PROHIBITED_CAUSE
= 28,
289 STORE_PROHIBITED_CAUSE
,
291 COPROCESSOR0_DISABLED
= 32,
309 typedef struct CPUArchState CPUXtensaState
;
311 typedef struct xtensa_tlb_entry
{
319 typedef struct xtensa_tlb
{
321 const unsigned way_size
[10];
323 unsigned nrefillentries
;
326 typedef struct xtensa_mpu_entry
{
331 typedef struct XtensaGdbReg
{
339 typedef struct XtensaGdbRegmap
{
342 /* PC + a + ar + sr + ur */
343 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
346 typedef struct XtensaCcompareTimer
{
349 } XtensaCcompareTimer
;
351 typedef struct XtensaMemory
{
353 struct XtensaMemoryRegion
{
356 } location
[MAX_NMEMORY
];
359 typedef struct opcode_arg
{
367 typedef struct DisasContext DisasContext
;
368 typedef void (*XtensaOpcodeOp
)(DisasContext
*dc
, const OpcodeArg arg
[],
369 const uint32_t par
[]);
370 typedef uint32_t (*XtensaOpcodeUintTest
)(DisasContext
*dc
,
371 const OpcodeArg arg
[],
372 const uint32_t par
[]);
376 XTENSA_OP_PRIVILEGED
= 0x2,
377 XTENSA_OP_SYSCALL
= 0x4,
378 XTENSA_OP_DEBUG_BREAK
= 0x8,
380 XTENSA_OP_OVERFLOW
= 0x10,
381 XTENSA_OP_UNDERFLOW
= 0x20,
382 XTENSA_OP_ALLOCA
= 0x40,
383 XTENSA_OP_COPROCESSOR
= 0x80,
385 XTENSA_OP_DIVIDE_BY_ZERO
= 0x100,
387 /* Postprocessing flags */
388 XTENSA_OP_CHECK_INTERRUPTS
= 0x200,
389 XTENSA_OP_EXIT_TB_M1
= 0x400,
390 XTENSA_OP_EXIT_TB_0
= 0x800,
391 XTENSA_OP_SYNC_REGISTER_WINDOW
= 0x1000,
393 XTENSA_OP_POSTPROCESS
=
394 XTENSA_OP_CHECK_INTERRUPTS
|
395 XTENSA_OP_EXIT_TB_M1
|
396 XTENSA_OP_EXIT_TB_0
|
397 XTENSA_OP_SYNC_REGISTER_WINDOW
,
399 XTENSA_OP_NAME_ARRAY
= 0x8000,
401 XTENSA_OP_CONTROL_FLOW
= 0x10000,
402 XTENSA_OP_STORE
= 0x20000,
403 XTENSA_OP_LOAD
= 0x40000,
404 XTENSA_OP_LOAD_STORE
=
405 XTENSA_OP_LOAD
| XTENSA_OP_STORE
,
408 typedef struct XtensaOpcodeOps
{
410 XtensaOpcodeOp translate
;
411 XtensaOpcodeUintTest test_exceptions
;
412 XtensaOpcodeUintTest test_overflow
;
415 uint32_t coprocessor
;
418 typedef struct XtensaOpcodeTranslators
{
419 unsigned num_opcodes
;
420 const XtensaOpcodeOps
*opcode
;
421 } XtensaOpcodeTranslators
;
423 extern const XtensaOpcodeTranslators xtensa_core_opcodes
;
424 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
;
425 extern const XtensaOpcodeTranslators xtensa_fpu_opcodes
;
427 typedef struct XtensaConfig
{
430 XtensaGdbRegmap gdb_regmap
;
434 unsigned inst_fetch_width
;
435 unsigned max_insn_size
;
437 uint32_t exception_vector
[EXC_MAX
];
441 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
442 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
443 uint32_t inttype_mask
[INTTYPE_MAX
];
446 interrupt_type inttype
;
447 } interrupt
[MAX_NINTERRUPT
];
449 uint32_t timerint
[MAX_NCCOMPARE
];
451 unsigned extint
[MAX_NINTERRUPT
];
453 unsigned debug_level
;
457 unsigned icache_ways
;
458 unsigned dcache_ways
;
459 unsigned dcache_line_bytes
;
460 uint32_t memctl_mask
;
462 XtensaMemory instrom
;
463 XtensaMemory instram
;
464 XtensaMemory datarom
;
465 XtensaMemory dataram
;
470 uint32_t configid
[2];
474 XtensaOpcodeOps
**opcode_ops
;
475 const XtensaOpcodeTranslators
**opcode_translators
;
476 xtensa_regfile a_regfile
;
479 uint32_t clock_freq_khz
;
485 unsigned n_mpu_fg_segments
;
486 unsigned n_mpu_bg_segments
;
487 const xtensa_mpu_entry
*mpu_bg
;
492 typedef struct XtensaConfigList
{
493 const XtensaConfig
*config
;
494 struct XtensaConfigList
*next
;
509 struct CPUArchState
{
510 const XtensaConfig
*config
;
515 uint32_t phys_regs
[MAX_NAREG
];
520 float_status fp_status
;
521 uint32_t windowbase_next
;
522 uint32_t exclusive_addr
;
523 uint32_t exclusive_val
;
525 #ifndef CONFIG_USER_ONLY
526 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
527 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
528 xtensa_mpu_entry mpu_fg
[MAX_MPU_FOREGROUND_SEGMENTS
];
529 unsigned autorefill_idx
;
531 AddressSpace
*address_space_er
;
532 MemoryRegion
*system_er
;
533 int pending_irq_level
; /* level of last raised IRQ */
534 qemu_irq
*irq_inputs
;
535 qemu_irq ext_irq_inputs
[MAX_NINTERRUPT
];
536 qemu_irq runstall_irq
;
537 XtensaCcompareTimer ccompare
[MAX_NCCOMPARE
];
539 uint64_t ccount_time
;
540 uint32_t ccount_base
;
544 unsigned static_vectors
;
546 /* Watchpoints for DBREAK registers */
547 struct CPUWatchpoint
*cpu_watchpoint
[MAX_NDBREAK
];
548 /* Breakpoints for IBREAK registers */
549 struct CPUBreakpoint
*cpu_breakpoint
[MAX_NIBREAK
];
554 * @env: #CPUXtensaState
567 * @parent_realize: The parent class' realize handler.
568 * @parent_phases: The parent class' reset phase handlers.
569 * @config: The CPU core configuration.
571 * An Xtensa CPU model.
573 struct XtensaCPUClass
{
574 CPUClass parent_class
;
576 DeviceRealize parent_realize
;
577 ResettablePhases parent_phases
;
579 const XtensaConfig
*config
;
582 #ifndef CONFIG_USER_ONLY
583 bool xtensa_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
584 MMUAccessType access_type
, int mmu_idx
,
585 bool probe
, uintptr_t retaddr
);
586 void xtensa_cpu_do_interrupt(CPUState
*cpu
);
587 bool xtensa_cpu_exec_interrupt(CPUState
*cpu
, int interrupt_request
);
588 void xtensa_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
, vaddr addr
,
589 unsigned size
, MMUAccessType access_type
,
590 int mmu_idx
, MemTxAttrs attrs
,
591 MemTxResult response
, uintptr_t retaddr
);
592 hwaddr
xtensa_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
593 bool xtensa_debug_check_breakpoint(CPUState
*cs
);
595 void xtensa_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
596 void xtensa_count_regs(const XtensaConfig
*config
,
597 unsigned *n_regs
, unsigned *n_core_regs
);
598 int xtensa_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
599 int xtensa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
600 G_NORETURN
void xtensa_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
601 MMUAccessType access_type
, int mmu_idx
,
604 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
606 #if TARGET_BIG_ENDIAN
607 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
608 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
610 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
611 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
613 #define XTENSA_DEFAULT_CPU_TYPE \
614 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
615 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
616 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
618 void xtensa_collect_sr_names(const XtensaConfig
*config
);
619 void xtensa_translate_init(void);
620 void **xtensa_get_regfile_by_name(const char *name
, int entries
, int bits
);
621 void xtensa_breakpoint_handler(CPUState
*cs
);
622 void xtensa_register_core(XtensaConfigList
*node
);
623 void xtensa_sim_open_console(Chardev
*chr
);
624 void check_interrupts(CPUXtensaState
*s
);
625 void xtensa_irq_init(CPUXtensaState
*env
);
626 qemu_irq
*xtensa_get_extints(CPUXtensaState
*env
);
627 qemu_irq
xtensa_get_runstall(CPUXtensaState
*env
);
628 void xtensa_sync_window_from_phys(CPUXtensaState
*env
);
629 void xtensa_sync_phys_from_window(CPUXtensaState
*env
);
630 void xtensa_rotate_window(CPUXtensaState
*env
, uint32_t delta
);
631 void xtensa_restore_owb(CPUXtensaState
*env
);
632 void debug_exception_env(CPUXtensaState
*new_env
, uint32_t cause
);
634 static inline void xtensa_select_static_vectors(CPUXtensaState
*env
,
638 env
->static_vectors
= n
;
640 void xtensa_runstall(CPUXtensaState
*env
, bool runstall
);
642 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
643 #define XTENSA_OPTION_ALL (~(uint64_t)0)
645 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
648 return (config
->options
& opt
) != 0;
651 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
653 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
656 static inline int xtensa_get_cintlevel(const CPUXtensaState
*env
)
658 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
659 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
660 level
= env
->config
->excm_level
;
665 static inline int xtensa_get_ring(const CPUXtensaState
*env
)
667 if (xtensa_option_bits_enabled(env
->config
,
668 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
669 XTENSA_OPTION_BIT(XTENSA_OPTION_MPU
))) {
670 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
676 static inline int xtensa_get_cring(const CPUXtensaState
*env
)
678 if (xtensa_option_bits_enabled(env
->config
,
679 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
680 XTENSA_OPTION_BIT(XTENSA_OPTION_MPU
)) &&
681 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
682 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
688 #ifndef CONFIG_USER_ONLY
689 int xtensa_get_physical_addr(CPUXtensaState
*env
, bool update_tlb
,
690 uint32_t vaddr
, int is_write
, int mmu_idx
,
691 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
692 void reset_mmu(CPUXtensaState
*env
);
693 void dump_mmu(CPUXtensaState
*env
);
695 static inline MemoryRegion
*xtensa_get_er_region(CPUXtensaState
*env
)
697 return env
->system_er
;
700 void xtensa_set_abi_call0(void);
701 bool xtensa_abi_call0(void);
704 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState
*env
)
706 return env
->sregs
[WINDOW_START
] |
707 (env
->sregs
[WINDOW_START
] << env
->config
->nareg
/ 4);
710 /* MMU modes definitions */
711 #define MMU_USER_IDX 3
713 #define XTENSA_TBFLAG_RING_MASK 0x3
714 #define XTENSA_TBFLAG_EXCM 0x4
715 #define XTENSA_TBFLAG_LITBASE 0x8
716 #define XTENSA_TBFLAG_DEBUG 0x10
717 #define XTENSA_TBFLAG_ICOUNT 0x20
718 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
719 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
720 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
721 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
722 #define XTENSA_TBFLAG_YIELD 0x20000
723 #define XTENSA_TBFLAG_CWOE 0x40000
724 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000
725 #define XTENSA_TBFLAG_CALLINC_SHIFT 19
727 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff
728 #define XTENSA_CSBASE_LEND_SHIFT 0
729 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
730 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
732 #include "exec/cpu-all.h"
734 static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env
, vaddr
*pc
,
735 uint64_t *cs_base
, uint32_t *flags
)
740 *flags
|= xtensa_get_ring(env
);
741 if (env
->sregs
[PS
] & PS_EXCM
) {
742 *flags
|= XTENSA_TBFLAG_EXCM
;
743 } else if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_LOOP
)) {
744 target_ulong lend_dist
=
745 env
->sregs
[LEND
] - (env
->pc
& -(1u << TARGET_PAGE_BITS
));
748 * 0 in the csbase_lend field means that there may not be a loopback
749 * for any instruction that starts inside this page. Any other value
750 * means that an instruction that ends at this offset from the page
751 * start may loop back and will need loopback code to be generated.
753 * lend_dist is 0 when LEND points to the start of the page, but
754 * no instruction that starts inside this page may end at offset 0,
755 * so it's still correct.
757 * When an instruction ends at a page boundary it may only start in
758 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
759 * for the TB that contains this instruction.
761 if (lend_dist
< (1u << TARGET_PAGE_BITS
) + env
->config
->max_insn_size
) {
762 target_ulong lbeg_off
= env
->sregs
[LEND
] - env
->sregs
[LBEG
];
764 *cs_base
= lend_dist
;
765 if (lbeg_off
< 256) {
766 *cs_base
|= lbeg_off
<< XTENSA_CSBASE_LBEG_OFF_SHIFT
;
770 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
771 (env
->sregs
[LITBASE
] & 1)) {
772 *flags
|= XTENSA_TBFLAG_LITBASE
;
774 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
775 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
776 *flags
|= XTENSA_TBFLAG_DEBUG
;
778 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
779 *flags
|= XTENSA_TBFLAG_ICOUNT
;
782 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_COPROCESSOR
)) {
783 *flags
|= env
->sregs
[CPENABLE
] << XTENSA_TBFLAG_CPENABLE_SHIFT
;
785 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
786 (env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) == PS_WOE
) {
787 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
788 (env
->sregs
[WINDOW_BASE
] + 1);
789 uint32_t w
= ctz32(windowstart
| 0x8);
791 *flags
|= (w
<< XTENSA_TBFLAG_WINDOW_SHIFT
) | XTENSA_TBFLAG_CWOE
;
792 *flags
|= extract32(env
->sregs
[PS
], PS_CALLINC_SHIFT
,
793 PS_CALLINC_LEN
) << XTENSA_TBFLAG_CALLINC_SHIFT
;
795 *flags
|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT
;
797 if (env
->yield_needed
) {
798 *flags
|= XTENSA_TBFLAG_YIELD
;
802 XtensaCPU
*xtensa_cpu_create_with_clock(const char *cpu_type
,