target-arm/cpu-qom.h

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_ARM_CPU_QOM_H
  21 #define QEMU_ARM_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24
  25 #define TYPE_ARM_CPU "arm-cpu"
  26
  27 #define ARM_CPU_CLASS(klass) \
  28     OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
  29 #define ARM_CPU(obj) \
  30     OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
  31 #define ARM_CPU_GET_CLASS(obj) \
  32     OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
  33
  34 /**
  35  * ARMCPUClass:
  36  * @parent_realize: The parent class' realize handler.
  37  * @parent_reset: The parent class' reset handler.
  38  *
  39  * An ARM CPU model.
  40  */
  41 typedef struct ARMCPUClass {
  42     /*< private >*/
  43     CPUClass parent_class;
  44     /*< public >*/
  45
  46     DeviceRealize parent_realize;
  47     void (*parent_reset)(CPUState *cpu);
  48 } ARMCPUClass;
  49
  50 /**
  51  * ARMCPU:
  52  * @env: #CPUARMState
  53  *
  54  * An ARM CPU core.
  55  */
  56 typedef struct ARMCPU {
  57     /*< private >*/
  58     CPUState parent_obj;
  59     /*< public >*/
  60
  61     CPUARMState env;
  62
  63     /* Coprocessor information */
  64     GHashTable *cp_regs;
  65     /* For marshalling (mostly coprocessor) register state between the
  66      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
  67      * we use these arrays.
  68      */
  69     /* List of register indexes managed via these arrays; (full KVM style
  70      * 64 bit indexes, not CPRegInfo 32 bit indexes)
  71      */
  72     uint64_t *cpreg_indexes;
  73     /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
  74     uint64_t *cpreg_values;
  75     /* Length of the indexes, values, reset_values arrays */
  76     int32_t cpreg_array_len;
  77     /* These are used only for migration: incoming data arrives in
  78      * these fields and is sanity checked in post_load before copying
  79      * to the working data structures above.
  80      */
  81     uint64_t *cpreg_vmstate_indexes;
  82     uint64_t *cpreg_vmstate_values;
  83     int32_t cpreg_vmstate_array_len;
  84
  85     /* Timers used by the generic (architected) timer */
  86     QEMUTimer *gt_timer[NUM_GTIMERS];
  87     /* GPIO outputs for generic timer */
  88     qemu_irq gt_timer_outputs[NUM_GTIMERS];
  89
  90     /* 'compatible' string for this CPU for Linux device trees */
  91     const char *dtb_compatible;
  92
  93     /* PSCI version for this CPU
  94      * Bits[31:16] = Major Version
  95      * Bits[15:0] = Minor Version
  96      */
  97     uint32_t psci_version;
  98
  99     /* Should CPU start in PSCI powered-off state? */
 100     bool start_powered_off;
 101     /* CPU currently in PSCI powered-off state */
 102     bool powered_off;
 103     /* CPU has security extension */
 104     bool has_el3;
 105
 106     /* CPU has memory protection unit */
 107     bool has_mpu;
 108     /* PMSAv7 MPU number of supported regions */
 109     uint32_t pmsav7_dregion;
 110
 111     /* PSCI conduit used to invoke PSCI methods
 112      * 0 - disabled, 1 - smc, 2 - hvc
 113      */
 114     uint32_t psci_conduit;
 115
 116     /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
 117      * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
 118      */
 119     uint32_t kvm_target;
 120
 121     /* KVM init features for this CPU */
 122     uint32_t kvm_init_features[7];
 123
 124     /* Uniprocessor system with MP extensions */
 125     bool mp_is_up;
 126
 127     /* The instance init functions for implementation-specific subclasses
 128      * set these fields to specify the implementation-dependent values of
 129      * various constant registers and reset values of non-constant
 130      * registers.
 131      * Some of these might become QOM properties eventually.
 132      * Field names match the official register names as defined in the
 133      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
 134      * is used for reset values of non-constant registers; no reset_
 135      * prefix means a constant register.
 136      */
 137     uint32_t midr;
 138     uint32_t revidr;
 139     uint32_t reset_fpsid;
 140     uint32_t mvfr0;
 141     uint32_t mvfr1;
 142     uint32_t mvfr2;
 143     uint32_t ctr;
 144     uint32_t reset_sctlr;
 145     uint32_t id_pfr0;
 146     uint32_t id_pfr1;
 147     uint32_t id_dfr0;
 148     uint32_t id_afr0;
 149     uint32_t id_mmfr0;
 150     uint32_t id_mmfr1;
 151     uint32_t id_mmfr2;
 152     uint32_t id_mmfr3;
 153     uint32_t id_isar0;
 154     uint32_t id_isar1;
 155     uint32_t id_isar2;
 156     uint32_t id_isar3;
 157     uint32_t id_isar4;
 158     uint32_t id_isar5;
 159     uint64_t id_aa64pfr0;
 160     uint64_t id_aa64pfr1;
 161     uint64_t id_aa64dfr0;
 162     uint64_t id_aa64dfr1;
 163     uint64_t id_aa64afr0;
 164     uint64_t id_aa64afr1;
 165     uint64_t id_aa64isar0;
 166     uint64_t id_aa64isar1;
 167     uint64_t id_aa64mmfr0;
 168     uint64_t id_aa64mmfr1;
 169     uint32_t dbgdidr;
 170     uint32_t clidr;
 171     uint64_t mp_affinity; /* MP ID without feature bits */
 172     /* The elements of this array are the CCSIDR values for each cache,
 173      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
 174      */
 175     uint32_t ccsidr[16];
 176     uint64_t reset_cbar;
 177     uint32_t reset_auxcr;
 178     bool reset_hivecs;
 179     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
 180     uint32_t dcz_blocksize;
 181     uint64_t rvbar;
 182 } ARMCPU;
 183
 184 #define TYPE_AARCH64_CPU "aarch64-cpu"
 185 #define AARCH64_CPU_CLASS(klass) \
 186     OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
 187 #define AARCH64_CPU_GET_CLASS(obj) \
 188     OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
 189
 190 typedef struct AArch64CPUClass {
 191     /*< private >*/
 192     ARMCPUClass parent_class;
 193     /*< public >*/
 194 } AArch64CPUClass;
 195
 196 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
 197 {
 198     return container_of(env, ARMCPU, env);
 199 }
 200
 201 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
 202
 203 #define ENV_OFFSET offsetof(ARMCPU, env)
 204
 205 #ifndef CONFIG_USER_ONLY
 206 extern const struct VMStateDescription vmstate_arm_cpu;
 207 #endif
 208
 209 void register_cp_regs_for_features(ARMCPU *cpu);
 210 void init_cpreg_list(ARMCPU *cpu);
 211
 212 void arm_cpu_do_interrupt(CPUState *cpu);
 213 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
 214 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
 215
 216 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 217                         int flags);
 218
 219 hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 220
 221 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 222 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 223
 224 /* Callback functions for the generic timer's timers. */
 225 void arm_gt_ptimer_cb(void *opaque);
 226 void arm_gt_vtimer_cb(void *opaque);
 227 void arm_gt_htimer_cb(void *opaque);
 228 void arm_gt_stimer_cb(void *opaque);
 229
 230 #define ARM_AFF0_SHIFT 0
 231 #define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
 232 #define ARM_AFF1_SHIFT 8
 233 #define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
 234 #define ARM_AFF2_SHIFT 16
 235 #define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
 236 #define ARM_AFF3_SHIFT 32
 237 #define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
 238
 239 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
 240 #define ARM64_AFFINITY_MASK \
 241     (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
 242
 243 #ifdef TARGET_AARCH64
 244 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 245 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 246
 247 void aarch64_cpu_do_interrupt(CPUState *cs);
 248 #endif
 249
 250 #endif