2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/serial.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/fw_cfg.h"
33 #include "hw/hpet_emul.h"
34 #include "hw/smbios.h"
35 #include "hw/loader.h"
37 #include "hw/multiboot.h"
38 #include "hw/mc146818rtc.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block-common.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
56 /* debug PC/ISA interrupts */
60 #define DPRINTF(fmt, ...) \
61 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
63 #define DPRINTF(fmt, ...)
66 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
67 #define ACPI_DATA_SIZE 0x10000
68 #define BIOS_CFG_IOPORT 0x510
69 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
70 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
71 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
72 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
73 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
75 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000
77 #define E820_NR_ENTRIES 16
83 } QEMU_PACKED
__attribute((__aligned__(4)));
87 struct e820_entry entry
[E820_NR_ENTRIES
];
88 } QEMU_PACKED
__attribute((__aligned__(4)));
90 static struct e820_table e820_table
;
91 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
93 void gsi_handler(void *opaque
, int n
, int level
)
97 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
98 if (n
< ISA_NUM_IRQS
) {
99 qemu_set_irq(s
->i8259_irq
[n
], level
);
101 qemu_set_irq(s
->ioapic_irq
[n
], level
);
104 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
109 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
111 return 0xffffffffffffffffULL
;
114 /* MSDOS compatibility mode FPU exception support */
115 static qemu_irq ferr_irq
;
117 void pc_register_ferr_irq(qemu_irq irq
)
122 /* XXX: add IGNNE support */
123 void cpu_set_ferr(CPUX86State
*s
)
125 qemu_irq_raise(ferr_irq
);
128 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
131 qemu_irq_lower(ferr_irq
);
134 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
136 return 0xffffffffffffffffULL
;
140 uint64_t cpu_get_tsc(CPUX86State
*env
)
142 return cpu_get_ticks();
147 static cpu_set_smm_t smm_set
;
148 static void *smm_arg
;
150 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
152 assert(smm_set
== NULL
);
153 assert(smm_arg
== NULL
);
158 void cpu_smm_update(CPUX86State
*env
)
160 if (smm_set
&& smm_arg
&& env
== first_cpu
)
161 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
166 int cpu_get_pic_interrupt(CPUX86State
*env
)
170 intno
= apic_get_interrupt(env
->apic_state
);
174 /* read the irq from the PIC */
175 if (!apic_accept_pic_intr(env
->apic_state
)) {
179 intno
= pic_read_irq(isa_pic
);
183 static void pic_irq_request(void *opaque
, int irq
, int level
)
185 CPUX86State
*env
= first_cpu
;
187 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
188 if (env
->apic_state
) {
190 if (apic_accept_pic_intr(env
->apic_state
)) {
191 apic_deliver_pic_intr(env
->apic_state
, level
);
196 CPUState
*cs
= CPU(x86_env_get_cpu(env
));
198 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
200 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
205 /* PC cmos mappings */
207 #define REG_EQUIPMENT_BYTE 0x14
209 static int cmos_get_fd_drive_type(FDriveType fd0
)
215 /* 1.44 Mb 3"5 drive */
219 /* 2.88 Mb 3"5 drive */
223 /* 1.2 Mb 5"5 drive */
226 case FDRIVE_DRV_NONE
:
234 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
235 int16_t cylinders
, int8_t heads
, int8_t sectors
)
237 rtc_set_memory(s
, type_ofs
, 47);
238 rtc_set_memory(s
, info_ofs
, cylinders
);
239 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
240 rtc_set_memory(s
, info_ofs
+ 2, heads
);
241 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
242 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
243 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
244 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
245 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
246 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
249 /* convert boot_device letter to something recognizable by the bios */
250 static int boot_device2nibble(char boot_device
)
252 switch(boot_device
) {
255 return 0x01; /* floppy boot */
257 return 0x02; /* hard drive boot */
259 return 0x03; /* CD-ROM boot */
261 return 0x04; /* Network boot */
266 static int set_boot_dev(ISADevice
*s
, const char *boot_device
, int fd_bootchk
)
268 #define PC_MAX_BOOT_DEVICES 3
269 int nbds
, bds
[3] = { 0, };
272 nbds
= strlen(boot_device
);
273 if (nbds
> PC_MAX_BOOT_DEVICES
) {
274 error_report("Too many boot devices for PC");
277 for (i
= 0; i
< nbds
; i
++) {
278 bds
[i
] = boot_device2nibble(boot_device
[i
]);
280 error_report("Invalid boot device for PC: '%c'",
285 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
286 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
290 static int pc_boot_set(void *opaque
, const char *boot_device
)
292 return set_boot_dev(opaque
, boot_device
, 0);
295 typedef struct pc_cmos_init_late_arg
{
296 ISADevice
*rtc_state
;
298 } pc_cmos_init_late_arg
;
300 static void pc_cmos_init_late(void *opaque
)
302 pc_cmos_init_late_arg
*arg
= opaque
;
303 ISADevice
*s
= arg
->rtc_state
;
305 int8_t heads
, sectors
;
310 if (ide_get_geometry(arg
->idebus
[0], 0,
311 &cylinders
, &heads
, §ors
) >= 0) {
312 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
315 if (ide_get_geometry(arg
->idebus
[0], 1,
316 &cylinders
, &heads
, §ors
) >= 0) {
317 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
320 rtc_set_memory(s
, 0x12, val
);
323 for (i
= 0; i
< 4; i
++) {
324 /* NOTE: ide_get_geometry() returns the physical
325 geometry. It is always such that: 1 <= sects <= 63, 1
326 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
327 geometry can be different if a translation is done. */
328 if (ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
329 &cylinders
, &heads
, §ors
) >= 0) {
330 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
331 assert((trans
& ~3) == 0);
332 val
|= trans
<< (i
* 2);
335 rtc_set_memory(s
, 0x39, val
);
337 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
340 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
341 const char *boot_device
,
342 ISADevice
*floppy
, BusState
*idebus0
, BusState
*idebus1
,
346 FDriveType fd_type
[2] = { FDRIVE_DRV_NONE
, FDRIVE_DRV_NONE
};
347 static pc_cmos_init_late_arg arg
;
349 /* various important CMOS locations needed by PC/Bochs bios */
352 /* base memory (first MiB) */
353 val
= MIN(ram_size
/ 1024, 640);
354 rtc_set_memory(s
, 0x15, val
);
355 rtc_set_memory(s
, 0x16, val
>> 8);
356 /* extended memory (next 64MiB) */
357 if (ram_size
> 1024 * 1024) {
358 val
= (ram_size
- 1024 * 1024) / 1024;
364 rtc_set_memory(s
, 0x17, val
);
365 rtc_set_memory(s
, 0x18, val
>> 8);
366 rtc_set_memory(s
, 0x30, val
);
367 rtc_set_memory(s
, 0x31, val
>> 8);
368 /* memory between 16MiB and 4GiB */
369 if (ram_size
> 16 * 1024 * 1024) {
370 val
= (ram_size
- 16 * 1024 * 1024) / 65536;
376 rtc_set_memory(s
, 0x34, val
);
377 rtc_set_memory(s
, 0x35, val
>> 8);
378 /* memory above 4GiB */
379 val
= above_4g_mem_size
/ 65536;
380 rtc_set_memory(s
, 0x5b, val
);
381 rtc_set_memory(s
, 0x5c, val
>> 8);
382 rtc_set_memory(s
, 0x5d, val
>> 16);
384 /* set the number of CPU */
385 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
387 /* set boot devices, and disable floppy signature check if requested */
388 if (set_boot_dev(s
, boot_device
, fd_bootchk
)) {
394 for (i
= 0; i
< 2; i
++) {
395 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
398 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
399 cmos_get_fd_drive_type(fd_type
[1]);
400 rtc_set_memory(s
, 0x10, val
);
404 if (fd_type
[0] < FDRIVE_DRV_NONE
) {
407 if (fd_type
[1] < FDRIVE_DRV_NONE
) {
414 val
|= 0x01; /* 1 drive, ready for boot */
417 val
|= 0x41; /* 2 drives, ready for boot */
420 val
|= 0x02; /* FPU is there */
421 val
|= 0x04; /* PS/2 mouse installed */
422 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
426 arg
.idebus
[0] = idebus0
;
427 arg
.idebus
[1] = idebus1
;
428 qemu_register_reset(pc_cmos_init_late
, &arg
);
431 /* port 92 stuff: could be split off */
432 typedef struct Port92State
{
439 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
442 Port92State
*s
= opaque
;
444 DPRINTF("port92: write 0x%02x\n", val
);
446 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
448 qemu_system_reset_request();
452 static uint64_t port92_read(void *opaque
, hwaddr addr
,
455 Port92State
*s
= opaque
;
459 DPRINTF("port92: read 0x%02x\n", ret
);
463 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
465 Port92State
*s
= DO_UPCAST(Port92State
, dev
, dev
);
467 s
->a20_out
= a20_out
;
470 static const VMStateDescription vmstate_port92_isa
= {
473 .minimum_version_id
= 1,
474 .minimum_version_id_old
= 1,
475 .fields
= (VMStateField
[]) {
476 VMSTATE_UINT8(outport
, Port92State
),
477 VMSTATE_END_OF_LIST()
481 static void port92_reset(DeviceState
*d
)
483 Port92State
*s
= container_of(d
, Port92State
, dev
.qdev
);
488 static const MemoryRegionOps port92_ops
= {
490 .write
= port92_write
,
492 .min_access_size
= 1,
493 .max_access_size
= 1,
495 .endianness
= DEVICE_LITTLE_ENDIAN
,
498 static int port92_initfn(ISADevice
*dev
)
500 Port92State
*s
= DO_UPCAST(Port92State
, dev
, dev
);
502 memory_region_init_io(&s
->io
, &port92_ops
, s
, "port92", 1);
503 isa_register_ioport(dev
, &s
->io
, 0x92);
509 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
511 DeviceClass
*dc
= DEVICE_CLASS(klass
);
512 ISADeviceClass
*ic
= ISA_DEVICE_CLASS(klass
);
513 ic
->init
= port92_initfn
;
515 dc
->reset
= port92_reset
;
516 dc
->vmsd
= &vmstate_port92_isa
;
519 static const TypeInfo port92_info
= {
521 .parent
= TYPE_ISA_DEVICE
,
522 .instance_size
= sizeof(Port92State
),
523 .class_init
= port92_class_initfn
,
526 static void port92_register_types(void)
528 type_register_static(&port92_info
);
531 type_init(port92_register_types
)
533 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
535 X86CPU
*cpu
= opaque
;
537 /* XXX: send to all CPUs ? */
538 /* XXX: add logic to handle multiple A20 line sources */
539 x86_cpu_set_a20(cpu
, level
);
542 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
544 int index
= le32_to_cpu(e820_table
.count
);
545 struct e820_entry
*entry
;
547 if (index
>= E820_NR_ENTRIES
)
549 entry
= &e820_table
.entry
[index
++];
551 entry
->address
= cpu_to_le64(address
);
552 entry
->length
= cpu_to_le64(length
);
553 entry
->type
= cpu_to_le32(type
);
555 e820_table
.count
= cpu_to_le32(index
);
559 /* Calculates the limit to CPU APIC ID values
561 * This function returns the limit for the APIC ID value, so that all
562 * CPU APIC IDs are < pc_apic_id_limit().
564 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
566 static unsigned int pc_apic_id_limit(unsigned int max_cpus
)
568 return x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
571 static void *bochs_bios_init(void)
574 uint8_t *smbios_table
;
576 uint64_t *numa_fw_cfg
;
578 unsigned int apic_id_limit
= pc_apic_id_limit(max_cpus
);
580 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
581 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
583 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
584 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
585 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
586 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
589 * So, this means we must not use max_cpus, here, but the maximum possible
590 * APIC ID value, plus one.
592 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
593 * the APIC ID, not the "CPU index"
595 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)apic_id_limit
);
596 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
597 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
598 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
599 acpi_tables
, acpi_tables_len
);
600 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
602 smbios_table
= smbios_get_table(&smbios_len
);
604 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
605 smbios_table
, smbios_len
);
606 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
607 &e820_table
, sizeof(e820_table
));
609 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
610 /* allocate memory for the NUMA channel: one (64bit) word for the number
611 * of nodes, one word for each VCPU->node and one word for each node to
612 * hold the amount of memory.
614 numa_fw_cfg
= g_new0(uint64_t, 1 + apic_id_limit
+ nb_numa_nodes
);
615 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
616 for (i
= 0; i
< max_cpus
; i
++) {
617 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
618 assert(apic_id
< apic_id_limit
);
619 for (j
= 0; j
< nb_numa_nodes
; j
++) {
620 if (test_bit(i
, node_cpumask
[j
])) {
621 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(j
);
626 for (i
= 0; i
< nb_numa_nodes
; i
++) {
627 numa_fw_cfg
[apic_id_limit
+ 1 + i
] = cpu_to_le64(node_mem
[i
]);
629 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
630 (1 + apic_id_limit
+ nb_numa_nodes
) *
631 sizeof(*numa_fw_cfg
));
636 static long get_file_size(FILE *f
)
640 /* XXX: on Unix systems, using fstat() probably makes more sense */
643 fseek(f
, 0, SEEK_END
);
645 fseek(f
, where
, SEEK_SET
);
650 static void load_linux(void *fw_cfg
,
651 const char *kernel_filename
,
652 const char *initrd_filename
,
653 const char *kernel_cmdline
,
657 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
659 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
660 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
664 /* Align to 16 bytes as a paranoia measure */
665 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
667 /* load the kernel header */
668 f
= fopen(kernel_filename
, "rb");
669 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
670 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
671 MIN(ARRAY_SIZE(header
), kernel_size
)) {
672 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
673 kernel_filename
, strerror(errno
));
677 /* kernel protocol version */
679 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
681 if (ldl_p(header
+0x202) == 0x53726448) {
682 protocol
= lduw_p(header
+0x206);
684 /* This looks like a multiboot kernel. If it is, let's stop
685 treating it like a Linux kernel. */
686 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
687 kernel_cmdline
, kernel_size
, header
)) {
693 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
696 cmdline_addr
= 0x9a000 - cmdline_size
;
698 } else if (protocol
< 0x202) {
699 /* High but ancient kernel */
701 cmdline_addr
= 0x9a000 - cmdline_size
;
702 prot_addr
= 0x100000;
704 /* High and recent kernel */
706 cmdline_addr
= 0x20000;
707 prot_addr
= 0x100000;
712 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
713 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
714 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
720 /* highest address for loading the initrd */
721 if (protocol
>= 0x203) {
722 initrd_max
= ldl_p(header
+0x22c);
724 initrd_max
= 0x37ffffff;
727 if (initrd_max
>= max_ram_size
-ACPI_DATA_SIZE
)
728 initrd_max
= max_ram_size
-ACPI_DATA_SIZE
-1;
730 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
731 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
732 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
734 if (protocol
>= 0x202) {
735 stl_p(header
+0x228, cmdline_addr
);
737 stw_p(header
+0x20, 0xA33F);
738 stw_p(header
+0x22, cmdline_addr
-real_addr
);
741 /* handle vga= parameter */
742 vmode
= strstr(kernel_cmdline
, "vga=");
744 unsigned int video_mode
;
747 if (!strncmp(vmode
, "normal", 6)) {
749 } else if (!strncmp(vmode
, "ext", 3)) {
751 } else if (!strncmp(vmode
, "ask", 3)) {
754 video_mode
= strtol(vmode
, NULL
, 0);
756 stw_p(header
+0x1fa, video_mode
);
760 /* High nybble = B reserved for QEMU; low nybble is revision number.
761 If this code is substantially changed, you may want to consider
762 incrementing the revision. */
763 if (protocol
>= 0x200) {
764 header
[0x210] = 0xB0;
767 if (protocol
>= 0x201) {
768 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
769 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
773 if (initrd_filename
) {
774 if (protocol
< 0x200) {
775 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
779 initrd_size
= get_image_size(initrd_filename
);
780 if (initrd_size
< 0) {
781 fprintf(stderr
, "qemu: error reading initrd %s\n",
786 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
788 initrd_data
= g_malloc(initrd_size
);
789 load_image(initrd_filename
, initrd_data
);
791 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
792 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
793 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
795 stl_p(header
+0x218, initrd_addr
);
796 stl_p(header
+0x21c, initrd_size
);
799 /* load kernel and setup */
800 setup_size
= header
[0x1f1];
801 if (setup_size
== 0) {
804 setup_size
= (setup_size
+1)*512;
805 kernel_size
-= setup_size
;
807 setup
= g_malloc(setup_size
);
808 kernel
= g_malloc(kernel_size
);
809 fseek(f
, 0, SEEK_SET
);
810 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
811 fprintf(stderr
, "fread() failed\n");
814 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
815 fprintf(stderr
, "fread() failed\n");
819 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
821 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
822 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
823 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
825 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
826 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
827 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
829 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
830 option_rom
[nb_option_roms
].bootindex
= 0;
834 #define NE2000_NB_MAX 6
836 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
838 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
840 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
841 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
843 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
845 static int nb_ne2k
= 0;
847 if (nb_ne2k
== NE2000_NB_MAX
)
849 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
850 ne2000_irq
[nb_ne2k
], nd
);
854 DeviceState
*cpu_get_current_apic(void)
856 if (cpu_single_env
) {
857 return cpu_single_env
->apic_state
;
863 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
865 X86CPU
*cpu
= opaque
;
868 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
872 void pc_cpus_init(const char *cpu_model
)
877 if (cpu_model
== NULL
) {
879 cpu_model
= "qemu64";
881 cpu_model
= "qemu32";
885 for (i
= 0; i
< smp_cpus
; i
++) {
886 if (!cpu_x86_init(cpu_model
)) {
892 void pc_acpi_init(const char *default_dsdt
)
896 if (acpi_tables
!= NULL
) {
897 /* manually set via -acpitable, leave it alone */
901 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
902 if (filename
== NULL
) {
903 fprintf(stderr
, "WARNING: failed to find %s\n", default_dsdt
);
909 arg
= g_strdup_printf("file=%s", filename
);
911 /* creates a deep copy of "arg" */
912 opts
= qemu_opts_parse(qemu_find_opts("acpi"), arg
, 0);
913 g_assert(opts
!= NULL
);
915 acpi_table_add(opts
, &err
);
917 fprintf(stderr
, "WARNING: failed to load %s: %s\n", filename
,
918 error_get_pretty(err
));
926 void *pc_memory_init(MemoryRegion
*system_memory
,
927 const char *kernel_filename
,
928 const char *kernel_cmdline
,
929 const char *initrd_filename
,
930 ram_addr_t below_4g_mem_size
,
931 ram_addr_t above_4g_mem_size
,
932 MemoryRegion
*rom_memory
,
933 MemoryRegion
**ram_memory
)
936 MemoryRegion
*ram
, *option_rom_mr
;
937 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
940 linux_boot
= (kernel_filename
!= NULL
);
942 /* Allocate RAM. We allocate it as a single memory region and use
943 * aliases to address portions of it, mostly for backwards compatibility
944 * with older qemus that used qemu_ram_alloc().
946 ram
= g_malloc(sizeof(*ram
));
947 memory_region_init_ram(ram
, "pc.ram",
948 below_4g_mem_size
+ above_4g_mem_size
);
949 vmstate_register_ram_global(ram
);
951 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
952 memory_region_init_alias(ram_below_4g
, "ram-below-4g", ram
,
953 0, below_4g_mem_size
);
954 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
955 if (above_4g_mem_size
> 0) {
956 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
957 memory_region_init_alias(ram_above_4g
, "ram-above-4g", ram
,
958 below_4g_mem_size
, above_4g_mem_size
);
959 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
964 /* Initialize PC system firmware */
965 pc_system_firmware_init(rom_memory
);
967 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
968 memory_region_init_ram(option_rom_mr
, "pc.rom", PC_ROM_SIZE
);
969 vmstate_register_ram_global(option_rom_mr
);
970 memory_region_add_subregion_overlap(rom_memory
,
975 fw_cfg
= bochs_bios_init();
979 load_linux(fw_cfg
, kernel_filename
, initrd_filename
, kernel_cmdline
, below_4g_mem_size
);
982 for (i
= 0; i
< nb_option_roms
; i
++) {
983 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
988 qemu_irq
*pc_allocate_cpu_irq(void)
990 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
993 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
995 DeviceState
*dev
= NULL
;
998 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
999 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1000 } else if (isa_bus
) {
1001 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1002 dev
= isadev
? &isadev
->qdev
: NULL
;
1007 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1009 CPUX86State
*env
= cpu_single_env
;
1016 static const MemoryRegionOps ioport80_io_ops
= {
1017 .write
= ioport80_write
,
1018 .read
= ioport80_read
,
1019 .endianness
= DEVICE_NATIVE_ENDIAN
,
1021 .min_access_size
= 1,
1022 .max_access_size
= 1,
1026 static const MemoryRegionOps ioportF0_io_ops
= {
1027 .write
= ioportF0_write
,
1028 .read
= ioportF0_read
,
1029 .endianness
= DEVICE_NATIVE_ENDIAN
,
1031 .min_access_size
= 1,
1032 .max_access_size
= 1,
1036 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1037 ISADevice
**rtc_state
,
1042 DriveInfo
*fd
[MAX_FD
];
1043 DeviceState
*hpet
= NULL
;
1044 int pit_isa_irq
= 0;
1045 qemu_irq pit_alt_irq
= NULL
;
1046 qemu_irq rtc_irq
= NULL
;
1048 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1049 qemu_irq
*cpu_exit_irq
;
1050 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1051 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1053 memory_region_init_io(ioport80_io
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1054 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1056 memory_region_init_io(ioportF0_io
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1057 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1060 * Check if an HPET shall be created.
1062 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1063 * when the HPET wants to take over. Thus we have to disable the latter.
1065 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1066 hpet
= sysbus_try_create_simple("hpet", HPET_BASE
, NULL
);
1069 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1070 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1073 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1074 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1077 *rtc_state
= rtc_init(isa_bus
, 2000, rtc_irq
);
1079 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1081 if (!xen_enabled()) {
1082 if (kvm_irqchip_in_kernel()) {
1083 pit
= kvm_pit_init(isa_bus
, 0x40);
1085 pit
= pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1088 /* connect PIT to output control line of the HPET */
1089 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(&pit
->qdev
, 0));
1091 pcspk_init(isa_bus
, pit
);
1094 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1095 if (serial_hds
[i
]) {
1096 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
1100 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1101 if (parallel_hds
[i
]) {
1102 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
1106 a20_line
= qemu_allocate_irqs(handle_a20_line_change
,
1107 x86_env_get_cpu(first_cpu
), 2);
1108 i8042
= isa_create_simple(isa_bus
, "i8042");
1109 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1111 vmport_init(isa_bus
);
1112 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1117 qdev_prop_set_ptr(&vmmouse
->qdev
, "ps2_mouse", i8042
);
1118 qdev_init_nofail(&vmmouse
->qdev
);
1120 port92
= isa_create_simple(isa_bus
, "port92");
1121 port92_init(port92
, &a20_line
[1]);
1123 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1124 DMA_init(0, cpu_exit_irq
);
1126 for(i
= 0; i
< MAX_FD
; i
++) {
1127 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1129 *floppy
= fdctrl_init_isa(isa_bus
, fd
);
1132 void pc_nic_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1136 for (i
= 0; i
< nb_nics
; i
++) {
1137 NICInfo
*nd
= &nd_table
[i
];
1139 if (!pci_bus
|| (nd
->model
&& strcmp(nd
->model
, "ne2k_isa") == 0)) {
1140 pc_init_ne2k_isa(isa_bus
, nd
);
1142 pci_nic_init_nofail(nd
, "e1000", NULL
);
1147 void pc_pci_device_init(PCIBus
*pci_bus
)
1152 max_bus
= drive_get_max_bus(IF_SCSI
);
1153 for (bus
= 0; bus
<= max_bus
; bus
++) {
1154 pci_create_simple(pci_bus
, -1, "lsi53c895a");
1158 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1164 if (kvm_irqchip_in_kernel()) {
1165 dev
= qdev_create(NULL
, "kvm-ioapic");
1167 dev
= qdev_create(NULL
, "ioapic");
1170 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1171 "ioapic", OBJECT(dev
), NULL
);
1173 qdev_init_nofail(dev
);
1174 d
= SYS_BUS_DEVICE(dev
);
1175 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1177 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1178 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);