hw/riscv/virt.c

   1 /*
   2  * QEMU RISC-V VirtIO Board
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * RISC-V machine with 16550a UART and VirtIO MMIO
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/units.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "qapi/error.h"
  26 #include "hw/boards.h"
  27 #include "hw/loader.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/char/serial.h"
  31 #include "target/riscv/cpu.h"
  32 #include "hw/riscv/riscv_hart.h"
  33 #include "hw/riscv/virt.h"
  34 #include "hw/riscv/boot.h"
  35 #include "hw/riscv/numa.h"
  36 #include "hw/intc/sifive_clint.h"
  37 #include "hw/intc/sifive_plic.h"
  38 #include "hw/misc/sifive_test.h"
  39 #include "chardev/char.h"
  40 #include "sysemu/arch_init.h"
  41 #include "sysemu/device_tree.h"
  42 #include "sysemu/sysemu.h"
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci-host/gpex.h"
  45
  46 static const struct MemmapEntry {
  47     hwaddr base;
  48     hwaddr size;
  49 } virt_memmap[] = {
  50     [VIRT_DEBUG] =       {        0x0,         0x100 },
  51     [VIRT_MROM] =        {     0x1000,        0xf000 },
  52     [VIRT_TEST] =        {   0x100000,        0x1000 },
  53     [VIRT_RTC] =         {   0x101000,        0x1000 },
  54     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
  55     [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
  56     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
  57     [VIRT_UART0] =       { 0x10000000,         0x100 },
  58     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
  59     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
  60     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
  61     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
  62     [VIRT_DRAM] =        { 0x80000000,           0x0 },
  63 };
  64
  65 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
  66
  67 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
  68                                        const char *name,
  69                                        const char *alias_prop_name)
  70 {
  71     /*
  72      * Create a single flash device.  We use the same parameters as
  73      * the flash devices on the ARM virt board.
  74      */
  75     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
  76
  77     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
  78     qdev_prop_set_uint8(dev, "width", 4);
  79     qdev_prop_set_uint8(dev, "device-width", 2);
  80     qdev_prop_set_bit(dev, "big-endian", false);
  81     qdev_prop_set_uint16(dev, "id0", 0x89);
  82     qdev_prop_set_uint16(dev, "id1", 0x18);
  83     qdev_prop_set_uint16(dev, "id2", 0x00);
  84     qdev_prop_set_uint16(dev, "id3", 0x00);
  85     qdev_prop_set_string(dev, "name", name);
  86
  87     object_property_add_child(OBJECT(s), name, OBJECT(dev));
  88     object_property_add_alias(OBJECT(s), alias_prop_name,
  89                               OBJECT(dev), "drive");
  90
  91     return PFLASH_CFI01(dev);
  92 }
  93
  94 static void virt_flash_create(RISCVVirtState *s)
  95 {
  96     s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
  97     s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
  98 }
  99
 100 static void virt_flash_map1(PFlashCFI01 *flash,
 101                             hwaddr base, hwaddr size,
 102                             MemoryRegion *sysmem)
 103 {
 104     DeviceState *dev = DEVICE(flash);
 105
 106     assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
 107     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
 108     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
 109     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 110
 111     memory_region_add_subregion(sysmem, base,
 112                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
 113                                                        0));
 114 }
 115
 116 static void virt_flash_map(RISCVVirtState *s,
 117                            MemoryRegion *sysmem)
 118 {
 119     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 120     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 121
 122     virt_flash_map1(s->flash[0], flashbase, flashsize,
 123                     sysmem);
 124     virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
 125                     sysmem);
 126 }
 127
 128 static void create_pcie_irq_map(void *fdt, char *nodename,
 129                                 uint32_t plic_phandle)
 130 {
 131     int pin, dev;
 132     uint32_t
 133         full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
 134     uint32_t *irq_map = full_irq_map;
 135
 136     /* This code creates a standard swizzle of interrupts such that
 137      * each device's first interrupt is based on it's PCI_SLOT number.
 138      * (See pci_swizzle_map_irq_fn())
 139      *
 140      * We only need one entry per interrupt in the table (not one per
 141      * possible slot) seeing the interrupt-map-mask will allow the table
 142      * to wrap to any number of devices.
 143      */
 144     for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
 145         int devfn = dev * 0x8;
 146
 147         for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
 148             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
 149             int i = 0;
 150
 151             irq_map[i] = cpu_to_be32(devfn << 8);
 152
 153             i += FDT_PCI_ADDR_CELLS;
 154             irq_map[i] = cpu_to_be32(pin + 1);
 155
 156             i += FDT_PCI_INT_CELLS;
 157             irq_map[i++] = cpu_to_be32(plic_phandle);
 158
 159             i += FDT_PLIC_ADDR_CELLS;
 160             irq_map[i] = cpu_to_be32(irq_nr);
 161
 162             irq_map += FDT_INT_MAP_WIDTH;
 163         }
 164     }
 165
 166     qemu_fdt_setprop(fdt, nodename, "interrupt-map",
 167                      full_irq_map, sizeof(full_irq_map));
 168
 169     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
 170                            0x1800, 0, 0, 0x7);
 171 }
 172
 173 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 174                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
 175 {
 176     void *fdt;
 177     int i, cpu, socket;
 178     MachineState *mc = MACHINE(s);
 179     uint64_t addr, size;
 180     uint32_t *clint_cells, *plic_cells;
 181     unsigned long clint_addr, plic_addr;
 182     uint32_t plic_phandle[MAX_NODES];
 183     uint32_t cpu_phandle, intc_phandle, test_phandle;
 184     uint32_t phandle = 1, plic_mmio_phandle = 1;
 185     uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
 186     char *mem_name, *cpu_name, *core_name, *intc_name;
 187     char *name, *clint_name, *plic_name, *clust_name;
 188     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 189     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 190
 191     if (mc->dtb) {
 192         fdt = s->fdt = load_device_tree(mc->dtb, &s->fdt_size);
 193         if (!fdt) {
 194             error_report("load_device_tree() failed");
 195             exit(1);
 196         }
 197         goto update_bootargs;
 198     } else {
 199         fdt = s->fdt = create_device_tree(&s->fdt_size);
 200         if (!fdt) {
 201             error_report("create_device_tree() failed");
 202             exit(1);
 203         }
 204     }
 205
 206     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
 207     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
 208     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 209     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 210
 211     qemu_fdt_add_subnode(fdt, "/soc");
 212     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 213     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 214     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 215     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 216
 217     qemu_fdt_add_subnode(fdt, "/cpus");
 218     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 219                           SIFIVE_CLINT_TIMEBASE_FREQ);
 220     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 221     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 222     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 223
 224     for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
 225         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
 226         qemu_fdt_add_subnode(fdt, clust_name);
 227
 228         plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 229         clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 230
 231         for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
 232             cpu_phandle = phandle++;
 233
 234             cpu_name = g_strdup_printf("/cpus/cpu@%d",
 235                 s->soc[socket].hartid_base + cpu);
 236             qemu_fdt_add_subnode(fdt, cpu_name);
 237             if (is_32_bit) {
 238                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
 239             } else {
 240                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
 241             }
 242             name = riscv_isa_string(&s->soc[socket].harts[cpu]);
 243             qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
 244             g_free(name);
 245             qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
 246             qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
 247             qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
 248                 s->soc[socket].hartid_base + cpu);
 249             qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
 250             riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
 251             qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 252
 253             intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
 254             qemu_fdt_add_subnode(fdt, intc_name);
 255             intc_phandle = phandle++;
 256             qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
 257             qemu_fdt_setprop_string(fdt, intc_name, "compatible",
 258                 "riscv,cpu-intc");
 259             qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
 260             qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
 261
 262             clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 263             clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 264             clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 265             clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 266
 267             plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 268             plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 269             plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 270             plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 271
 272             core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
 273             qemu_fdt_add_subnode(fdt, core_name);
 274             qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
 275
 276             g_free(core_name);
 277             g_free(intc_name);
 278             g_free(cpu_name);
 279         }
 280
 281         addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
 282         size = riscv_socket_mem_size(mc, socket);
 283         mem_name = g_strdup_printf("/memory@%lx", (long)addr);
 284         qemu_fdt_add_subnode(fdt, mem_name);
 285         qemu_fdt_setprop_cells(fdt, mem_name, "reg",
 286             addr >> 32, addr, size >> 32, size);
 287         qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
 288         riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
 289         g_free(mem_name);
 290
 291         clint_addr = memmap[VIRT_CLINT].base +
 292             (memmap[VIRT_CLINT].size * socket);
 293         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
 294         qemu_fdt_add_subnode(fdt, clint_name);
 295         qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
 296         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
 297             0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
 298         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
 299             clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 300         riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
 301         g_free(clint_name);
 302
 303         plic_phandle[socket] = phandle++;
 304         plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
 305         plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
 306         qemu_fdt_add_subnode(fdt, plic_name);
 307         qemu_fdt_setprop_cell(fdt, plic_name,
 308             "#address-cells", FDT_PLIC_ADDR_CELLS);
 309         qemu_fdt_setprop_cell(fdt, plic_name,
 310             "#interrupt-cells", FDT_PLIC_INT_CELLS);
 311         qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
 312         qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
 313         qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
 314             plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 315         qemu_fdt_setprop_cells(fdt, plic_name, "reg",
 316             0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
 317         qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
 318         riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
 319         qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
 320         g_free(plic_name);
 321
 322         g_free(clint_cells);
 323         g_free(plic_cells);
 324         g_free(clust_name);
 325     }
 326
 327     for (socket = 0; socket < riscv_socket_count(mc); socket++) {
 328         if (socket == 0) {
 329             plic_mmio_phandle = plic_phandle[socket];
 330             plic_virtio_phandle = plic_phandle[socket];
 331             plic_pcie_phandle = plic_phandle[socket];
 332         }
 333         if (socket == 1) {
 334             plic_virtio_phandle = plic_phandle[socket];
 335             plic_pcie_phandle = plic_phandle[socket];
 336         }
 337         if (socket == 2) {
 338             plic_pcie_phandle = plic_phandle[socket];
 339         }
 340     }
 341
 342     riscv_socket_fdt_write_distance_matrix(mc, fdt);
 343
 344     for (i = 0; i < VIRTIO_COUNT; i++) {
 345         name = g_strdup_printf("/soc/virtio_mmio@%lx",
 346             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
 347         qemu_fdt_add_subnode(fdt, name);
 348         qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
 349         qemu_fdt_setprop_cells(fdt, name, "reg",
 350             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 351             0x0, memmap[VIRT_VIRTIO].size);
 352         qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
 353             plic_virtio_phandle);
 354         qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
 355         g_free(name);
 356     }
 357
 358     name = g_strdup_printf("/soc/pci@%lx",
 359         (long) memmap[VIRT_PCIE_ECAM].base);
 360     qemu_fdt_add_subnode(fdt, name);
 361     qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
 362     qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
 363     qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
 364     qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
 365     qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
 366     qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
 367     qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
 368         memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
 369     qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
 370     qemu_fdt_setprop_cells(fdt, name, "reg", 0,
 371         memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
 372     qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
 373         1, FDT_PCI_RANGE_IOPORT, 2, 0,
 374         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
 375         1, FDT_PCI_RANGE_MMIO,
 376         2, memmap[VIRT_PCIE_MMIO].base,
 377         2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
 378     create_pcie_irq_map(fdt, name, plic_pcie_phandle);
 379     g_free(name);
 380
 381     test_phandle = phandle++;
 382     name = g_strdup_printf("/soc/test@%lx",
 383         (long)memmap[VIRT_TEST].base);
 384     qemu_fdt_add_subnode(fdt, name);
 385     {
 386         const char compat[] = "sifive,test1\0sifive,test0\0syscon";
 387         qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
 388     }
 389     qemu_fdt_setprop_cells(fdt, name, "reg",
 390         0x0, memmap[VIRT_TEST].base,
 391         0x0, memmap[VIRT_TEST].size);
 392     qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
 393     test_phandle = qemu_fdt_get_phandle(fdt, name);
 394     g_free(name);
 395
 396     name = g_strdup_printf("/soc/reboot");
 397     qemu_fdt_add_subnode(fdt, name);
 398     qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
 399     qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
 400     qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
 401     qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
 402     g_free(name);
 403
 404     name = g_strdup_printf("/soc/poweroff");
 405     qemu_fdt_add_subnode(fdt, name);
 406     qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
 407     qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
 408     qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
 409     qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
 410     g_free(name);
 411
 412     name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
 413     qemu_fdt_add_subnode(fdt, name);
 414     qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
 415     qemu_fdt_setprop_cells(fdt, name, "reg",
 416         0x0, memmap[VIRT_UART0].base,
 417         0x0, memmap[VIRT_UART0].size);
 418     qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
 419     qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
 420     qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
 421
 422     qemu_fdt_add_subnode(fdt, "/chosen");
 423     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
 424     g_free(name);
 425
 426     name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
 427     qemu_fdt_add_subnode(fdt, name);
 428     qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
 429     qemu_fdt_setprop_cells(fdt, name, "reg",
 430         0x0, memmap[VIRT_RTC].base,
 431         0x0, memmap[VIRT_RTC].size);
 432     qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
 433     qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
 434     g_free(name);
 435
 436     name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
 437     qemu_fdt_add_subnode(s->fdt, name);
 438     qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash");
 439     qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 440                                  2, flashbase, 2, flashsize,
 441                                  2, flashbase + flashsize, 2, flashsize);
 442     qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
 443     g_free(name);
 444
 445 update_bootargs:
 446     if (cmdline) {
 447         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 448     }
 449 }
 450
 451 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
 452                                           hwaddr ecam_base, hwaddr ecam_size,
 453                                           hwaddr mmio_base, hwaddr mmio_size,
 454                                           hwaddr pio_base,
 455                                           DeviceState *plic, bool link_up)
 456 {
 457     DeviceState *dev;
 458     MemoryRegion *ecam_alias, *ecam_reg;
 459     MemoryRegion *mmio_alias, *mmio_reg;
 460     qemu_irq irq;
 461     int i;
 462
 463     dev = qdev_new(TYPE_GPEX_HOST);
 464
 465     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 466
 467     ecam_alias = g_new0(MemoryRegion, 1);
 468     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 469     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 470                              ecam_reg, 0, ecam_size);
 471     memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
 472
 473     mmio_alias = g_new0(MemoryRegion, 1);
 474     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 475     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
 476                              mmio_reg, mmio_base, mmio_size);
 477     memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
 478
 479     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
 480
 481     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 482         irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
 483
 484         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
 485         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
 486     }
 487
 488     return dev;
 489 }
 490
 491 static void virt_machine_init(MachineState *machine)
 492 {
 493     const struct MemmapEntry *memmap = virt_memmap;
 494     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
 495     MemoryRegion *system_memory = get_system_memory();
 496     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 497     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 498     char *plic_hart_config, *soc_name;
 499     size_t plic_hart_config_len;
 500     target_ulong start_addr = memmap[VIRT_DRAM].base;
 501     target_ulong firmware_end_addr, kernel_start_addr;
 502     uint32_t fdt_load_addr;
 503     uint64_t kernel_entry;
 504     DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
 505     int i, j, base_hartid, hart_count;
 506
 507     /* Check socket count limit */
 508     if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
 509         error_report("number of sockets/nodes should be less than %d",
 510             VIRT_SOCKETS_MAX);
 511         exit(1);
 512     }
 513
 514     /* Initialize sockets */
 515     mmio_plic = virtio_plic = pcie_plic = NULL;
 516     for (i = 0; i < riscv_socket_count(machine); i++) {
 517         if (!riscv_socket_check_hartids(machine, i)) {
 518             error_report("discontinuous hartids in socket%d", i);
 519             exit(1);
 520         }
 521
 522         base_hartid = riscv_socket_first_hartid(machine, i);
 523         if (base_hartid < 0) {
 524             error_report("can't find hartid base for socket%d", i);
 525             exit(1);
 526         }
 527
 528         hart_count = riscv_socket_hart_count(machine, i);
 529         if (hart_count < 0) {
 530             error_report("can't find hart count for socket%d", i);
 531             exit(1);
 532         }
 533
 534         soc_name = g_strdup_printf("soc%d", i);
 535         object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
 536                                 TYPE_RISCV_HART_ARRAY);
 537         g_free(soc_name);
 538         object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
 539                                 machine->cpu_type, &error_abort);
 540         object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
 541                                 base_hartid, &error_abort);
 542         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
 543                                 hart_count, &error_abort);
 544         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 545
 546         /* Per-socket CLINT */
 547         sifive_clint_create(
 548             memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 549             memmap[VIRT_CLINT].size, base_hartid, hart_count,
 550             SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 551             SIFIVE_CLINT_TIMEBASE_FREQ, true);
 552
 553         /* Per-socket PLIC hart topology configuration string */
 554         plic_hart_config_len =
 555             (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
 556         plic_hart_config = g_malloc0(plic_hart_config_len);
 557         for (j = 0; j < hart_count; j++) {
 558             if (j != 0) {
 559                 strncat(plic_hart_config, ",", plic_hart_config_len);
 560             }
 561             strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
 562                 plic_hart_config_len);
 563             plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 564         }
 565
 566         /* Per-socket PLIC */
 567         s->plic[i] = sifive_plic_create(
 568             memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
 569             plic_hart_config, base_hartid,
 570             VIRT_PLIC_NUM_SOURCES,
 571             VIRT_PLIC_NUM_PRIORITIES,
 572             VIRT_PLIC_PRIORITY_BASE,
 573             VIRT_PLIC_PENDING_BASE,
 574             VIRT_PLIC_ENABLE_BASE,
 575             VIRT_PLIC_ENABLE_STRIDE,
 576             VIRT_PLIC_CONTEXT_BASE,
 577             VIRT_PLIC_CONTEXT_STRIDE,
 578             memmap[VIRT_PLIC].size);
 579         g_free(plic_hart_config);
 580
 581         /* Try to use different PLIC instance based device type */
 582         if (i == 0) {
 583             mmio_plic = s->plic[i];
 584             virtio_plic = s->plic[i];
 585             pcie_plic = s->plic[i];
 586         }
 587         if (i == 1) {
 588             virtio_plic = s->plic[i];
 589             pcie_plic = s->plic[i];
 590         }
 591         if (i == 2) {
 592             pcie_plic = s->plic[i];
 593         }
 594     }
 595
 596     /* register system main memory (actual RAM) */
 597     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 598                            machine->ram_size, &error_fatal);
 599     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 600         main_mem);
 601
 602     /* create device tree */
 603     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 604                riscv_is_32bit(&s->soc[0]));
 605
 606     /* boot rom */
 607     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
 608                            memmap[VIRT_MROM].size, &error_fatal);
 609     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
 610                                 mask_rom);
 611
 612     if (riscv_is_32bit(&s->soc[0])) {
 613         firmware_end_addr = riscv_find_and_load_firmware(machine,
 614                                     "opensbi-riscv32-generic-fw_dynamic.bin",
 615                                     start_addr, NULL);
 616     } else {
 617         firmware_end_addr = riscv_find_and_load_firmware(machine,
 618                                     "opensbi-riscv64-generic-fw_dynamic.bin",
 619                                     start_addr, NULL);
 620     }
 621
 622     if (machine->kernel_filename) {
 623         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
 624                                                          firmware_end_addr);
 625
 626         kernel_entry = riscv_load_kernel(machine->kernel_filename,
 627                                          kernel_start_addr, NULL);
 628
 629         if (machine->initrd_filename) {
 630             hwaddr start;
 631             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 632                                            machine->ram_size, kernel_entry,
 633                                            &start);
 634             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 635                                   "linux,initrd-start", start);
 636             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 637                                   end);
 638         }
 639     } else {
 640        /*
 641         * If dynamic firmware is used, it doesn't know where is the next mode
 642         * if kernel argument is not set.
 643         */
 644         kernel_entry = 0;
 645     }
 646
 647     if (drive_get(IF_PFLASH, 0, 0)) {
 648         /*
 649          * Pflash was supplied, let's overwrite the address we jump to after
 650          * reset to the base of the flash.
 651          */
 652         start_addr = virt_memmap[VIRT_FLASH].base;
 653     }
 654
 655     /* Compute the fdt load address in dram */
 656     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
 657                                    machine->ram_size, s->fdt);
 658     /* load the reset vector */
 659     riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
 660                               virt_memmap[VIRT_MROM].base,
 661                               virt_memmap[VIRT_MROM].size, kernel_entry,
 662                               fdt_load_addr, s->fdt);
 663
 664     /* SiFive Test MMIO device */
 665     sifive_test_create(memmap[VIRT_TEST].base);
 666
 667     /* VirtIO MMIO devices */
 668     for (i = 0; i < VIRTIO_COUNT; i++) {
 669         sysbus_create_simple("virtio-mmio",
 670             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 671             qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
 672     }
 673
 674     gpex_pcie_init(system_memory,
 675                          memmap[VIRT_PCIE_ECAM].base,
 676                          memmap[VIRT_PCIE_ECAM].size,
 677                          memmap[VIRT_PCIE_MMIO].base,
 678                          memmap[VIRT_PCIE_MMIO].size,
 679                          memmap[VIRT_PCIE_PIO].base,
 680                          DEVICE(pcie_plic), true);
 681
 682     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 683         0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
 684         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 685
 686     sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
 687         qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
 688
 689     virt_flash_create(s);
 690
 691     for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
 692         /* Map legacy -drive if=pflash to machine properties */
 693         pflash_cfi01_legacy_drive(s->flash[i],
 694                                   drive_get(IF_PFLASH, 0, i));
 695     }
 696     virt_flash_map(s, system_memory);
 697 }
 698
 699 static void virt_machine_instance_init(Object *obj)
 700 {
 701 }
 702
 703 static void virt_machine_class_init(ObjectClass *oc, void *data)
 704 {
 705     MachineClass *mc = MACHINE_CLASS(oc);
 706
 707     mc->desc = "RISC-V VirtIO board";
 708     mc->init = virt_machine_init;
 709     mc->max_cpus = VIRT_CPUS_MAX;
 710     mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
 711     mc->pci_allow_0_address = true;
 712     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
 713     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
 714     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
 715     mc->numa_mem_supported = true;
 716 }
 717
 718 static const TypeInfo virt_machine_typeinfo = {
 719     .name       = MACHINE_TYPE_NAME("virt"),
 720     .parent     = TYPE_MACHINE,
 721     .class_init = virt_machine_class_init,
 722     .instance_init = virt_machine_instance_init,
 723     .instance_size = sizeof(RISCVVirtState),
 724 };
 725
 726 static void virt_machine_init_register_types(void)
 727 {
 728     type_register_static(&virt_machine_typeinfo);
 729 }
 730
 731 type_init(virt_machine_init_register_types)