target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <signal.h>
  21
  22 #include "qemu-common.h"
  23 #include "cpu.h"
  24 #include "sysemu/kvm.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 enum {
  28     TLBRET_XI = -6,
  29     TLBRET_RI = -5,
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ;
  45     if (rw) {
  46         *prot |= PAGE_WRITE;
  47     }
  48     return TLBRET_MATCH;
  49 }
  50
  51 /* fixed mapping MMU emulation */
  52 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  53                            target_ulong address, int rw, int access_type)
  54 {
  55     if (address <= (int32_t)0x7FFFFFFFUL) {
  56         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  57             *physical = address + 0x40000000UL;
  58         else
  59             *physical = address;
  60     } else if (address <= (int32_t)0xBFFFFFFFUL)
  61         *physical = address & 0x1FFFFFFF;
  62     else
  63         *physical = address;
  64
  65     *prot = PAGE_READ;
  66     if (rw) {
  67         *prot |= PAGE_WRITE;
  68     }
  69     return TLBRET_MATCH;
  70 }
  71
  72 /* MIPS32/MIPS64 R4000-style MMU emulation */
  73 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  74                      target_ulong address, int rw, int access_type)
  75 {
  76     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  77     int i;
  78
  79     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  80         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  81         /* 1k pages are not supported. */
  82         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  83         target_ulong tag = address & ~mask;
  84         target_ulong VPN = tlb->VPN & ~mask;
  85 #if defined(TARGET_MIPS64)
  86         tag &= env->SEGMask;
  87 #endif
  88
  89         /* Check ASID, virtual page number & size */
  90         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  91             /* TLB match */
  92             int n = !!(address & mask & ~(mask >> 1));
  93             /* Check access rights */
  94             if (!(n ? tlb->V1 : tlb->V0)) {
  95                 return TLBRET_INVALID;
  96             }
  97             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  98                 return TLBRET_XI;
  99             }
 100             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
 101                 return TLBRET_RI;
 102             }
 103             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
 104                 *physical = tlb->PFN[n] | (address & (mask >> 1));
 105                 *prot = PAGE_READ;
 106                 if (n ? tlb->D1 : tlb->D0)
 107                     *prot |= PAGE_WRITE;
 108                 return TLBRET_MATCH;
 109             }
 110             return TLBRET_DIRTY;
 111         }
 112     }
 113     return TLBRET_NOMATCH;
 114 }
 115
 116 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 117                                 int *prot, target_ulong real_address,
 118                                 int rw, int access_type)
 119 {
 120     /* User mode can only access useg/xuseg */
 121     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 122     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 123     int kernel_mode = !user_mode && !supervisor_mode;
 124 #if defined(TARGET_MIPS64)
 125     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 126     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 127     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 128 #endif
 129     int ret = TLBRET_MATCH;
 130     /* effective address (modified for KVM T&E kernel segments) */
 131     target_ulong address = real_address;
 132
 133 #define USEG_LIMIT      0x7FFFFFFFUL
 134 #define KSEG0_BASE      0x80000000UL
 135 #define KSEG1_BASE      0xA0000000UL
 136 #define KSEG2_BASE      0xC0000000UL
 137 #define KSEG3_BASE      0xE0000000UL
 138
 139 #define KVM_KSEG0_BASE  0x40000000UL
 140 #define KVM_KSEG2_BASE  0x60000000UL
 141
 142     if (kvm_enabled()) {
 143         /* KVM T&E adds guest kernel segments in useg */
 144         if (real_address >= KVM_KSEG0_BASE) {
 145             if (real_address < KVM_KSEG2_BASE) {
 146                 /* kseg0 */
 147                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 148             } else if (real_address <= USEG_LIMIT) {
 149                 /* kseg2/3 */
 150                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 151             }
 152         }
 153     }
 154
 155     if (address <= USEG_LIMIT) {
 156         /* useg */
 157         if (env->CP0_Status & (1 << CP0St_ERL)) {
 158             *physical = address & 0xFFFFFFFF;
 159             *prot = PAGE_READ;
 160             if (rw) {
 161                 *prot |= PAGE_WRITE;
 162             }
 163         } else {
 164             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 165         }
 166 #if defined(TARGET_MIPS64)
 167     } else if (address < 0x4000000000000000ULL) {
 168         /* xuseg */
 169         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 170             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 171         } else {
 172             ret = TLBRET_BADADDR;
 173         }
 174     } else if (address < 0x8000000000000000ULL) {
 175         /* xsseg */
 176         if ((supervisor_mode || kernel_mode) &&
 177             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 178             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 179         } else {
 180             ret = TLBRET_BADADDR;
 181         }
 182     } else if (address < 0xC000000000000000ULL) {
 183         /* xkphys */
 184         if (kernel_mode && KX &&
 185             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 186             *physical = address & env->PAMask;
 187             *prot = PAGE_READ;
 188             if (rw) {
 189                 *prot |= PAGE_WRITE;
 190             }
 191         } else {
 192             ret = TLBRET_BADADDR;
 193         }
 194     } else if (address < 0xFFFFFFFF80000000ULL) {
 195         /* xkseg */
 196         if (kernel_mode && KX &&
 197             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 198             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 199         } else {
 200             ret = TLBRET_BADADDR;
 201         }
 202 #endif
 203     } else if (address < (int32_t)KSEG1_BASE) {
 204         /* kseg0 */
 205         if (kernel_mode) {
 206             *physical = address - (int32_t)KSEG0_BASE;
 207             *prot = PAGE_READ;
 208             if (rw) {
 209                 *prot |= PAGE_WRITE;
 210             }
 211         } else {
 212             ret = TLBRET_BADADDR;
 213         }
 214     } else if (address < (int32_t)KSEG2_BASE) {
 215         /* kseg1 */
 216         if (kernel_mode) {
 217             *physical = address - (int32_t)KSEG1_BASE;
 218             *prot = PAGE_READ;
 219             if (rw) {
 220                 *prot |= PAGE_WRITE;
 221             }
 222         } else {
 223             ret = TLBRET_BADADDR;
 224         }
 225     } else if (address < (int32_t)KSEG3_BASE) {
 226         /* sseg (kseg2) */
 227         if (supervisor_mode || kernel_mode) {
 228             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 229         } else {
 230             ret = TLBRET_BADADDR;
 231         }
 232     } else {
 233         /* kseg3 */
 234         /* XXX: debug segment is not emulated */
 235         if (kernel_mode) {
 236             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 237         } else {
 238             ret = TLBRET_BADADDR;
 239         }
 240     }
 241     return ret;
 242 }
 243 #endif
 244
 245 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 246                                 int rw, int tlb_error)
 247 {
 248     CPUState *cs = CPU(mips_env_get_cpu(env));
 249     int exception = 0, error_code = 0;
 250
 251     if (rw == MMU_INST_FETCH) {
 252         error_code |= EXCP_INST_NOTAVAIL;
 253     }
 254
 255     switch (tlb_error) {
 256     default:
 257     case TLBRET_BADADDR:
 258         /* Reference to kernel address from user mode or supervisor mode */
 259         /* Reference to supervisor address from user mode */
 260         if (rw == MMU_DATA_STORE) {
 261             exception = EXCP_AdES;
 262         } else {
 263             exception = EXCP_AdEL;
 264         }
 265         break;
 266     case TLBRET_NOMATCH:
 267         /* No TLB match for a mapped address */
 268         if (rw == MMU_DATA_STORE) {
 269             exception = EXCP_TLBS;
 270         } else {
 271             exception = EXCP_TLBL;
 272         }
 273         error_code |= EXCP_TLB_NOMATCH;
 274         break;
 275     case TLBRET_INVALID:
 276         /* TLB match with no valid bit */
 277         if (rw == MMU_DATA_STORE) {
 278             exception = EXCP_TLBS;
 279         } else {
 280             exception = EXCP_TLBL;
 281         }
 282         break;
 283     case TLBRET_DIRTY:
 284         /* TLB match but 'D' bit is cleared */
 285         exception = EXCP_LTLBL;
 286         break;
 287     case TLBRET_XI:
 288         /* Execute-Inhibit Exception */
 289         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 290             exception = EXCP_TLBXI;
 291         } else {
 292             exception = EXCP_TLBL;
 293         }
 294         break;
 295     case TLBRET_RI:
 296         /* Read-Inhibit Exception */
 297         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 298             exception = EXCP_TLBRI;
 299         } else {
 300             exception = EXCP_TLBL;
 301         }
 302         break;
 303     }
 304     /* Raise exception */
 305     env->CP0_BadVAddr = address;
 306     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 307                        ((address >> 9) & 0x007ffff0);
 308     env->CP0_EntryHi =
 309         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 310 #if defined(TARGET_MIPS64)
 311     env->CP0_EntryHi &= env->SEGMask;
 312     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 313                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 314                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 315 #endif
 316     cs->exception_index = exception;
 317     env->error_code = error_code;
 318 }
 319
 320 #if !defined(CONFIG_USER_ONLY)
 321 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 322 {
 323     MIPSCPU *cpu = MIPS_CPU(cs);
 324     hwaddr phys_addr;
 325     int prot;
 326
 327     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 328                              ACCESS_INT) != 0) {
 329         return -1;
 330     }
 331     return phys_addr;
 332 }
 333 #endif
 334
 335 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 336                               int mmu_idx)
 337 {
 338     MIPSCPU *cpu = MIPS_CPU(cs);
 339     CPUMIPSState *env = &cpu->env;
 340 #if !defined(CONFIG_USER_ONLY)
 341     hwaddr physical;
 342     int prot;
 343     int access_type;
 344 #endif
 345     int ret = 0;
 346
 347 #if 0
 348     log_cpu_state(cs, 0);
 349 #endif
 350     qemu_log_mask(CPU_LOG_MMU,
 351               "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 352               __func__, env->active_tc.PC, address, rw, mmu_idx);
 353
 354     /* data access */
 355 #if !defined(CONFIG_USER_ONLY)
 356     /* XXX: put correct access by using cpu_restore_state()
 357        correctly */
 358     access_type = ACCESS_INT;
 359     ret = get_physical_address(env, &physical, &prot,
 360                                address, rw, access_type);
 361     qemu_log_mask(CPU_LOG_MMU,
 362              "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 363              " prot %d\n",
 364              __func__, address, ret, physical, prot);
 365     if (ret == TLBRET_MATCH) {
 366         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 367                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 368                      mmu_idx, TARGET_PAGE_SIZE);
 369         ret = 0;
 370     } else if (ret < 0)
 371 #endif
 372     {
 373         raise_mmu_exception(env, address, rw, ret);
 374         ret = 1;
 375     }
 376
 377     return ret;
 378 }
 379
 380 #if !defined(CONFIG_USER_ONLY)
 381 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 382 {
 383     hwaddr physical;
 384     int prot;
 385     int access_type;
 386     int ret = 0;
 387
 388     /* data access */
 389     access_type = ACCESS_INT;
 390     ret = get_physical_address(env, &physical, &prot,
 391                                address, rw, access_type);
 392     if (ret != TLBRET_MATCH) {
 393         raise_mmu_exception(env, address, rw, ret);
 394         return -1LL;
 395     } else {
 396         return physical;
 397     }
 398 }
 399
 400 static const char * const excp_names[EXCP_LAST + 1] = {
 401     [EXCP_RESET] = "reset",
 402     [EXCP_SRESET] = "soft reset",
 403     [EXCP_DSS] = "debug single step",
 404     [EXCP_DINT] = "debug interrupt",
 405     [EXCP_NMI] = "non-maskable interrupt",
 406     [EXCP_MCHECK] = "machine check",
 407     [EXCP_EXT_INTERRUPT] = "interrupt",
 408     [EXCP_DFWATCH] = "deferred watchpoint",
 409     [EXCP_DIB] = "debug instruction breakpoint",
 410     [EXCP_IWATCH] = "instruction fetch watchpoint",
 411     [EXCP_AdEL] = "address error load",
 412     [EXCP_AdES] = "address error store",
 413     [EXCP_TLBF] = "TLB refill",
 414     [EXCP_IBE] = "instruction bus error",
 415     [EXCP_DBp] = "debug breakpoint",
 416     [EXCP_SYSCALL] = "syscall",
 417     [EXCP_BREAK] = "break",
 418     [EXCP_CpU] = "coprocessor unusable",
 419     [EXCP_RI] = "reserved instruction",
 420     [EXCP_OVERFLOW] = "arithmetic overflow",
 421     [EXCP_TRAP] = "trap",
 422     [EXCP_FPE] = "floating point",
 423     [EXCP_DDBS] = "debug data break store",
 424     [EXCP_DWATCH] = "data watchpoint",
 425     [EXCP_LTLBL] = "TLB modify",
 426     [EXCP_TLBL] = "TLB load",
 427     [EXCP_TLBS] = "TLB store",
 428     [EXCP_DBE] = "data bus error",
 429     [EXCP_DDBL] = "debug data break load",
 430     [EXCP_THREAD] = "thread",
 431     [EXCP_MDMX] = "MDMX",
 432     [EXCP_C2E] = "precise coprocessor 2",
 433     [EXCP_CACHE] = "cache error",
 434     [EXCP_TLBXI] = "TLB execute-inhibit",
 435     [EXCP_TLBRI] = "TLB read-inhibit",
 436     [EXCP_MSADIS] = "MSA disabled",
 437     [EXCP_MSAFPE] = "MSA floating point",
 438 };
 439 #endif
 440
 441 target_ulong exception_resume_pc (CPUMIPSState *env)
 442 {
 443     target_ulong bad_pc;
 444     target_ulong isa_mode;
 445
 446     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 447     bad_pc = env->active_tc.PC | isa_mode;
 448     if (env->hflags & MIPS_HFLAG_BMASK) {
 449         /* If the exception was raised from a delay slot, come back to
 450            the jump.  */
 451         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 452     }
 453
 454     return bad_pc;
 455 }
 456
 457 #if !defined(CONFIG_USER_ONLY)
 458 static void set_hflags_for_handler (CPUMIPSState *env)
 459 {
 460     /* Exception handlers are entered in 32-bit mode.  */
 461     env->hflags &= ~(MIPS_HFLAG_M16);
 462     /* ...except that microMIPS lets you choose.  */
 463     if (env->insn_flags & ASE_MICROMIPS) {
 464         env->hflags |= (!!(env->CP0_Config3
 465                            & (1 << CP0C3_ISA_ON_EXC))
 466                         << MIPS_HFLAG_M16_SHIFT);
 467     }
 468 }
 469
 470 static inline void set_badinstr_registers(CPUMIPSState *env)
 471 {
 472     if (env->hflags & MIPS_HFLAG_M16) {
 473         /* TODO: add BadInstr support for microMIPS */
 474         return;
 475     }
 476     if (env->CP0_Config3 & (1 << CP0C3_BI)) {
 477         env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
 478     }
 479     if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
 480         (env->hflags & MIPS_HFLAG_BMASK)) {
 481         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
 482     }
 483 }
 484 #endif
 485
 486 void mips_cpu_do_interrupt(CPUState *cs)
 487 {
 488 #if !defined(CONFIG_USER_ONLY)
 489     MIPSCPU *cpu = MIPS_CPU(cs);
 490     CPUMIPSState *env = &cpu->env;
 491     bool update_badinstr = 0;
 492     target_ulong offset;
 493     int cause = -1;
 494     const char *name;
 495
 496     if (qemu_loglevel_mask(CPU_LOG_INT)
 497         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 498         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 499             name = "unknown";
 500         } else {
 501             name = excp_names[cs->exception_index];
 502         }
 503
 504         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
 505                  " %s exception\n",
 506                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 507     }
 508     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 509         (env->hflags & MIPS_HFLAG_DM)) {
 510         cs->exception_index = EXCP_DINT;
 511     }
 512     offset = 0x180;
 513     switch (cs->exception_index) {
 514     case EXCP_DSS:
 515         env->CP0_Debug |= 1 << CP0DB_DSS;
 516         /* Debug single step cannot be raised inside a delay slot and
 517            resume will always occur on the next instruction
 518            (but we assume the pc has always been updated during
 519            code translation). */
 520         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 521         goto enter_debug_mode;
 522     case EXCP_DINT:
 523         env->CP0_Debug |= 1 << CP0DB_DINT;
 524         goto set_DEPC;
 525     case EXCP_DIB:
 526         env->CP0_Debug |= 1 << CP0DB_DIB;
 527         goto set_DEPC;
 528     case EXCP_DBp:
 529         env->CP0_Debug |= 1 << CP0DB_DBp;
 530         goto set_DEPC;
 531     case EXCP_DDBS:
 532         env->CP0_Debug |= 1 << CP0DB_DDBS;
 533         goto set_DEPC;
 534     case EXCP_DDBL:
 535         env->CP0_Debug |= 1 << CP0DB_DDBL;
 536     set_DEPC:
 537         env->CP0_DEPC = exception_resume_pc(env);
 538         env->hflags &= ~MIPS_HFLAG_BMASK;
 539  enter_debug_mode:
 540         if (env->insn_flags & ISA_MIPS3) {
 541             env->hflags |= MIPS_HFLAG_64;
 542         }
 543         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
 544         env->hflags &= ~(MIPS_HFLAG_KSU);
 545         /* EJTAG probe trap enable is not implemented... */
 546         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 547             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 548         env->active_tc.PC = (int32_t)0xBFC00480;
 549         set_hflags_for_handler(env);
 550         break;
 551     case EXCP_RESET:
 552         cpu_reset(CPU(cpu));
 553         break;
 554     case EXCP_SRESET:
 555         env->CP0_Status |= (1 << CP0St_SR);
 556         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 557         goto set_error_EPC;
 558     case EXCP_NMI:
 559         env->CP0_Status |= (1 << CP0St_NMI);
 560  set_error_EPC:
 561         env->CP0_ErrorEPC = exception_resume_pc(env);
 562         env->hflags &= ~MIPS_HFLAG_BMASK;
 563         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 564         if (env->insn_flags & ISA_MIPS3) {
 565             env->hflags |= MIPS_HFLAG_64;
 566         }
 567         env->hflags |= MIPS_HFLAG_CP0;
 568         env->hflags &= ~(MIPS_HFLAG_KSU);
 569         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 570             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 571         env->active_tc.PC = (int32_t)0xBFC00000;
 572         set_hflags_for_handler(env);
 573         break;
 574     case EXCP_EXT_INTERRUPT:
 575         cause = 0;
 576         if (env->CP0_Cause & (1 << CP0Ca_IV)) {
 577             uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
 578
 579             if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
 580                 offset = 0x200;
 581             } else {
 582                 uint32_t vector = 0;
 583                 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
 584
 585                 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 586                     /* For VEIC mode, the external interrupt controller feeds
 587                      * the vector through the CP0Cause IP lines.  */
 588                     vector = pending;
 589                 } else {
 590                     /* Vectored Interrupts
 591                      * Mask with Status.IM7-IM0 to get enabled interrupts. */
 592                     pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
 593                     /* Find the highest-priority interrupt. */
 594                     while (pending >>= 1) {
 595                         vector++;
 596                     }
 597                 }
 598                 offset = 0x200 + (vector * (spacing << 5));
 599             }
 600         }
 601         goto set_EPC;
 602     case EXCP_LTLBL:
 603         cause = 1;
 604         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 605         goto set_EPC;
 606     case EXCP_TLBL:
 607         cause = 2;
 608         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 609         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 610             !(env->CP0_Status & (1 << CP0St_EXL))) {
 611 #if defined(TARGET_MIPS64)
 612             int R = env->CP0_BadVAddr >> 62;
 613             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 614             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 615             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 616
 617             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 618                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 619                 offset = 0x080;
 620             else
 621 #endif
 622                 offset = 0x000;
 623         }
 624         goto set_EPC;
 625     case EXCP_TLBS:
 626         cause = 3;
 627         update_badinstr = 1;
 628         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 629             !(env->CP0_Status & (1 << CP0St_EXL))) {
 630 #if defined(TARGET_MIPS64)
 631             int R = env->CP0_BadVAddr >> 62;
 632             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 633             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 634             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 635
 636             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 637                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 638                 offset = 0x080;
 639             else
 640 #endif
 641                 offset = 0x000;
 642         }
 643         goto set_EPC;
 644     case EXCP_AdEL:
 645         cause = 4;
 646         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 647         goto set_EPC;
 648     case EXCP_AdES:
 649         cause = 5;
 650         update_badinstr = 1;
 651         goto set_EPC;
 652     case EXCP_IBE:
 653         cause = 6;
 654         goto set_EPC;
 655     case EXCP_DBE:
 656         cause = 7;
 657         goto set_EPC;
 658     case EXCP_SYSCALL:
 659         cause = 8;
 660         update_badinstr = 1;
 661         goto set_EPC;
 662     case EXCP_BREAK:
 663         cause = 9;
 664         update_badinstr = 1;
 665         goto set_EPC;
 666     case EXCP_RI:
 667         cause = 10;
 668         update_badinstr = 1;
 669         goto set_EPC;
 670     case EXCP_CpU:
 671         cause = 11;
 672         update_badinstr = 1;
 673         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 674                          (env->error_code << CP0Ca_CE);
 675         goto set_EPC;
 676     case EXCP_OVERFLOW:
 677         cause = 12;
 678         update_badinstr = 1;
 679         goto set_EPC;
 680     case EXCP_TRAP:
 681         cause = 13;
 682         update_badinstr = 1;
 683         goto set_EPC;
 684     case EXCP_MSAFPE:
 685         cause = 14;
 686         update_badinstr = 1;
 687         goto set_EPC;
 688     case EXCP_FPE:
 689         cause = 15;
 690         update_badinstr = 1;
 691         goto set_EPC;
 692     case EXCP_C2E:
 693         cause = 18;
 694         goto set_EPC;
 695     case EXCP_TLBRI:
 696         cause = 19;
 697         update_badinstr = 1;
 698         goto set_EPC;
 699     case EXCP_TLBXI:
 700         cause = 20;
 701         goto set_EPC;
 702     case EXCP_MSADIS:
 703         cause = 21;
 704         update_badinstr = 1;
 705         goto set_EPC;
 706     case EXCP_MDMX:
 707         cause = 22;
 708         goto set_EPC;
 709     case EXCP_DWATCH:
 710         cause = 23;
 711         /* XXX: TODO: manage defered watch exceptions */
 712         goto set_EPC;
 713     case EXCP_MCHECK:
 714         cause = 24;
 715         goto set_EPC;
 716     case EXCP_THREAD:
 717         cause = 25;
 718         goto set_EPC;
 719     case EXCP_DSPDIS:
 720         cause = 26;
 721         goto set_EPC;
 722     case EXCP_CACHE:
 723         cause = 30;
 724         if (env->CP0_Status & (1 << CP0St_BEV)) {
 725             offset = 0x100;
 726         } else {
 727             offset = 0x20000100;
 728         }
 729  set_EPC:
 730         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 731             env->CP0_EPC = exception_resume_pc(env);
 732             if (update_badinstr) {
 733                 set_badinstr_registers(env);
 734             }
 735             if (env->hflags & MIPS_HFLAG_BMASK) {
 736                 env->CP0_Cause |= (1U << CP0Ca_BD);
 737             } else {
 738                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 739             }
 740             env->CP0_Status |= (1 << CP0St_EXL);
 741             if (env->insn_flags & ISA_MIPS3) {
 742                 env->hflags |= MIPS_HFLAG_64;
 743             }
 744             env->hflags |= MIPS_HFLAG_CP0;
 745             env->hflags &= ~(MIPS_HFLAG_KSU);
 746         }
 747         env->hflags &= ~MIPS_HFLAG_BMASK;
 748         if (env->CP0_Status & (1 << CP0St_BEV)) {
 749             env->active_tc.PC = (int32_t)0xBFC00200;
 750         } else {
 751             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 752         }
 753         env->active_tc.PC += offset;
 754         set_hflags_for_handler(env);
 755         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 756         break;
 757     default:
 758         abort();
 759     }
 760     if (qemu_loglevel_mask(CPU_LOG_INT)
 761         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 762         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 763                  "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 764                  __func__, env->active_tc.PC, env->CP0_EPC, cause,
 765                  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 766                  env->CP0_DEPC);
 767     }
 768 #endif
 769     cs->exception_index = EXCP_NONE;
 770 }
 771
 772 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 773 {
 774     if (interrupt_request & CPU_INTERRUPT_HARD) {
 775         MIPSCPU *cpu = MIPS_CPU(cs);
 776         CPUMIPSState *env = &cpu->env;
 777
 778         if (cpu_mips_hw_interrupts_pending(env)) {
 779             /* Raise it */
 780             cs->exception_index = EXCP_EXT_INTERRUPT;
 781             env->error_code = 0;
 782             mips_cpu_do_interrupt(cs);
 783             return true;
 784         }
 785     }
 786     return false;
 787 }
 788
 789 #if !defined(CONFIG_USER_ONLY)
 790 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 791 {
 792     MIPSCPU *cpu = mips_env_get_cpu(env);
 793     CPUState *cs;
 794     r4k_tlb_t *tlb;
 795     target_ulong addr;
 796     target_ulong end;
 797     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 798     target_ulong mask;
 799
 800     tlb = &env->tlb->mmu.r4k.tlb[idx];
 801     /* The qemu TLB is flushed when the ASID changes, so no need to
 802        flush these entries again.  */
 803     if (tlb->G == 0 && tlb->ASID != ASID) {
 804         return;
 805     }
 806
 807     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 808         /* For tlbwr, we can shadow the discarded entry into
 809            a new (fake) TLB entry, as long as the guest can not
 810            tell that it's there.  */
 811         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 812         env->tlb->tlb_in_use++;
 813         return;
 814     }
 815
 816     /* 1k pages are not supported. */
 817     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 818     if (tlb->V0) {
 819         cs = CPU(cpu);
 820         addr = tlb->VPN & ~mask;
 821 #if defined(TARGET_MIPS64)
 822         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 823             addr |= 0x3FFFFF0000000000ULL;
 824         }
 825 #endif
 826         end = addr | (mask >> 1);
 827         while (addr < end) {
 828             // optimize memset in tlb_flush_page!!!
 829             tlb_flush_page(cs, addr);
 830             addr += TARGET_PAGE_SIZE;
 831         }
 832     }
 833     if (tlb->V1) {
 834         cs = CPU(cpu);
 835         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 836 #if defined(TARGET_MIPS64)
 837         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 838             addr |= 0x3FFFFF0000000000ULL;
 839         }
 840 #endif
 841         end = addr | mask;
 842         while (addr - 1 < end) {
 843             // optimize memset in tlb_flush_page!!!
 844             tlb_flush_page(cs, addr);
 845             addr += TARGET_PAGE_SIZE;
 846         }
 847     }
 848 }
 849 #endif