target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7
   8 #define ELF_MACHINE     EM_MIPS
   9
  10 #define CPUArchState struct CPUMIPSState
  11
  12 #include "config.h"
  13 #include "qemu-common.h"
  14 #include "mips-defs.h"
  15 #include "exec/cpu-defs.h"
  16 #include "fpu/softfloat.h"
  17
  18 struct CPUMIPSState;
  19
  20 typedef struct r4k_tlb_t r4k_tlb_t;
  21 struct r4k_tlb_t {
  22     target_ulong VPN;
  23     uint32_t PageMask;
  24     uint_fast8_t ASID;
  25     uint_fast16_t G:1;
  26     uint_fast16_t C0:3;
  27     uint_fast16_t C1:3;
  28     uint_fast16_t V0:1;
  29     uint_fast16_t V1:1;
  30     uint_fast16_t D0:1;
  31     uint_fast16_t D1:1;
  32     uint_fast16_t XI0:1;
  33     uint_fast16_t XI1:1;
  34     uint_fast16_t RI0:1;
  35     uint_fast16_t RI1:1;
  36     uint_fast16_t EHINV:1;
  37     uint64_t PFN[2];
  38 };
  39
  40 #if !defined(CONFIG_USER_ONLY)
  41 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  42 struct CPUMIPSTLBContext {
  43     uint32_t nb_tlb;
  44     uint32_t tlb_in_use;
  45     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  46     void (*helper_tlbwi)(struct CPUMIPSState *env);
  47     void (*helper_tlbwr)(struct CPUMIPSState *env);
  48     void (*helper_tlbp)(struct CPUMIPSState *env);
  49     void (*helper_tlbr)(struct CPUMIPSState *env);
  50     void (*helper_tlbinv)(struct CPUMIPSState *env);
  51     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  52     union {
  53         struct {
  54             r4k_tlb_t tlb[MIPS_TLB_MAX];
  55         } r4k;
  56     } mmu;
  57 };
  58 #endif
  59
  60 /* MSA Context */
  61 #define MSA_WRLEN (128)
  62
  63 enum CPUMIPSMSADataFormat {
  64     DF_BYTE = 0,
  65     DF_HALF,
  66     DF_WORD,
  67     DF_DOUBLE
  68 };
  69
  70 typedef union wr_t wr_t;
  71 union wr_t {
  72     int8_t  b[MSA_WRLEN/8];
  73     int16_t h[MSA_WRLEN/16];
  74     int32_t w[MSA_WRLEN/32];
  75     int64_t d[MSA_WRLEN/64];
  76 };
  77
  78 typedef union fpr_t fpr_t;
  79 union fpr_t {
  80     float64  fd;   /* ieee double precision */
  81     float32  fs[2];/* ieee single precision */
  82     uint64_t d;    /* binary double fixed-point */
  83     uint32_t w[2]; /* binary single fixed-point */
  84 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  85     wr_t     wr;   /* vector data */
  86 };
  87 /* define FP_ENDIAN_IDX to access the same location
  88  * in the fpr_t union regardless of the host endianness
  89  */
  90 #if defined(HOST_WORDS_BIGENDIAN)
  91 #  define FP_ENDIAN_IDX 1
  92 #else
  93 #  define FP_ENDIAN_IDX 0
  94 #endif
  95
  96 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  97 struct CPUMIPSFPUContext {
  98     /* Floating point registers */
  99     fpr_t fpr[32];
 100     float_status fp_status;
 101     /* fpu implementation/revision register (fir) */
 102     uint32_t fcr0;
 103 #define FCR0_FREP 29
 104 #define FCR0_UFRP 28
 105 #define FCR0_F64 22
 106 #define FCR0_L 21
 107 #define FCR0_W 20
 108 #define FCR0_3D 19
 109 #define FCR0_PS 18
 110 #define FCR0_D 17
 111 #define FCR0_S 16
 112 #define FCR0_PRID 8
 113 #define FCR0_REV 0
 114     /* fcsr */
 115     uint32_t fcr31;
 116 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 117 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 118 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 119 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 120 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 121 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 122 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 123 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 124 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 125 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 126 #define FP_INEXACT        1
 127 #define FP_UNDERFLOW      2
 128 #define FP_OVERFLOW       4
 129 #define FP_DIV0           8
 130 #define FP_INVALID        16
 131 #define FP_UNIMPLEMENTED  32
 132 };
 133
 134 #define NB_MMU_MODES 3
 135
 136 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 137 struct CPUMIPSMVPContext {
 138     int32_t CP0_MVPControl;
 139 #define CP0MVPCo_CPA    3
 140 #define CP0MVPCo_STLB   2
 141 #define CP0MVPCo_VPC    1
 142 #define CP0MVPCo_EVP    0
 143     int32_t CP0_MVPConf0;
 144 #define CP0MVPC0_M      31
 145 #define CP0MVPC0_TLBS   29
 146 #define CP0MVPC0_GS     28
 147 #define CP0MVPC0_PCP    27
 148 #define CP0MVPC0_PTLBE  16
 149 #define CP0MVPC0_TCA    15
 150 #define CP0MVPC0_PVPE   10
 151 #define CP0MVPC0_PTC    0
 152     int32_t CP0_MVPConf1;
 153 #define CP0MVPC1_CIM    31
 154 #define CP0MVPC1_CIF    30
 155 #define CP0MVPC1_PCX    20
 156 #define CP0MVPC1_PCP2   10
 157 #define CP0MVPC1_PCP1   0
 158 };
 159
 160 typedef struct mips_def_t mips_def_t;
 161
 162 #define MIPS_SHADOW_SET_MAX 16
 163 #define MIPS_TC_MAX 5
 164 #define MIPS_FPU_MAX 1
 165 #define MIPS_DSP_ACC 4
 166 #define MIPS_KSCRATCH_NUM 6
 167
 168 typedef struct TCState TCState;
 169 struct TCState {
 170     target_ulong gpr[32];
 171     target_ulong PC;
 172     target_ulong HI[MIPS_DSP_ACC];
 173     target_ulong LO[MIPS_DSP_ACC];
 174     target_ulong ACX[MIPS_DSP_ACC];
 175     target_ulong DSPControl;
 176     int32_t CP0_TCStatus;
 177 #define CP0TCSt_TCU3    31
 178 #define CP0TCSt_TCU2    30
 179 #define CP0TCSt_TCU1    29
 180 #define CP0TCSt_TCU0    28
 181 #define CP0TCSt_TMX     27
 182 #define CP0TCSt_RNST    23
 183 #define CP0TCSt_TDS     21
 184 #define CP0TCSt_DT      20
 185 #define CP0TCSt_DA      15
 186 #define CP0TCSt_A       13
 187 #define CP0TCSt_TKSU    11
 188 #define CP0TCSt_IXMT    10
 189 #define CP0TCSt_TASID   0
 190     int32_t CP0_TCBind;
 191 #define CP0TCBd_CurTC   21
 192 #define CP0TCBd_TBE     17
 193 #define CP0TCBd_CurVPE  0
 194     target_ulong CP0_TCHalt;
 195     target_ulong CP0_TCContext;
 196     target_ulong CP0_TCSchedule;
 197     target_ulong CP0_TCScheFBack;
 198     int32_t CP0_Debug_tcstatus;
 199     target_ulong CP0_UserLocal;
 200
 201     int32_t msacsr;
 202
 203 #define MSACSR_FS       24
 204 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 205 #define MSACSR_NX       18
 206 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 207 #define MSACSR_CEF      2
 208 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 209 #define MSACSR_RM       0
 210 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 211 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 212         MSACSR_FS_MASK)
 213
 214     float_status msa_fp_status;
 215 };
 216
 217 typedef struct CPUMIPSState CPUMIPSState;
 218 struct CPUMIPSState {
 219     TCState active_tc;
 220     CPUMIPSFPUContext active_fpu;
 221
 222     uint32_t current_tc;
 223     uint32_t current_fpu;
 224
 225     uint32_t SEGBITS;
 226     uint32_t PABITS;
 227 #if defined(TARGET_MIPS64)
 228 # define PABITS_BASE 36
 229 #else
 230 # define PABITS_BASE 32
 231 #endif
 232     target_ulong SEGMask;
 233     uint64_t PAMask;
 234 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 235
 236     int32_t msair;
 237 #define MSAIR_ProcID    8
 238 #define MSAIR_Rev       0
 239
 240     int32_t CP0_Index;
 241     /* CP0_MVP* are per MVP registers. */
 242     int32_t CP0_Random;
 243     int32_t CP0_VPEControl;
 244 #define CP0VPECo_YSI    21
 245 #define CP0VPECo_GSI    20
 246 #define CP0VPECo_EXCPT  16
 247 #define CP0VPECo_TE     15
 248 #define CP0VPECo_TargTC 0
 249     int32_t CP0_VPEConf0;
 250 #define CP0VPEC0_M      31
 251 #define CP0VPEC0_XTC    21
 252 #define CP0VPEC0_TCS    19
 253 #define CP0VPEC0_SCS    18
 254 #define CP0VPEC0_DSC    17
 255 #define CP0VPEC0_ICS    16
 256 #define CP0VPEC0_MVP    1
 257 #define CP0VPEC0_VPA    0
 258     int32_t CP0_VPEConf1;
 259 #define CP0VPEC1_NCX    20
 260 #define CP0VPEC1_NCP2   10
 261 #define CP0VPEC1_NCP1   0
 262     target_ulong CP0_YQMask;
 263     target_ulong CP0_VPESchedule;
 264     target_ulong CP0_VPEScheFBack;
 265     int32_t CP0_VPEOpt;
 266 #define CP0VPEOpt_IWX7  15
 267 #define CP0VPEOpt_IWX6  14
 268 #define CP0VPEOpt_IWX5  13
 269 #define CP0VPEOpt_IWX4  12
 270 #define CP0VPEOpt_IWX3  11
 271 #define CP0VPEOpt_IWX2  10
 272 #define CP0VPEOpt_IWX1  9
 273 #define CP0VPEOpt_IWX0  8
 274 #define CP0VPEOpt_DWX7  7
 275 #define CP0VPEOpt_DWX6  6
 276 #define CP0VPEOpt_DWX5  5
 277 #define CP0VPEOpt_DWX4  4
 278 #define CP0VPEOpt_DWX3  3
 279 #define CP0VPEOpt_DWX2  2
 280 #define CP0VPEOpt_DWX1  1
 281 #define CP0VPEOpt_DWX0  0
 282     uint64_t CP0_EntryLo0;
 283     uint64_t CP0_EntryLo1;
 284 #if defined(TARGET_MIPS64)
 285 # define CP0EnLo_RI 63
 286 # define CP0EnLo_XI 62
 287 #else
 288 # define CP0EnLo_RI 31
 289 # define CP0EnLo_XI 30
 290 #endif
 291     target_ulong CP0_Context;
 292     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 293     int32_t CP0_PageMask;
 294     int32_t CP0_PageGrain_rw_bitmask;
 295     int32_t CP0_PageGrain;
 296 #define CP0PG_RIE 31
 297 #define CP0PG_XIE 30
 298 #define CP0PG_ELPA 29
 299 #define CP0PG_IEC 27
 300     int32_t CP0_Wired;
 301     int32_t CP0_SRSConf0_rw_bitmask;
 302     int32_t CP0_SRSConf0;
 303 #define CP0SRSC0_M      31
 304 #define CP0SRSC0_SRS3   20
 305 #define CP0SRSC0_SRS2   10
 306 #define CP0SRSC0_SRS1   0
 307     int32_t CP0_SRSConf1_rw_bitmask;
 308     int32_t CP0_SRSConf1;
 309 #define CP0SRSC1_M      31
 310 #define CP0SRSC1_SRS6   20
 311 #define CP0SRSC1_SRS5   10
 312 #define CP0SRSC1_SRS4   0
 313     int32_t CP0_SRSConf2_rw_bitmask;
 314     int32_t CP0_SRSConf2;
 315 #define CP0SRSC2_M      31
 316 #define CP0SRSC2_SRS9   20
 317 #define CP0SRSC2_SRS8   10
 318 #define CP0SRSC2_SRS7   0
 319     int32_t CP0_SRSConf3_rw_bitmask;
 320     int32_t CP0_SRSConf3;
 321 #define CP0SRSC3_M      31
 322 #define CP0SRSC3_SRS12  20
 323 #define CP0SRSC3_SRS11  10
 324 #define CP0SRSC3_SRS10  0
 325     int32_t CP0_SRSConf4_rw_bitmask;
 326     int32_t CP0_SRSConf4;
 327 #define CP0SRSC4_SRS15  20
 328 #define CP0SRSC4_SRS14  10
 329 #define CP0SRSC4_SRS13  0
 330     int32_t CP0_HWREna;
 331     target_ulong CP0_BadVAddr;
 332     uint32_t CP0_BadInstr;
 333     uint32_t CP0_BadInstrP;
 334     int32_t CP0_Count;
 335     target_ulong CP0_EntryHi;
 336 #define CP0EnHi_EHINV 10
 337     int32_t CP0_Compare;
 338     int32_t CP0_Status;
 339 #define CP0St_CU3   31
 340 #define CP0St_CU2   30
 341 #define CP0St_CU1   29
 342 #define CP0St_CU0   28
 343 #define CP0St_RP    27
 344 #define CP0St_FR    26
 345 #define CP0St_RE    25
 346 #define CP0St_MX    24
 347 #define CP0St_PX    23
 348 #define CP0St_BEV   22
 349 #define CP0St_TS    21
 350 #define CP0St_SR    20
 351 #define CP0St_NMI   19
 352 #define CP0St_IM    8
 353 #define CP0St_KX    7
 354 #define CP0St_SX    6
 355 #define CP0St_UX    5
 356 #define CP0St_KSU   3
 357 #define CP0St_ERL   2
 358 #define CP0St_EXL   1
 359 #define CP0St_IE    0
 360     int32_t CP0_IntCtl;
 361 #define CP0IntCtl_IPTI 29
 362 #define CP0IntCtl_IPPC1 26
 363 #define CP0IntCtl_VS 5
 364     int32_t CP0_SRSCtl;
 365 #define CP0SRSCtl_HSS 26
 366 #define CP0SRSCtl_EICSS 18
 367 #define CP0SRSCtl_ESS 12
 368 #define CP0SRSCtl_PSS 6
 369 #define CP0SRSCtl_CSS 0
 370     int32_t CP0_SRSMap;
 371 #define CP0SRSMap_SSV7 28
 372 #define CP0SRSMap_SSV6 24
 373 #define CP0SRSMap_SSV5 20
 374 #define CP0SRSMap_SSV4 16
 375 #define CP0SRSMap_SSV3 12
 376 #define CP0SRSMap_SSV2 8
 377 #define CP0SRSMap_SSV1 4
 378 #define CP0SRSMap_SSV0 0
 379     int32_t CP0_Cause;
 380 #define CP0Ca_BD   31
 381 #define CP0Ca_TI   30
 382 #define CP0Ca_CE   28
 383 #define CP0Ca_DC   27
 384 #define CP0Ca_PCI  26
 385 #define CP0Ca_IV   23
 386 #define CP0Ca_WP   22
 387 #define CP0Ca_IP    8
 388 #define CP0Ca_IP_mask 0x0000FF00
 389 #define CP0Ca_EC    2
 390     target_ulong CP0_EPC;
 391     int32_t CP0_PRid;
 392     int32_t CP0_EBase;
 393     int32_t CP0_Config0;
 394 #define CP0C0_M    31
 395 #define CP0C0_K23  28
 396 #define CP0C0_KU   25
 397 #define CP0C0_SB   21
 398 #define CP0C0_MDU  20
 399 #define CP0C0_MM   18
 400 #define CP0C0_BM   16
 401 #define CP0C0_BE   15
 402 #define CP0C0_AT   13
 403 #define CP0C0_AR   10
 404 #define CP0C0_MT   7
 405 #define CP0C0_VI   3
 406 #define CP0C0_K0   0
 407     int32_t CP0_Config1;
 408 #define CP0C1_M    31
 409 #define CP0C1_MMU  25
 410 #define CP0C1_IS   22
 411 #define CP0C1_IL   19
 412 #define CP0C1_IA   16
 413 #define CP0C1_DS   13
 414 #define CP0C1_DL   10
 415 #define CP0C1_DA   7
 416 #define CP0C1_C2   6
 417 #define CP0C1_MD   5
 418 #define CP0C1_PC   4
 419 #define CP0C1_WR   3
 420 #define CP0C1_CA   2
 421 #define CP0C1_EP   1
 422 #define CP0C1_FP   0
 423     int32_t CP0_Config2;
 424 #define CP0C2_M    31
 425 #define CP0C2_TU   28
 426 #define CP0C2_TS   24
 427 #define CP0C2_TL   20
 428 #define CP0C2_TA   16
 429 #define CP0C2_SU   12
 430 #define CP0C2_SS   8
 431 #define CP0C2_SL   4
 432 #define CP0C2_SA   0
 433     int32_t CP0_Config3;
 434 #define CP0C3_M    31
 435 #define CP0C3_BPG  30
 436 #define CP0C3_CMCGR 29
 437 #define CP0C3_MSAP  28
 438 #define CP0C3_BP 27
 439 #define CP0C3_BI 26
 440 #define CP0C3_IPLW 21
 441 #define CP0C3_MMAR 18
 442 #define CP0C3_MCU  17
 443 #define CP0C3_ISA_ON_EXC 16
 444 #define CP0C3_ISA  14
 445 #define CP0C3_ULRI 13
 446 #define CP0C3_RXI  12
 447 #define CP0C3_DSP2P 11
 448 #define CP0C3_DSPP 10
 449 #define CP0C3_LPA  7
 450 #define CP0C3_VEIC 6
 451 #define CP0C3_VInt 5
 452 #define CP0C3_SP   4
 453 #define CP0C3_CDMM 3
 454 #define CP0C3_MT   2
 455 #define CP0C3_SM   1
 456 #define CP0C3_TL   0
 457     int32_t CP0_Config4;
 458     int32_t CP0_Config4_rw_bitmask;
 459 #define CP0C4_M    31
 460 #define CP0C4_IE   29
 461 #define CP0C4_KScrExist 16
 462 #define CP0C4_MMUExtDef 14
 463 #define CP0C4_FTLBPageSize 8
 464 #define CP0C4_FTLBWays 4
 465 #define CP0C4_FTLBSets 0
 466 #define CP0C4_MMUSizeExt 0
 467     int32_t CP0_Config5;
 468     int32_t CP0_Config5_rw_bitmask;
 469 #define CP0C5_M          31
 470 #define CP0C5_K          30
 471 #define CP0C5_CV         29
 472 #define CP0C5_EVA        28
 473 #define CP0C5_MSAEn      27
 474 #define CP0C5_UFE        9
 475 #define CP0C5_FRE        8
 476 #define CP0C5_SBRI       6
 477 #define CP0C5_MVH        5
 478 #define CP0C5_LLB        4
 479 #define CP0C5_UFR        2
 480 #define CP0C5_NFExists   0
 481     int32_t CP0_Config6;
 482     int32_t CP0_Config7;
 483     /* XXX: Maybe make LLAddr per-TC? */
 484     uint64_t lladdr;
 485     target_ulong llval;
 486     target_ulong llnewval;
 487     target_ulong llreg;
 488     uint64_t CP0_LLAddr_rw_bitmask;
 489     int CP0_LLAddr_shift;
 490     target_ulong CP0_WatchLo[8];
 491     int32_t CP0_WatchHi[8];
 492     target_ulong CP0_XContext;
 493     int32_t CP0_Framemask;
 494     int32_t CP0_Debug;
 495 #define CP0DB_DBD  31
 496 #define CP0DB_DM   30
 497 #define CP0DB_LSNM 28
 498 #define CP0DB_Doze 27
 499 #define CP0DB_Halt 26
 500 #define CP0DB_CNT  25
 501 #define CP0DB_IBEP 24
 502 #define CP0DB_DBEP 21
 503 #define CP0DB_IEXI 20
 504 #define CP0DB_VER  15
 505 #define CP0DB_DEC  10
 506 #define CP0DB_SSt  8
 507 #define CP0DB_DINT 5
 508 #define CP0DB_DIB  4
 509 #define CP0DB_DDBS 3
 510 #define CP0DB_DDBL 2
 511 #define CP0DB_DBp  1
 512 #define CP0DB_DSS  0
 513     target_ulong CP0_DEPC;
 514     //~ uint32_t CP0_ErrCtl;
 515     int32_t CP0_Performance0;
 516     uint64_t CP0_TagLo;
 517     int32_t CP0_DataLo;
 518     int32_t CP0_TagHi;
 519     int32_t CP0_DataHi;
 520     target_ulong CP0_ErrorEPC;
 521     int32_t CP0_DESAVE;
 522     /* We waste some space so we can handle shadow registers like TCs. */
 523     TCState tcs[MIPS_SHADOW_SET_MAX];
 524     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 525     /* QEMU */
 526     int error_code;
 527 #define EXCP_TLB_NOMATCH   0x1
 528 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 529     uint32_t hflags;    /* CPU State */
 530     /* TMASK defines different execution modes */
 531 #define MIPS_HFLAG_TMASK  0x75807FF
 532 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 533     /* The KSU flags must be the lowest bits in hflags. The flag order
 534        must be the same as defined for CP0 Status. This allows to use
 535        the bits as the value of mmu_idx. */
 536 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 537 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 538 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 539 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 540 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 541 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 542 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 543 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 544 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 545     /* True if the MIPS IV COP1X instructions can be used.  This also
 546        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 547        and RSQRT.D.  */
 548 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 549 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 550 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 551 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 552 #define MIPS_HFLAG_M16_SHIFT 10
 553     /* If translation is interrupted between the branch instruction and
 554      * the delay slot, record what type of branch it is so that we can
 555      * resume translation properly.  It might be possible to reduce
 556      * this from three bits to two.  */
 557 #define MIPS_HFLAG_BMASK_BASE  0x803800
 558 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 559 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 560 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 561 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 562     /* Extra flags about the current pending branch.  */
 563 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 564 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 565 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 566 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 567 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 568 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 569 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 570     /* MIPS DSP resources access. */
 571 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 572 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 573     /* Extra flag about HWREna register. */
 574 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 575 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 576 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 577 #define MIPS_HFLAG_MSA   0x1000000
 578 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 579 #define MIPS_HFLAG_ELPA  0x4000000
 580     target_ulong btarget;        /* Jump / branch target               */
 581     target_ulong bcond;          /* Branch condition (if needed)       */
 582
 583     int SYNCI_Step; /* Address step size for SYNCI */
 584     int CCRes; /* Cycle count resolution/divisor */
 585     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 586     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 587     int insn_flags; /* Supported instruction set */
 588
 589     CPU_COMMON
 590
 591     /* Fields from here on are preserved across CPU reset. */
 592     CPUMIPSMVPContext *mvp;
 593 #if !defined(CONFIG_USER_ONLY)
 594     CPUMIPSTLBContext *tlb;
 595 #endif
 596
 597     const mips_def_t *cpu_model;
 598     void *irq[8];
 599     QEMUTimer *timer; /* Internal timer */
 600 };
 601
 602 #include "cpu-qom.h"
 603
 604 #if !defined(CONFIG_USER_ONLY)
 605 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 606                         target_ulong address, int rw, int access_type);
 607 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 608                            target_ulong address, int rw, int access_type);
 609 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 610                      target_ulong address, int rw, int access_type);
 611 void r4k_helper_tlbwi(CPUMIPSState *env);
 612 void r4k_helper_tlbwr(CPUMIPSState *env);
 613 void r4k_helper_tlbp(CPUMIPSState *env);
 614 void r4k_helper_tlbr(CPUMIPSState *env);
 615 void r4k_helper_tlbinv(CPUMIPSState *env);
 616 void r4k_helper_tlbinvf(CPUMIPSState *env);
 617
 618 void QEMU_NORETURN mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 619                                               bool is_write, bool is_exec,
 620                                               int unused, unsigned size);
 621 #endif
 622
 623 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 624
 625 #define cpu_exec cpu_mips_exec
 626 #define cpu_gen_code cpu_mips_gen_code
 627 #define cpu_signal_handler cpu_mips_signal_handler
 628 #define cpu_list mips_cpu_list
 629
 630 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 631 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 632
 633 /* MMU modes definitions. We carefully match the indices with our
 634    hflags layout. */
 635 #define MMU_MODE0_SUFFIX _kernel
 636 #define MMU_MODE1_SUFFIX _super
 637 #define MMU_MODE2_SUFFIX _user
 638 #define MMU_USER_IDX 2
 639 static inline int cpu_mmu_index (CPUMIPSState *env)
 640 {
 641     return env->hflags & MIPS_HFLAG_KSU;
 642 }
 643
 644 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 645 {
 646     int32_t pending;
 647     int32_t status;
 648     int r;
 649
 650     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
 651         (env->CP0_Status & (1 << CP0St_EXL)) ||
 652         (env->CP0_Status & (1 << CP0St_ERL)) ||
 653         /* Note that the TCStatus IXMT field is initialized to zero,
 654            and only MT capable cores can set it to one. So we don't
 655            need to check for MT capabilities here.  */
 656         (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
 657         (env->hflags & MIPS_HFLAG_DM)) {
 658         /* Interrupts are disabled */
 659         return 0;
 660     }
 661
 662     pending = env->CP0_Cause & CP0Ca_IP_mask;
 663     status = env->CP0_Status & CP0Ca_IP_mask;
 664
 665     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 666         /* A MIPS configured with a vectorizing external interrupt controller
 667            will feed a vector into the Cause pending lines. The core treats
 668            the status lines as a vector level, not as indiviual masks.  */
 669         r = pending > status;
 670     } else {
 671         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 672            treats the pending lines as individual interrupt lines, the status
 673            lines are individual masks.  */
 674         r = pending & status;
 675     }
 676     return r;
 677 }
 678
 679 #include "exec/cpu-all.h"
 680
 681 /* Memory access type :
 682  * may be needed for precise access rights control and precise exceptions.
 683  */
 684 enum {
 685     /* 1 bit to define user level / supervisor access */
 686     ACCESS_USER  = 0x00,
 687     ACCESS_SUPER = 0x01,
 688     /* 1 bit to indicate direction */
 689     ACCESS_STORE = 0x02,
 690     /* Type of instruction that generated the access */
 691     ACCESS_CODE  = 0x10, /* Code fetch access                */
 692     ACCESS_INT   = 0x20, /* Integer load/store access        */
 693     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 694 };
 695
 696 /* Exceptions */
 697 enum {
 698     EXCP_NONE          = -1,
 699     EXCP_RESET         = 0,
 700     EXCP_SRESET,
 701     EXCP_DSS,
 702     EXCP_DINT,
 703     EXCP_DDBL,
 704     EXCP_DDBS,
 705     EXCP_NMI,
 706     EXCP_MCHECK,
 707     EXCP_EXT_INTERRUPT, /* 8 */
 708     EXCP_DFWATCH,
 709     EXCP_DIB,
 710     EXCP_IWATCH,
 711     EXCP_AdEL,
 712     EXCP_AdES,
 713     EXCP_TLBF,
 714     EXCP_IBE,
 715     EXCP_DBp, /* 16 */
 716     EXCP_SYSCALL,
 717     EXCP_BREAK,
 718     EXCP_CpU,
 719     EXCP_RI,
 720     EXCP_OVERFLOW,
 721     EXCP_TRAP,
 722     EXCP_FPE,
 723     EXCP_DWATCH, /* 24 */
 724     EXCP_LTLBL,
 725     EXCP_TLBL,
 726     EXCP_TLBS,
 727     EXCP_DBE,
 728     EXCP_THREAD,
 729     EXCP_MDMX,
 730     EXCP_C2E,
 731     EXCP_CACHE, /* 32 */
 732     EXCP_DSPDIS,
 733     EXCP_MSADIS,
 734     EXCP_MSAFPE,
 735     EXCP_TLBXI,
 736     EXCP_TLBRI,
 737
 738     EXCP_LAST = EXCP_TLBRI,
 739 };
 740 /* Dummy exception for conditional stores.  */
 741 #define EXCP_SC 0x100
 742
 743 /*
 744  * This is an interrnally generated WAKE request line.
 745  * It is driven by the CPU itself. Raised when the MT
 746  * block wants to wake a VPE from an inactive state and
 747  * cleared when VPE goes from active to inactive.
 748  */
 749 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 750
 751 int cpu_mips_exec(CPUState *cpu);
 752 void mips_tcg_init(void);
 753 MIPSCPU *cpu_mips_init(const char *cpu_model);
 754 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 755
 756 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 757
 758 /* TODO QOM'ify CPU reset and remove */
 759 void cpu_state_reset(CPUMIPSState *s);
 760
 761 /* mips_timer.c */
 762 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 763 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 764 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 765 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 766 void cpu_mips_start_count(CPUMIPSState *env);
 767 void cpu_mips_stop_count(CPUMIPSState *env);
 768
 769 /* mips_int.c */
 770 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 771
 772 /* helper.c */
 773 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 774                               int mmu_idx);
 775 #if !defined(CONFIG_USER_ONLY)
 776 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 777 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 778                                                int rw);
 779 #endif
 780 target_ulong exception_resume_pc (CPUMIPSState *env);
 781
 782 /* op_helper.c */
 783 extern unsigned int ieee_rm[];
 784 int ieee_ex_to_mips(int xcpt);
 785
 786 static inline void restore_rounding_mode(CPUMIPSState *env)
 787 {
 788     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 789                             &env->active_fpu.fp_status);
 790 }
 791
 792 static inline void restore_flush_mode(CPUMIPSState *env)
 793 {
 794     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
 795                       &env->active_fpu.fp_status);
 796 }
 797
 798 static inline void restore_fp_status(CPUMIPSState *env)
 799 {
 800     restore_rounding_mode(env);
 801     restore_flush_mode(env);
 802 }
 803
 804 static inline void restore_msa_fp_status(CPUMIPSState *env)
 805 {
 806     float_status *status = &env->active_tc.msa_fp_status;
 807     int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 808     bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 809
 810     set_float_rounding_mode(ieee_rm[rounding_mode], status);
 811     set_flush_to_zero(flush_to_zero, status);
 812     set_flush_inputs_to_zero(flush_to_zero, status);
 813 }
 814
 815 static inline void restore_pamask(CPUMIPSState *env)
 816 {
 817     if (env->hflags & MIPS_HFLAG_ELPA) {
 818         env->PAMask = (1ULL << env->PABITS) - 1;
 819     } else {
 820         env->PAMask = PAMASK_BASE;
 821     }
 822 }
 823
 824 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 825                                         target_ulong *cs_base, int *flags)
 826 {
 827     *pc = env->active_tc.PC;
 828     *cs_base = 0;
 829     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 830                             MIPS_HFLAG_HWRENA_ULR);
 831 }
 832
 833 static inline int mips_vpe_active(CPUMIPSState *env)
 834 {
 835     int active = 1;
 836
 837     /* Check that the VPE is enabled.  */
 838     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 839         active = 0;
 840     }
 841     /* Check that the VPE is activated.  */
 842     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 843         active = 0;
 844     }
 845
 846     /* Now verify that there are active thread contexts in the VPE.
 847
 848        This assumes the CPU model will internally reschedule threads
 849        if the active one goes to sleep. If there are no threads available
 850        the active one will be in a sleeping state, and we can turn off
 851        the entire VPE.  */
 852     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 853         /* TC is not activated.  */
 854         active = 0;
 855     }
 856     if (env->active_tc.CP0_TCHalt & 1) {
 857         /* TC is in halt state.  */
 858         active = 0;
 859     }
 860
 861     return active;
 862 }
 863
 864 #include "exec/exec-all.h"
 865
 866 static inline void compute_hflags(CPUMIPSState *env)
 867 {
 868     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 869                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 870                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 871                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 872                      MIPS_HFLAG_ELPA);
 873     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 874         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 875         !(env->hflags & MIPS_HFLAG_DM)) {
 876         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 877     }
 878 #if defined(TARGET_MIPS64)
 879     if ((env->insn_flags & ISA_MIPS3) &&
 880         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 881          (env->CP0_Status & (1 << CP0St_PX)) ||
 882          (env->CP0_Status & (1 << CP0St_UX)))) {
 883         env->hflags |= MIPS_HFLAG_64;
 884     }
 885
 886     if (!(env->insn_flags & ISA_MIPS3)) {
 887         env->hflags |= MIPS_HFLAG_AWRAP;
 888     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 889                !(env->CP0_Status & (1 << CP0St_UX))) {
 890         env->hflags |= MIPS_HFLAG_AWRAP;
 891     } else if (env->insn_flags & ISA_MIPS64R6) {
 892         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 893         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 894              !(env->CP0_Status & (1 << CP0St_SX))) ||
 895             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 896              !(env->CP0_Status & (1 << CP0St_KX)))) {
 897             env->hflags |= MIPS_HFLAG_AWRAP;
 898         }
 899     }
 900 #endif
 901     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 902          !(env->insn_flags & ISA_MIPS32R6)) ||
 903         !(env->hflags & MIPS_HFLAG_KSU)) {
 904         env->hflags |= MIPS_HFLAG_CP0;
 905     }
 906     if (env->CP0_Status & (1 << CP0St_CU1)) {
 907         env->hflags |= MIPS_HFLAG_FPU;
 908     }
 909     if (env->CP0_Status & (1 << CP0St_FR)) {
 910         env->hflags |= MIPS_HFLAG_F64;
 911     }
 912     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 913         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 914         env->hflags |= MIPS_HFLAG_SBRI;
 915     }
 916     if (env->insn_flags & ASE_DSPR2) {
 917         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 918            so enable to access DSPR2 resources. */
 919         if (env->CP0_Status & (1 << CP0St_MX)) {
 920             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 921         }
 922
 923     } else if (env->insn_flags & ASE_DSP) {
 924         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 925            so enable to access DSP resources. */
 926         if (env->CP0_Status & (1 << CP0St_MX)) {
 927             env->hflags |= MIPS_HFLAG_DSP;
 928         }
 929
 930     }
 931     if (env->insn_flags & ISA_MIPS32R2) {
 932         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 933             env->hflags |= MIPS_HFLAG_COP1X;
 934         }
 935     } else if (env->insn_flags & ISA_MIPS32) {
 936         if (env->hflags & MIPS_HFLAG_64) {
 937             env->hflags |= MIPS_HFLAG_COP1X;
 938         }
 939     } else if (env->insn_flags & ISA_MIPS4) {
 940         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 941            and disable the MIPS IV extensions to the MIPS III ISA.
 942            Some other MIPS IV CPUs ignore the bit, so the check here
 943            would be too restrictive for them.  */
 944         if (env->CP0_Status & (1U << CP0St_CU3)) {
 945             env->hflags |= MIPS_HFLAG_COP1X;
 946         }
 947     }
 948     if (env->insn_flags & ASE_MSA) {
 949         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 950             env->hflags |= MIPS_HFLAG_MSA;
 951         }
 952     }
 953     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 954         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 955             env->hflags |= MIPS_HFLAG_FRE;
 956         }
 957     }
 958     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 959         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 960             env->hflags |= MIPS_HFLAG_ELPA;
 961         }
 962     }
 963 }
 964
 965 #ifndef CONFIG_USER_ONLY
 966 /* Called for updates to CP0_Status.  */
 967 static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 968 {
 969     int32_t tcstatus, *tcst;
 970     uint32_t v = cpu->CP0_Status;
 971     uint32_t cu, mx, asid, ksu;
 972     uint32_t mask = ((1 << CP0TCSt_TCU3)
 973                        | (1 << CP0TCSt_TCU2)
 974                        | (1 << CP0TCSt_TCU1)
 975                        | (1 << CP0TCSt_TCU0)
 976                        | (1 << CP0TCSt_TMX)
 977                        | (3 << CP0TCSt_TKSU)
 978                        | (0xff << CP0TCSt_TASID));
 979
 980     cu = (v >> CP0St_CU0) & 0xf;
 981     mx = (v >> CP0St_MX) & 0x1;
 982     ksu = (v >> CP0St_KSU) & 0x3;
 983     asid = env->CP0_EntryHi & 0xff;
 984
 985     tcstatus = cu << CP0TCSt_TCU0;
 986     tcstatus |= mx << CP0TCSt_TMX;
 987     tcstatus |= ksu << CP0TCSt_TKSU;
 988     tcstatus |= asid;
 989
 990     if (tc == cpu->current_tc) {
 991         tcst = &cpu->active_tc.CP0_TCStatus;
 992     } else {
 993         tcst = &cpu->tcs[tc].CP0_TCStatus;
 994     }
 995
 996     *tcst &= ~mask;
 997     *tcst |= tcstatus;
 998     compute_hflags(cpu);
 999 }
1000
1001 static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
1002 {
1003     uint32_t mask = env->CP0_Status_rw_bitmask;
1004
1005     if (env->insn_flags & ISA_MIPS32R6) {
1006         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
1007
1008         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
1009             mask &= ~(3 << CP0St_KSU);
1010         }
1011         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
1012     }
1013
1014     env->CP0_Status = (env->CP0_Status & ~mask) | (val & mask);
1015     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1016         sync_c0_status(env, env, env->current_tc);
1017     } else {
1018         compute_hflags(env);
1019     }
1020 }
1021
1022 static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
1023 {
1024     uint32_t mask = 0x00C00300;
1025     uint32_t old = env->CP0_Cause;
1026     int i;
1027
1028     if (env->insn_flags & ISA_MIPS32R2) {
1029         mask |= 1 << CP0Ca_DC;
1030     }
1031     if (env->insn_flags & ISA_MIPS32R6) {
1032         mask &= ~((1 << CP0Ca_WP) & val);
1033     }
1034
1035     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
1036
1037     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1038         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
1039             cpu_mips_stop_count(env);
1040         } else {
1041             cpu_mips_start_count(env);
1042         }
1043     }
1044
1045     /* Set/reset software interrupts */
1046     for (i = 0 ; i < 2 ; i++) {
1047         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1048             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
1049         }
1050     }
1051 }
1052 #endif
1053
1054 #endif /* !defined (__MIPS_CPU_H__) */