target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13 #include "exec/semihost.h"
  14
  15 #ifndef CONFIG_USER_ONLY
  16 static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
  17                                  int access_type, ARMMMUIdx mmu_idx,
  18                                  hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  19                                  target_ulong *page_size, uint32_t *fsr);
  20
  21 /* Definitions for the PMCCNTR and PMCR registers */
  22 #define PMCRD   0x8
  23 #define PMCRC   0x4
  24 #define PMCRE   0x1
  25 #endif
  26
  27 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  28 {
  29     int nregs;
  30
  31     /* VFP data registers are always little-endian.  */
  32     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  33     if (reg < nregs) {
  34         stfq_le_p(buf, env->vfp.regs[reg]);
  35         return 8;
  36     }
  37     if (arm_feature(env, ARM_FEATURE_NEON)) {
  38         /* Aliases for Q regs.  */
  39         nregs += 16;
  40         if (reg < nregs) {
  41             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  42             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  43             return 16;
  44         }
  45     }
  46     switch (reg - nregs) {
  47     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  48     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  49     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  50     }
  51     return 0;
  52 }
  53
  54 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  55 {
  56     int nregs;
  57
  58     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  59     if (reg < nregs) {
  60         env->vfp.regs[reg] = ldfq_le_p(buf);
  61         return 8;
  62     }
  63     if (arm_feature(env, ARM_FEATURE_NEON)) {
  64         nregs += 16;
  65         if (reg < nregs) {
  66             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  67             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  68             return 16;
  69         }
  70     }
  71     switch (reg - nregs) {
  72     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  73     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  74     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  75     }
  76     return 0;
  77 }
  78
  79 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  80 {
  81     switch (reg) {
  82     case 0 ... 31:
  83         /* 128 bit FP register */
  84         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  85         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  86         return 16;
  87     case 32:
  88         /* FPSR */
  89         stl_p(buf, vfp_get_fpsr(env));
  90         return 4;
  91     case 33:
  92         /* FPCR */
  93         stl_p(buf, vfp_get_fpcr(env));
  94         return 4;
  95     default:
  96         return 0;
  97     }
  98 }
  99
 100 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 101 {
 102     switch (reg) {
 103     case 0 ... 31:
 104         /* 128 bit FP register */
 105         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 106         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 107         return 16;
 108     case 32:
 109         /* FPSR */
 110         vfp_set_fpsr(env, ldl_p(buf));
 111         return 4;
 112     case 33:
 113         /* FPCR */
 114         vfp_set_fpcr(env, ldl_p(buf));
 115         return 4;
 116     default:
 117         return 0;
 118     }
 119 }
 120
 121 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 122 {
 123     assert(ri->fieldoffset);
 124     if (cpreg_field_is_64bit(ri)) {
 125         return CPREG_FIELD64(env, ri);
 126     } else {
 127         return CPREG_FIELD32(env, ri);
 128     }
 129 }
 130
 131 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 132                       uint64_t value)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         CPREG_FIELD64(env, ri) = value;
 137     } else {
 138         CPREG_FIELD32(env, ri) = value;
 139     }
 140 }
 141
 142 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 143 {
 144     return (char *)env + ri->fieldoffset;
 145 }
 146
 147 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 148 {
 149     /* Raw read of a coprocessor register (as needed for migration, etc). */
 150     if (ri->type & ARM_CP_CONST) {
 151         return ri->resetvalue;
 152     } else if (ri->raw_readfn) {
 153         return ri->raw_readfn(env, ri);
 154     } else if (ri->readfn) {
 155         return ri->readfn(env, ri);
 156     } else {
 157         return raw_read(env, ri);
 158     }
 159 }
 160
 161 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 162                              uint64_t v)
 163 {
 164     /* Raw write of a coprocessor register (as needed for migration, etc).
 165      * Note that constant registers are treated as write-ignored; the
 166      * caller should check for success by whether a readback gives the
 167      * value written.
 168      */
 169     if (ri->type & ARM_CP_CONST) {
 170         return;
 171     } else if (ri->raw_writefn) {
 172         ri->raw_writefn(env, ri, v);
 173     } else if (ri->writefn) {
 174         ri->writefn(env, ri, v);
 175     } else {
 176         raw_write(env, ri, v);
 177     }
 178 }
 179
 180 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 181 {
 182    /* Return true if the regdef would cause an assertion if you called
 183     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 184     * program bug for it not to have the NO_RAW flag).
 185     * NB that returning false here doesn't necessarily mean that calling
 186     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 187     * read/write access functions which are safe for raw use" from "has
 188     * read/write access functions which have side effects but has forgotten
 189     * to provide raw access functions".
 190     * The tests here line up with the conditions in read/write_raw_cp_reg()
 191     * and assertions in raw_read()/raw_write().
 192     */
 193     if ((ri->type & ARM_CP_CONST) ||
 194         ri->fieldoffset ||
 195         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 196         return false;
 197     }
 198     return true;
 199 }
 200
 201 bool write_cpustate_to_list(ARMCPU *cpu)
 202 {
 203     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 204     int i;
 205     bool ok = true;
 206
 207     for (i = 0; i < cpu->cpreg_array_len; i++) {
 208         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 209         const ARMCPRegInfo *ri;
 210
 211         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 212         if (!ri) {
 213             ok = false;
 214             continue;
 215         }
 216         if (ri->type & ARM_CP_NO_RAW) {
 217             continue;
 218         }
 219         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 220     }
 221     return ok;
 222 }
 223
 224 bool write_list_to_cpustate(ARMCPU *cpu)
 225 {
 226     int i;
 227     bool ok = true;
 228
 229     for (i = 0; i < cpu->cpreg_array_len; i++) {
 230         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 231         uint64_t v = cpu->cpreg_values[i];
 232         const ARMCPRegInfo *ri;
 233
 234         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 235         if (!ri) {
 236             ok = false;
 237             continue;
 238         }
 239         if (ri->type & ARM_CP_NO_RAW) {
 240             continue;
 241         }
 242         /* Write value and confirm it reads back as written
 243          * (to catch read-only registers and partially read-only
 244          * registers where the incoming migration value doesn't match)
 245          */
 246         write_raw_cp_reg(&cpu->env, ri, v);
 247         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 248             ok = false;
 249         }
 250     }
 251     return ok;
 252 }
 253
 254 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 255 {
 256     ARMCPU *cpu = opaque;
 257     uint64_t regidx;
 258     const ARMCPRegInfo *ri;
 259
 260     regidx = *(uint32_t *)key;
 261     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 262
 263     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 264         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 265         /* The value array need not be initialized at this point */
 266         cpu->cpreg_array_len++;
 267     }
 268 }
 269
 270 static void count_cpreg(gpointer key, gpointer opaque)
 271 {
 272     ARMCPU *cpu = opaque;
 273     uint64_t regidx;
 274     const ARMCPRegInfo *ri;
 275
 276     regidx = *(uint32_t *)key;
 277     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 278
 279     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 280         cpu->cpreg_array_len++;
 281     }
 282 }
 283
 284 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 285 {
 286     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 287     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 288
 289     if (aidx > bidx) {
 290         return 1;
 291     }
 292     if (aidx < bidx) {
 293         return -1;
 294     }
 295     return 0;
 296 }
 297
 298 void init_cpreg_list(ARMCPU *cpu)
 299 {
 300     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 301      * Note that we require cpreg_tuples[] to be sorted by key ID.
 302      */
 303     GList *keys;
 304     int arraylen;
 305
 306     keys = g_hash_table_get_keys(cpu->cp_regs);
 307     keys = g_list_sort(keys, cpreg_key_compare);
 308
 309     cpu->cpreg_array_len = 0;
 310
 311     g_list_foreach(keys, count_cpreg, cpu);
 312
 313     arraylen = cpu->cpreg_array_len;
 314     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 315     cpu->cpreg_values = g_new(uint64_t, arraylen);
 316     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 317     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 318     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 319     cpu->cpreg_array_len = 0;
 320
 321     g_list_foreach(keys, add_cpreg_to_list, cpu);
 322
 323     assert(cpu->cpreg_array_len == arraylen);
 324
 325     g_list_free(keys);
 326 }
 327
 328 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 329 {
 330     ARMCPU *cpu = arm_env_get_cpu(env);
 331
 332     raw_write(env, ri, value);
 333     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 334 }
 335
 336 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 337 {
 338     ARMCPU *cpu = arm_env_get_cpu(env);
 339
 340     if (raw_read(env, ri) != value) {
 341         /* Unlike real hardware the qemu TLB uses virtual addresses,
 342          * not modified virtual addresses, so this causes a TLB flush.
 343          */
 344         tlb_flush(CPU(cpu), 1);
 345         raw_write(env, ri, value);
 346     }
 347 }
 348
 349 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 350                              uint64_t value)
 351 {
 352     ARMCPU *cpu = arm_env_get_cpu(env);
 353
 354     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 355         && !extended_addresses_enabled(env)) {
 356         /* For VMSA (when not using the LPAE long descriptor page table
 357          * format) this register includes the ASID, so do a TLB flush.
 358          * For PMSA it is purely a process ID and no action is needed.
 359          */
 360         tlb_flush(CPU(cpu), 1);
 361     }
 362     raw_write(env, ri, value);
 363 }
 364
 365 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 366                           uint64_t value)
 367 {
 368     /* Invalidate all (TLBIALL) */
 369     ARMCPU *cpu = arm_env_get_cpu(env);
 370
 371     tlb_flush(CPU(cpu), 1);
 372 }
 373
 374 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 375                           uint64_t value)
 376 {
 377     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 378     ARMCPU *cpu = arm_env_get_cpu(env);
 379
 380     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 381 }
 382
 383 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 384                            uint64_t value)
 385 {
 386     /* Invalidate by ASID (TLBIASID) */
 387     ARMCPU *cpu = arm_env_get_cpu(env);
 388
 389     tlb_flush(CPU(cpu), value == 0);
 390 }
 391
 392 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 393                            uint64_t value)
 394 {
 395     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 396     ARMCPU *cpu = arm_env_get_cpu(env);
 397
 398     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 399 }
 400
 401 /* IS variants of TLB operations must affect all cores */
 402 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 403                              uint64_t value)
 404 {
 405     CPUState *other_cs;
 406
 407     CPU_FOREACH(other_cs) {
 408         tlb_flush(other_cs, 1);
 409     }
 410 }
 411
 412 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 413                              uint64_t value)
 414 {
 415     CPUState *other_cs;
 416
 417     CPU_FOREACH(other_cs) {
 418         tlb_flush(other_cs, value == 0);
 419     }
 420 }
 421
 422 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 423                              uint64_t value)
 424 {
 425     CPUState *other_cs;
 426
 427     CPU_FOREACH(other_cs) {
 428         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 429     }
 430 }
 431
 432 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 433                              uint64_t value)
 434 {
 435     CPUState *other_cs;
 436
 437     CPU_FOREACH(other_cs) {
 438         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 439     }
 440 }
 441
 442 static const ARMCPRegInfo cp_reginfo[] = {
 443     /* Define the secure and non-secure FCSE identifier CP registers
 444      * separately because there is no secure bank in V8 (no _EL3).  This allows
 445      * the secure register to be properly reset and migrated. There is also no
 446      * v8 EL1 version of the register so the non-secure instance stands alone.
 447      */
 448     { .name = "FCSEIDR(NS)",
 449       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 450       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 451       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 452       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 453     { .name = "FCSEIDR(S)",
 454       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 455       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 456       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 457       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 458     /* Define the secure and non-secure context identifier CP registers
 459      * separately because there is no secure bank in V8 (no _EL3).  This allows
 460      * the secure register to be properly reset and migrated.  In the
 461      * non-secure case, the 32-bit register will have reset and migration
 462      * disabled during registration as it is handled by the 64-bit instance.
 463      */
 464     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 465       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 466       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 467       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 468       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 469     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 470       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 471       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 472       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 473       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 474     REGINFO_SENTINEL
 475 };
 476
 477 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 478     /* NB: Some of these registers exist in v8 but with more precise
 479      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 480      */
 481     /* MMU Domain access control / MPU write buffer control */
 482     { .name = "DACR",
 483       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 484       .access = PL1_RW, .resetvalue = 0,
 485       .writefn = dacr_write, .raw_writefn = raw_write,
 486       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 487                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 488     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 489      * For v6 and v5, these mappings are overly broad.
 490      */
 491     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 492       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 493     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 494       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 495     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 496       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 497     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 498       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 499     /* Cache maintenance ops; some of this space may be overridden later. */
 500     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 501       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 502       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 503     REGINFO_SENTINEL
 504 };
 505
 506 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 507     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 508      * over-broad.
 509      */
 510     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 511       .access = PL1_W, .type = ARM_CP_WFI },
 512     REGINFO_SENTINEL
 513 };
 514
 515 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 516     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 517      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 518      */
 519     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 520       .access = PL1_W, .type = ARM_CP_WFI },
 521     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 522      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 523      * OMAPCP will override this space.
 524      */
 525     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 526       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 527       .resetvalue = 0 },
 528     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 529       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 530       .resetvalue = 0 },
 531     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 532     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 533       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 534       .resetvalue = 0 },
 535     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 536      * implementing it as RAZ means the "debug architecture version" bits
 537      * will read as a reserved value, which should cause Linux to not try
 538      * to use the debug hardware.
 539      */
 540     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 541       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 542     /* MMU TLB control. Note that the wildcarding means we cover not just
 543      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 544      */
 545     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 546       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 547       .type = ARM_CP_NO_RAW },
 548     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 549       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 550       .type = ARM_CP_NO_RAW },
 551     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 552       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 553       .type = ARM_CP_NO_RAW },
 554     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 555       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 556       .type = ARM_CP_NO_RAW },
 557     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 558       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 559     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 560       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 561     REGINFO_SENTINEL
 562 };
 563
 564 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 565                         uint64_t value)
 566 {
 567     uint32_t mask = 0;
 568
 569     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 570     if (!arm_feature(env, ARM_FEATURE_V8)) {
 571         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 572          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 573          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 574          */
 575         if (arm_feature(env, ARM_FEATURE_VFP)) {
 576             /* VFP coprocessor: cp10 & cp11 [23:20] */
 577             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 578
 579             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 580                 /* ASEDIS [31] bit is RAO/WI */
 581                 value |= (1 << 31);
 582             }
 583
 584             /* VFPv3 and upwards with NEON implement 32 double precision
 585              * registers (D0-D31).
 586              */
 587             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 588                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 589                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 590                 value |= (1 << 30);
 591             }
 592         }
 593         value &= mask;
 594     }
 595     env->cp15.cpacr_el1 = value;
 596 }
 597
 598 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 599 {
 600     if (arm_feature(env, ARM_FEATURE_V8)) {
 601         /* Check if CPACR accesses are to be trapped to EL2 */
 602         if (arm_current_el(env) == 1 &&
 603             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 604             return CP_ACCESS_TRAP_EL2;
 605         /* Check if CPACR accesses are to be trapped to EL3 */
 606         } else if (arm_current_el(env) < 3 &&
 607                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 608             return CP_ACCESS_TRAP_EL3;
 609         }
 610     }
 611
 612     return CP_ACCESS_OK;
 613 }
 614
 615 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 616 {
 617     /* Check if CPTR accesses are set to trap to EL3 */
 618     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 619         return CP_ACCESS_TRAP_EL3;
 620     }
 621
 622     return CP_ACCESS_OK;
 623 }
 624
 625 static const ARMCPRegInfo v6_cp_reginfo[] = {
 626     /* prefetch by MVA in v6, NOP in v7 */
 627     { .name = "MVA_prefetch",
 628       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 629       .access = PL1_W, .type = ARM_CP_NOP },
 630     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 631       .access = PL0_W, .type = ARM_CP_NOP },
 632     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 633       .access = PL0_W, .type = ARM_CP_NOP },
 634     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 635       .access = PL0_W, .type = ARM_CP_NOP },
 636     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 637       .access = PL1_RW,
 638       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 639                              offsetof(CPUARMState, cp15.ifar_ns) },
 640       .resetvalue = 0, },
 641     /* Watchpoint Fault Address Register : should actually only be present
 642      * for 1136, 1176, 11MPCore.
 643      */
 644     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 645       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 646     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 647       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 648       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 649       .resetvalue = 0, .writefn = cpacr_write },
 650     REGINFO_SENTINEL
 651 };
 652
 653 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 654 {
 655     /* Performance monitor registers user accessibility is controlled
 656      * by PMUSERENR.
 657      */
 658     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 659         return CP_ACCESS_TRAP;
 660     }
 661     return CP_ACCESS_OK;
 662 }
 663
 664 #ifndef CONFIG_USER_ONLY
 665
 666 static inline bool arm_ccnt_enabled(CPUARMState *env)
 667 {
 668     /* This does not support checking PMCCFILTR_EL0 register */
 669
 670     if (!(env->cp15.c9_pmcr & PMCRE)) {
 671         return false;
 672     }
 673
 674     return true;
 675 }
 676
 677 void pmccntr_sync(CPUARMState *env)
 678 {
 679     uint64_t temp_ticks;
 680
 681     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 682                           get_ticks_per_sec(), 1000000);
 683
 684     if (env->cp15.c9_pmcr & PMCRD) {
 685         /* Increment once every 64 processor clock cycles */
 686         temp_ticks /= 64;
 687     }
 688
 689     if (arm_ccnt_enabled(env)) {
 690         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 691     }
 692 }
 693
 694 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 695                        uint64_t value)
 696 {
 697     pmccntr_sync(env);
 698
 699     if (value & PMCRC) {
 700         /* The counter has been reset */
 701         env->cp15.c15_ccnt = 0;
 702     }
 703
 704     /* only the DP, X, D and E bits are writable */
 705     env->cp15.c9_pmcr &= ~0x39;
 706     env->cp15.c9_pmcr |= (value & 0x39);
 707
 708     pmccntr_sync(env);
 709 }
 710
 711 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 712 {
 713     uint64_t total_ticks;
 714
 715     if (!arm_ccnt_enabled(env)) {
 716         /* Counter is disabled, do not change value */
 717         return env->cp15.c15_ccnt;
 718     }
 719
 720     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 721                            get_ticks_per_sec(), 1000000);
 722
 723     if (env->cp15.c9_pmcr & PMCRD) {
 724         /* Increment once every 64 processor clock cycles */
 725         total_ticks /= 64;
 726     }
 727     return total_ticks - env->cp15.c15_ccnt;
 728 }
 729
 730 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 731                         uint64_t value)
 732 {
 733     uint64_t total_ticks;
 734
 735     if (!arm_ccnt_enabled(env)) {
 736         /* Counter is disabled, set the absolute value */
 737         env->cp15.c15_ccnt = value;
 738         return;
 739     }
 740
 741     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 742                            get_ticks_per_sec(), 1000000);
 743
 744     if (env->cp15.c9_pmcr & PMCRD) {
 745         /* Increment once every 64 processor clock cycles */
 746         total_ticks /= 64;
 747     }
 748     env->cp15.c15_ccnt = total_ticks - value;
 749 }
 750
 751 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 752                             uint64_t value)
 753 {
 754     uint64_t cur_val = pmccntr_read(env, NULL);
 755
 756     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 757 }
 758
 759 #else /* CONFIG_USER_ONLY */
 760
 761 void pmccntr_sync(CPUARMState *env)
 762 {
 763 }
 764
 765 #endif
 766
 767 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 768                             uint64_t value)
 769 {
 770     pmccntr_sync(env);
 771     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 772     pmccntr_sync(env);
 773 }
 774
 775 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 776                             uint64_t value)
 777 {
 778     value &= (1 << 31);
 779     env->cp15.c9_pmcnten |= value;
 780 }
 781
 782 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 783                              uint64_t value)
 784 {
 785     value &= (1 << 31);
 786     env->cp15.c9_pmcnten &= ~value;
 787 }
 788
 789 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 790                          uint64_t value)
 791 {
 792     env->cp15.c9_pmovsr &= ~value;
 793 }
 794
 795 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 796                              uint64_t value)
 797 {
 798     env->cp15.c9_pmxevtyper = value & 0xff;
 799 }
 800
 801 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 802                             uint64_t value)
 803 {
 804     env->cp15.c9_pmuserenr = value & 1;
 805 }
 806
 807 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 808                              uint64_t value)
 809 {
 810     /* We have no event counters so only the C bit can be changed */
 811     value &= (1 << 31);
 812     env->cp15.c9_pminten |= value;
 813 }
 814
 815 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 816                              uint64_t value)
 817 {
 818     value &= (1 << 31);
 819     env->cp15.c9_pminten &= ~value;
 820 }
 821
 822 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 823                        uint64_t value)
 824 {
 825     /* Note that even though the AArch64 view of this register has bits
 826      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 827      * architectural requirements for bits which are RES0 only in some
 828      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 829      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 830      */
 831     raw_write(env, ri, value & ~0x1FULL);
 832 }
 833
 834 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 835 {
 836     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 837      * For bits that vary between AArch32/64, code needs to check the
 838      * current execution mode before directly using the feature bit.
 839      */
 840     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 841
 842     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 843         valid_mask &= ~SCR_HCE;
 844
 845         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 846          * supported if EL2 exists. The bit is UNK/SBZP when
 847          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 848          * when EL2 is unavailable.
 849          * On ARMv8, this bit is always available.
 850          */
 851         if (arm_feature(env, ARM_FEATURE_V7) &&
 852             !arm_feature(env, ARM_FEATURE_V8)) {
 853             valid_mask &= ~SCR_SMD;
 854         }
 855     }
 856
 857     /* Clear all-context RES0 bits.  */
 858     value &= valid_mask;
 859     raw_write(env, ri, value);
 860 }
 861
 862 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 863 {
 864     ARMCPU *cpu = arm_env_get_cpu(env);
 865
 866     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 867      * bank
 868      */
 869     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 870                                         ri->secure & ARM_CP_SECSTATE_S);
 871
 872     return cpu->ccsidr[index];
 873 }
 874
 875 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 876                          uint64_t value)
 877 {
 878     raw_write(env, ri, value & 0xf);
 879 }
 880
 881 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 882 {
 883     CPUState *cs = ENV_GET_CPU(env);
 884     uint64_t ret = 0;
 885
 886     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 887         ret |= CPSR_I;
 888     }
 889     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 890         ret |= CPSR_F;
 891     }
 892     /* External aborts are not possible in QEMU so A bit is always clear */
 893     return ret;
 894 }
 895
 896 static const ARMCPRegInfo v7_cp_reginfo[] = {
 897     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 898     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 899       .access = PL1_W, .type = ARM_CP_NOP },
 900     /* Performance monitors are implementation defined in v7,
 901      * but with an ARM recommended set of registers, which we
 902      * follow (although we don't actually implement any counters)
 903      *
 904      * Performance registers fall into three categories:
 905      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 906      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 907      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 908      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 909      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 910      */
 911     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 912       .access = PL0_RW, .type = ARM_CP_ALIAS,
 913       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 914       .writefn = pmcntenset_write,
 915       .accessfn = pmreg_access,
 916       .raw_writefn = raw_write },
 917     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 918       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 919       .access = PL0_RW, .accessfn = pmreg_access,
 920       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 921       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 922     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 923       .access = PL0_RW,
 924       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 925       .accessfn = pmreg_access,
 926       .writefn = pmcntenclr_write,
 927       .type = ARM_CP_ALIAS },
 928     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 929       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 930       .access = PL0_RW, .accessfn = pmreg_access,
 931       .type = ARM_CP_ALIAS,
 932       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 933       .writefn = pmcntenclr_write },
 934     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 935       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 936       .accessfn = pmreg_access,
 937       .writefn = pmovsr_write,
 938       .raw_writefn = raw_write },
 939     /* Unimplemented so WI. */
 940     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 941       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 942     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 943      * We choose to RAZ/WI.
 944      */
 945     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 946       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 947       .accessfn = pmreg_access },
 948 #ifndef CONFIG_USER_ONLY
 949     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 950       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 951       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 952       .accessfn = pmreg_access },
 953     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 954       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 955       .access = PL0_RW, .accessfn = pmreg_access,
 956       .type = ARM_CP_IO,
 957       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 958 #endif
 959     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 960       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 961       .writefn = pmccfiltr_write,
 962       .access = PL0_RW, .accessfn = pmreg_access,
 963       .type = ARM_CP_IO,
 964       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 965       .resetvalue = 0, },
 966     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 967       .access = PL0_RW,
 968       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 969       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 970       .raw_writefn = raw_write },
 971     /* Unimplemented, RAZ/WI. */
 972     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 973       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 974       .accessfn = pmreg_access },
 975     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 976       .access = PL0_R | PL1_RW,
 977       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 978       .resetvalue = 0,
 979       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 980     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 981       .access = PL1_RW,
 982       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 983       .resetvalue = 0,
 984       .writefn = pmintenset_write, .raw_writefn = raw_write },
 985     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 986       .access = PL1_RW, .type = ARM_CP_ALIAS,
 987       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 988       .writefn = pmintenclr_write, },
 989     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 990       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 991       .access = PL1_RW, .writefn = vbar_write,
 992       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
 993                              offsetof(CPUARMState, cp15.vbar_ns) },
 994       .resetvalue = 0 },
 995     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 996       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 997       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
 998     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 999       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1000       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1001       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1002                              offsetof(CPUARMState, cp15.csselr_ns) } },
1003     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1004      * just RAZ for all cores:
1005      */
1006     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1007       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1008       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1009     /* Auxiliary fault status registers: these also are IMPDEF, and we
1010      * choose to RAZ/WI for all cores.
1011      */
1012     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1013       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1014       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1015     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1016       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1017       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1018     /* MAIR can just read-as-written because we don't implement caches
1019      * and so don't need to care about memory attributes.
1020      */
1021     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1022       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1023       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1024       .resetvalue = 0 },
1025     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1026       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1027       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1028       .resetvalue = 0 },
1029     /* For non-long-descriptor page tables these are PRRR and NMRR;
1030      * regardless they still act as reads-as-written for QEMU.
1031      */
1032      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1033       * allows them to assign the correct fieldoffset based on the endianness
1034       * handled in the field definitions.
1035       */
1036     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1037       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1038       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1039                              offsetof(CPUARMState, cp15.mair0_ns) },
1040       .resetfn = arm_cp_reset_ignore },
1041     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1042       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1043       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1044                              offsetof(CPUARMState, cp15.mair1_ns) },
1045       .resetfn = arm_cp_reset_ignore },
1046     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1047       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1048       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1049     /* 32 bit ITLB invalidates */
1050     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1051       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1052     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1053       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1054     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1055       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1056     /* 32 bit DTLB invalidates */
1057     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1058       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1059     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1060       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1061     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1062       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1063     /* 32 bit TLB invalidates */
1064     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1065       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1066     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1067       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1068     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1069       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1070     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1071       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1072     REGINFO_SENTINEL
1073 };
1074
1075 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1076     /* 32 bit TLB invalidates, Inner Shareable */
1077     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1078       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1079     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1080       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1081     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1082       .type = ARM_CP_NO_RAW, .access = PL1_W,
1083       .writefn = tlbiasid_is_write },
1084     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1085       .type = ARM_CP_NO_RAW, .access = PL1_W,
1086       .writefn = tlbimvaa_is_write },
1087     REGINFO_SENTINEL
1088 };
1089
1090 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1091                         uint64_t value)
1092 {
1093     value &= 1;
1094     env->teecr = value;
1095 }
1096
1097 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1098 {
1099     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1100         return CP_ACCESS_TRAP;
1101     }
1102     return CP_ACCESS_OK;
1103 }
1104
1105 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1106     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1107       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1108       .resetvalue = 0,
1109       .writefn = teecr_write },
1110     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1111       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1112       .accessfn = teehbr_access, .resetvalue = 0 },
1113     REGINFO_SENTINEL
1114 };
1115
1116 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1117     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1118       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1119       .access = PL0_RW,
1120       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1121     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1122       .access = PL0_RW,
1123       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1124                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1125       .resetfn = arm_cp_reset_ignore },
1126     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1127       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1128       .access = PL0_R|PL1_W,
1129       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1130       .resetvalue = 0},
1131     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1132       .access = PL0_R|PL1_W,
1133       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1134                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1135       .resetfn = arm_cp_reset_ignore },
1136     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1137       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1138       .access = PL1_RW,
1139       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1140     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1141       .access = PL1_RW,
1142       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1143                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1144       .resetvalue = 0 },
1145     REGINFO_SENTINEL
1146 };
1147
1148 #ifndef CONFIG_USER_ONLY
1149
1150 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1151 {
1152     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1153     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1154         return CP_ACCESS_TRAP;
1155     }
1156     return CP_ACCESS_OK;
1157 }
1158
1159 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1160 {
1161     unsigned int cur_el = arm_current_el(env);
1162     bool secure = arm_is_secure(env);
1163
1164     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1165     if (cur_el == 0 &&
1166         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1167         return CP_ACCESS_TRAP;
1168     }
1169
1170     if (arm_feature(env, ARM_FEATURE_EL2) &&
1171         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1172         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1173         return CP_ACCESS_TRAP_EL2;
1174     }
1175     return CP_ACCESS_OK;
1176 }
1177
1178 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1179 {
1180     unsigned int cur_el = arm_current_el(env);
1181     bool secure = arm_is_secure(env);
1182
1183     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1184      * EL0[PV]TEN is zero.
1185      */
1186     if (cur_el == 0 &&
1187         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1188         return CP_ACCESS_TRAP;
1189     }
1190
1191     if (arm_feature(env, ARM_FEATURE_EL2) &&
1192         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1193         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1194         return CP_ACCESS_TRAP_EL2;
1195     }
1196     return CP_ACCESS_OK;
1197 }
1198
1199 static CPAccessResult gt_pct_access(CPUARMState *env,
1200                                          const ARMCPRegInfo *ri)
1201 {
1202     return gt_counter_access(env, GTIMER_PHYS);
1203 }
1204
1205 static CPAccessResult gt_vct_access(CPUARMState *env,
1206                                          const ARMCPRegInfo *ri)
1207 {
1208     return gt_counter_access(env, GTIMER_VIRT);
1209 }
1210
1211 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1212 {
1213     return gt_timer_access(env, GTIMER_PHYS);
1214 }
1215
1216 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1217 {
1218     return gt_timer_access(env, GTIMER_VIRT);
1219 }
1220
1221 static CPAccessResult gt_stimer_access(CPUARMState *env,
1222                                        const ARMCPRegInfo *ri)
1223 {
1224     /* The AArch64 register view of the secure physical timer is
1225      * always accessible from EL3, and configurably accessible from
1226      * Secure EL1.
1227      */
1228     switch (arm_current_el(env)) {
1229     case 1:
1230         if (!arm_is_secure(env)) {
1231             return CP_ACCESS_TRAP;
1232         }
1233         if (!(env->cp15.scr_el3 & SCR_ST)) {
1234             return CP_ACCESS_TRAP_EL3;
1235         }
1236         return CP_ACCESS_OK;
1237     case 0:
1238     case 2:
1239         return CP_ACCESS_TRAP;
1240     case 3:
1241         return CP_ACCESS_OK;
1242     default:
1243         g_assert_not_reached();
1244     }
1245 }
1246
1247 static uint64_t gt_get_countervalue(CPUARMState *env)
1248 {
1249     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1250 }
1251
1252 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1253 {
1254     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1255
1256     if (gt->ctl & 1) {
1257         /* Timer enabled: calculate and set current ISTATUS, irq, and
1258          * reset timer to when ISTATUS next has to change
1259          */
1260         uint64_t offset = timeridx == GTIMER_VIRT ?
1261                                       cpu->env.cp15.cntvoff_el2 : 0;
1262         uint64_t count = gt_get_countervalue(&cpu->env);
1263         /* Note that this must be unsigned 64 bit arithmetic: */
1264         int istatus = count - offset >= gt->cval;
1265         uint64_t nexttick;
1266
1267         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1268         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1269                      (istatus && !(gt->ctl & 2)));
1270         if (istatus) {
1271             /* Next transition is when count rolls back over to zero */
1272             nexttick = UINT64_MAX;
1273         } else {
1274             /* Next transition is when we hit cval */
1275             nexttick = gt->cval + offset;
1276         }
1277         /* Note that the desired next expiry time might be beyond the
1278          * signed-64-bit range of a QEMUTimer -- in this case we just
1279          * set the timer for as far in the future as possible. When the
1280          * timer expires we will reset the timer for any remaining period.
1281          */
1282         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1283             nexttick = INT64_MAX / GTIMER_SCALE;
1284         }
1285         timer_mod(cpu->gt_timer[timeridx], nexttick);
1286     } else {
1287         /* Timer disabled: ISTATUS and timer output always clear */
1288         gt->ctl &= ~4;
1289         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1290         timer_del(cpu->gt_timer[timeridx]);
1291     }
1292 }
1293
1294 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1295                            int timeridx)
1296 {
1297     ARMCPU *cpu = arm_env_get_cpu(env);
1298
1299     timer_del(cpu->gt_timer[timeridx]);
1300 }
1301
1302 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1303 {
1304     return gt_get_countervalue(env);
1305 }
1306
1307 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1308 {
1309     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1310 }
1311
1312 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1313                           int timeridx,
1314                           uint64_t value)
1315 {
1316     env->cp15.c14_timer[timeridx].cval = value;
1317     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1318 }
1319
1320 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1321                              int timeridx)
1322 {
1323     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1324
1325     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1326                       (gt_get_countervalue(env) - offset));
1327 }
1328
1329 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1330                           int timeridx,
1331                           uint64_t value)
1332 {
1333     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1334
1335     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1336                                          sextract64(value, 0, 32);
1337     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1338 }
1339
1340 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1341                          int timeridx,
1342                          uint64_t value)
1343 {
1344     ARMCPU *cpu = arm_env_get_cpu(env);
1345     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1346
1347     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1348     if ((oldval ^ value) & 1) {
1349         /* Enable toggled */
1350         gt_recalc_timer(cpu, timeridx);
1351     } else if ((oldval ^ value) & 2) {
1352         /* IMASK toggled: don't need to recalculate,
1353          * just set the interrupt line based on ISTATUS
1354          */
1355         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1356                      (oldval & 4) && !(value & 2));
1357     }
1358 }
1359
1360 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1361 {
1362     gt_timer_reset(env, ri, GTIMER_PHYS);
1363 }
1364
1365 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1366                                uint64_t value)
1367 {
1368     gt_cval_write(env, ri, GTIMER_PHYS, value);
1369 }
1370
1371 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1372 {
1373     return gt_tval_read(env, ri, GTIMER_PHYS);
1374 }
1375
1376 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1377                                uint64_t value)
1378 {
1379     gt_tval_write(env, ri, GTIMER_PHYS, value);
1380 }
1381
1382 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1383                               uint64_t value)
1384 {
1385     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1386 }
1387
1388 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1389 {
1390     gt_timer_reset(env, ri, GTIMER_VIRT);
1391 }
1392
1393 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1394                                uint64_t value)
1395 {
1396     gt_cval_write(env, ri, GTIMER_VIRT, value);
1397 }
1398
1399 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1400 {
1401     return gt_tval_read(env, ri, GTIMER_VIRT);
1402 }
1403
1404 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1405                                uint64_t value)
1406 {
1407     gt_tval_write(env, ri, GTIMER_VIRT, value);
1408 }
1409
1410 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1411                               uint64_t value)
1412 {
1413     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1414 }
1415
1416 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1417                               uint64_t value)
1418 {
1419     ARMCPU *cpu = arm_env_get_cpu(env);
1420
1421     raw_write(env, ri, value);
1422     gt_recalc_timer(cpu, GTIMER_VIRT);
1423 }
1424
1425 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1426 {
1427     gt_timer_reset(env, ri, GTIMER_HYP);
1428 }
1429
1430 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1431                               uint64_t value)
1432 {
1433     gt_cval_write(env, ri, GTIMER_HYP, value);
1434 }
1435
1436 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1437 {
1438     return gt_tval_read(env, ri, GTIMER_HYP);
1439 }
1440
1441 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1442                               uint64_t value)
1443 {
1444     gt_tval_write(env, ri, GTIMER_HYP, value);
1445 }
1446
1447 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1448                               uint64_t value)
1449 {
1450     gt_ctl_write(env, ri, GTIMER_HYP, value);
1451 }
1452
1453 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1454 {
1455     gt_timer_reset(env, ri, GTIMER_SEC);
1456 }
1457
1458 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1459                               uint64_t value)
1460 {
1461     gt_cval_write(env, ri, GTIMER_SEC, value);
1462 }
1463
1464 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1465 {
1466     return gt_tval_read(env, ri, GTIMER_SEC);
1467 }
1468
1469 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1470                               uint64_t value)
1471 {
1472     gt_tval_write(env, ri, GTIMER_SEC, value);
1473 }
1474
1475 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1476                               uint64_t value)
1477 {
1478     gt_ctl_write(env, ri, GTIMER_SEC, value);
1479 }
1480
1481 void arm_gt_ptimer_cb(void *opaque)
1482 {
1483     ARMCPU *cpu = opaque;
1484
1485     gt_recalc_timer(cpu, GTIMER_PHYS);
1486 }
1487
1488 void arm_gt_vtimer_cb(void *opaque)
1489 {
1490     ARMCPU *cpu = opaque;
1491
1492     gt_recalc_timer(cpu, GTIMER_VIRT);
1493 }
1494
1495 void arm_gt_htimer_cb(void *opaque)
1496 {
1497     ARMCPU *cpu = opaque;
1498
1499     gt_recalc_timer(cpu, GTIMER_HYP);
1500 }
1501
1502 void arm_gt_stimer_cb(void *opaque)
1503 {
1504     ARMCPU *cpu = opaque;
1505
1506     gt_recalc_timer(cpu, GTIMER_SEC);
1507 }
1508
1509 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1510     /* Note that CNTFRQ is purely reads-as-written for the benefit
1511      * of software; writing it doesn't actually change the timer frequency.
1512      * Our reset value matches the fixed frequency we implement the timer at.
1513      */
1514     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1515       .type = ARM_CP_ALIAS,
1516       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1517       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1518     },
1519     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1520       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1521       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1522       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1523       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1524     },
1525     /* overall control: mostly access permissions */
1526     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1527       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1528       .access = PL1_RW,
1529       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1530       .resetvalue = 0,
1531     },
1532     /* per-timer control */
1533     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1534       .secure = ARM_CP_SECSTATE_NS,
1535       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1536       .accessfn = gt_ptimer_access,
1537       .fieldoffset = offsetoflow32(CPUARMState,
1538                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1539       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1540     },
1541     { .name = "CNTP_CTL(S)",
1542       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1543       .secure = ARM_CP_SECSTATE_S,
1544       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1545       .accessfn = gt_ptimer_access,
1546       .fieldoffset = offsetoflow32(CPUARMState,
1547                                    cp15.c14_timer[GTIMER_SEC].ctl),
1548       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1549     },
1550     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1551       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1552       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1553       .accessfn = gt_ptimer_access,
1554       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1555       .resetvalue = 0,
1556       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1557     },
1558     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1559       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1560       .accessfn = gt_vtimer_access,
1561       .fieldoffset = offsetoflow32(CPUARMState,
1562                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1563       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1564     },
1565     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1566       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1567       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1568       .accessfn = gt_vtimer_access,
1569       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1570       .resetvalue = 0,
1571       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1572     },
1573     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1574     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1575       .secure = ARM_CP_SECSTATE_NS,
1576       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1577       .accessfn = gt_ptimer_access,
1578       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1579     },
1580     { .name = "CNTP_TVAL(S)",
1581       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1582       .secure = ARM_CP_SECSTATE_S,
1583       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1584       .accessfn = gt_ptimer_access,
1585       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1586     },
1587     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1588       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1589       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1590       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1591       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1592     },
1593     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1594       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1595       .accessfn = gt_vtimer_access,
1596       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1597     },
1598     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1599       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1600       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1601       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1602       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1603     },
1604     /* The counter itself */
1605     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1606       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1607       .accessfn = gt_pct_access,
1608       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1609     },
1610     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1611       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1612       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1613       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1614     },
1615     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1616       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1617       .accessfn = gt_vct_access,
1618       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1619     },
1620     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1621       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1622       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1623       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1624     },
1625     /* Comparison value, indicating when the timer goes off */
1626     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1627       .secure = ARM_CP_SECSTATE_NS,
1628       .access = PL1_RW | PL0_R,
1629       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1630       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1631       .accessfn = gt_ptimer_access,
1632       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1633     },
1634     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1635       .secure = ARM_CP_SECSTATE_S,
1636       .access = PL1_RW | PL0_R,
1637       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1638       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1639       .accessfn = gt_ptimer_access,
1640       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1641     },
1642     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1643       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1644       .access = PL1_RW | PL0_R,
1645       .type = ARM_CP_IO,
1646       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1647       .resetvalue = 0, .accessfn = gt_ptimer_access,
1648       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1649     },
1650     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1651       .access = PL1_RW | PL0_R,
1652       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1653       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1654       .accessfn = gt_vtimer_access,
1655       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1656     },
1657     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1658       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1659       .access = PL1_RW | PL0_R,
1660       .type = ARM_CP_IO,
1661       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1662       .resetvalue = 0, .accessfn = gt_vtimer_access,
1663       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1664     },
1665     /* Secure timer -- this is actually restricted to only EL3
1666      * and configurably Secure-EL1 via the accessfn.
1667      */
1668     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1669       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1670       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1671       .accessfn = gt_stimer_access,
1672       .readfn = gt_sec_tval_read,
1673       .writefn = gt_sec_tval_write,
1674       .resetfn = gt_sec_timer_reset,
1675     },
1676     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1677       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1678       .type = ARM_CP_IO, .access = PL1_RW,
1679       .accessfn = gt_stimer_access,
1680       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1681       .resetvalue = 0,
1682       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1683     },
1684     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1685       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1686       .type = ARM_CP_IO, .access = PL1_RW,
1687       .accessfn = gt_stimer_access,
1688       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1689       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1690     },
1691     REGINFO_SENTINEL
1692 };
1693
1694 #else
1695 /* In user-mode none of the generic timer registers are accessible,
1696  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1697  * so instead just don't register any of them.
1698  */
1699 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1700     REGINFO_SENTINEL
1701 };
1702
1703 #endif
1704
1705 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1706 {
1707     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1708         raw_write(env, ri, value);
1709     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1710         raw_write(env, ri, value & 0xfffff6ff);
1711     } else {
1712         raw_write(env, ri, value & 0xfffff1ff);
1713     }
1714 }
1715
1716 #ifndef CONFIG_USER_ONLY
1717 /* get_phys_addr() isn't present for user-mode-only targets */
1718
1719 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1720 {
1721     if (ri->opc2 & 4) {
1722         /* The ATS12NSO* operations must trap to EL3 if executed in
1723          * Secure EL1 (which can only happen if EL3 is AArch64).
1724          * They are simply UNDEF if executed from NS EL1.
1725          * They function normally from EL2 or EL3.
1726          */
1727         if (arm_current_el(env) == 1) {
1728             if (arm_is_secure_below_el3(env)) {
1729                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1730             }
1731             return CP_ACCESS_TRAP_UNCATEGORIZED;
1732         }
1733     }
1734     return CP_ACCESS_OK;
1735 }
1736
1737 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1738                              int access_type, ARMMMUIdx mmu_idx)
1739 {
1740     hwaddr phys_addr;
1741     target_ulong page_size;
1742     int prot;
1743     uint32_t fsr;
1744     bool ret;
1745     uint64_t par64;
1746     MemTxAttrs attrs = {};
1747
1748     ret = get_phys_addr(env, value, access_type, mmu_idx,
1749                         &phys_addr, &attrs, &prot, &page_size, &fsr);
1750     if (extended_addresses_enabled(env)) {
1751         /* fsr is a DFSR/IFSR value for the long descriptor
1752          * translation table format, but with WnR always clear.
1753          * Convert it to a 64-bit PAR.
1754          */
1755         par64 = (1 << 11); /* LPAE bit always set */
1756         if (!ret) {
1757             par64 |= phys_addr & ~0xfffULL;
1758             if (!attrs.secure) {
1759                 par64 |= (1 << 9); /* NS */
1760             }
1761             /* We don't set the ATTR or SH fields in the PAR. */
1762         } else {
1763             par64 |= 1; /* F */
1764             par64 |= (fsr & 0x3f) << 1; /* FS */
1765             /* Note that S2WLK and FSTAGE are always zero, because we don't
1766              * implement virtualization and therefore there can't be a stage 2
1767              * fault.
1768              */
1769         }
1770     } else {
1771         /* fsr is a DFSR/IFSR value for the short descriptor
1772          * translation table format (with WnR always clear).
1773          * Convert it to a 32-bit PAR.
1774          */
1775         if (!ret) {
1776             /* We do not set any attribute bits in the PAR */
1777             if (page_size == (1 << 24)
1778                 && arm_feature(env, ARM_FEATURE_V7)) {
1779                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1780             } else {
1781                 par64 = phys_addr & 0xfffff000;
1782             }
1783             if (!attrs.secure) {
1784                 par64 |= (1 << 9); /* NS */
1785             }
1786         } else {
1787             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1788                     ((fsr & 0xf) << 1) | 1;
1789         }
1790     }
1791     return par64;
1792 }
1793
1794 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1795 {
1796     int access_type = ri->opc2 & 1;
1797     uint64_t par64;
1798     ARMMMUIdx mmu_idx;
1799     int el = arm_current_el(env);
1800     bool secure = arm_is_secure_below_el3(env);
1801
1802     switch (ri->opc2 & 6) {
1803     case 0:
1804         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1805         switch (el) {
1806         case 3:
1807             mmu_idx = ARMMMUIdx_S1E3;
1808             break;
1809         case 2:
1810             mmu_idx = ARMMMUIdx_S1NSE1;
1811             break;
1812         case 1:
1813             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1814             break;
1815         default:
1816             g_assert_not_reached();
1817         }
1818         break;
1819     case 2:
1820         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1821         switch (el) {
1822         case 3:
1823             mmu_idx = ARMMMUIdx_S1SE0;
1824             break;
1825         case 2:
1826             mmu_idx = ARMMMUIdx_S1NSE0;
1827             break;
1828         case 1:
1829             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1830             break;
1831         default:
1832             g_assert_not_reached();
1833         }
1834         break;
1835     case 4:
1836         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1837         mmu_idx = ARMMMUIdx_S12NSE1;
1838         break;
1839     case 6:
1840         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1841         mmu_idx = ARMMMUIdx_S12NSE0;
1842         break;
1843     default:
1844         g_assert_not_reached();
1845     }
1846
1847     par64 = do_ats_write(env, value, access_type, mmu_idx);
1848
1849     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1850 }
1851
1852 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1853                         uint64_t value)
1854 {
1855     int access_type = ri->opc2 & 1;
1856     uint64_t par64;
1857
1858     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1859
1860     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1861 }
1862
1863 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
1864 {
1865     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1866         return CP_ACCESS_TRAP;
1867     }
1868     return CP_ACCESS_OK;
1869 }
1870
1871 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1872                         uint64_t value)
1873 {
1874     int access_type = ri->opc2 & 1;
1875     ARMMMUIdx mmu_idx;
1876     int secure = arm_is_secure_below_el3(env);
1877
1878     switch (ri->opc2 & 6) {
1879     case 0:
1880         switch (ri->opc1) {
1881         case 0: /* AT S1E1R, AT S1E1W */
1882             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1883             break;
1884         case 4: /* AT S1E2R, AT S1E2W */
1885             mmu_idx = ARMMMUIdx_S1E2;
1886             break;
1887         case 6: /* AT S1E3R, AT S1E3W */
1888             mmu_idx = ARMMMUIdx_S1E3;
1889             break;
1890         default:
1891             g_assert_not_reached();
1892         }
1893         break;
1894     case 2: /* AT S1E0R, AT S1E0W */
1895         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1896         break;
1897     case 4: /* AT S12E1R, AT S12E1W */
1898         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1899         break;
1900     case 6: /* AT S12E0R, AT S12E0W */
1901         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1902         break;
1903     default:
1904         g_assert_not_reached();
1905     }
1906
1907     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1908 }
1909 #endif
1910
1911 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1912     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1913       .access = PL1_RW, .resetvalue = 0,
1914       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1915                              offsetoflow32(CPUARMState, cp15.par_ns) },
1916       .writefn = par_write },
1917 #ifndef CONFIG_USER_ONLY
1918     /* This underdecoding is safe because the reginfo is NO_RAW. */
1919     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1920       .access = PL1_W, .accessfn = ats_access,
1921       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1922 #endif
1923     REGINFO_SENTINEL
1924 };
1925
1926 /* Return basic MPU access permission bits.  */
1927 static uint32_t simple_mpu_ap_bits(uint32_t val)
1928 {
1929     uint32_t ret;
1930     uint32_t mask;
1931     int i;
1932     ret = 0;
1933     mask = 3;
1934     for (i = 0; i < 16; i += 2) {
1935         ret |= (val >> i) & mask;
1936         mask <<= 2;
1937     }
1938     return ret;
1939 }
1940
1941 /* Pad basic MPU access permission bits to extended format.  */
1942 static uint32_t extended_mpu_ap_bits(uint32_t val)
1943 {
1944     uint32_t ret;
1945     uint32_t mask;
1946     int i;
1947     ret = 0;
1948     mask = 3;
1949     for (i = 0; i < 16; i += 2) {
1950         ret |= (val & mask) << i;
1951         mask <<= 2;
1952     }
1953     return ret;
1954 }
1955
1956 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1957                                  uint64_t value)
1958 {
1959     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1960 }
1961
1962 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1963 {
1964     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1965 }
1966
1967 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1968                                  uint64_t value)
1969 {
1970     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1971 }
1972
1973 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1974 {
1975     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1976 }
1977
1978 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
1979 {
1980     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
1981
1982     if (!u32p) {
1983         return 0;
1984     }
1985
1986     u32p += env->cp15.c6_rgnr;
1987     return *u32p;
1988 }
1989
1990 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
1991                          uint64_t value)
1992 {
1993     ARMCPU *cpu = arm_env_get_cpu(env);
1994     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
1995
1996     if (!u32p) {
1997         return;
1998     }
1999
2000     u32p += env->cp15.c6_rgnr;
2001     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2002     *u32p = value;
2003 }
2004
2005 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2006 {
2007     ARMCPU *cpu = arm_env_get_cpu(env);
2008     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2009
2010     if (!u32p) {
2011         return;
2012     }
2013
2014     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2015 }
2016
2017 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2018                               uint64_t value)
2019 {
2020     ARMCPU *cpu = arm_env_get_cpu(env);
2021     uint32_t nrgs = cpu->pmsav7_dregion;
2022
2023     if (value >= nrgs) {
2024         qemu_log_mask(LOG_GUEST_ERROR,
2025                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2026                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2027         return;
2028     }
2029
2030     raw_write(env, ri, value);
2031 }
2032
2033 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2034     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2035       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2036       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2037       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2038     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2039       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2040       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2041       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2042     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2043       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2044       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2045       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2046     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2047       .access = PL1_RW,
2048       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2049       .writefn = pmsav7_rgnr_write },
2050     REGINFO_SENTINEL
2051 };
2052
2053 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2054     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2055       .access = PL1_RW, .type = ARM_CP_ALIAS,
2056       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2057       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2058     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2059       .access = PL1_RW, .type = ARM_CP_ALIAS,
2060       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2061       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2062     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2063       .access = PL1_RW,
2064       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2065       .resetvalue = 0, },
2066     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2067       .access = PL1_RW,
2068       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2069       .resetvalue = 0, },
2070     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2071       .access = PL1_RW,
2072       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2073     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2074       .access = PL1_RW,
2075       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2076     /* Protection region base and size registers */
2077     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2078       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2079       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2080     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2081       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2082       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2083     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2084       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2085       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2086     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2087       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2088       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2089     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2090       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2091       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2092     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2093       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2094       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2095     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2096       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2097       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2098     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2099       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2100       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2101     REGINFO_SENTINEL
2102 };
2103
2104 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2105                                  uint64_t value)
2106 {
2107     TCR *tcr = raw_ptr(env, ri);
2108     int maskshift = extract32(value, 0, 3);
2109
2110     if (!arm_feature(env, ARM_FEATURE_V8)) {
2111         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2112             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2113              * using Long-desciptor translation table format */
2114             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2115         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2116             /* In an implementation that includes the Security Extensions
2117              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2118              * Short-descriptor translation table format.
2119              */
2120             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2121         } else {
2122             value &= TTBCR_N;
2123         }
2124     }
2125
2126     /* Update the masks corresponding to the the TCR bank being written
2127      * Note that we always calculate mask and base_mask, but
2128      * they are only used for short-descriptor tables (ie if EAE is 0);
2129      * for long-descriptor tables the TCR fields are used differently
2130      * and the mask and base_mask values are meaningless.
2131      */
2132     tcr->raw_tcr = value;
2133     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2134     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2135 }
2136
2137 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2138                              uint64_t value)
2139 {
2140     ARMCPU *cpu = arm_env_get_cpu(env);
2141
2142     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2143         /* With LPAE the TTBCR could result in a change of ASID
2144          * via the TTBCR.A1 bit, so do a TLB flush.
2145          */
2146         tlb_flush(CPU(cpu), 1);
2147     }
2148     vmsa_ttbcr_raw_write(env, ri, value);
2149 }
2150
2151 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2152 {
2153     TCR *tcr = raw_ptr(env, ri);
2154
2155     /* Reset both the TCR as well as the masks corresponding to the bank of
2156      * the TCR being reset.
2157      */
2158     tcr->raw_tcr = 0;
2159     tcr->mask = 0;
2160     tcr->base_mask = 0xffffc000u;
2161 }
2162
2163 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2164                                uint64_t value)
2165 {
2166     ARMCPU *cpu = arm_env_get_cpu(env);
2167     TCR *tcr = raw_ptr(env, ri);
2168
2169     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2170     tlb_flush(CPU(cpu), 1);
2171     tcr->raw_tcr = value;
2172 }
2173
2174 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2175                             uint64_t value)
2176 {
2177     /* 64 bit accesses to the TTBRs can change the ASID and so we
2178      * must flush the TLB.
2179      */
2180     if (cpreg_field_is_64bit(ri)) {
2181         ARMCPU *cpu = arm_env_get_cpu(env);
2182
2183         tlb_flush(CPU(cpu), 1);
2184     }
2185     raw_write(env, ri, value);
2186 }
2187
2188 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2189     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2190       .access = PL1_RW, .type = ARM_CP_ALIAS,
2191       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2192                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2193     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2194       .access = PL1_RW, .resetvalue = 0,
2195       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2196                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2197     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2198       .access = PL1_RW, .resetvalue = 0,
2199       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2200                              offsetof(CPUARMState, cp15.dfar_ns) } },
2201     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2202       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2203       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2204       .resetvalue = 0, },
2205     REGINFO_SENTINEL
2206 };
2207
2208 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2209     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2210       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2211       .access = PL1_RW,
2212       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2213     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2214       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2215       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2216       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2217                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2218     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2219       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2220       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2221       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2222                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2223     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2224       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2225       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2226       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2227       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2228     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2229       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2230       .raw_writefn = vmsa_ttbcr_raw_write,
2231       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2232                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2233     REGINFO_SENTINEL
2234 };
2235
2236 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2237                                 uint64_t value)
2238 {
2239     env->cp15.c15_ticonfig = value & 0xe7;
2240     /* The OS_TYPE bit in this register changes the reported CPUID! */
2241     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2242         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2243 }
2244
2245 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2246                                 uint64_t value)
2247 {
2248     env->cp15.c15_threadid = value & 0xffff;
2249 }
2250
2251 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2252                            uint64_t value)
2253 {
2254     /* Wait-for-interrupt (deprecated) */
2255     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2256 }
2257
2258 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2259                                   uint64_t value)
2260 {
2261     /* On OMAP there are registers indicating the max/min index of dcache lines
2262      * containing a dirty line; cache flush operations have to reset these.
2263      */
2264     env->cp15.c15_i_max = 0x000;
2265     env->cp15.c15_i_min = 0xff0;
2266 }
2267
2268 static const ARMCPRegInfo omap_cp_reginfo[] = {
2269     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2270       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2271       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2272       .resetvalue = 0, },
2273     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2274       .access = PL1_RW, .type = ARM_CP_NOP },
2275     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2276       .access = PL1_RW,
2277       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2278       .writefn = omap_ticonfig_write },
2279     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2280       .access = PL1_RW,
2281       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2282     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2283       .access = PL1_RW, .resetvalue = 0xff0,
2284       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2285     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2286       .access = PL1_RW,
2287       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2288       .writefn = omap_threadid_write },
2289     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2290       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2291       .type = ARM_CP_NO_RAW,
2292       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2293     /* TODO: Peripheral port remap register:
2294      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2295      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2296      * when MMU is off.
2297      */
2298     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2299       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2300       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2301       .writefn = omap_cachemaint_write },
2302     { .name = "C9", .cp = 15, .crn = 9,
2303       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2304       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2305     REGINFO_SENTINEL
2306 };
2307
2308 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2309                               uint64_t value)
2310 {
2311     env->cp15.c15_cpar = value & 0x3fff;
2312 }
2313
2314 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2315     { .name = "XSCALE_CPAR",
2316       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2317       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2318       .writefn = xscale_cpar_write, },
2319     { .name = "XSCALE_AUXCR",
2320       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2321       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2322       .resetvalue = 0, },
2323     /* XScale specific cache-lockdown: since we have no cache we NOP these
2324      * and hope the guest does not really rely on cache behaviour.
2325      */
2326     { .name = "XSCALE_LOCK_ICACHE_LINE",
2327       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2328       .access = PL1_W, .type = ARM_CP_NOP },
2329     { .name = "XSCALE_UNLOCK_ICACHE",
2330       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2331       .access = PL1_W, .type = ARM_CP_NOP },
2332     { .name = "XSCALE_DCACHE_LOCK",
2333       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2334       .access = PL1_RW, .type = ARM_CP_NOP },
2335     { .name = "XSCALE_UNLOCK_DCACHE",
2336       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2337       .access = PL1_W, .type = ARM_CP_NOP },
2338     REGINFO_SENTINEL
2339 };
2340
2341 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2342     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2343      * implementation of this implementation-defined space.
2344      * Ideally this should eventually disappear in favour of actually
2345      * implementing the correct behaviour for all cores.
2346      */
2347     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2348       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2349       .access = PL1_RW,
2350       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2351       .resetvalue = 0 },
2352     REGINFO_SENTINEL
2353 };
2354
2355 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2356     /* Cache status: RAZ because we have no cache so it's always clean */
2357     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2358       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2359       .resetvalue = 0 },
2360     REGINFO_SENTINEL
2361 };
2362
2363 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2364     /* We never have a a block transfer operation in progress */
2365     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2366       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2367       .resetvalue = 0 },
2368     /* The cache ops themselves: these all NOP for QEMU */
2369     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2370       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2371     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2372       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2373     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2374       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2375     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2376       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2377     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2378       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2379     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2380       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2381     REGINFO_SENTINEL
2382 };
2383
2384 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2385     /* The cache test-and-clean instructions always return (1 << 30)
2386      * to indicate that there are no dirty cache lines.
2387      */
2388     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2389       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2390       .resetvalue = (1 << 30) },
2391     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2392       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2393       .resetvalue = (1 << 30) },
2394     REGINFO_SENTINEL
2395 };
2396
2397 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2398     /* Ignore ReadBuffer accesses */
2399     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2400       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2401       .access = PL1_RW, .resetvalue = 0,
2402       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2403     REGINFO_SENTINEL
2404 };
2405
2406 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2407 {
2408     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2409     uint64_t mpidr = cpu->mp_affinity;
2410
2411     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2412         mpidr |= (1U << 31);
2413         /* Cores which are uniprocessor (non-coherent)
2414          * but still implement the MP extensions set
2415          * bit 30. (For instance, Cortex-R5).
2416          */
2417         if (cpu->mp_is_up) {
2418             mpidr |= (1u << 30);
2419         }
2420     }
2421     return mpidr;
2422 }
2423
2424 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2425     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2426       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2427       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2428     REGINFO_SENTINEL
2429 };
2430
2431 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2432     /* NOP AMAIR0/1 */
2433     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2434       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2435       .access = PL1_RW, .type = ARM_CP_CONST,
2436       .resetvalue = 0 },
2437     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2438     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2439       .access = PL1_RW, .type = ARM_CP_CONST,
2440       .resetvalue = 0 },
2441     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2442       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2443       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2444                              offsetof(CPUARMState, cp15.par_ns)} },
2445     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2446       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2447       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2448                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2449       .writefn = vmsa_ttbr_write, },
2450     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2451       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2452       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2453                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2454       .writefn = vmsa_ttbr_write, },
2455     REGINFO_SENTINEL
2456 };
2457
2458 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2459 {
2460     return vfp_get_fpcr(env);
2461 }
2462
2463 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2464                             uint64_t value)
2465 {
2466     vfp_set_fpcr(env, value);
2467 }
2468
2469 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2470 {
2471     return vfp_get_fpsr(env);
2472 }
2473
2474 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2475                             uint64_t value)
2476 {
2477     vfp_set_fpsr(env, value);
2478 }
2479
2480 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2481 {
2482     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2483         return CP_ACCESS_TRAP;
2484     }
2485     return CP_ACCESS_OK;
2486 }
2487
2488 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2489                             uint64_t value)
2490 {
2491     env->daif = value & PSTATE_DAIF;
2492 }
2493
2494 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2495                                           const ARMCPRegInfo *ri)
2496 {
2497     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2498      * SCTLR_EL1.UCI is set.
2499      */
2500     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2501         return CP_ACCESS_TRAP;
2502     }
2503     return CP_ACCESS_OK;
2504 }
2505
2506 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2507  * Page D4-1736 (DDI0487A.b)
2508  */
2509
2510 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2511                                     uint64_t value)
2512 {
2513     ARMCPU *cpu = arm_env_get_cpu(env);
2514     CPUState *cs = CPU(cpu);
2515
2516     if (arm_is_secure_below_el3(env)) {
2517         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2518     } else {
2519         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2520     }
2521 }
2522
2523 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2524                                       uint64_t value)
2525 {
2526     bool sec = arm_is_secure_below_el3(env);
2527     CPUState *other_cs;
2528
2529     CPU_FOREACH(other_cs) {
2530         if (sec) {
2531             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2532         } else {
2533             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2534                                 ARMMMUIdx_S12NSE0, -1);
2535         }
2536     }
2537 }
2538
2539 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2540                                   uint64_t value)
2541 {
2542     /* Note that the 'ALL' scope must invalidate both stage 1 and
2543      * stage 2 translations, whereas most other scopes only invalidate
2544      * stage 1 translations.
2545      */
2546     ARMCPU *cpu = arm_env_get_cpu(env);
2547     CPUState *cs = CPU(cpu);
2548
2549     if (arm_is_secure_below_el3(env)) {
2550         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2551     } else {
2552         if (arm_feature(env, ARM_FEATURE_EL2)) {
2553             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2554                                 ARMMMUIdx_S2NS, -1);
2555         } else {
2556             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2557         }
2558     }
2559 }
2560
2561 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2562                                   uint64_t value)
2563 {
2564     ARMCPU *cpu = arm_env_get_cpu(env);
2565     CPUState *cs = CPU(cpu);
2566
2567     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2568 }
2569
2570 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2571                                   uint64_t value)
2572 {
2573     ARMCPU *cpu = arm_env_get_cpu(env);
2574     CPUState *cs = CPU(cpu);
2575
2576     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2577 }
2578
2579 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2580                                     uint64_t value)
2581 {
2582     /* Note that the 'ALL' scope must invalidate both stage 1 and
2583      * stage 2 translations, whereas most other scopes only invalidate
2584      * stage 1 translations.
2585      */
2586     bool sec = arm_is_secure_below_el3(env);
2587     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2588     CPUState *other_cs;
2589
2590     CPU_FOREACH(other_cs) {
2591         if (sec) {
2592             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2593         } else if (has_el2) {
2594             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2595                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2596         } else {
2597             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2598                                 ARMMMUIdx_S12NSE0, -1);
2599         }
2600     }
2601 }
2602
2603 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2604                                     uint64_t value)
2605 {
2606     CPUState *other_cs;
2607
2608     CPU_FOREACH(other_cs) {
2609         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2610     }
2611 }
2612
2613 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2614                                     uint64_t value)
2615 {
2616     CPUState *other_cs;
2617
2618     CPU_FOREACH(other_cs) {
2619         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2620     }
2621 }
2622
2623 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2624                                  uint64_t value)
2625 {
2626     /* Invalidate by VA, EL1&0 (AArch64 version).
2627      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2628      * since we don't support flush-for-specific-ASID-only or
2629      * flush-last-level-only.
2630      */
2631     ARMCPU *cpu = arm_env_get_cpu(env);
2632     CPUState *cs = CPU(cpu);
2633     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2634
2635     if (arm_is_secure_below_el3(env)) {
2636         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2637                                  ARMMMUIdx_S1SE0, -1);
2638     } else {
2639         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2640                                  ARMMMUIdx_S12NSE0, -1);
2641     }
2642 }
2643
2644 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2645                                  uint64_t value)
2646 {
2647     /* Invalidate by VA, EL2
2648      * Currently handles both VAE2 and VALE2, since we don't support
2649      * flush-last-level-only.
2650      */
2651     ARMCPU *cpu = arm_env_get_cpu(env);
2652     CPUState *cs = CPU(cpu);
2653     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2654
2655     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2656 }
2657
2658 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2659                                  uint64_t value)
2660 {
2661     /* Invalidate by VA, EL3
2662      * Currently handles both VAE3 and VALE3, since we don't support
2663      * flush-last-level-only.
2664      */
2665     ARMCPU *cpu = arm_env_get_cpu(env);
2666     CPUState *cs = CPU(cpu);
2667     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2668
2669     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2670 }
2671
2672 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2673                                    uint64_t value)
2674 {
2675     bool sec = arm_is_secure_below_el3(env);
2676     CPUState *other_cs;
2677     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2678
2679     CPU_FOREACH(other_cs) {
2680         if (sec) {
2681             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2682                                      ARMMMUIdx_S1SE0, -1);
2683         } else {
2684             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2685                                      ARMMMUIdx_S12NSE0, -1);
2686         }
2687     }
2688 }
2689
2690 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2691                                    uint64_t value)
2692 {
2693     CPUState *other_cs;
2694     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2695
2696     CPU_FOREACH(other_cs) {
2697         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2698     }
2699 }
2700
2701 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2702                                    uint64_t value)
2703 {
2704     CPUState *other_cs;
2705     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2706
2707     CPU_FOREACH(other_cs) {
2708         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2709     }
2710 }
2711
2712 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2713                                     uint64_t value)
2714 {
2715     /* Invalidate by IPA. This has to invalidate any structures that
2716      * contain only stage 2 translation information, but does not need
2717      * to apply to structures that contain combined stage 1 and stage 2
2718      * translation information.
2719      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2720      */
2721     ARMCPU *cpu = arm_env_get_cpu(env);
2722     CPUState *cs = CPU(cpu);
2723     uint64_t pageaddr;
2724
2725     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2726         return;
2727     }
2728
2729     pageaddr = sextract64(value << 12, 0, 48);
2730
2731     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2732 }
2733
2734 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2735                                       uint64_t value)
2736 {
2737     CPUState *other_cs;
2738     uint64_t pageaddr;
2739
2740     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2741         return;
2742     }
2743
2744     pageaddr = sextract64(value << 12, 0, 48);
2745
2746     CPU_FOREACH(other_cs) {
2747         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2748     }
2749 }
2750
2751 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2752 {
2753     /* We don't implement EL2, so the only control on DC ZVA is the
2754      * bit in the SCTLR which can prohibit access for EL0.
2755      */
2756     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2757         return CP_ACCESS_TRAP;
2758     }
2759     return CP_ACCESS_OK;
2760 }
2761
2762 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2763 {
2764     ARMCPU *cpu = arm_env_get_cpu(env);
2765     int dzp_bit = 1 << 4;
2766
2767     /* DZP indicates whether DC ZVA access is allowed */
2768     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2769         dzp_bit = 0;
2770     }
2771     return cpu->dcz_blocksize | dzp_bit;
2772 }
2773
2774 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2775 {
2776     if (!(env->pstate & PSTATE_SP)) {
2777         /* Access to SP_EL0 is undefined if it's being used as
2778          * the stack pointer.
2779          */
2780         return CP_ACCESS_TRAP_UNCATEGORIZED;
2781     }
2782     return CP_ACCESS_OK;
2783 }
2784
2785 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2786 {
2787     return env->pstate & PSTATE_SP;
2788 }
2789
2790 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2791 {
2792     update_spsel(env, val);
2793 }
2794
2795 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2796                         uint64_t value)
2797 {
2798     ARMCPU *cpu = arm_env_get_cpu(env);
2799
2800     if (raw_read(env, ri) == value) {
2801         /* Skip the TLB flush if nothing actually changed; Linux likes
2802          * to do a lot of pointless SCTLR writes.
2803          */
2804         return;
2805     }
2806
2807     raw_write(env, ri, value);
2808     /* ??? Lots of these bits are not implemented.  */
2809     /* This may enable/disable the MMU, so do a TLB flush.  */
2810     tlb_flush(CPU(cpu), 1);
2811 }
2812
2813 static const ARMCPRegInfo v8_cp_reginfo[] = {
2814     /* Minimal set of EL0-visible registers. This will need to be expanded
2815      * significantly for system emulation of AArch64 CPUs.
2816      */
2817     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2818       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2819       .access = PL0_RW, .type = ARM_CP_NZCV },
2820     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2821       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2822       .type = ARM_CP_NO_RAW,
2823       .access = PL0_RW, .accessfn = aa64_daif_access,
2824       .fieldoffset = offsetof(CPUARMState, daif),
2825       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2826     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2827       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2828       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2829     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2830       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2831       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2832     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2833       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2834       .access = PL0_R, .type = ARM_CP_NO_RAW,
2835       .readfn = aa64_dczid_read },
2836     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2837       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2838       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2839 #ifndef CONFIG_USER_ONLY
2840       /* Avoid overhead of an access check that always passes in user-mode */
2841       .accessfn = aa64_zva_access,
2842 #endif
2843     },
2844     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2845       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2846       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2847     /* Cache ops: all NOPs since we don't emulate caches */
2848     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2849       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2850       .access = PL1_W, .type = ARM_CP_NOP },
2851     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2852       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2853       .access = PL1_W, .type = ARM_CP_NOP },
2854     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2855       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2856       .access = PL0_W, .type = ARM_CP_NOP,
2857       .accessfn = aa64_cacheop_access },
2858     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2859       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2860       .access = PL1_W, .type = ARM_CP_NOP },
2861     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2862       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2863       .access = PL1_W, .type = ARM_CP_NOP },
2864     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2865       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2866       .access = PL0_W, .type = ARM_CP_NOP,
2867       .accessfn = aa64_cacheop_access },
2868     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2869       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2870       .access = PL1_W, .type = ARM_CP_NOP },
2871     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2872       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2873       .access = PL0_W, .type = ARM_CP_NOP,
2874       .accessfn = aa64_cacheop_access },
2875     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2876       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2877       .access = PL0_W, .type = ARM_CP_NOP,
2878       .accessfn = aa64_cacheop_access },
2879     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2880       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2881       .access = PL1_W, .type = ARM_CP_NOP },
2882     /* TLBI operations */
2883     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2884       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2885       .access = PL1_W, .type = ARM_CP_NO_RAW,
2886       .writefn = tlbi_aa64_vmalle1is_write },
2887     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2888       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2889       .access = PL1_W, .type = ARM_CP_NO_RAW,
2890       .writefn = tlbi_aa64_vae1is_write },
2891     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2892       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2893       .access = PL1_W, .type = ARM_CP_NO_RAW,
2894       .writefn = tlbi_aa64_vmalle1is_write },
2895     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2896       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2897       .access = PL1_W, .type = ARM_CP_NO_RAW,
2898       .writefn = tlbi_aa64_vae1is_write },
2899     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2900       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2901       .access = PL1_W, .type = ARM_CP_NO_RAW,
2902       .writefn = tlbi_aa64_vae1is_write },
2903     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2904       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2905       .access = PL1_W, .type = ARM_CP_NO_RAW,
2906       .writefn = tlbi_aa64_vae1is_write },
2907     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2908       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2909       .access = PL1_W, .type = ARM_CP_NO_RAW,
2910       .writefn = tlbi_aa64_vmalle1_write },
2911     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2912       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2913       .access = PL1_W, .type = ARM_CP_NO_RAW,
2914       .writefn = tlbi_aa64_vae1_write },
2915     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2916       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2917       .access = PL1_W, .type = ARM_CP_NO_RAW,
2918       .writefn = tlbi_aa64_vmalle1_write },
2919     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2920       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2921       .access = PL1_W, .type = ARM_CP_NO_RAW,
2922       .writefn = tlbi_aa64_vae1_write },
2923     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2924       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2925       .access = PL1_W, .type = ARM_CP_NO_RAW,
2926       .writefn = tlbi_aa64_vae1_write },
2927     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2928       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2929       .access = PL1_W, .type = ARM_CP_NO_RAW,
2930       .writefn = tlbi_aa64_vae1_write },
2931     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
2932       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
2933       .access = PL2_W, .type = ARM_CP_NO_RAW,
2934       .writefn = tlbi_aa64_ipas2e1is_write },
2935     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
2936       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
2937       .access = PL2_W, .type = ARM_CP_NO_RAW,
2938       .writefn = tlbi_aa64_ipas2e1is_write },
2939     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
2940       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
2941       .access = PL2_W, .type = ARM_CP_NO_RAW,
2942       .writefn = tlbi_aa64_alle1is_write },
2943     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
2944       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
2945       .access = PL2_W, .type = ARM_CP_NO_RAW,
2946       .writefn = tlbi_aa64_alle1is_write },
2947     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
2948       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
2949       .access = PL2_W, .type = ARM_CP_NO_RAW,
2950       .writefn = tlbi_aa64_ipas2e1_write },
2951     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
2952       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
2953       .access = PL2_W, .type = ARM_CP_NO_RAW,
2954       .writefn = tlbi_aa64_ipas2e1_write },
2955     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
2956       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
2957       .access = PL2_W, .type = ARM_CP_NO_RAW,
2958       .writefn = tlbi_aa64_alle1_write },
2959     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
2960       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
2961       .access = PL2_W, .type = ARM_CP_NO_RAW,
2962       .writefn = tlbi_aa64_alle1is_write },
2963 #ifndef CONFIG_USER_ONLY
2964     /* 64 bit address translation operations */
2965     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2966       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2967       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2968     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2969       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2970       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2971     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2972       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2973       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2974     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2975       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2976       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2977     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
2978       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 4,
2979       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2980     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
2981       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 5,
2982       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2983     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
2984       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
2985       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2986     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
2987       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 7,
2988       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2989     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
2990     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
2991       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
2992       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2993     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
2994       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
2995       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2996 #endif
2997     /* TLB invalidate last level of translation table walk */
2998     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2999       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3000     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3001       .type = ARM_CP_NO_RAW, .access = PL1_W,
3002       .writefn = tlbimvaa_is_write },
3003     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3004       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3005     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3006       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3007     /* 32 bit cache operations */
3008     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3009       .type = ARM_CP_NOP, .access = PL1_W },
3010     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3011       .type = ARM_CP_NOP, .access = PL1_W },
3012     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3013       .type = ARM_CP_NOP, .access = PL1_W },
3014     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3015       .type = ARM_CP_NOP, .access = PL1_W },
3016     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3017       .type = ARM_CP_NOP, .access = PL1_W },
3018     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3019       .type = ARM_CP_NOP, .access = PL1_W },
3020     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3021       .type = ARM_CP_NOP, .access = PL1_W },
3022     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3023       .type = ARM_CP_NOP, .access = PL1_W },
3024     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3025       .type = ARM_CP_NOP, .access = PL1_W },
3026     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3027       .type = ARM_CP_NOP, .access = PL1_W },
3028     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3029       .type = ARM_CP_NOP, .access = PL1_W },
3030     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3031       .type = ARM_CP_NOP, .access = PL1_W },
3032     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3033       .type = ARM_CP_NOP, .access = PL1_W },
3034     /* MMU Domain access control / MPU write buffer control */
3035     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3036       .access = PL1_RW, .resetvalue = 0,
3037       .writefn = dacr_write, .raw_writefn = raw_write,
3038       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3039                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3040     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3041       .type = ARM_CP_ALIAS,
3042       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3043       .access = PL1_RW,
3044       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3045     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3046       .type = ARM_CP_ALIAS,
3047       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3048       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
3049     /* We rely on the access checks not allowing the guest to write to the
3050      * state field when SPSel indicates that it's being used as the stack
3051      * pointer.
3052      */
3053     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3054       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3055       .access = PL1_RW, .accessfn = sp_el0_access,
3056       .type = ARM_CP_ALIAS,
3057       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3058     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3059       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3060       .access = PL2_RW, .type = ARM_CP_ALIAS,
3061       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3062     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3063       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3064       .type = ARM_CP_NO_RAW,
3065       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3066     REGINFO_SENTINEL
3067 };
3068
3069 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3070 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3071     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3072       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3073       .access = PL2_RW,
3074       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3075     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3076       .type = ARM_CP_NO_RAW,
3077       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3078       .access = PL2_RW,
3079       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3080     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3081       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3082       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3083     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3084       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3085       .access = PL2_RW, .type = ARM_CP_CONST,
3086       .resetvalue = 0 },
3087     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3088       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3089       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3090     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3091       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3092       .access = PL2_RW, .type = ARM_CP_CONST,
3093       .resetvalue = 0 },
3094     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3095       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3096       .access = PL2_RW, .type = ARM_CP_CONST,
3097       .resetvalue = 0 },
3098     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3099       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3100       .access = PL2_RW, .type = ARM_CP_CONST,
3101       .resetvalue = 0 },
3102     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3103       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3104       .access = PL2_RW, .type = ARM_CP_CONST,
3105       .resetvalue = 0 },
3106     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3107       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3108       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3109     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3110       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3111       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3112     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3113       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3114       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3115     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3116       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3117       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3118     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3119       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3120       .resetvalue = 0 },
3121     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3122       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3123       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3124     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3125       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3126       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3127     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3128       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3129       .resetvalue = 0 },
3130     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3131       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3132       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3133     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3134       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3135       .resetvalue = 0 },
3136     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3137       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3138       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3139     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3140       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3141       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3142     REGINFO_SENTINEL
3143 };
3144
3145 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3146 {
3147     ARMCPU *cpu = arm_env_get_cpu(env);
3148     uint64_t valid_mask = HCR_MASK;
3149
3150     if (arm_feature(env, ARM_FEATURE_EL3)) {
3151         valid_mask &= ~HCR_HCD;
3152     } else {
3153         valid_mask &= ~HCR_TSC;
3154     }
3155
3156     /* Clear RES0 bits.  */
3157     value &= valid_mask;
3158
3159     /* These bits change the MMU setup:
3160      * HCR_VM enables stage 2 translation
3161      * HCR_PTW forbids certain page-table setups
3162      * HCR_DC Disables stage1 and enables stage2 translation
3163      */
3164     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3165         tlb_flush(CPU(cpu), 1);
3166     }
3167     raw_write(env, ri, value);
3168 }
3169
3170 static const ARMCPRegInfo el2_cp_reginfo[] = {
3171     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3172       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3173       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3174       .writefn = hcr_write },
3175     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3176       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3177       .access = PL2_RW, .resetvalue = 0,
3178       .writefn = dacr_write, .raw_writefn = raw_write,
3179       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3180     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3181       .type = ARM_CP_ALIAS,
3182       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3183       .access = PL2_RW,
3184       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3185     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3186       .type = ARM_CP_ALIAS,
3187       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3188       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3189     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3190       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3191       .access = PL2_RW, .resetvalue = 0,
3192       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3193     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3194       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3195       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3196     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3197       .type = ARM_CP_ALIAS,
3198       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3199       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
3200     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3201       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3202       .access = PL2_RW, .writefn = vbar_write,
3203       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3204       .resetvalue = 0 },
3205     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3207       .access = PL3_RW, .type = ARM_CP_ALIAS,
3208       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3209     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3210       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3211       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3212       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3213     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3214       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3215       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3216       .resetvalue = 0 },
3217     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3218       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3219       .access = PL2_RW, .type = ARM_CP_ALIAS,
3220       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3221     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3222       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3223       .access = PL2_RW, .type = ARM_CP_CONST,
3224       .resetvalue = 0 },
3225     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3226     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3227       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3228       .access = PL2_RW, .type = ARM_CP_CONST,
3229       .resetvalue = 0 },
3230     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3231       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3232       .access = PL2_RW, .type = ARM_CP_CONST,
3233       .resetvalue = 0 },
3234     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3235       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3236       .access = PL2_RW, .type = ARM_CP_CONST,
3237       .resetvalue = 0 },
3238     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3239       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3240       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3241       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3242       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3243     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3244       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3245       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3246       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3247     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3248       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3249       .access = PL2_RW, .resetvalue = 0,
3250       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3251     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3252       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3253       .access = PL2_RW, .resetvalue = 0,
3254       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3255     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3256       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3257       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3258     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3259       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3260       .type = ARM_CP_NO_RAW, .access = PL2_W,
3261       .writefn = tlbi_aa64_alle2_write },
3262     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3263       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3264       .type = ARM_CP_NO_RAW, .access = PL2_W,
3265       .writefn = tlbi_aa64_vae2_write },
3266     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3267       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3268       .access = PL2_W, .type = ARM_CP_NO_RAW,
3269       .writefn = tlbi_aa64_vae2_write },
3270     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3271       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3272       .access = PL2_W, .type = ARM_CP_NO_RAW,
3273       .writefn = tlbi_aa64_alle2is_write },
3274     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3275       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3276       .type = ARM_CP_NO_RAW, .access = PL2_W,
3277       .writefn = tlbi_aa64_vae2is_write },
3278     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3279       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3280       .access = PL2_W, .type = ARM_CP_NO_RAW,
3281       .writefn = tlbi_aa64_vae2is_write },
3282 #ifndef CONFIG_USER_ONLY
3283     /* Unlike the other EL2-related AT operations, these must
3284      * UNDEF from EL3 if EL2 is not implemented, which is why we
3285      * define them here rather than with the rest of the AT ops.
3286      */
3287     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3288       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3289       .access = PL2_W, .accessfn = at_s1e2_access,
3290       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3291     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3292       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3293       .access = PL2_W, .accessfn = at_s1e2_access,
3294       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3295     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3296      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3297      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3298      * to behave as if SCR.NS was 1.
3299      */
3300     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3301       .access = PL2_W,
3302       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3303     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3304       .access = PL2_W,
3305       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3306     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3307       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3308       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3309        * reset values as IMPDEF. We choose to reset to 3 to comply with
3310        * both ARMv7 and ARMv8.
3311        */
3312       .access = PL2_RW, .resetvalue = 3,
3313       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3314     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3315       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3316       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3317       .writefn = gt_cntvoff_write,
3318       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3319     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3320       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3321       .writefn = gt_cntvoff_write,
3322       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3323     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3324       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3325       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3326       .type = ARM_CP_IO, .access = PL2_RW,
3327       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3328     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3329       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3330       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3331       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3332     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3333       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3334       .type = ARM_CP_IO, .access = PL2_RW,
3335       .resetfn = gt_hyp_timer_reset,
3336       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3337     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3338       .type = ARM_CP_IO,
3339       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3340       .access = PL2_RW,
3341       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3342       .resetvalue = 0,
3343       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3344 #endif
3345     REGINFO_SENTINEL
3346 };
3347
3348 static const ARMCPRegInfo el3_cp_reginfo[] = {
3349     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3350       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3351       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3352       .resetvalue = 0, .writefn = scr_write },
3353     { .name = "SCR",  .type = ARM_CP_ALIAS,
3354       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3355       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3356       .writefn = scr_write },
3357     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3358       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3359       .access = PL3_RW, .resetvalue = 0,
3360       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3361     { .name = "SDER",
3362       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3363       .access = PL3_RW, .resetvalue = 0,
3364       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3365       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3366     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
3367       .access = PL3_W | PL1_R, .resetvalue = 0,
3368       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
3369     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3370       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
3371       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3372     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3373       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3374       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3375       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3376       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3377     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3378       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3379       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3380       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3381     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3382       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3383       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3384       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3385       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3386     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3387       .type = ARM_CP_ALIAS,
3388       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3389       .access = PL3_RW,
3390       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3391     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3392       .type = ARM_CP_ALIAS,
3393       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3394       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3395     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3396       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3397       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3398     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3399       .type = ARM_CP_ALIAS,
3400       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3401       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
3402     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3403       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3404       .access = PL3_RW, .writefn = vbar_write,
3405       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3406       .resetvalue = 0 },
3407     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3408       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3409       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3410       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3411     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3412       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3413       .access = PL3_RW, .resetvalue = 0,
3414       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3415     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3416       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3417       .access = PL3_RW, .type = ARM_CP_CONST,
3418       .resetvalue = 0 },
3419     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3420       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3421       .access = PL3_RW, .type = ARM_CP_CONST,
3422       .resetvalue = 0 },
3423     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3424       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3425       .access = PL3_RW, .type = ARM_CP_CONST,
3426       .resetvalue = 0 },
3427     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3428       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3429       .access = PL3_W, .type = ARM_CP_NO_RAW,
3430       .writefn = tlbi_aa64_alle3is_write },
3431     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3432       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3433       .access = PL3_W, .type = ARM_CP_NO_RAW,
3434       .writefn = tlbi_aa64_vae3is_write },
3435     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3436       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3437       .access = PL3_W, .type = ARM_CP_NO_RAW,
3438       .writefn = tlbi_aa64_vae3is_write },
3439     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3440       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3441       .access = PL3_W, .type = ARM_CP_NO_RAW,
3442       .writefn = tlbi_aa64_alle3_write },
3443     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3444       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3445       .access = PL3_W, .type = ARM_CP_NO_RAW,
3446       .writefn = tlbi_aa64_vae3_write },
3447     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3448       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3449       .access = PL3_W, .type = ARM_CP_NO_RAW,
3450       .writefn = tlbi_aa64_vae3_write },
3451     REGINFO_SENTINEL
3452 };
3453
3454 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
3455 {
3456     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3457      * but the AArch32 CTR has its own reginfo struct)
3458      */
3459     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3460         return CP_ACCESS_TRAP;
3461     }
3462     return CP_ACCESS_OK;
3463 }
3464
3465 static const ARMCPRegInfo debug_cp_reginfo[] = {
3466     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3467      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3468      * unlike DBGDRAR it is never accessible from EL0.
3469      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3470      * accessor.
3471      */
3472     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3473       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3474     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3475       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3476       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3477     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3478       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3479     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3480     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3481       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3482       .access = PL1_RW,
3483       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3484       .resetvalue = 0 },
3485     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3486      * We don't implement the configurable EL0 access.
3487      */
3488     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3489       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3490       .type = ARM_CP_ALIAS,
3491       .access = PL1_R,
3492       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3493     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
3494     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3495       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3496       .access = PL1_W, .type = ARM_CP_NOP },
3497     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3498     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3499       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3500       .access = PL1_RW, .type = ARM_CP_NOP },
3501     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3502      * implement vector catch debug events yet.
3503      */
3504     { .name = "DBGVCR",
3505       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3506       .access = PL1_RW, .type = ARM_CP_NOP },
3507     REGINFO_SENTINEL
3508 };
3509
3510 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3511     /* 64 bit access versions of the (dummy) debug registers */
3512     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3513       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3514     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3515       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3516     REGINFO_SENTINEL
3517 };
3518
3519 void hw_watchpoint_update(ARMCPU *cpu, int n)
3520 {
3521     CPUARMState *env = &cpu->env;
3522     vaddr len = 0;
3523     vaddr wvr = env->cp15.dbgwvr[n];
3524     uint64_t wcr = env->cp15.dbgwcr[n];
3525     int mask;
3526     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3527
3528     if (env->cpu_watchpoint[n]) {
3529         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3530         env->cpu_watchpoint[n] = NULL;
3531     }
3532
3533     if (!extract64(wcr, 0, 1)) {
3534         /* E bit clear : watchpoint disabled */
3535         return;
3536     }
3537
3538     switch (extract64(wcr, 3, 2)) {
3539     case 0:
3540         /* LSC 00 is reserved and must behave as if the wp is disabled */
3541         return;
3542     case 1:
3543         flags |= BP_MEM_READ;
3544         break;
3545     case 2:
3546         flags |= BP_MEM_WRITE;
3547         break;
3548     case 3:
3549         flags |= BP_MEM_ACCESS;
3550         break;
3551     }
3552
3553     /* Attempts to use both MASK and BAS fields simultaneously are
3554      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3555      * thus generating a watchpoint for every byte in the masked region.
3556      */
3557     mask = extract64(wcr, 24, 4);
3558     if (mask == 1 || mask == 2) {
3559         /* Reserved values of MASK; we must act as if the mask value was
3560          * some non-reserved value, or as if the watchpoint were disabled.
3561          * We choose the latter.
3562          */
3563         return;
3564     } else if (mask) {
3565         /* Watchpoint covers an aligned area up to 2GB in size */
3566         len = 1ULL << mask;
3567         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3568          * whether the watchpoint fires when the unmasked bits match; we opt
3569          * to generate the exceptions.
3570          */
3571         wvr &= ~(len - 1);
3572     } else {
3573         /* Watchpoint covers bytes defined by the byte address select bits */
3574         int bas = extract64(wcr, 5, 8);
3575         int basstart;
3576
3577         if (bas == 0) {
3578             /* This must act as if the watchpoint is disabled */
3579             return;
3580         }
3581
3582         if (extract64(wvr, 2, 1)) {
3583             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3584              * ignored, and BAS[3:0] define which bytes to watch.
3585              */
3586             bas &= 0xf;
3587         }
3588         /* The BAS bits are supposed to be programmed to indicate a contiguous
3589          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3590          * we fire for each byte in the word/doubleword addressed by the WVR.
3591          * We choose to ignore any non-zero bits after the first range of 1s.
3592          */
3593         basstart = ctz32(bas);
3594         len = cto32(bas >> basstart);
3595         wvr += basstart;
3596     }
3597
3598     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3599                           &env->cpu_watchpoint[n]);
3600 }
3601
3602 void hw_watchpoint_update_all(ARMCPU *cpu)
3603 {
3604     int i;
3605     CPUARMState *env = &cpu->env;
3606
3607     /* Completely clear out existing QEMU watchpoints and our array, to
3608      * avoid possible stale entries following migration load.
3609      */
3610     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3611     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3612
3613     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3614         hw_watchpoint_update(cpu, i);
3615     }
3616 }
3617
3618 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3619                          uint64_t value)
3620 {
3621     ARMCPU *cpu = arm_env_get_cpu(env);
3622     int i = ri->crm;
3623
3624     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3625      * register reads and behaves as if values written are sign extended.
3626      * Bits [1:0] are RES0.
3627      */
3628     value = sextract64(value, 0, 49) & ~3ULL;
3629
3630     raw_write(env, ri, value);
3631     hw_watchpoint_update(cpu, i);
3632 }
3633
3634 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3635                          uint64_t value)
3636 {
3637     ARMCPU *cpu = arm_env_get_cpu(env);
3638     int i = ri->crm;
3639
3640     raw_write(env, ri, value);
3641     hw_watchpoint_update(cpu, i);
3642 }
3643
3644 void hw_breakpoint_update(ARMCPU *cpu, int n)
3645 {
3646     CPUARMState *env = &cpu->env;
3647     uint64_t bvr = env->cp15.dbgbvr[n];
3648     uint64_t bcr = env->cp15.dbgbcr[n];
3649     vaddr addr;
3650     int bt;
3651     int flags = BP_CPU;
3652
3653     if (env->cpu_breakpoint[n]) {
3654         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3655         env->cpu_breakpoint[n] = NULL;
3656     }
3657
3658     if (!extract64(bcr, 0, 1)) {
3659         /* E bit clear : watchpoint disabled */
3660         return;
3661     }
3662
3663     bt = extract64(bcr, 20, 4);
3664
3665     switch (bt) {
3666     case 4: /* unlinked address mismatch (reserved if AArch64) */
3667     case 5: /* linked address mismatch (reserved if AArch64) */
3668         qemu_log_mask(LOG_UNIMP,
3669                       "arm: address mismatch breakpoint types not implemented");
3670         return;
3671     case 0: /* unlinked address match */
3672     case 1: /* linked address match */
3673     {
3674         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3675          * we behave as if the register was sign extended. Bits [1:0] are
3676          * RES0. The BAS field is used to allow setting breakpoints on 16
3677          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3678          * a bp will fire if the addresses covered by the bp and the addresses
3679          * covered by the insn overlap but the insn doesn't start at the
3680          * start of the bp address range. We choose to require the insn and
3681          * the bp to have the same address. The constraints on writing to
3682          * BAS enforced in dbgbcr_write mean we have only four cases:
3683          *  0b0000  => no breakpoint
3684          *  0b0011  => breakpoint on addr
3685          *  0b1100  => breakpoint on addr + 2
3686          *  0b1111  => breakpoint on addr
3687          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3688          */
3689         int bas = extract64(bcr, 5, 4);
3690         addr = sextract64(bvr, 0, 49) & ~3ULL;
3691         if (bas == 0) {
3692             return;
3693         }
3694         if (bas == 0xc) {
3695             addr += 2;
3696         }
3697         break;
3698     }
3699     case 2: /* unlinked context ID match */
3700     case 8: /* unlinked VMID match (reserved if no EL2) */
3701     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3702         qemu_log_mask(LOG_UNIMP,
3703                       "arm: unlinked context breakpoint types not implemented");
3704         return;
3705     case 9: /* linked VMID match (reserved if no EL2) */
3706     case 11: /* linked context ID and VMID match (reserved if no EL2) */
3707     case 3: /* linked context ID match */
3708     default:
3709         /* We must generate no events for Linked context matches (unless
3710          * they are linked to by some other bp/wp, which is handled in
3711          * updates for the linking bp/wp). We choose to also generate no events
3712          * for reserved values.
3713          */
3714         return;
3715     }
3716
3717     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3718 }
3719
3720 void hw_breakpoint_update_all(ARMCPU *cpu)
3721 {
3722     int i;
3723     CPUARMState *env = &cpu->env;
3724
3725     /* Completely clear out existing QEMU breakpoints and our array, to
3726      * avoid possible stale entries following migration load.
3727      */
3728     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3729     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3730
3731     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3732         hw_breakpoint_update(cpu, i);
3733     }
3734 }
3735
3736 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3737                          uint64_t value)
3738 {
3739     ARMCPU *cpu = arm_env_get_cpu(env);
3740     int i = ri->crm;
3741
3742     raw_write(env, ri, value);
3743     hw_breakpoint_update(cpu, i);
3744 }
3745
3746 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3747                          uint64_t value)
3748 {
3749     ARMCPU *cpu = arm_env_get_cpu(env);
3750     int i = ri->crm;
3751
3752     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3753      * copy of BAS[0].
3754      */
3755     value = deposit64(value, 6, 1, extract64(value, 5, 1));
3756     value = deposit64(value, 8, 1, extract64(value, 7, 1));
3757
3758     raw_write(env, ri, value);
3759     hw_breakpoint_update(cpu, i);
3760 }
3761
3762 static void define_debug_regs(ARMCPU *cpu)
3763 {
3764     /* Define v7 and v8 architectural debug registers.
3765      * These are just dummy implementations for now.
3766      */
3767     int i;
3768     int wrps, brps, ctx_cmps;
3769     ARMCPRegInfo dbgdidr = {
3770         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3771         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3772     };
3773
3774     /* Note that all these register fields hold "number of Xs minus 1". */
3775     brps = extract32(cpu->dbgdidr, 24, 4);
3776     wrps = extract32(cpu->dbgdidr, 28, 4);
3777     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3778
3779     assert(ctx_cmps <= brps);
3780
3781     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3782      * of the debug registers such as number of breakpoints;
3783      * check that if they both exist then they agree.
3784      */
3785     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3786         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3787         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3788         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3789     }
3790
3791     define_one_arm_cp_reg(cpu, &dbgdidr);
3792     define_arm_cp_regs(cpu, debug_cp_reginfo);
3793
3794     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3795         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3796     }
3797
3798     for (i = 0; i < brps + 1; i++) {
3799         ARMCPRegInfo dbgregs[] = {
3800             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3801               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3802               .access = PL1_RW,
3803               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3804               .writefn = dbgbvr_write, .raw_writefn = raw_write
3805             },
3806             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3807               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3808               .access = PL1_RW,
3809               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3810               .writefn = dbgbcr_write, .raw_writefn = raw_write
3811             },
3812             REGINFO_SENTINEL
3813         };
3814         define_arm_cp_regs(cpu, dbgregs);
3815     }
3816
3817     for (i = 0; i < wrps + 1; i++) {
3818         ARMCPRegInfo dbgregs[] = {
3819             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
3820               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
3821               .access = PL1_RW,
3822               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
3823               .writefn = dbgwvr_write, .raw_writefn = raw_write
3824             },
3825             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
3826               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
3827               .access = PL1_RW,
3828               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
3829               .writefn = dbgwcr_write, .raw_writefn = raw_write
3830             },
3831             REGINFO_SENTINEL
3832         };
3833         define_arm_cp_regs(cpu, dbgregs);
3834     }
3835 }
3836
3837 void register_cp_regs_for_features(ARMCPU *cpu)
3838 {
3839     /* Register all the coprocessor registers based on feature bits */
3840     CPUARMState *env = &cpu->env;
3841     if (arm_feature(env, ARM_FEATURE_M)) {
3842         /* M profile has no coprocessor registers */
3843         return;
3844     }
3845
3846     define_arm_cp_regs(cpu, cp_reginfo);
3847     if (!arm_feature(env, ARM_FEATURE_V8)) {
3848         /* Must go early as it is full of wildcards that may be
3849          * overridden by later definitions.
3850          */
3851         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
3852     }
3853
3854     if (arm_feature(env, ARM_FEATURE_V6)) {
3855         /* The ID registers all have impdef reset values */
3856         ARMCPRegInfo v6_idregs[] = {
3857             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
3858               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3859               .access = PL1_R, .type = ARM_CP_CONST,
3860               .resetvalue = cpu->id_pfr0 },
3861             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
3862               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
3863               .access = PL1_R, .type = ARM_CP_CONST,
3864               .resetvalue = cpu->id_pfr1 },
3865             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
3866               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
3867               .access = PL1_R, .type = ARM_CP_CONST,
3868               .resetvalue = cpu->id_dfr0 },
3869             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
3870               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
3871               .access = PL1_R, .type = ARM_CP_CONST,
3872               .resetvalue = cpu->id_afr0 },
3873             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
3874               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
3875               .access = PL1_R, .type = ARM_CP_CONST,
3876               .resetvalue = cpu->id_mmfr0 },
3877             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
3878               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
3879               .access = PL1_R, .type = ARM_CP_CONST,
3880               .resetvalue = cpu->id_mmfr1 },
3881             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
3882               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
3883               .access = PL1_R, .type = ARM_CP_CONST,
3884               .resetvalue = cpu->id_mmfr2 },
3885             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
3886               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
3887               .access = PL1_R, .type = ARM_CP_CONST,
3888               .resetvalue = cpu->id_mmfr3 },
3889             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
3890               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
3891               .access = PL1_R, .type = ARM_CP_CONST,
3892               .resetvalue = cpu->id_isar0 },
3893             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
3894               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
3895               .access = PL1_R, .type = ARM_CP_CONST,
3896               .resetvalue = cpu->id_isar1 },
3897             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
3898               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3899               .access = PL1_R, .type = ARM_CP_CONST,
3900               .resetvalue = cpu->id_isar2 },
3901             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
3902               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
3903               .access = PL1_R, .type = ARM_CP_CONST,
3904               .resetvalue = cpu->id_isar3 },
3905             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
3906               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
3907               .access = PL1_R, .type = ARM_CP_CONST,
3908               .resetvalue = cpu->id_isar4 },
3909             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
3910               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
3911               .access = PL1_R, .type = ARM_CP_CONST,
3912               .resetvalue = cpu->id_isar5 },
3913             /* 6..7 are as yet unallocated and must RAZ */
3914             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
3915               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
3916               .resetvalue = 0 },
3917             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
3918               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
3919               .resetvalue = 0 },
3920             REGINFO_SENTINEL
3921         };
3922         define_arm_cp_regs(cpu, v6_idregs);
3923         define_arm_cp_regs(cpu, v6_cp_reginfo);
3924     } else {
3925         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
3926     }
3927     if (arm_feature(env, ARM_FEATURE_V6K)) {
3928         define_arm_cp_regs(cpu, v6k_cp_reginfo);
3929     }
3930     if (arm_feature(env, ARM_FEATURE_V7MP) &&
3931         !arm_feature(env, ARM_FEATURE_MPU)) {
3932         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
3933     }
3934     if (arm_feature(env, ARM_FEATURE_V7)) {
3935         /* v7 performance monitor control register: same implementor
3936          * field as main ID register, and we implement only the cycle
3937          * count register.
3938          */
3939 #ifndef CONFIG_USER_ONLY
3940         ARMCPRegInfo pmcr = {
3941             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
3942             .access = PL0_RW,
3943             .type = ARM_CP_IO | ARM_CP_ALIAS,
3944             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
3945             .accessfn = pmreg_access, .writefn = pmcr_write,
3946             .raw_writefn = raw_write,
3947         };
3948         ARMCPRegInfo pmcr64 = {
3949             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
3950             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
3951             .access = PL0_RW, .accessfn = pmreg_access,
3952             .type = ARM_CP_IO,
3953             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
3954             .resetvalue = cpu->midr & 0xff000000,
3955             .writefn = pmcr_write, .raw_writefn = raw_write,
3956         };
3957         define_one_arm_cp_reg(cpu, &pmcr);
3958         define_one_arm_cp_reg(cpu, &pmcr64);
3959 #endif
3960         ARMCPRegInfo clidr = {
3961             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
3962             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
3963             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
3964         };
3965         define_one_arm_cp_reg(cpu, &clidr);
3966         define_arm_cp_regs(cpu, v7_cp_reginfo);
3967         define_debug_regs(cpu);
3968     } else {
3969         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
3970     }
3971     if (arm_feature(env, ARM_FEATURE_V8)) {
3972         /* AArch64 ID registers, which all have impdef reset values */
3973         ARMCPRegInfo v8_idregs[] = {
3974             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
3975               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
3976               .access = PL1_R, .type = ARM_CP_CONST,
3977               .resetvalue = cpu->id_aa64pfr0 },
3978             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
3979               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
3980               .access = PL1_R, .type = ARM_CP_CONST,
3981               .resetvalue = cpu->id_aa64pfr1},
3982             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
3983               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
3984               .access = PL1_R, .type = ARM_CP_CONST,
3985               /* We mask out the PMUVer field, because we don't currently
3986                * implement the PMU. Not advertising it prevents the guest
3987                * from trying to use it and getting UNDEFs on registers we
3988                * don't implement.
3989                */
3990               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
3991             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
3992               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
3993               .access = PL1_R, .type = ARM_CP_CONST,
3994               .resetvalue = cpu->id_aa64dfr1 },
3995             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
3996               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
3997               .access = PL1_R, .type = ARM_CP_CONST,
3998               .resetvalue = cpu->id_aa64afr0 },
3999             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4000               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4001               .access = PL1_R, .type = ARM_CP_CONST,
4002               .resetvalue = cpu->id_aa64afr1 },
4003             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4004               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4005               .access = PL1_R, .type = ARM_CP_CONST,
4006               .resetvalue = cpu->id_aa64isar0 },
4007             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4008               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4009               .access = PL1_R, .type = ARM_CP_CONST,
4010               .resetvalue = cpu->id_aa64isar1 },
4011             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4012               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4013               .access = PL1_R, .type = ARM_CP_CONST,
4014               .resetvalue = cpu->id_aa64mmfr0 },
4015             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4016               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4017               .access = PL1_R, .type = ARM_CP_CONST,
4018               .resetvalue = cpu->id_aa64mmfr1 },
4019             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4020               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4021               .access = PL1_R, .type = ARM_CP_CONST,
4022               .resetvalue = cpu->mvfr0 },
4023             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4024               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4025               .access = PL1_R, .type = ARM_CP_CONST,
4026               .resetvalue = cpu->mvfr1 },
4027             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4028               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4029               .access = PL1_R, .type = ARM_CP_CONST,
4030               .resetvalue = cpu->mvfr2 },
4031             REGINFO_SENTINEL
4032         };
4033         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4034         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4035             !arm_feature(env, ARM_FEATURE_EL2)) {
4036             ARMCPRegInfo rvbar = {
4037                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4038                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4039                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4040             };
4041             define_one_arm_cp_reg(cpu, &rvbar);
4042         }
4043         define_arm_cp_regs(cpu, v8_idregs);
4044         define_arm_cp_regs(cpu, v8_cp_reginfo);
4045     }
4046     if (arm_feature(env, ARM_FEATURE_EL2)) {
4047         define_arm_cp_regs(cpu, el2_cp_reginfo);
4048         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4049         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4050             ARMCPRegInfo rvbar = {
4051                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4052                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4053                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4054             };
4055             define_one_arm_cp_reg(cpu, &rvbar);
4056         }
4057     } else {
4058         /* If EL2 is missing but higher ELs are enabled, we need to
4059          * register the no_el2 reginfos.
4060          */
4061         if (arm_feature(env, ARM_FEATURE_EL3)) {
4062             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4063         }
4064     }
4065     if (arm_feature(env, ARM_FEATURE_EL3)) {
4066         define_arm_cp_regs(cpu, el3_cp_reginfo);
4067         ARMCPRegInfo rvbar = {
4068             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4069             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4070             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4071         };
4072         define_one_arm_cp_reg(cpu, &rvbar);
4073     }
4074     if (arm_feature(env, ARM_FEATURE_MPU)) {
4075         if (arm_feature(env, ARM_FEATURE_V6)) {
4076             /* PMSAv6 not implemented */
4077             assert(arm_feature(env, ARM_FEATURE_V7));
4078             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4079             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4080         } else {
4081             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4082         }
4083     } else {
4084         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4085         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4086     }
4087     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4088         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4089     }
4090     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4091         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4092     }
4093     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4094         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4095     }
4096     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4097         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4098     }
4099     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4100         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4101     }
4102     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4103         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4104     }
4105     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4106         define_arm_cp_regs(cpu, omap_cp_reginfo);
4107     }
4108     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4109         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4110     }
4111     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4112         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4113     }
4114     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4115         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4116     }
4117     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4118         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4119     }
4120     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4121      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4122      * be read-only (ie write causes UNDEF exception).
4123      */
4124     {
4125         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4126             /* Pre-v8 MIDR space.
4127              * Note that the MIDR isn't a simple constant register because
4128              * of the TI925 behaviour where writes to another register can
4129              * cause the MIDR value to change.
4130              *
4131              * Unimplemented registers in the c15 0 0 0 space default to
4132              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4133              * and friends override accordingly.
4134              */
4135             { .name = "MIDR",
4136               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4137               .access = PL1_R, .resetvalue = cpu->midr,
4138               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4139               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4140               .type = ARM_CP_OVERRIDE },
4141             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4142             { .name = "DUMMY",
4143               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4144               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4145             { .name = "DUMMY",
4146               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4147               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4148             { .name = "DUMMY",
4149               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4150               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4151             { .name = "DUMMY",
4152               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4153               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4154             { .name = "DUMMY",
4155               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4156               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4157             REGINFO_SENTINEL
4158         };
4159         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4160             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4161               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4162               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
4163             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4164             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4165               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4166               .access = PL1_R, .resetvalue = cpu->midr },
4167             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4168               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4169               .access = PL1_R, .resetvalue = cpu->midr },
4170             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4171               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4172               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4173             REGINFO_SENTINEL
4174         };
4175         ARMCPRegInfo id_cp_reginfo[] = {
4176             /* These are common to v8 and pre-v8 */
4177             { .name = "CTR",
4178               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4179               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4180             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4181               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4182               .access = PL0_R, .accessfn = ctr_el0_access,
4183               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4184             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4185             { .name = "TCMTR",
4186               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4187               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4188             REGINFO_SENTINEL
4189         };
4190         /* TLBTR is specific to VMSA */
4191         ARMCPRegInfo id_tlbtr_reginfo = {
4192               .name = "TLBTR",
4193               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4194               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4195         };
4196         /* MPUIR is specific to PMSA V6+ */
4197         ARMCPRegInfo id_mpuir_reginfo = {
4198               .name = "MPUIR",
4199               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4200               .access = PL1_R, .type = ARM_CP_CONST,
4201               .resetvalue = cpu->pmsav7_dregion << 8
4202         };
4203         ARMCPRegInfo crn0_wi_reginfo = {
4204             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4205             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4206             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4207         };
4208         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4209             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4210             ARMCPRegInfo *r;
4211             /* Register the blanket "writes ignored" value first to cover the
4212              * whole space. Then update the specific ID registers to allow write
4213              * access, so that they ignore writes rather than causing them to
4214              * UNDEF.
4215              */
4216             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4217             for (r = id_pre_v8_midr_cp_reginfo;
4218                  r->type != ARM_CP_SENTINEL; r++) {
4219                 r->access = PL1_RW;
4220             }
4221             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4222                 r->access = PL1_RW;
4223             }
4224             id_tlbtr_reginfo.access = PL1_RW;
4225             id_tlbtr_reginfo.access = PL1_RW;
4226         }
4227         if (arm_feature(env, ARM_FEATURE_V8)) {
4228             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4229         } else {
4230             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4231         }
4232         define_arm_cp_regs(cpu, id_cp_reginfo);
4233         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4234             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4235         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4236             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4237         }
4238     }
4239
4240     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4241         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4242     }
4243
4244     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4245         ARMCPRegInfo auxcr_reginfo[] = {
4246             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4247               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4248               .access = PL1_RW, .type = ARM_CP_CONST,
4249               .resetvalue = cpu->reset_auxcr },
4250             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4251               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4252               .access = PL2_RW, .type = ARM_CP_CONST,
4253               .resetvalue = 0 },
4254             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4255               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4256               .access = PL3_RW, .type = ARM_CP_CONST,
4257               .resetvalue = 0 },
4258             REGINFO_SENTINEL
4259         };
4260         define_arm_cp_regs(cpu, auxcr_reginfo);
4261     }
4262
4263     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4264         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4265             /* 32 bit view is [31:18] 0...0 [43:32]. */
4266             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4267                 | extract64(cpu->reset_cbar, 32, 12);
4268             ARMCPRegInfo cbar_reginfo[] = {
4269                 { .name = "CBAR",
4270                   .type = ARM_CP_CONST,
4271                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4272                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4273                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4274                   .type = ARM_CP_CONST,
4275                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4276                   .access = PL1_R, .resetvalue = cbar32 },
4277                 REGINFO_SENTINEL
4278             };
4279             /* We don't implement a r/w 64 bit CBAR currently */
4280             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4281             define_arm_cp_regs(cpu, cbar_reginfo);
4282         } else {
4283             ARMCPRegInfo cbar = {
4284                 .name = "CBAR",
4285                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4286                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4287                 .fieldoffset = offsetof(CPUARMState,
4288                                         cp15.c15_config_base_address)
4289             };
4290             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4291                 cbar.access = PL1_R;
4292                 cbar.fieldoffset = 0;
4293                 cbar.type = ARM_CP_CONST;
4294             }
4295             define_one_arm_cp_reg(cpu, &cbar);
4296         }
4297     }
4298
4299     /* Generic registers whose values depend on the implementation */
4300     {
4301         ARMCPRegInfo sctlr = {
4302             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4303             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4304             .access = PL1_RW,
4305             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4306                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4307             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4308             .raw_writefn = raw_write,
4309         };
4310         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4311             /* Normally we would always end the TB on an SCTLR write, but Linux
4312              * arch/arm/mach-pxa/sleep.S expects two instructions following
4313              * an MMU enable to execute from cache.  Imitate this behaviour.
4314              */
4315             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4316         }
4317         define_one_arm_cp_reg(cpu, &sctlr);
4318     }
4319 }
4320
4321 ARMCPU *cpu_arm_init(const char *cpu_model)
4322 {
4323     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4324 }
4325
4326 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4327 {
4328     CPUState *cs = CPU(cpu);
4329     CPUARMState *env = &cpu->env;
4330
4331     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4332         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4333                                  aarch64_fpu_gdb_set_reg,
4334                                  34, "aarch64-fpu.xml", 0);
4335     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4336         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4337                                  51, "arm-neon.xml", 0);
4338     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4339         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4340                                  35, "arm-vfp3.xml", 0);
4341     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4342         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4343                                  19, "arm-vfp.xml", 0);
4344     }
4345 }
4346
4347 /* Sort alphabetically by type name, except for "any". */
4348 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4349 {
4350     ObjectClass *class_a = (ObjectClass *)a;
4351     ObjectClass *class_b = (ObjectClass *)b;
4352     const char *name_a, *name_b;
4353
4354     name_a = object_class_get_name(class_a);
4355     name_b = object_class_get_name(class_b);
4356     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4357         return 1;
4358     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4359         return -1;
4360     } else {
4361         return strcmp(name_a, name_b);
4362     }
4363 }
4364
4365 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4366 {
4367     ObjectClass *oc = data;
4368     CPUListState *s = user_data;
4369     const char *typename;
4370     char *name;
4371
4372     typename = object_class_get_name(oc);
4373     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4374     (*s->cpu_fprintf)(s->file, "  %s\n",
4375                       name);
4376     g_free(name);
4377 }
4378
4379 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4380 {
4381     CPUListState s = {
4382         .file = f,
4383         .cpu_fprintf = cpu_fprintf,
4384     };
4385     GSList *list;
4386
4387     list = object_class_get_list(TYPE_ARM_CPU, false);
4388     list = g_slist_sort(list, arm_cpu_list_compare);
4389     (*cpu_fprintf)(f, "Available CPUs:\n");
4390     g_slist_foreach(list, arm_cpu_list_entry, &s);
4391     g_slist_free(list);
4392 #ifdef CONFIG_KVM
4393     /* The 'host' CPU type is dynamically registered only if KVM is
4394      * enabled, so we have to special-case it here:
4395      */
4396     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
4397 #endif
4398 }
4399
4400 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4401 {
4402     ObjectClass *oc = data;
4403     CpuDefinitionInfoList **cpu_list = user_data;
4404     CpuDefinitionInfoList *entry;
4405     CpuDefinitionInfo *info;
4406     const char *typename;
4407
4408     typename = object_class_get_name(oc);
4409     info = g_malloc0(sizeof(*info));
4410     info->name = g_strndup(typename,
4411                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
4412
4413     entry = g_malloc0(sizeof(*entry));
4414     entry->value = info;
4415     entry->next = *cpu_list;
4416     *cpu_list = entry;
4417 }
4418
4419 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4420 {
4421     CpuDefinitionInfoList *cpu_list = NULL;
4422     GSList *list;
4423
4424     list = object_class_get_list(TYPE_ARM_CPU, false);
4425     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4426     g_slist_free(list);
4427
4428     return cpu_list;
4429 }
4430
4431 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4432                                    void *opaque, int state, int secstate,
4433                                    int crm, int opc1, int opc2)
4434 {
4435     /* Private utility function for define_one_arm_cp_reg_with_opaque():
4436      * add a single reginfo struct to the hash table.
4437      */
4438     uint32_t *key = g_new(uint32_t, 1);
4439     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4440     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4441     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4442
4443     /* Reset the secure state to the specific incoming state.  This is
4444      * necessary as the register may have been defined with both states.
4445      */
4446     r2->secure = secstate;
4447
4448     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4449         /* Register is banked (using both entries in array).
4450          * Overwriting fieldoffset as the array is only used to define
4451          * banked registers but later only fieldoffset is used.
4452          */
4453         r2->fieldoffset = r->bank_fieldoffsets[ns];
4454     }
4455
4456     if (state == ARM_CP_STATE_AA32) {
4457         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4458             /* If the register is banked then we don't need to migrate or
4459              * reset the 32-bit instance in certain cases:
4460              *
4461              * 1) If the register has both 32-bit and 64-bit instances then we
4462              *    can count on the 64-bit instance taking care of the
4463              *    non-secure bank.
4464              * 2) If ARMv8 is enabled then we can count on a 64-bit version
4465              *    taking care of the secure bank.  This requires that separate
4466              *    32 and 64-bit definitions are provided.
4467              */
4468             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4469                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4470                 r2->type |= ARM_CP_ALIAS;
4471             }
4472         } else if ((secstate != r->secure) && !ns) {
4473             /* The register is not banked so we only want to allow migration of
4474              * the non-secure instance.
4475              */
4476             r2->type |= ARM_CP_ALIAS;
4477         }
4478
4479         if (r->state == ARM_CP_STATE_BOTH) {
4480             /* We assume it is a cp15 register if the .cp field is left unset.
4481              */
4482             if (r2->cp == 0) {
4483                 r2->cp = 15;
4484             }
4485
4486 #ifdef HOST_WORDS_BIGENDIAN
4487             if (r2->fieldoffset) {
4488                 r2->fieldoffset += sizeof(uint32_t);
4489             }
4490 #endif
4491         }
4492     }
4493     if (state == ARM_CP_STATE_AA64) {
4494         /* To allow abbreviation of ARMCPRegInfo
4495          * definitions, we treat cp == 0 as equivalent to
4496          * the value for "standard guest-visible sysreg".
4497          * STATE_BOTH definitions are also always "standard
4498          * sysreg" in their AArch64 view (the .cp value may
4499          * be non-zero for the benefit of the AArch32 view).
4500          */
4501         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4502             r2->cp = CP_REG_ARM64_SYSREG_CP;
4503         }
4504         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4505                                   r2->opc0, opc1, opc2);
4506     } else {
4507         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4508     }
4509     if (opaque) {
4510         r2->opaque = opaque;
4511     }
4512     /* reginfo passed to helpers is correct for the actual access,
4513      * and is never ARM_CP_STATE_BOTH:
4514      */
4515     r2->state = state;
4516     /* Make sure reginfo passed to helpers for wildcarded regs
4517      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4518      */
4519     r2->crm = crm;
4520     r2->opc1 = opc1;
4521     r2->opc2 = opc2;
4522     /* By convention, for wildcarded registers only the first
4523      * entry is used for migration; the others are marked as
4524      * ALIAS so we don't try to transfer the register
4525      * multiple times. Special registers (ie NOP/WFI) are
4526      * never migratable and not even raw-accessible.
4527      */
4528     if ((r->type & ARM_CP_SPECIAL)) {
4529         r2->type |= ARM_CP_NO_RAW;
4530     }
4531     if (((r->crm == CP_ANY) && crm != 0) ||
4532         ((r->opc1 == CP_ANY) && opc1 != 0) ||
4533         ((r->opc2 == CP_ANY) && opc2 != 0)) {
4534         r2->type |= ARM_CP_ALIAS;
4535     }
4536
4537     /* Check that raw accesses are either forbidden or handled. Note that
4538      * we can't assert this earlier because the setup of fieldoffset for
4539      * banked registers has to be done first.
4540      */
4541     if (!(r2->type & ARM_CP_NO_RAW)) {
4542         assert(!raw_accessors_invalid(r2));
4543     }
4544
4545     /* Overriding of an existing definition must be explicitly
4546      * requested.
4547      */
4548     if (!(r->type & ARM_CP_OVERRIDE)) {
4549         ARMCPRegInfo *oldreg;
4550         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4551         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4552             fprintf(stderr, "Register redefined: cp=%d %d bit "
4553                     "crn=%d crm=%d opc1=%d opc2=%d, "
4554                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4555                     r2->crn, r2->crm, r2->opc1, r2->opc2,
4556                     oldreg->name, r2->name);
4557             g_assert_not_reached();
4558         }
4559     }
4560     g_hash_table_insert(cpu->cp_regs, key, r2);
4561 }
4562
4563
4564 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4565                                        const ARMCPRegInfo *r, void *opaque)
4566 {
4567     /* Define implementations of coprocessor registers.
4568      * We store these in a hashtable because typically
4569      * there are less than 150 registers in a space which
4570      * is 16*16*16*8*8 = 262144 in size.
4571      * Wildcarding is supported for the crm, opc1 and opc2 fields.
4572      * If a register is defined twice then the second definition is
4573      * used, so this can be used to define some generic registers and
4574      * then override them with implementation specific variations.
4575      * At least one of the original and the second definition should
4576      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4577      * against accidental use.
4578      *
4579      * The state field defines whether the register is to be
4580      * visible in the AArch32 or AArch64 execution state. If the
4581      * state is set to ARM_CP_STATE_BOTH then we synthesise a
4582      * reginfo structure for the AArch32 view, which sees the lower
4583      * 32 bits of the 64 bit register.
4584      *
4585      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4586      * be wildcarded. AArch64 registers are always considered to be 64
4587      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4588      * the register, if any.
4589      */
4590     int crm, opc1, opc2, state;
4591     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4592     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4593     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4594     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4595     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4596     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4597     /* 64 bit registers have only CRm and Opc1 fields */
4598     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4599     /* op0 only exists in the AArch64 encodings */
4600     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4601     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4602     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4603     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4604      * encodes a minimum access level for the register. We roll this
4605      * runtime check into our general permission check code, so check
4606      * here that the reginfo's specified permissions are strict enough
4607      * to encompass the generic architectural permission check.
4608      */
4609     if (r->state != ARM_CP_STATE_AA32) {
4610         int mask = 0;
4611         switch (r->opc1) {
4612         case 0: case 1: case 2:
4613             /* min_EL EL1 */
4614             mask = PL1_RW;
4615             break;
4616         case 3:
4617             /* min_EL EL0 */
4618             mask = PL0_RW;
4619             break;
4620         case 4:
4621             /* min_EL EL2 */
4622             mask = PL2_RW;
4623             break;
4624         case 5:
4625             /* unallocated encoding, so not possible */
4626             assert(false);
4627             break;
4628         case 6:
4629             /* min_EL EL3 */
4630             mask = PL3_RW;
4631             break;
4632         case 7:
4633             /* min_EL EL1, secure mode only (we don't check the latter) */
4634             mask = PL1_RW;
4635             break;
4636         default:
4637             /* broken reginfo with out-of-range opc1 */
4638             assert(false);
4639             break;
4640         }
4641         /* assert our permissions are not too lax (stricter is fine) */
4642         assert((r->access & ~mask) == 0);
4643     }
4644
4645     /* Check that the register definition has enough info to handle
4646      * reads and writes if they are permitted.
4647      */
4648     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4649         if (r->access & PL3_R) {
4650             assert((r->fieldoffset ||
4651                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4652                    r->readfn);
4653         }
4654         if (r->access & PL3_W) {
4655             assert((r->fieldoffset ||
4656                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4657                    r->writefn);
4658         }
4659     }
4660     /* Bad type field probably means missing sentinel at end of reg list */
4661     assert(cptype_valid(r->type));
4662     for (crm = crmmin; crm <= crmmax; crm++) {
4663         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
4664             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
4665                 for (state = ARM_CP_STATE_AA32;
4666                      state <= ARM_CP_STATE_AA64; state++) {
4667                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
4668                         continue;
4669                     }
4670                     if (state == ARM_CP_STATE_AA32) {
4671                         /* Under AArch32 CP registers can be common
4672                          * (same for secure and non-secure world) or banked.
4673                          */
4674                         switch (r->secure) {
4675                         case ARM_CP_SECSTATE_S:
4676                         case ARM_CP_SECSTATE_NS:
4677                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4678                                                    r->secure, crm, opc1, opc2);
4679                             break;
4680                         default:
4681                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4682                                                    ARM_CP_SECSTATE_S,
4683                                                    crm, opc1, opc2);
4684                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4685                                                    ARM_CP_SECSTATE_NS,
4686                                                    crm, opc1, opc2);
4687                             break;
4688                         }
4689                     } else {
4690                         /* AArch64 registers get mapped to non-secure instance
4691                          * of AArch32 */
4692                         add_cpreg_to_hashtable(cpu, r, opaque, state,
4693                                                ARM_CP_SECSTATE_NS,
4694                                                crm, opc1, opc2);
4695                     }
4696                 }
4697             }
4698         }
4699     }
4700 }
4701
4702 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
4703                                     const ARMCPRegInfo *regs, void *opaque)
4704 {
4705     /* Define a whole list of registers */
4706     const ARMCPRegInfo *r;
4707     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
4708         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
4709     }
4710 }
4711
4712 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4713 {
4714     return g_hash_table_lookup(cpregs, &encoded_cp);
4715 }
4716
4717 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
4718                          uint64_t value)
4719 {
4720     /* Helper coprocessor write function for write-ignore registers */
4721 }
4722
4723 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4724 {
4725     /* Helper coprocessor write function for read-as-zero registers */
4726     return 0;
4727 }
4728
4729 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
4730 {
4731     /* Helper coprocessor reset function for do-nothing-on-reset registers */
4732 }
4733
4734 static int bad_mode_switch(CPUARMState *env, int mode)
4735 {
4736     /* Return true if it is not valid for us to switch to
4737      * this CPU mode (ie all the UNPREDICTABLE cases in
4738      * the ARM ARM CPSRWriteByInstr pseudocode).
4739      */
4740     switch (mode) {
4741     case ARM_CPU_MODE_USR:
4742     case ARM_CPU_MODE_SYS:
4743     case ARM_CPU_MODE_SVC:
4744     case ARM_CPU_MODE_ABT:
4745     case ARM_CPU_MODE_UND:
4746     case ARM_CPU_MODE_IRQ:
4747     case ARM_CPU_MODE_FIQ:
4748         return 0;
4749     case ARM_CPU_MODE_MON:
4750         return !arm_is_secure(env);
4751     default:
4752         return 1;
4753     }
4754 }
4755
4756 uint32_t cpsr_read(CPUARMState *env)
4757 {
4758     int ZF;
4759     ZF = (env->ZF == 0);
4760     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
4761         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
4762         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
4763         | ((env->condexec_bits & 0xfc) << 8)
4764         | (env->GE << 16) | (env->daif & CPSR_AIF);
4765 }
4766
4767 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
4768 {
4769     uint32_t changed_daif;
4770
4771     if (mask & CPSR_NZCV) {
4772         env->ZF = (~val) & CPSR_Z;
4773         env->NF = val;
4774         env->CF = (val >> 29) & 1;
4775         env->VF = (val << 3) & 0x80000000;
4776     }
4777     if (mask & CPSR_Q)
4778         env->QF = ((val & CPSR_Q) != 0);
4779     if (mask & CPSR_T)
4780         env->thumb = ((val & CPSR_T) != 0);
4781     if (mask & CPSR_IT_0_1) {
4782         env->condexec_bits &= ~3;
4783         env->condexec_bits |= (val >> 25) & 3;
4784     }
4785     if (mask & CPSR_IT_2_7) {
4786         env->condexec_bits &= 3;
4787         env->condexec_bits |= (val >> 8) & 0xfc;
4788     }
4789     if (mask & CPSR_GE) {
4790         env->GE = (val >> 16) & 0xf;
4791     }
4792
4793     /* In a V7 implementation that includes the security extensions but does
4794      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
4795      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
4796      * bits respectively.
4797      *
4798      * In a V8 implementation, it is permitted for privileged software to
4799      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
4800      */
4801     if (!arm_feature(env, ARM_FEATURE_V8) &&
4802         arm_feature(env, ARM_FEATURE_EL3) &&
4803         !arm_feature(env, ARM_FEATURE_EL2) &&
4804         !arm_is_secure(env)) {
4805
4806         changed_daif = (env->daif ^ val) & mask;
4807
4808         if (changed_daif & CPSR_A) {
4809             /* Check to see if we are allowed to change the masking of async
4810              * abort exceptions from a non-secure state.
4811              */
4812             if (!(env->cp15.scr_el3 & SCR_AW)) {
4813                 qemu_log_mask(LOG_GUEST_ERROR,
4814                               "Ignoring attempt to switch CPSR_A flag from "
4815                               "non-secure world with SCR.AW bit clear\n");
4816                 mask &= ~CPSR_A;
4817             }
4818         }
4819
4820         if (changed_daif & CPSR_F) {
4821             /* Check to see if we are allowed to change the masking of FIQ
4822              * exceptions from a non-secure state.
4823              */
4824             if (!(env->cp15.scr_el3 & SCR_FW)) {
4825                 qemu_log_mask(LOG_GUEST_ERROR,
4826                               "Ignoring attempt to switch CPSR_F flag from "
4827                               "non-secure world with SCR.FW bit clear\n");
4828                 mask &= ~CPSR_F;
4829             }
4830
4831             /* Check whether non-maskable FIQ (NMFI) support is enabled.
4832              * If this bit is set software is not allowed to mask
4833              * FIQs, but is allowed to set CPSR_F to 0.
4834              */
4835             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
4836                 (val & CPSR_F)) {
4837                 qemu_log_mask(LOG_GUEST_ERROR,
4838                               "Ignoring attempt to enable CPSR_F flag "
4839                               "(non-maskable FIQ [NMFI] support enabled)\n");
4840                 mask &= ~CPSR_F;
4841             }
4842         }
4843     }
4844
4845     env->daif &= ~(CPSR_AIF & mask);
4846     env->daif |= val & CPSR_AIF & mask;
4847
4848     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
4849         if (bad_mode_switch(env, val & CPSR_M)) {
4850             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4851              * We choose to ignore the attempt and leave the CPSR M field
4852              * untouched.
4853              */
4854             mask &= ~CPSR_M;
4855         } else {
4856             switch_mode(env, val & CPSR_M);
4857         }
4858     }
4859     mask &= ~CACHED_CPSR_BITS;
4860     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
4861 }
4862
4863 /* Sign/zero extend */
4864 uint32_t HELPER(sxtb16)(uint32_t x)
4865 {
4866     uint32_t res;
4867     res = (uint16_t)(int8_t)x;
4868     res |= (uint32_t)(int8_t)(x >> 16) << 16;
4869     return res;
4870 }
4871
4872 uint32_t HELPER(uxtb16)(uint32_t x)
4873 {
4874     uint32_t res;
4875     res = (uint16_t)(uint8_t)x;
4876     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
4877     return res;
4878 }
4879
4880 uint32_t HELPER(clz)(uint32_t x)
4881 {
4882     return clz32(x);
4883 }
4884
4885 int32_t HELPER(sdiv)(int32_t num, int32_t den)
4886 {
4887     if (den == 0)
4888       return 0;
4889     if (num == INT_MIN && den == -1)
4890       return INT_MIN;
4891     return num / den;
4892 }
4893
4894 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
4895 {
4896     if (den == 0)
4897       return 0;
4898     return num / den;
4899 }
4900
4901 uint32_t HELPER(rbit)(uint32_t x)
4902 {
4903     x =  ((x & 0xff000000) >> 24)
4904        | ((x & 0x00ff0000) >> 8)
4905        | ((x & 0x0000ff00) << 8)
4906        | ((x & 0x000000ff) << 24);
4907     x =  ((x & 0xf0f0f0f0) >> 4)
4908        | ((x & 0x0f0f0f0f) << 4);
4909     x =  ((x & 0x88888888) >> 3)
4910        | ((x & 0x44444444) >> 1)
4911        | ((x & 0x22222222) << 1)
4912        | ((x & 0x11111111) << 3);
4913     return x;
4914 }
4915
4916 #if defined(CONFIG_USER_ONLY)
4917
4918 /* These should probably raise undefined insn exceptions.  */
4919 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4920 {
4921     ARMCPU *cpu = arm_env_get_cpu(env);
4922
4923     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
4924 }
4925
4926 uint32_t QEMU_NORETURN HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4927 {
4928     ARMCPU *cpu = arm_env_get_cpu(env);
4929
4930     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
4931 }
4932
4933 void switch_mode(CPUARMState *env, int mode)
4934 {
4935     ARMCPU *cpu = arm_env_get_cpu(env);
4936
4937     if (mode != ARM_CPU_MODE_USR) {
4938         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
4939     }
4940 }
4941
4942 void QEMU_NORETURN HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4943 {
4944     ARMCPU *cpu = arm_env_get_cpu(env);
4945
4946     cpu_abort(CPU(cpu), "banked r13 write\n");
4947 }
4948
4949 uint32_t QEMU_NORETURN HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4950 {
4951     ARMCPU *cpu = arm_env_get_cpu(env);
4952
4953     cpu_abort(CPU(cpu), "banked r13 read\n");
4954 }
4955
4956 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4957                                  uint32_t cur_el, bool secure)
4958 {
4959     return 1;
4960 }
4961
4962 void aarch64_sync_64_to_32(CPUARMState *env)
4963 {
4964     g_assert_not_reached();
4965 }
4966
4967 #else
4968
4969 /* Map CPU modes onto saved register banks.  */
4970 int bank_number(int mode)
4971 {
4972     switch (mode) {
4973     case ARM_CPU_MODE_USR:
4974     case ARM_CPU_MODE_SYS:
4975         return 0;
4976     case ARM_CPU_MODE_SVC:
4977         return 1;
4978     case ARM_CPU_MODE_ABT:
4979         return 2;
4980     case ARM_CPU_MODE_UND:
4981         return 3;
4982     case ARM_CPU_MODE_IRQ:
4983         return 4;
4984     case ARM_CPU_MODE_FIQ:
4985         return 5;
4986     case ARM_CPU_MODE_HYP:
4987         return 6;
4988     case ARM_CPU_MODE_MON:
4989         return 7;
4990     }
4991     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
4992 }
4993
4994 void switch_mode(CPUARMState *env, int mode)
4995 {
4996     int old_mode;
4997     int i;
4998
4999     old_mode = env->uncached_cpsr & CPSR_M;
5000     if (mode == old_mode)
5001         return;
5002
5003     if (old_mode == ARM_CPU_MODE_FIQ) {
5004         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5005         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5006     } else if (mode == ARM_CPU_MODE_FIQ) {
5007         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5008         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5009     }
5010
5011     i = bank_number(old_mode);
5012     env->banked_r13[i] = env->regs[13];
5013     env->banked_r14[i] = env->regs[14];
5014     env->banked_spsr[i] = env->spsr;
5015
5016     i = bank_number(mode);
5017     env->regs[13] = env->banked_r13[i];
5018     env->regs[14] = env->banked_r14[i];
5019     env->spsr = env->banked_spsr[i];
5020 }
5021
5022 /* Physical Interrupt Target EL Lookup Table
5023  *
5024  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5025  *
5026  * The below multi-dimensional table is used for looking up the target
5027  * exception level given numerous condition criteria.  Specifically, the
5028  * target EL is based on SCR and HCR routing controls as well as the
5029  * currently executing EL and secure state.
5030  *
5031  *    Dimensions:
5032  *    target_el_table[2][2][2][2][2][4]
5033  *                    |  |  |  |  |  +--- Current EL
5034  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5035  *                    |  |  |  +--------- HCR mask override
5036  *                    |  |  +------------ SCR exec state control
5037  *                    |  +--------------- SCR mask override
5038  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5039  *
5040  *    The table values are as such:
5041  *    0-3 = EL0-EL3
5042  *     -1 = Cannot occur
5043  *
5044  * The ARM ARM target EL table includes entries indicating that an "exception
5045  * is not taken".  The two cases where this is applicable are:
5046  *    1) An exception is taken from EL3 but the SCR does not have the exception
5047  *    routed to EL3.
5048  *    2) An exception is taken from EL2 but the HCR does not have the exception
5049  *    routed to EL2.
5050  * In these two cases, the below table contain a target of EL1.  This value is
5051  * returned as it is expected that the consumer of the table data will check
5052  * for "target EL >= current EL" to ensure the exception is not taken.
5053  *
5054  *            SCR     HCR
5055  *         64  EA     AMO                 From
5056  *        BIT IRQ     IMO      Non-secure         Secure
5057  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5058  */
5059 const int8_t target_el_table[2][2][2][2][2][4] = {
5060     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5061        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5062       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5063        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5064      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5065        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5066       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5067        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5068     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5069        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5070       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5071        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5072      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5073        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5074       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5075        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5076 };
5077
5078 /*
5079  * Determine the target EL for physical exceptions
5080  */
5081 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5082                                  uint32_t cur_el, bool secure)
5083 {
5084     CPUARMState *env = cs->env_ptr;
5085     int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5086     int scr;
5087     int hcr;
5088     int target_el;
5089     int is64 = arm_el_is_aa64(env, 3);
5090
5091     switch (excp_idx) {
5092     case EXCP_IRQ:
5093         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5094         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5095         break;
5096     case EXCP_FIQ:
5097         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5098         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5099         break;
5100     default:
5101         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5102         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5103         break;
5104     };
5105
5106     /* If HCR.TGE is set then HCR is treated as being 1 */
5107     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5108
5109     /* Perform a table-lookup for the target EL given the current state */
5110     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5111
5112     assert(target_el > 0);
5113
5114     return target_el;
5115 }
5116
5117 static void v7m_push(CPUARMState *env, uint32_t val)
5118 {
5119     CPUState *cs = CPU(arm_env_get_cpu(env));
5120
5121     env->regs[13] -= 4;
5122     stl_phys(cs->as, env->regs[13], val);
5123 }
5124
5125 static uint32_t v7m_pop(CPUARMState *env)
5126 {
5127     CPUState *cs = CPU(arm_env_get_cpu(env));
5128     uint32_t val;
5129
5130     val = ldl_phys(cs->as, env->regs[13]);
5131     env->regs[13] += 4;
5132     return val;
5133 }
5134
5135 /* Switch to V7M main or process stack pointer.  */
5136 static void switch_v7m_sp(CPUARMState *env, int process)
5137 {
5138     uint32_t tmp;
5139     if (env->v7m.current_sp != process) {
5140         tmp = env->v7m.other_sp;
5141         env->v7m.other_sp = env->regs[13];
5142         env->regs[13] = tmp;
5143         env->v7m.current_sp = process;
5144     }
5145 }
5146
5147 static void do_v7m_exception_exit(CPUARMState *env)
5148 {
5149     uint32_t type;
5150     uint32_t xpsr;
5151
5152     type = env->regs[15];
5153     if (env->v7m.exception != 0)
5154         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5155
5156     /* Switch to the target stack.  */
5157     switch_v7m_sp(env, (type & 4) != 0);
5158     /* Pop registers.  */
5159     env->regs[0] = v7m_pop(env);
5160     env->regs[1] = v7m_pop(env);
5161     env->regs[2] = v7m_pop(env);
5162     env->regs[3] = v7m_pop(env);
5163     env->regs[12] = v7m_pop(env);
5164     env->regs[14] = v7m_pop(env);
5165     env->regs[15] = v7m_pop(env);
5166     if (env->regs[15] & 1) {
5167         qemu_log_mask(LOG_GUEST_ERROR,
5168                       "M profile return from interrupt with misaligned "
5169                       "PC is UNPREDICTABLE\n");
5170         /* Actual hardware seems to ignore the lsbit, and there are several
5171          * RTOSes out there which incorrectly assume the r15 in the stack
5172          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5173          */
5174         env->regs[15] &= ~1U;
5175     }
5176     xpsr = v7m_pop(env);
5177     xpsr_write(env, xpsr, 0xfffffdff);
5178     /* Undo stack alignment.  */
5179     if (xpsr & 0x200)
5180         env->regs[13] |= 4;
5181     /* ??? The exception return type specifies Thread/Handler mode.  However
5182        this is also implied by the xPSR value. Not sure what to do
5183        if there is a mismatch.  */
5184     /* ??? Likewise for mismatches between the CONTROL register and the stack
5185        pointer.  */
5186 }
5187
5188 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5189 {
5190     ARMCPU *cpu = ARM_CPU(cs);
5191     CPUARMState *env = &cpu->env;
5192     uint32_t xpsr = xpsr_read(env);
5193     uint32_t lr;
5194     uint32_t addr;
5195
5196     arm_log_exception(cs->exception_index);
5197
5198     lr = 0xfffffff1;
5199     if (env->v7m.current_sp)
5200         lr |= 4;
5201     if (env->v7m.exception == 0)
5202         lr |= 8;
5203
5204     /* For exceptions we just mark as pending on the NVIC, and let that
5205        handle it.  */
5206     /* TODO: Need to escalate if the current priority is higher than the
5207        one we're raising.  */
5208     switch (cs->exception_index) {
5209     case EXCP_UDEF:
5210         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5211         return;
5212     case EXCP_SWI:
5213         /* The PC already points to the next instruction.  */
5214         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5215         return;
5216     case EXCP_PREFETCH_ABORT:
5217     case EXCP_DATA_ABORT:
5218         /* TODO: if we implemented the MPU registers, this is where we
5219          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5220          */
5221         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5222         return;
5223     case EXCP_BKPT:
5224         if (semihosting_enabled()) {
5225             int nr;
5226             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5227             if (nr == 0xab) {
5228                 env->regs[15] += 2;
5229                 env->regs[0] = do_arm_semihosting(env);
5230                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
5231                 return;
5232             }
5233         }
5234         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5235         return;
5236     case EXCP_IRQ:
5237         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5238         break;
5239     case EXCP_EXCEPTION_EXIT:
5240         do_v7m_exception_exit(env);
5241         return;
5242     default:
5243         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5244         return; /* Never happens.  Keep compiler happy.  */
5245     }
5246
5247     /* Align stack pointer.  */
5248     /* ??? Should only do this if Configuration Control Register
5249        STACKALIGN bit is set.  */
5250     if (env->regs[13] & 4) {
5251         env->regs[13] -= 4;
5252         xpsr |= 0x200;
5253     }
5254     /* Switch to the handler mode.  */
5255     v7m_push(env, xpsr);
5256     v7m_push(env, env->regs[15]);
5257     v7m_push(env, env->regs[14]);
5258     v7m_push(env, env->regs[12]);
5259     v7m_push(env, env->regs[3]);
5260     v7m_push(env, env->regs[2]);
5261     v7m_push(env, env->regs[1]);
5262     v7m_push(env, env->regs[0]);
5263     switch_v7m_sp(env, 0);
5264     /* Clear IT bits */
5265     env->condexec_bits = 0;
5266     env->regs[14] = lr;
5267     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5268     env->regs[15] = addr & 0xfffffffe;
5269     env->thumb = addr & 1;
5270 }
5271
5272 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5273  * register set.  This is necessary when switching between AArch32 and AArch64
5274  * execution state.
5275  */
5276 void aarch64_sync_32_to_64(CPUARMState *env)
5277 {
5278     int i;
5279     uint32_t mode = env->uncached_cpsr & CPSR_M;
5280
5281     /* We can blanket copy R[0:7] to X[0:7] */
5282     for (i = 0; i < 8; i++) {
5283         env->xregs[i] = env->regs[i];
5284     }
5285
5286     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5287      * Otherwise, they come from the banked user regs.
5288      */
5289     if (mode == ARM_CPU_MODE_FIQ) {
5290         for (i = 8; i < 13; i++) {
5291             env->xregs[i] = env->usr_regs[i - 8];
5292         }
5293     } else {
5294         for (i = 8; i < 13; i++) {
5295             env->xregs[i] = env->regs[i];
5296         }
5297     }
5298
5299     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5300      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5301      * from the mode banked register.
5302      */
5303     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5304         env->xregs[13] = env->regs[13];
5305         env->xregs[14] = env->regs[14];
5306     } else {
5307         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5308         /* HYP is an exception in that it is copied from r14 */
5309         if (mode == ARM_CPU_MODE_HYP) {
5310             env->xregs[14] = env->regs[14];
5311         } else {
5312             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5313         }
5314     }
5315
5316     if (mode == ARM_CPU_MODE_HYP) {
5317         env->xregs[15] = env->regs[13];
5318     } else {
5319         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5320     }
5321
5322     if (mode == ARM_CPU_MODE_IRQ) {
5323         env->xregs[16] = env->regs[13];
5324         env->xregs[17] = env->regs[14];
5325     } else {
5326         env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5327         env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5328     }
5329
5330     if (mode == ARM_CPU_MODE_SVC) {
5331         env->xregs[18] = env->regs[13];
5332         env->xregs[19] = env->regs[14];
5333     } else {
5334         env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5335         env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5336     }
5337
5338     if (mode == ARM_CPU_MODE_ABT) {
5339         env->xregs[20] = env->regs[13];
5340         env->xregs[21] = env->regs[14];
5341     } else {
5342         env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5343         env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5344     }
5345
5346     if (mode == ARM_CPU_MODE_UND) {
5347         env->xregs[22] = env->regs[13];
5348         env->xregs[23] = env->regs[14];
5349     } else {
5350         env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5351         env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5352     }
5353
5354     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5355      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5356      * FIQ bank for r8-r14.
5357      */
5358     if (mode == ARM_CPU_MODE_FIQ) {
5359         for (i = 24; i < 31; i++) {
5360             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5361         }
5362     } else {
5363         for (i = 24; i < 29; i++) {
5364             env->xregs[i] = env->fiq_regs[i - 24];
5365         }
5366         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5367         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5368     }
5369
5370     env->pc = env->regs[15];
5371 }
5372
5373 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5374  * register set.  This is necessary when switching between AArch32 and AArch64
5375  * execution state.
5376  */
5377 void aarch64_sync_64_to_32(CPUARMState *env)
5378 {
5379     int i;
5380     uint32_t mode = env->uncached_cpsr & CPSR_M;
5381
5382     /* We can blanket copy X[0:7] to R[0:7] */
5383     for (i = 0; i < 8; i++) {
5384         env->regs[i] = env->xregs[i];
5385     }
5386
5387     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5388      * Otherwise, we copy x8-x12 into the banked user regs.
5389      */
5390     if (mode == ARM_CPU_MODE_FIQ) {
5391         for (i = 8; i < 13; i++) {
5392             env->usr_regs[i - 8] = env->xregs[i];
5393         }
5394     } else {
5395         for (i = 8; i < 13; i++) {
5396             env->regs[i] = env->xregs[i];
5397         }
5398     }
5399
5400     /* Registers r13 & r14 depend on the current mode.
5401      * If we are in a given mode, we copy the corresponding x registers to r13
5402      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
5403      * for the mode.
5404      */
5405     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5406         env->regs[13] = env->xregs[13];
5407         env->regs[14] = env->xregs[14];
5408     } else {
5409         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5410
5411         /* HYP is an exception in that it does not have its own banked r14 but
5412          * shares the USR r14
5413          */
5414         if (mode == ARM_CPU_MODE_HYP) {
5415             env->regs[14] = env->xregs[14];
5416         } else {
5417             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5418         }
5419     }
5420
5421     if (mode == ARM_CPU_MODE_HYP) {
5422         env->regs[13] = env->xregs[15];
5423     } else {
5424         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5425     }
5426
5427     if (mode == ARM_CPU_MODE_IRQ) {
5428         env->regs[13] = env->xregs[16];
5429         env->regs[14] = env->xregs[17];
5430     } else {
5431         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5432         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5433     }
5434
5435     if (mode == ARM_CPU_MODE_SVC) {
5436         env->regs[13] = env->xregs[18];
5437         env->regs[14] = env->xregs[19];
5438     } else {
5439         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5440         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5441     }
5442
5443     if (mode == ARM_CPU_MODE_ABT) {
5444         env->regs[13] = env->xregs[20];
5445         env->regs[14] = env->xregs[21];
5446     } else {
5447         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5448         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5449     }
5450
5451     if (mode == ARM_CPU_MODE_UND) {
5452         env->regs[13] = env->xregs[22];
5453         env->regs[14] = env->xregs[23];
5454     } else {
5455         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5456         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5457     }
5458
5459     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5460      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
5461      * FIQ bank for r8-r14.
5462      */
5463     if (mode == ARM_CPU_MODE_FIQ) {
5464         for (i = 24; i < 31; i++) {
5465             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
5466         }
5467     } else {
5468         for (i = 24; i < 29; i++) {
5469             env->fiq_regs[i - 24] = env->xregs[i];
5470         }
5471         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5472         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5473     }
5474
5475     env->regs[15] = env->pc;
5476 }
5477
5478 /* Handle a CPU exception.  */
5479 void arm_cpu_do_interrupt(CPUState *cs)
5480 {
5481     ARMCPU *cpu = ARM_CPU(cs);
5482     CPUARMState *env = &cpu->env;
5483     uint32_t addr;
5484     uint32_t mask;
5485     int new_mode;
5486     uint32_t offset;
5487     uint32_t moe;
5488
5489     assert(!IS_M(env));
5490
5491     arm_log_exception(cs->exception_index);
5492
5493     if (arm_is_psci_call(cpu, cs->exception_index)) {
5494         arm_handle_psci_call(cpu);
5495         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
5496         return;
5497     }
5498
5499     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5500     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5501     case EC_BREAKPOINT:
5502     case EC_BREAKPOINT_SAME_EL:
5503         moe = 1;
5504         break;
5505     case EC_WATCHPOINT:
5506     case EC_WATCHPOINT_SAME_EL:
5507         moe = 10;
5508         break;
5509     case EC_AA32_BKPT:
5510         moe = 3;
5511         break;
5512     case EC_VECTORCATCH:
5513         moe = 5;
5514         break;
5515     default:
5516         moe = 0;
5517         break;
5518     }
5519
5520     if (moe) {
5521         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5522     }
5523
5524     /* TODO: Vectored interrupt controller.  */
5525     switch (cs->exception_index) {
5526     case EXCP_UDEF:
5527         new_mode = ARM_CPU_MODE_UND;
5528         addr = 0x04;
5529         mask = CPSR_I;
5530         if (env->thumb)
5531             offset = 2;
5532         else
5533             offset = 4;
5534         break;
5535     case EXCP_SWI:
5536         if (semihosting_enabled()) {
5537             /* Check for semihosting interrupt.  */
5538             if (env->thumb) {
5539                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
5540                     & 0xff;
5541             } else {
5542                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
5543                     & 0xffffff;
5544             }
5545             /* Only intercept calls from privileged modes, to provide some
5546                semblance of security.  */
5547             if (((mask == 0x123456 && !env->thumb)
5548                     || (mask == 0xab && env->thumb))
5549                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5550                 env->regs[0] = do_arm_semihosting(env);
5551                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
5552                 return;
5553             }
5554         }
5555         new_mode = ARM_CPU_MODE_SVC;
5556         addr = 0x08;
5557         mask = CPSR_I;
5558         /* The PC already points to the next instruction.  */
5559         offset = 0;
5560         break;
5561     case EXCP_BKPT:
5562         /* See if this is a semihosting syscall.  */
5563         if (env->thumb && semihosting_enabled()) {
5564             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5565             if (mask == 0xab
5566                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5567                 env->regs[15] += 2;
5568                 env->regs[0] = do_arm_semihosting(env);
5569                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
5570                 return;
5571             }
5572         }
5573         env->exception.fsr = 2;
5574         /* Fall through to prefetch abort.  */
5575     case EXCP_PREFETCH_ABORT:
5576         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5577         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5578         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5579                       env->exception.fsr, (uint32_t)env->exception.vaddress);
5580         new_mode = ARM_CPU_MODE_ABT;
5581         addr = 0x0c;
5582         mask = CPSR_A | CPSR_I;
5583         offset = 4;
5584         break;
5585     case EXCP_DATA_ABORT:
5586         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5587         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5588         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5589                       env->exception.fsr,
5590                       (uint32_t)env->exception.vaddress);
5591         new_mode = ARM_CPU_MODE_ABT;
5592         addr = 0x10;
5593         mask = CPSR_A | CPSR_I;
5594         offset = 8;
5595         break;
5596     case EXCP_IRQ:
5597         new_mode = ARM_CPU_MODE_IRQ;
5598         addr = 0x18;
5599         /* Disable IRQ and imprecise data aborts.  */
5600         mask = CPSR_A | CPSR_I;
5601         offset = 4;
5602         if (env->cp15.scr_el3 & SCR_IRQ) {
5603             /* IRQ routed to monitor mode */
5604             new_mode = ARM_CPU_MODE_MON;
5605             mask |= CPSR_F;
5606         }
5607         break;
5608     case EXCP_FIQ:
5609         new_mode = ARM_CPU_MODE_FIQ;
5610         addr = 0x1c;
5611         /* Disable FIQ, IRQ and imprecise data aborts.  */
5612         mask = CPSR_A | CPSR_I | CPSR_F;
5613         if (env->cp15.scr_el3 & SCR_FIQ) {
5614             /* FIQ routed to monitor mode */
5615             new_mode = ARM_CPU_MODE_MON;
5616         }
5617         offset = 4;
5618         break;
5619     case EXCP_SMC:
5620         new_mode = ARM_CPU_MODE_MON;
5621         addr = 0x08;
5622         mask = CPSR_A | CPSR_I | CPSR_F;
5623         offset = 0;
5624         break;
5625     default:
5626         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5627         return; /* Never happens.  Keep compiler happy.  */
5628     }
5629
5630     if (new_mode == ARM_CPU_MODE_MON) {
5631         addr += env->cp15.mvbar;
5632     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5633         /* High vectors. When enabled, base address cannot be remapped. */
5634         addr += 0xffff0000;
5635     } else {
5636         /* ARM v7 architectures provide a vector base address register to remap
5637          * the interrupt vector table.
5638          * This register is only followed in non-monitor mode, and is banked.
5639          * Note: only bits 31:5 are valid.
5640          */
5641         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5642     }
5643
5644     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5645         env->cp15.scr_el3 &= ~SCR_NS;
5646     }
5647
5648     switch_mode (env, new_mode);
5649     /* For exceptions taken to AArch32 we must clear the SS bit in both
5650      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5651      */
5652     env->uncached_cpsr &= ~PSTATE_SS;
5653     env->spsr = cpsr_read(env);
5654     /* Clear IT bits.  */
5655     env->condexec_bits = 0;
5656     /* Switch to the new mode, and to the correct instruction set.  */
5657     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5658     env->daif |= mask;
5659     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5660      * and we should just guard the thumb mode on V4 */
5661     if (arm_feature(env, ARM_FEATURE_V4T)) {
5662         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5663     }
5664     env->regs[14] = env->regs[15] + offset;
5665     env->regs[15] = addr;
5666     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
5667 }
5668
5669
5670 /* Return the exception level which controls this address translation regime */
5671 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
5672 {
5673     switch (mmu_idx) {
5674     case ARMMMUIdx_S2NS:
5675     case ARMMMUIdx_S1E2:
5676         return 2;
5677     case ARMMMUIdx_S1E3:
5678         return 3;
5679     case ARMMMUIdx_S1SE0:
5680         return arm_el_is_aa64(env, 3) ? 1 : 3;
5681     case ARMMMUIdx_S1SE1:
5682     case ARMMMUIdx_S1NSE0:
5683     case ARMMMUIdx_S1NSE1:
5684         return 1;
5685     default:
5686         g_assert_not_reached();
5687     }
5688 }
5689
5690 /* Return true if this address translation regime is secure */
5691 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
5692 {
5693     switch (mmu_idx) {
5694     case ARMMMUIdx_S12NSE0:
5695     case ARMMMUIdx_S12NSE1:
5696     case ARMMMUIdx_S1NSE0:
5697     case ARMMMUIdx_S1NSE1:
5698     case ARMMMUIdx_S1E2:
5699     case ARMMMUIdx_S2NS:
5700         return false;
5701     case ARMMMUIdx_S1E3:
5702     case ARMMMUIdx_S1SE0:
5703     case ARMMMUIdx_S1SE1:
5704         return true;
5705     default:
5706         g_assert_not_reached();
5707     }
5708 }
5709
5710 /* Return the SCTLR value which controls this address translation regime */
5711 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
5712 {
5713     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
5714 }
5715
5716 /* Return true if the specified stage of address translation is disabled */
5717 static inline bool regime_translation_disabled(CPUARMState *env,
5718                                                ARMMMUIdx mmu_idx)
5719 {
5720     if (mmu_idx == ARMMMUIdx_S2NS) {
5721         return (env->cp15.hcr_el2 & HCR_VM) == 0;
5722     }
5723     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
5724 }
5725
5726 /* Return the TCR controlling this translation regime */
5727 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
5728 {
5729     if (mmu_idx == ARMMMUIdx_S2NS) {
5730         /* TODO: return VTCR_EL2 */
5731         g_assert_not_reached();
5732     }
5733     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
5734 }
5735
5736 /* Return the TTBR associated with this translation regime */
5737 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
5738                                    int ttbrn)
5739 {
5740     if (mmu_idx == ARMMMUIdx_S2NS) {
5741         /* TODO: return VTTBR_EL2 */
5742         g_assert_not_reached();
5743     }
5744     if (ttbrn == 0) {
5745         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
5746     } else {
5747         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
5748     }
5749 }
5750
5751 /* Return true if the translation regime is using LPAE format page tables */
5752 static inline bool regime_using_lpae_format(CPUARMState *env,
5753                                             ARMMMUIdx mmu_idx)
5754 {
5755     int el = regime_el(env, mmu_idx);
5756     if (el == 2 || arm_el_is_aa64(env, el)) {
5757         return true;
5758     }
5759     if (arm_feature(env, ARM_FEATURE_LPAE)
5760         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
5761         return true;
5762     }
5763     return false;
5764 }
5765
5766 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
5767 {
5768     switch (mmu_idx) {
5769     case ARMMMUIdx_S1SE0:
5770     case ARMMMUIdx_S1NSE0:
5771         return true;
5772     default:
5773         return false;
5774     case ARMMMUIdx_S12NSE0:
5775     case ARMMMUIdx_S12NSE1:
5776         g_assert_not_reached();
5777     }
5778 }
5779
5780 /* Translate section/page access permissions to page
5781  * R/W protection flags
5782  *
5783  * @env:         CPUARMState
5784  * @mmu_idx:     MMU index indicating required translation regime
5785  * @ap:          The 3-bit access permissions (AP[2:0])
5786  * @domain_prot: The 2-bit domain access permissions
5787  */
5788 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
5789                                 int ap, int domain_prot)
5790 {
5791     bool is_user = regime_is_user(env, mmu_idx);
5792
5793     if (domain_prot == 3) {
5794         return PAGE_READ | PAGE_WRITE;
5795     }
5796
5797     switch (ap) {
5798     case 0:
5799         if (arm_feature(env, ARM_FEATURE_V7)) {
5800             return 0;
5801         }
5802         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
5803         case SCTLR_S:
5804             return is_user ? 0 : PAGE_READ;
5805         case SCTLR_R:
5806             return PAGE_READ;
5807         default:
5808             return 0;
5809         }
5810     case 1:
5811         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5812     case 2:
5813         if (is_user) {
5814             return PAGE_READ;
5815         } else {
5816             return PAGE_READ | PAGE_WRITE;
5817         }
5818     case 3:
5819         return PAGE_READ | PAGE_WRITE;
5820     case 4: /* Reserved.  */
5821         return 0;
5822     case 5:
5823         return is_user ? 0 : PAGE_READ;
5824     case 6:
5825         return PAGE_READ;
5826     case 7:
5827         if (!arm_feature(env, ARM_FEATURE_V6K)) {
5828             return 0;
5829         }
5830         return PAGE_READ;
5831     default:
5832         g_assert_not_reached();
5833     }
5834 }
5835
5836 /* Translate section/page access permissions to page
5837  * R/W protection flags.
5838  *
5839  * @ap:      The 2-bit simple AP (AP[2:1])
5840  * @is_user: TRUE if accessing from PL0
5841  */
5842 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
5843 {
5844     switch (ap) {
5845     case 0:
5846         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5847     case 1:
5848         return PAGE_READ | PAGE_WRITE;
5849     case 2:
5850         return is_user ? 0 : PAGE_READ;
5851     case 3:
5852         return PAGE_READ;
5853     default:
5854         g_assert_not_reached();
5855     }
5856 }
5857
5858 static inline int
5859 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
5860 {
5861     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
5862 }
5863
5864 /* Translate section/page access permissions to protection flags
5865  *
5866  * @env:     CPUARMState
5867  * @mmu_idx: MMU index indicating required translation regime
5868  * @is_aa64: TRUE if AArch64
5869  * @ap:      The 2-bit simple AP (AP[2:1])
5870  * @ns:      NS (non-secure) bit
5871  * @xn:      XN (execute-never) bit
5872  * @pxn:     PXN (privileged execute-never) bit
5873  */
5874 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
5875                       int ap, int ns, int xn, int pxn)
5876 {
5877     bool is_user = regime_is_user(env, mmu_idx);
5878     int prot_rw, user_rw;
5879     bool have_wxn;
5880     int wxn = 0;
5881
5882     assert(mmu_idx != ARMMMUIdx_S2NS);
5883
5884     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
5885     if (is_user) {
5886         prot_rw = user_rw;
5887     } else {
5888         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
5889     }
5890
5891     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
5892         return prot_rw;
5893     }
5894
5895     /* TODO have_wxn should be replaced with
5896      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
5897      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
5898      * compatible processors have EL2, which is required for [U]WXN.
5899      */
5900     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
5901
5902     if (have_wxn) {
5903         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
5904     }
5905
5906     if (is_aa64) {
5907         switch (regime_el(env, mmu_idx)) {
5908         case 1:
5909             if (!is_user) {
5910                 xn = pxn || (user_rw & PAGE_WRITE);
5911             }
5912             break;
5913         case 2:
5914         case 3:
5915             break;
5916         }
5917     } else if (arm_feature(env, ARM_FEATURE_V7)) {
5918         switch (regime_el(env, mmu_idx)) {
5919         case 1:
5920         case 3:
5921             if (is_user) {
5922                 xn = xn || !(user_rw & PAGE_READ);
5923             } else {
5924                 int uwxn = 0;
5925                 if (have_wxn) {
5926                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
5927                 }
5928                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
5929                      (uwxn && (user_rw & PAGE_WRITE));
5930             }
5931             break;
5932         case 2:
5933             break;
5934         }
5935     } else {
5936         xn = wxn = 0;
5937     }
5938
5939     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
5940         return prot_rw;
5941     }
5942     return prot_rw | PAGE_EXEC;
5943 }
5944
5945 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
5946                                      uint32_t *table, uint32_t address)
5947 {
5948     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
5949     TCR *tcr = regime_tcr(env, mmu_idx);
5950
5951     if (address & tcr->mask) {
5952         if (tcr->raw_tcr & TTBCR_PD1) {
5953             /* Translation table walk disabled for TTBR1 */
5954             return false;
5955         }
5956         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
5957     } else {
5958         if (tcr->raw_tcr & TTBCR_PD0) {
5959             /* Translation table walk disabled for TTBR0 */
5960             return false;
5961         }
5962         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
5963     }
5964     *table |= (address >> 18) & 0x3ffc;
5965     return true;
5966 }
5967
5968 /* All loads done in the course of a page table walk go through here.
5969  * TODO: rather than ignoring errors from physical memory reads (which
5970  * are external aborts in ARM terminology) we should propagate this
5971  * error out so that we can turn it into a Data Abort if this walk
5972  * was being done for a CPU load/store or an address translation instruction
5973  * (but not if it was for a debug access).
5974  */
5975 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5976 {
5977     MemTxAttrs attrs = {};
5978
5979     attrs.secure = is_secure;
5980     return address_space_ldl(cs->as, addr, attrs, NULL);
5981 }
5982
5983 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5984 {
5985     MemTxAttrs attrs = {};
5986
5987     attrs.secure = is_secure;
5988     return address_space_ldq(cs->as, addr, attrs, NULL);
5989 }
5990
5991 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
5992                              int access_type, ARMMMUIdx mmu_idx,
5993                              hwaddr *phys_ptr, int *prot,
5994                              target_ulong *page_size, uint32_t *fsr)
5995 {
5996     CPUState *cs = CPU(arm_env_get_cpu(env));
5997     int code;
5998     uint32_t table;
5999     uint32_t desc;
6000     int type;
6001     int ap;
6002     int domain = 0;
6003     int domain_prot;
6004     hwaddr phys_addr;
6005     uint32_t dacr;
6006
6007     /* Pagetable walk.  */
6008     /* Lookup l1 descriptor.  */
6009     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6010         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6011         code = 5;
6012         goto do_fault;
6013     }
6014     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6015     type = (desc & 3);
6016     domain = (desc >> 5) & 0x0f;
6017     if (regime_el(env, mmu_idx) == 1) {
6018         dacr = env->cp15.dacr_ns;
6019     } else {
6020         dacr = env->cp15.dacr_s;
6021     }
6022     domain_prot = (dacr >> (domain * 2)) & 3;
6023     if (type == 0) {
6024         /* Section translation fault.  */
6025         code = 5;
6026         goto do_fault;
6027     }
6028     if (domain_prot == 0 || domain_prot == 2) {
6029         if (type == 2)
6030             code = 9; /* Section domain fault.  */
6031         else
6032             code = 11; /* Page domain fault.  */
6033         goto do_fault;
6034     }
6035     if (type == 2) {
6036         /* 1Mb section.  */
6037         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6038         ap = (desc >> 10) & 3;
6039         code = 13;
6040         *page_size = 1024 * 1024;
6041     } else {
6042         /* Lookup l2 entry.  */
6043         if (type == 1) {
6044             /* Coarse pagetable.  */
6045             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6046         } else {
6047             /* Fine pagetable.  */
6048             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6049         }
6050         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6051         switch (desc & 3) {
6052         case 0: /* Page translation fault.  */
6053             code = 7;
6054             goto do_fault;
6055         case 1: /* 64k page.  */
6056             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6057             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6058             *page_size = 0x10000;
6059             break;
6060         case 2: /* 4k page.  */
6061             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6062             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6063             *page_size = 0x1000;
6064             break;
6065         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6066             if (type == 1) {
6067                 /* ARMv6/XScale extended small page format */
6068                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6069                     || arm_feature(env, ARM_FEATURE_V6)) {
6070                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6071                     *page_size = 0x1000;
6072                 } else {
6073                     /* UNPREDICTABLE in ARMv5; we choose to take a
6074                      * page translation fault.
6075                      */
6076                     code = 7;
6077                     goto do_fault;
6078                 }
6079             } else {
6080                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6081                 *page_size = 0x400;
6082             }
6083             ap = (desc >> 4) & 3;
6084             break;
6085         default:
6086             /* Never happens, but compiler isn't smart enough to tell.  */
6087             abort();
6088         }
6089         code = 15;
6090     }
6091     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6092     *prot |= *prot ? PAGE_EXEC : 0;
6093     if (!(*prot & (1 << access_type))) {
6094         /* Access permission fault.  */
6095         goto do_fault;
6096     }
6097     *phys_ptr = phys_addr;
6098     return false;
6099 do_fault:
6100     *fsr = code | (domain << 4);
6101     return true;
6102 }
6103
6104 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6105                              int access_type, ARMMMUIdx mmu_idx,
6106                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6107                              target_ulong *page_size, uint32_t *fsr)
6108 {
6109     CPUState *cs = CPU(arm_env_get_cpu(env));
6110     int code;
6111     uint32_t table;
6112     uint32_t desc;
6113     uint32_t xn;
6114     uint32_t pxn = 0;
6115     int type;
6116     int ap;
6117     int domain = 0;
6118     int domain_prot;
6119     hwaddr phys_addr;
6120     uint32_t dacr;
6121     bool ns;
6122
6123     /* Pagetable walk.  */
6124     /* Lookup l1 descriptor.  */
6125     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6126         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6127         code = 5;
6128         goto do_fault;
6129     }
6130     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6131     type = (desc & 3);
6132     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6133         /* Section translation fault, or attempt to use the encoding
6134          * which is Reserved on implementations without PXN.
6135          */
6136         code = 5;
6137         goto do_fault;
6138     }
6139     if ((type == 1) || !(desc & (1 << 18))) {
6140         /* Page or Section.  */
6141         domain = (desc >> 5) & 0x0f;
6142     }
6143     if (regime_el(env, mmu_idx) == 1) {
6144         dacr = env->cp15.dacr_ns;
6145     } else {
6146         dacr = env->cp15.dacr_s;
6147     }
6148     domain_prot = (dacr >> (domain * 2)) & 3;
6149     if (domain_prot == 0 || domain_prot == 2) {
6150         if (type != 1) {
6151             code = 9; /* Section domain fault.  */
6152         } else {
6153             code = 11; /* Page domain fault.  */
6154         }
6155         goto do_fault;
6156     }
6157     if (type != 1) {
6158         if (desc & (1 << 18)) {
6159             /* Supersection.  */
6160             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6161             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6162             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6163             *page_size = 0x1000000;
6164         } else {
6165             /* Section.  */
6166             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6167             *page_size = 0x100000;
6168         }
6169         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6170         xn = desc & (1 << 4);
6171         pxn = desc & 1;
6172         code = 13;
6173         ns = extract32(desc, 19, 1);
6174     } else {
6175         if (arm_feature(env, ARM_FEATURE_PXN)) {
6176             pxn = (desc >> 2) & 1;
6177         }
6178         ns = extract32(desc, 3, 1);
6179         /* Lookup l2 entry.  */
6180         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6181         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
6182         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6183         switch (desc & 3) {
6184         case 0: /* Page translation fault.  */
6185             code = 7;
6186             goto do_fault;
6187         case 1: /* 64k page.  */
6188             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6189             xn = desc & (1 << 15);
6190             *page_size = 0x10000;
6191             break;
6192         case 2: case 3: /* 4k page.  */
6193             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6194             xn = desc & 1;
6195             *page_size = 0x1000;
6196             break;
6197         default:
6198             /* Never happens, but compiler isn't smart enough to tell.  */
6199             abort();
6200         }
6201         code = 15;
6202     }
6203     if (domain_prot == 3) {
6204         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6205     } else {
6206         if (pxn && !regime_is_user(env, mmu_idx)) {
6207             xn = 1;
6208         }
6209         if (xn && access_type == 2)
6210             goto do_fault;
6211
6212         if (arm_feature(env, ARM_FEATURE_V6K) &&
6213                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6214             /* The simplified model uses AP[0] as an access control bit.  */
6215             if ((ap & 1) == 0) {
6216                 /* Access flag fault.  */
6217                 code = (code == 15) ? 6 : 3;
6218                 goto do_fault;
6219             }
6220             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6221         } else {
6222             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6223         }
6224         if (*prot && !xn) {
6225             *prot |= PAGE_EXEC;
6226         }
6227         if (!(*prot & (1 << access_type))) {
6228             /* Access permission fault.  */
6229             goto do_fault;
6230         }
6231     }
6232     if (ns) {
6233         /* The NS bit will (as required by the architecture) have no effect if
6234          * the CPU doesn't support TZ or this is a non-secure translation
6235          * regime, because the attribute will already be non-secure.
6236          */
6237         attrs->secure = false;
6238     }
6239     *phys_ptr = phys_addr;
6240     return false;
6241 do_fault:
6242     *fsr = code | (domain << 4);
6243     return true;
6244 }
6245
6246 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6247  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6248  */
6249 typedef enum {
6250     translation_fault = 1,
6251     access_fault = 2,
6252     permission_fault = 3,
6253 } MMUFaultType;
6254
6255 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6256                                int access_type, ARMMMUIdx mmu_idx,
6257                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6258                                target_ulong *page_size_ptr, uint32_t *fsr)
6259 {
6260     CPUState *cs = CPU(arm_env_get_cpu(env));
6261     /* Read an LPAE long-descriptor translation table. */
6262     MMUFaultType fault_type = translation_fault;
6263     uint32_t level = 1;
6264     uint32_t epd;
6265     int32_t tsz;
6266     uint32_t tg;
6267     uint64_t ttbr;
6268     int ttbr_select;
6269     hwaddr descaddr, descmask;
6270     uint32_t tableattrs;
6271     target_ulong page_size;
6272     uint32_t attrs;
6273     int32_t granule_sz = 9;
6274     int32_t va_size = 32;
6275     int32_t tbi = 0;
6276     TCR *tcr = regime_tcr(env, mmu_idx);
6277     int ap, ns, xn, pxn;
6278     uint32_t el = regime_el(env, mmu_idx);
6279     bool ttbr1_valid = true;
6280
6281     /* TODO:
6282      * This code does not handle the different format TCR for VTCR_EL2.
6283      * This code also does not support shareability levels.
6284      * Attribute and permission bit handling should also be checked when adding
6285      * support for those page table walks.
6286      */
6287     if (arm_el_is_aa64(env, el)) {
6288         va_size = 64;
6289         if (el > 1) {
6290             tbi = extract64(tcr->raw_tcr, 20, 1);
6291         } else {
6292             if (extract64(address, 55, 1)) {
6293                 tbi = extract64(tcr->raw_tcr, 38, 1);
6294             } else {
6295                 tbi = extract64(tcr->raw_tcr, 37, 1);
6296             }
6297         }
6298         tbi *= 8;
6299
6300         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6301          * invalid.
6302          */
6303         if (el > 1) {
6304             ttbr1_valid = false;
6305         }
6306     } else {
6307         /* There is no TTBR1 for EL2 */
6308         if (el == 2) {
6309             ttbr1_valid = false;
6310         }
6311     }
6312
6313     /* Determine whether this address is in the region controlled by
6314      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6315      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6316      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6317      */
6318     uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
6319     if (va_size == 64) {
6320         t0sz = MIN(t0sz, 39);
6321         t0sz = MAX(t0sz, 16);
6322     }
6323     uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
6324     if (va_size == 64) {
6325         t1sz = MIN(t1sz, 39);
6326         t1sz = MAX(t1sz, 16);
6327     }
6328     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
6329         /* there is a ttbr0 region and we are in it (high bits all zero) */
6330         ttbr_select = 0;
6331     } else if (ttbr1_valid && t1sz &&
6332                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
6333         /* there is a ttbr1 region and we are in it (high bits all one) */
6334         ttbr_select = 1;
6335     } else if (!t0sz) {
6336         /* ttbr0 region is "everything not in the ttbr1 region" */
6337         ttbr_select = 0;
6338     } else if (!t1sz && ttbr1_valid) {
6339         /* ttbr1 region is "everything not in the ttbr0 region" */
6340         ttbr_select = 1;
6341     } else {
6342         /* in the gap between the two regions, this is a Translation fault */
6343         fault_type = translation_fault;
6344         goto do_fault;
6345     }
6346
6347     /* Note that QEMU ignores shareability and cacheability attributes,
6348      * so we don't need to do anything with the SH, ORGN, IRGN fields
6349      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
6350      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6351      * implement any ASID-like capability so we can ignore it (instead
6352      * we will always flush the TLB any time the ASID is changed).
6353      */
6354     if (ttbr_select == 0) {
6355         ttbr = regime_ttbr(env, mmu_idx, 0);
6356         epd = extract32(tcr->raw_tcr, 7, 1);
6357         tsz = t0sz;
6358
6359         tg = extract32(tcr->raw_tcr, 14, 2);
6360         if (tg == 1) { /* 64KB pages */
6361             granule_sz = 13;
6362         }
6363         if (tg == 2) { /* 16KB pages */
6364             granule_sz = 11;
6365         }
6366     } else {
6367         /* We should only be here if TTBR1 is valid */
6368         assert(ttbr1_valid);
6369
6370         ttbr = regime_ttbr(env, mmu_idx, 1);
6371         epd = extract32(tcr->raw_tcr, 23, 1);
6372         tsz = t1sz;
6373
6374         tg = extract32(tcr->raw_tcr, 30, 2);
6375         if (tg == 3)  { /* 64KB pages */
6376             granule_sz = 13;
6377         }
6378         if (tg == 1) { /* 16KB pages */
6379             granule_sz = 11;
6380         }
6381     }
6382
6383     /* Here we should have set up all the parameters for the translation:
6384      * va_size, ttbr, epd, tsz, granule_sz, tbi
6385      */
6386
6387     if (epd) {
6388         /* Translation table walk disabled => Translation fault on TLB miss
6389          * Note: This is always 0 on 64-bit EL2 and EL3.
6390          */
6391         goto do_fault;
6392     }
6393
6394     /* The starting level depends on the virtual address size (which can be
6395      * up to 48 bits) and the translation granule size. It indicates the number
6396      * of strides (granule_sz bits at a time) needed to consume the bits
6397      * of the input address. In the pseudocode this is:
6398      *  level = 4 - RoundUp((inputsize - grainsize) / stride)
6399      * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
6400      * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
6401      * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6402      *     = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
6403      *     = 4 - (va_size - tsz - 4) / granule_sz;
6404      */
6405     level = 4 - (va_size - tsz - 4) / granule_sz;
6406
6407     /* Clear the vaddr bits which aren't part of the within-region address,
6408      * so that we don't have to special case things when calculating the
6409      * first descriptor address.
6410      */
6411     if (tsz) {
6412         address &= (1ULL << (va_size - tsz)) - 1;
6413     }
6414
6415     descmask = (1ULL << (granule_sz + 3)) - 1;
6416
6417     /* Now we can extract the actual base address from the TTBR */
6418     descaddr = extract64(ttbr, 0, 48);
6419     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
6420
6421     /* Secure accesses start with the page table in secure memory and
6422      * can be downgraded to non-secure at any step. Non-secure accesses
6423      * remain non-secure. We implement this by just ORing in the NSTable/NS
6424      * bits at each step.
6425      */
6426     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
6427     for (;;) {
6428         uint64_t descriptor;
6429         bool nstable;
6430
6431         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
6432         descaddr &= ~7ULL;
6433         nstable = extract32(tableattrs, 4, 1);
6434         descriptor = arm_ldq_ptw(cs, descaddr, !nstable);
6435         if (!(descriptor & 1) ||
6436             (!(descriptor & 2) && (level == 3))) {
6437             /* Invalid, or the Reserved level 3 encoding */
6438             goto do_fault;
6439         }
6440         descaddr = descriptor & 0xfffffff000ULL;
6441
6442         if ((descriptor & 2) && (level < 3)) {
6443             /* Table entry. The top five bits are attributes which  may
6444              * propagate down through lower levels of the table (and
6445              * which are all arranged so that 0 means "no effect", so
6446              * we can gather them up by ORing in the bits at each level).
6447              */
6448             tableattrs |= extract64(descriptor, 59, 5);
6449             level++;
6450             continue;
6451         }
6452         /* Block entry at level 1 or 2, or page entry at level 3.
6453          * These are basically the same thing, although the number
6454          * of bits we pull in from the vaddr varies.
6455          */
6456         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
6457         descaddr |= (address & (page_size - 1));
6458         /* Extract attributes from the descriptor and merge with table attrs */
6459         attrs = extract64(descriptor, 2, 10)
6460             | (extract64(descriptor, 52, 12) << 10);
6461         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
6462         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
6463         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
6464          * means "force PL1 access only", which means forcing AP[1] to 0.
6465          */
6466         if (extract32(tableattrs, 2, 1)) {
6467             attrs &= ~(1 << 4);
6468         }
6469         attrs |= nstable << 3; /* NS */
6470         break;
6471     }
6472     /* Here descaddr is the final physical address, and attributes
6473      * are all in attrs.
6474      */
6475     fault_type = access_fault;
6476     if ((attrs & (1 << 8)) == 0) {
6477         /* Access flag */
6478         goto do_fault;
6479     }
6480
6481     ap = extract32(attrs, 4, 2);
6482     ns = extract32(attrs, 3, 1);
6483     xn = extract32(attrs, 12, 1);
6484     pxn = extract32(attrs, 11, 1);
6485
6486     *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
6487
6488     fault_type = permission_fault;
6489     if (!(*prot & (1 << access_type))) {
6490         goto do_fault;
6491     }
6492
6493     if (ns) {
6494         /* The NS bit will (as required by the architecture) have no effect if
6495          * the CPU doesn't support TZ or this is a non-secure translation
6496          * regime, because the attribute will already be non-secure.
6497          */
6498         txattrs->secure = false;
6499     }
6500     *phys_ptr = descaddr;
6501     *page_size_ptr = page_size;
6502     return false;
6503
6504 do_fault:
6505     /* Long-descriptor format IFSR/DFSR value */
6506     *fsr = (1 << 9) | (fault_type << 2) | level;
6507     return true;
6508 }
6509
6510 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
6511                                                 ARMMMUIdx mmu_idx,
6512                                                 int32_t address, int *prot)
6513 {
6514     *prot = PAGE_READ | PAGE_WRITE;
6515     switch (address) {
6516     case 0xF0000000 ... 0xFFFFFFFF:
6517         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
6518             *prot |= PAGE_EXEC;
6519         }
6520         break;
6521     case 0x00000000 ... 0x7FFFFFFF:
6522         *prot |= PAGE_EXEC;
6523         break;
6524     }
6525
6526 }
6527
6528 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
6529                                  int access_type, ARMMMUIdx mmu_idx,
6530                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
6531 {
6532     ARMCPU *cpu = arm_env_get_cpu(env);
6533     int n;
6534     bool is_user = regime_is_user(env, mmu_idx);
6535
6536     *phys_ptr = address;
6537     *prot = 0;
6538
6539     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
6540         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
6541     } else { /* MPU enabled */
6542         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
6543             /* region search */
6544             uint32_t base = env->pmsav7.drbar[n];
6545             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
6546             uint32_t rmask;
6547             bool srdis = false;
6548
6549             if (!(env->pmsav7.drsr[n] & 0x1)) {
6550                 continue;
6551             }
6552
6553             if (!rsize) {
6554                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
6555                 continue;
6556             }
6557             rsize++;
6558             rmask = (1ull << rsize) - 1;
6559
6560             if (base & rmask) {
6561                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
6562                               "to DRSR region size, mask = %" PRIx32,
6563                               base, rmask);
6564                 continue;
6565             }
6566
6567             if (address < base || address > base + rmask) {
6568                 continue;
6569             }
6570
6571             /* Region matched */
6572
6573             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
6574                 int i, snd;
6575                 uint32_t srdis_mask;
6576
6577                 rsize -= 3; /* sub region size (power of 2) */
6578                 snd = ((address - base) >> rsize) & 0x7;
6579                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
6580
6581                 srdis_mask = srdis ? 0x3 : 0x0;
6582                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
6583                     /* This will check in groups of 2, 4 and then 8, whether
6584                      * the subregion bits are consistent. rsize is incremented
6585                      * back up to give the region size, considering consistent
6586                      * adjacent subregions as one region. Stop testing if rsize
6587                      * is already big enough for an entire QEMU page.
6588                      */
6589                     int snd_rounded = snd & ~(i - 1);
6590                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
6591                                                      snd_rounded + 8, i);
6592                     if (srdis_mask ^ srdis_multi) {
6593                         break;
6594                     }
6595                     srdis_mask = (srdis_mask << i) | srdis_mask;
6596                     rsize++;
6597                 }
6598             }
6599             if (rsize < TARGET_PAGE_BITS) {
6600                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
6601                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
6602                               rsize, TARGET_PAGE_BITS);
6603                 continue;
6604             }
6605             if (srdis) {
6606                 continue;
6607             }
6608             break;
6609         }
6610
6611         if (n == -1) { /* no hits */
6612             if (cpu->pmsav7_dregion &&
6613                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
6614                 /* background fault */
6615                 *fsr = 0;
6616                 return true;
6617             }
6618             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
6619         } else { /* a MPU hit! */
6620             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
6621
6622             if (is_user) { /* User mode AP bit decoding */
6623                 switch (ap) {
6624                 case 0:
6625                 case 1:
6626                 case 5:
6627                     break; /* no access */
6628                 case 3:
6629                     *prot |= PAGE_WRITE;
6630                     /* fall through */
6631                 case 2:
6632                 case 6:
6633                     *prot |= PAGE_READ | PAGE_EXEC;
6634                     break;
6635                 default:
6636                     qemu_log_mask(LOG_GUEST_ERROR,
6637                                   "Bad value for AP bits in DRACR %"
6638                                   PRIx32 "\n", ap);
6639                 }
6640             } else { /* Priv. mode AP bits decoding */
6641                 switch (ap) {
6642                 case 0:
6643                     break; /* no access */
6644                 case 1:
6645                 case 2:
6646                 case 3:
6647                     *prot |= PAGE_WRITE;
6648                     /* fall through */
6649                 case 5:
6650                 case 6:
6651                     *prot |= PAGE_READ | PAGE_EXEC;
6652                     break;
6653                 default:
6654                     qemu_log_mask(LOG_GUEST_ERROR,
6655                                   "Bad value for AP bits in DRACR %"
6656                                   PRIx32 "\n", ap);
6657                 }
6658             }
6659
6660             /* execute never */
6661             if (env->pmsav7.dracr[n] & (1 << 12)) {
6662                 *prot &= ~PAGE_EXEC;
6663             }
6664         }
6665     }
6666
6667     *fsr = 0x00d; /* Permission fault */
6668     return !(*prot & (1 << access_type));
6669 }
6670
6671 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
6672                                  int access_type, ARMMMUIdx mmu_idx,
6673                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
6674 {
6675     int n;
6676     uint32_t mask;
6677     uint32_t base;
6678     bool is_user = regime_is_user(env, mmu_idx);
6679
6680     *phys_ptr = address;
6681     for (n = 7; n >= 0; n--) {
6682         base = env->cp15.c6_region[n];
6683         if ((base & 1) == 0) {
6684             continue;
6685         }
6686         mask = 1 << ((base >> 1) & 0x1f);
6687         /* Keep this shift separate from the above to avoid an
6688            (undefined) << 32.  */
6689         mask = (mask << 1) - 1;
6690         if (((base ^ address) & ~mask) == 0) {
6691             break;
6692         }
6693     }
6694     if (n < 0) {
6695         *fsr = 2;
6696         return true;
6697     }
6698
6699     if (access_type == 2) {
6700         mask = env->cp15.pmsav5_insn_ap;
6701     } else {
6702         mask = env->cp15.pmsav5_data_ap;
6703     }
6704     mask = (mask >> (n * 4)) & 0xf;
6705     switch (mask) {
6706     case 0:
6707         *fsr = 1;
6708         return true;
6709     case 1:
6710         if (is_user) {
6711             *fsr = 1;
6712             return true;
6713         }
6714         *prot = PAGE_READ | PAGE_WRITE;
6715         break;
6716     case 2:
6717         *prot = PAGE_READ;
6718         if (!is_user) {
6719             *prot |= PAGE_WRITE;
6720         }
6721         break;
6722     case 3:
6723         *prot = PAGE_READ | PAGE_WRITE;
6724         break;
6725     case 5:
6726         if (is_user) {
6727             *fsr = 1;
6728             return true;
6729         }
6730         *prot = PAGE_READ;
6731         break;
6732     case 6:
6733         *prot = PAGE_READ;
6734         break;
6735     default:
6736         /* Bad permission.  */
6737         *fsr = 1;
6738         return true;
6739     }
6740     *prot |= PAGE_EXEC;
6741     return false;
6742 }
6743
6744 /* get_phys_addr - get the physical address for this virtual address
6745  *
6746  * Find the physical address corresponding to the given virtual address,
6747  * by doing a translation table walk on MMU based systems or using the
6748  * MPU state on MPU based systems.
6749  *
6750  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
6751  * prot and page_size may not be filled in, and the populated fsr value provides
6752  * information on why the translation aborted, in the format of a
6753  * DFSR/IFSR fault register, with the following caveats:
6754  *  * we honour the short vs long DFSR format differences.
6755  *  * the WnR bit is never set (the caller must do this).
6756  *  * for PSMAv5 based systems we don't bother to return a full FSR format
6757  *    value.
6758  *
6759  * @env: CPUARMState
6760  * @address: virtual address to get physical address for
6761  * @access_type: 0 for read, 1 for write, 2 for execute
6762  * @mmu_idx: MMU index indicating required translation regime
6763  * @phys_ptr: set to the physical address corresponding to the virtual address
6764  * @attrs: set to the memory transaction attributes to use
6765  * @prot: set to the permissions for the page containing phys_ptr
6766  * @page_size: set to the size of the page containing phys_ptr
6767  * @fsr: set to the DFSR/IFSR value on failure
6768  */
6769 static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
6770                                  int access_type, ARMMMUIdx mmu_idx,
6771                                  hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6772                                  target_ulong *page_size, uint32_t *fsr)
6773 {
6774     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6775         /* TODO: when we support EL2 we should here call ourselves recursively
6776          * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
6777          * functions will also need changing to perform ARMMMUIdx_S2NS loads
6778          * rather than direct physical memory loads when appropriate.
6779          * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
6780          */
6781         assert(!arm_feature(env, ARM_FEATURE_EL2));
6782         mmu_idx += ARMMMUIdx_S1NSE0;
6783     }
6784
6785     /* The page table entries may downgrade secure to non-secure, but
6786      * cannot upgrade an non-secure translation regime's attributes
6787      * to secure.
6788      */
6789     attrs->secure = regime_is_secure(env, mmu_idx);
6790     attrs->user = regime_is_user(env, mmu_idx);
6791
6792     /* Fast Context Switch Extension. This doesn't exist at all in v8.
6793      * In v7 and earlier it affects all stage 1 translations.
6794      */
6795     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
6796         && !arm_feature(env, ARM_FEATURE_V8)) {
6797         if (regime_el(env, mmu_idx) == 3) {
6798             address += env->cp15.fcseidr_s;
6799         } else {
6800             address += env->cp15.fcseidr_ns;
6801         }
6802     }
6803
6804     /* pmsav7 has special handling for when MPU is disabled so call it before
6805      * the common MMU/MPU disabled check below.
6806      */
6807     if (arm_feature(env, ARM_FEATURE_MPU) &&
6808         arm_feature(env, ARM_FEATURE_V7)) {
6809         *page_size = TARGET_PAGE_SIZE;
6810         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
6811                                     phys_ptr, prot, fsr);
6812     }
6813
6814     if (regime_translation_disabled(env, mmu_idx)) {
6815         /* MMU/MPU disabled.  */
6816         *phys_ptr = address;
6817         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6818         *page_size = TARGET_PAGE_SIZE;
6819         return 0;
6820     }
6821
6822     if (arm_feature(env, ARM_FEATURE_MPU)) {
6823         /* Pre-v7 MPU */
6824         *page_size = TARGET_PAGE_SIZE;
6825         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
6826                                     phys_ptr, prot, fsr);
6827     }
6828
6829     if (regime_using_lpae_format(env, mmu_idx)) {
6830         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
6831                                   attrs, prot, page_size, fsr);
6832     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
6833         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
6834                                 attrs, prot, page_size, fsr);
6835     } else {
6836         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
6837                                 prot, page_size, fsr);
6838     }
6839 }
6840
6841 /* Walk the page table and (if the mapping exists) add the page
6842  * to the TLB. Return false on success, or true on failure. Populate
6843  * fsr with ARM DFSR/IFSR fault register format value on failure.
6844  */
6845 bool arm_tlb_fill(CPUState *cs, vaddr address,
6846                   int access_type, int mmu_idx, uint32_t *fsr)
6847 {
6848     ARMCPU *cpu = ARM_CPU(cs);
6849     CPUARMState *env = &cpu->env;
6850     hwaddr phys_addr;
6851     target_ulong page_size;
6852     int prot;
6853     int ret;
6854     MemTxAttrs attrs = {};
6855
6856     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
6857                         &attrs, &prot, &page_size, fsr);
6858     if (!ret) {
6859         /* Map a single [sub]page.  */
6860         phys_addr &= TARGET_PAGE_MASK;
6861         address &= TARGET_PAGE_MASK;
6862         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
6863                                 prot, mmu_idx, page_size);
6864         return 0;
6865     }
6866
6867     return ret;
6868 }
6869
6870 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
6871 {
6872     ARMCPU *cpu = ARM_CPU(cs);
6873     CPUARMState *env = &cpu->env;
6874     hwaddr phys_addr;
6875     target_ulong page_size;
6876     int prot;
6877     bool ret;
6878     uint32_t fsr;
6879     MemTxAttrs attrs = {};
6880
6881     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
6882                         &attrs, &prot, &page_size, &fsr);
6883
6884     if (ret) {
6885         return -1;
6886     }
6887
6888     return phys_addr;
6889 }
6890
6891 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
6892 {
6893     if ((env->uncached_cpsr & CPSR_M) == mode) {
6894         env->regs[13] = val;
6895     } else {
6896         env->banked_r13[bank_number(mode)] = val;
6897     }
6898 }
6899
6900 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
6901 {
6902     if ((env->uncached_cpsr & CPSR_M) == mode) {
6903         return env->regs[13];
6904     } else {
6905         return env->banked_r13[bank_number(mode)];
6906     }
6907 }
6908
6909 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
6910 {
6911     ARMCPU *cpu = arm_env_get_cpu(env);
6912
6913     switch (reg) {
6914     case 0: /* APSR */
6915         return xpsr_read(env) & 0xf8000000;
6916     case 1: /* IAPSR */
6917         return xpsr_read(env) & 0xf80001ff;
6918     case 2: /* EAPSR */
6919         return xpsr_read(env) & 0xff00fc00;
6920     case 3: /* xPSR */
6921         return xpsr_read(env) & 0xff00fdff;
6922     case 5: /* IPSR */
6923         return xpsr_read(env) & 0x000001ff;
6924     case 6: /* EPSR */
6925         return xpsr_read(env) & 0x0700fc00;
6926     case 7: /* IEPSR */
6927         return xpsr_read(env) & 0x0700edff;
6928     case 8: /* MSP */
6929         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
6930     case 9: /* PSP */
6931         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
6932     case 16: /* PRIMASK */
6933         return (env->daif & PSTATE_I) != 0;
6934     case 17: /* BASEPRI */
6935     case 18: /* BASEPRI_MAX */
6936         return env->v7m.basepri;
6937     case 19: /* FAULTMASK */
6938         return (env->daif & PSTATE_F) != 0;
6939     case 20: /* CONTROL */
6940         return env->v7m.control;
6941     default:
6942         /* ??? For debugging only.  */
6943         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
6944         return 0;
6945     }
6946 }
6947
6948 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
6949 {
6950     ARMCPU *cpu = arm_env_get_cpu(env);
6951
6952     switch (reg) {
6953     case 0: /* APSR */
6954         xpsr_write(env, val, 0xf8000000);
6955         break;
6956     case 1: /* IAPSR */
6957         xpsr_write(env, val, 0xf8000000);
6958         break;
6959     case 2: /* EAPSR */
6960         xpsr_write(env, val, 0xfe00fc00);
6961         break;
6962     case 3: /* xPSR */
6963         xpsr_write(env, val, 0xfe00fc00);
6964         break;
6965     case 5: /* IPSR */
6966         /* IPSR bits are readonly.  */
6967         break;
6968     case 6: /* EPSR */
6969         xpsr_write(env, val, 0x0600fc00);
6970         break;
6971     case 7: /* IEPSR */
6972         xpsr_write(env, val, 0x0600fc00);
6973         break;
6974     case 8: /* MSP */
6975         if (env->v7m.current_sp)
6976             env->v7m.other_sp = val;
6977         else
6978             env->regs[13] = val;
6979         break;
6980     case 9: /* PSP */
6981         if (env->v7m.current_sp)
6982             env->regs[13] = val;
6983         else
6984             env->v7m.other_sp = val;
6985         break;
6986     case 16: /* PRIMASK */
6987         if (val & 1) {
6988             env->daif |= PSTATE_I;
6989         } else {
6990             env->daif &= ~PSTATE_I;
6991         }
6992         break;
6993     case 17: /* BASEPRI */
6994         env->v7m.basepri = val & 0xff;
6995         break;
6996     case 18: /* BASEPRI_MAX */
6997         val &= 0xff;
6998         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
6999             env->v7m.basepri = val;
7000         break;
7001     case 19: /* FAULTMASK */
7002         if (val & 1) {
7003             env->daif |= PSTATE_F;
7004         } else {
7005             env->daif &= ~PSTATE_F;
7006         }
7007         break;
7008     case 20: /* CONTROL */
7009         env->v7m.control = val & 3;
7010         switch_v7m_sp(env, (val & 2) != 0);
7011         break;
7012     default:
7013         /* ??? For debugging only.  */
7014         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7015         return;
7016     }
7017 }
7018
7019 #endif
7020
7021 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7022 {
7023     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7024      * Note that we do not implement the (architecturally mandated)
7025      * alignment fault for attempts to use this on Device memory
7026      * (which matches the usual QEMU behaviour of not implementing either
7027      * alignment faults or any memory attribute handling).
7028      */
7029
7030     ARMCPU *cpu = arm_env_get_cpu(env);
7031     uint64_t blocklen = 4 << cpu->dcz_blocksize;
7032     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7033
7034 #ifndef CONFIG_USER_ONLY
7035     {
7036         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7037          * the block size so we might have to do more than one TLB lookup.
7038          * We know that in fact for any v8 CPU the page size is at least 4K
7039          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7040          * 1K as an artefact of legacy v5 subpage support being present in the
7041          * same QEMU executable.
7042          */
7043         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7044         void *hostaddr[maxidx];
7045         int try, i;
7046         unsigned mmu_idx = cpu_mmu_index(env);
7047         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7048
7049         for (try = 0; try < 2; try++) {
7050
7051             for (i = 0; i < maxidx; i++) {
7052                 hostaddr[i] = tlb_vaddr_to_host(env,
7053                                                 vaddr + TARGET_PAGE_SIZE * i,
7054                                                 1, mmu_idx);
7055                 if (!hostaddr[i]) {
7056                     break;
7057                 }
7058             }
7059             if (i == maxidx) {
7060                 /* If it's all in the TLB it's fair game for just writing to;
7061                  * we know we don't need to update dirty status, etc.
7062                  */
7063                 for (i = 0; i < maxidx - 1; i++) {
7064                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7065                 }
7066                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7067                 return;
7068             }
7069             /* OK, try a store and see if we can populate the tlb. This
7070              * might cause an exception if the memory isn't writable,
7071              * in which case we will longjmp out of here. We must for
7072              * this purpose use the actual register value passed to us
7073              * so that we get the fault address right.
7074              */
7075             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7076             /* Now we can populate the other TLB entries, if any */
7077             for (i = 0; i < maxidx; i++) {
7078                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7079                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7080                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7081                 }
7082             }
7083         }
7084
7085         /* Slow path (probably attempt to do this to an I/O device or
7086          * similar, or clearing of a block of code we have translations
7087          * cached for). Just do a series of byte writes as the architecture
7088          * demands. It's not worth trying to use a cpu_physical_memory_map(),
7089          * memset(), unmap() sequence here because:
7090          *  + we'd need to account for the blocksize being larger than a page
7091          *  + the direct-RAM access case is almost always going to be dealt
7092          *    with in the fastpath code above, so there's no speed benefit
7093          *  + we would have to deal with the map returning NULL because the
7094          *    bounce buffer was in use
7095          */
7096         for (i = 0; i < blocklen; i++) {
7097             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7098         }
7099     }
7100 #else
7101     memset(g2h(vaddr), 0, blocklen);
7102 #endif
7103 }
7104
7105 /* Note that signed overflow is undefined in C.  The following routines are
7106    careful to use unsigned types where modulo arithmetic is required.
7107    Failure to do so _will_ break on newer gcc.  */
7108
7109 /* Signed saturating arithmetic.  */
7110
7111 /* Perform 16-bit signed saturating addition.  */
7112 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7113 {
7114     uint16_t res;
7115
7116     res = a + b;
7117     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7118         if (a & 0x8000)
7119             res = 0x8000;
7120         else
7121             res = 0x7fff;
7122     }
7123     return res;
7124 }
7125
7126 /* Perform 8-bit signed saturating addition.  */
7127 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7128 {
7129     uint8_t res;
7130
7131     res = a + b;
7132     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7133         if (a & 0x80)
7134             res = 0x80;
7135         else
7136             res = 0x7f;
7137     }
7138     return res;
7139 }
7140
7141 /* Perform 16-bit signed saturating subtraction.  */
7142 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7143 {
7144     uint16_t res;
7145
7146     res = a - b;
7147     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7148         if (a & 0x8000)
7149             res = 0x8000;
7150         else
7151             res = 0x7fff;
7152     }
7153     return res;
7154 }
7155
7156 /* Perform 8-bit signed saturating subtraction.  */
7157 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7158 {
7159     uint8_t res;
7160
7161     res = a - b;
7162     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7163         if (a & 0x80)
7164             res = 0x80;
7165         else
7166             res = 0x7f;
7167     }
7168     return res;
7169 }
7170
7171 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7172 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7173 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
7174 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
7175 #define PFX q
7176
7177 #include "op_addsub.h"
7178
7179 /* Unsigned saturating arithmetic.  */
7180 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7181 {
7182     uint16_t res;
7183     res = a + b;
7184     if (res < a)
7185         res = 0xffff;
7186     return res;
7187 }
7188
7189 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7190 {
7191     if (a > b)
7192         return a - b;
7193     else
7194         return 0;
7195 }
7196
7197 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7198 {
7199     uint8_t res;
7200     res = a + b;
7201     if (res < a)
7202         res = 0xff;
7203     return res;
7204 }
7205
7206 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7207 {
7208     if (a > b)
7209         return a - b;
7210     else
7211         return 0;
7212 }
7213
7214 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7215 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7216 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
7217 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
7218 #define PFX uq
7219
7220 #include "op_addsub.h"
7221
7222 /* Signed modulo arithmetic.  */
7223 #define SARITH16(a, b, n, op) do { \
7224     int32_t sum; \
7225     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7226     RESULT(sum, n, 16); \
7227     if (sum >= 0) \
7228         ge |= 3 << (n * 2); \
7229     } while(0)
7230
7231 #define SARITH8(a, b, n, op) do { \
7232     int32_t sum; \
7233     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7234     RESULT(sum, n, 8); \
7235     if (sum >= 0) \
7236         ge |= 1 << n; \
7237     } while(0)
7238
7239
7240 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7241 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7242 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
7243 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
7244 #define PFX s
7245 #define ARITH_GE
7246
7247 #include "op_addsub.h"
7248
7249 /* Unsigned modulo arithmetic.  */
7250 #define ADD16(a, b, n) do { \
7251     uint32_t sum; \
7252     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7253     RESULT(sum, n, 16); \
7254     if ((sum >> 16) == 1) \
7255         ge |= 3 << (n * 2); \
7256     } while(0)
7257
7258 #define ADD8(a, b, n) do { \
7259     uint32_t sum; \
7260     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7261     RESULT(sum, n, 8); \
7262     if ((sum >> 8) == 1) \
7263         ge |= 1 << n; \
7264     } while(0)
7265
7266 #define SUB16(a, b, n) do { \
7267     uint32_t sum; \
7268     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7269     RESULT(sum, n, 16); \
7270     if ((sum >> 16) == 0) \
7271         ge |= 3 << (n * 2); \
7272     } while(0)
7273
7274 #define SUB8(a, b, n) do { \
7275     uint32_t sum; \
7276     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7277     RESULT(sum, n, 8); \
7278     if ((sum >> 8) == 0) \
7279         ge |= 1 << n; \
7280     } while(0)
7281
7282 #define PFX u
7283 #define ARITH_GE
7284
7285 #include "op_addsub.h"
7286
7287 /* Halved signed arithmetic.  */
7288 #define ADD16(a, b, n) \
7289   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7290 #define SUB16(a, b, n) \
7291   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7292 #define ADD8(a, b, n) \
7293   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7294 #define SUB8(a, b, n) \
7295   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7296 #define PFX sh
7297
7298 #include "op_addsub.h"
7299
7300 /* Halved unsigned arithmetic.  */
7301 #define ADD16(a, b, n) \
7302   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7303 #define SUB16(a, b, n) \
7304   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7305 #define ADD8(a, b, n) \
7306   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7307 #define SUB8(a, b, n) \
7308   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7309 #define PFX uh
7310
7311 #include "op_addsub.h"
7312
7313 static inline uint8_t do_usad(uint8_t a, uint8_t b)
7314 {
7315     if (a > b)
7316         return a - b;
7317     else
7318         return b - a;
7319 }
7320
7321 /* Unsigned sum of absolute byte differences.  */
7322 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
7323 {
7324     uint32_t sum;
7325     sum = do_usad(a, b);
7326     sum += do_usad(a >> 8, b >> 8);
7327     sum += do_usad(a >> 16, b >>16);
7328     sum += do_usad(a >> 24, b >> 24);
7329     return sum;
7330 }
7331
7332 /* For ARMv6 SEL instruction.  */
7333 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
7334 {
7335     uint32_t mask;
7336
7337     mask = 0;
7338     if (flags & 1)
7339         mask |= 0xff;
7340     if (flags & 2)
7341         mask |= 0xff00;
7342     if (flags & 4)
7343         mask |= 0xff0000;
7344     if (flags & 8)
7345         mask |= 0xff000000;
7346     return (a & mask) | (b & ~mask);
7347 }
7348
7349 /* VFP support.  We follow the convention used for VFP instructions:
7350    Single precision routines have a "s" suffix, double precision a
7351    "d" suffix.  */
7352
7353 /* Convert host exception flags to vfp form.  */
7354 static inline int vfp_exceptbits_from_host(int host_bits)
7355 {
7356     int target_bits = 0;
7357
7358     if (host_bits & float_flag_invalid)
7359         target_bits |= 1;
7360     if (host_bits & float_flag_divbyzero)
7361         target_bits |= 2;
7362     if (host_bits & float_flag_overflow)
7363         target_bits |= 4;
7364     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
7365         target_bits |= 8;
7366     if (host_bits & float_flag_inexact)
7367         target_bits |= 0x10;
7368     if (host_bits & float_flag_input_denormal)
7369         target_bits |= 0x80;
7370     return target_bits;
7371 }
7372
7373 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
7374 {
7375     int i;
7376     uint32_t fpscr;
7377
7378     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
7379             | (env->vfp.vec_len << 16)
7380             | (env->vfp.vec_stride << 20);
7381     i = get_float_exception_flags(&env->vfp.fp_status);
7382     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
7383     fpscr |= vfp_exceptbits_from_host(i);
7384     return fpscr;
7385 }
7386
7387 uint32_t vfp_get_fpscr(CPUARMState *env)
7388 {
7389     return HELPER(vfp_get_fpscr)(env);
7390 }
7391
7392 /* Convert vfp exception flags to target form.  */
7393 static inline int vfp_exceptbits_to_host(int target_bits)
7394 {
7395     int host_bits = 0;
7396
7397     if (target_bits & 1)
7398         host_bits |= float_flag_invalid;
7399     if (target_bits & 2)
7400         host_bits |= float_flag_divbyzero;
7401     if (target_bits & 4)
7402         host_bits |= float_flag_overflow;
7403     if (target_bits & 8)
7404         host_bits |= float_flag_underflow;
7405     if (target_bits & 0x10)
7406         host_bits |= float_flag_inexact;
7407     if (target_bits & 0x80)
7408         host_bits |= float_flag_input_denormal;
7409     return host_bits;
7410 }
7411
7412 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
7413 {
7414     int i;
7415     uint32_t changed;
7416
7417     changed = env->vfp.xregs[ARM_VFP_FPSCR];
7418     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
7419     env->vfp.vec_len = (val >> 16) & 7;
7420     env->vfp.vec_stride = (val >> 20) & 3;
7421
7422     changed ^= val;
7423     if (changed & (3 << 22)) {
7424         i = (val >> 22) & 3;
7425         switch (i) {
7426         case FPROUNDING_TIEEVEN:
7427             i = float_round_nearest_even;
7428             break;
7429         case FPROUNDING_POSINF:
7430             i = float_round_up;
7431             break;
7432         case FPROUNDING_NEGINF:
7433             i = float_round_down;
7434             break;
7435         case FPROUNDING_ZERO:
7436             i = float_round_to_zero;
7437             break;
7438         }
7439         set_float_rounding_mode(i, &env->vfp.fp_status);
7440     }
7441     if (changed & (1 << 24)) {
7442         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7443         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7444     }
7445     if (changed & (1 << 25))
7446         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
7447
7448     i = vfp_exceptbits_to_host(val);
7449     set_float_exception_flags(i, &env->vfp.fp_status);
7450     set_float_exception_flags(0, &env->vfp.standard_fp_status);
7451 }
7452
7453 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
7454 {
7455     HELPER(vfp_set_fpscr)(env, val);
7456 }
7457
7458 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
7459
7460 #define VFP_BINOP(name) \
7461 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
7462 { \
7463     float_status *fpst = fpstp; \
7464     return float32_ ## name(a, b, fpst); \
7465 } \
7466 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
7467 { \
7468     float_status *fpst = fpstp; \
7469     return float64_ ## name(a, b, fpst); \
7470 }
7471 VFP_BINOP(add)
7472 VFP_BINOP(sub)
7473 VFP_BINOP(mul)
7474 VFP_BINOP(div)
7475 VFP_BINOP(min)
7476 VFP_BINOP(max)
7477 VFP_BINOP(minnum)
7478 VFP_BINOP(maxnum)
7479 #undef VFP_BINOP
7480
7481 float32 VFP_HELPER(neg, s)(float32 a)
7482 {
7483     return float32_chs(a);
7484 }
7485
7486 float64 VFP_HELPER(neg, d)(float64 a)
7487 {
7488     return float64_chs(a);
7489 }
7490
7491 float32 VFP_HELPER(abs, s)(float32 a)
7492 {
7493     return float32_abs(a);
7494 }
7495
7496 float64 VFP_HELPER(abs, d)(float64 a)
7497 {
7498     return float64_abs(a);
7499 }
7500
7501 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
7502 {
7503     return float32_sqrt(a, &env->vfp.fp_status);
7504 }
7505
7506 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
7507 {
7508     return float64_sqrt(a, &env->vfp.fp_status);
7509 }
7510
7511 /* XXX: check quiet/signaling case */
7512 #define DO_VFP_cmp(p, type) \
7513 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
7514 { \
7515     uint32_t flags; \
7516     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
7517     case 0: flags = 0x6; break; \
7518     case -1: flags = 0x8; break; \
7519     case 1: flags = 0x2; break; \
7520     default: case 2: flags = 0x3; break; \
7521     } \
7522     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7523         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7524 } \
7525 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
7526 { \
7527     uint32_t flags; \
7528     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
7529     case 0: flags = 0x6; break; \
7530     case -1: flags = 0x8; break; \
7531     case 1: flags = 0x2; break; \
7532     default: case 2: flags = 0x3; break; \
7533     } \
7534     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7535         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7536 }
7537 DO_VFP_cmp(s, float32)
7538 DO_VFP_cmp(d, float64)
7539 #undef DO_VFP_cmp
7540
7541 /* Integer to float and float to integer conversions */
7542
7543 #define CONV_ITOF(name, fsz, sign) \
7544     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
7545 { \
7546     float_status *fpst = fpstp; \
7547     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
7548 }
7549
7550 #define CONV_FTOI(name, fsz, sign, round) \
7551 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
7552 { \
7553     float_status *fpst = fpstp; \
7554     if (float##fsz##_is_any_nan(x)) { \
7555         float_raise(float_flag_invalid, fpst); \
7556         return 0; \
7557     } \
7558     return float##fsz##_to_##sign##int32##round(x, fpst); \
7559 }
7560
7561 #define FLOAT_CONVS(name, p, fsz, sign) \
7562 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
7563 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
7564 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
7565
7566 FLOAT_CONVS(si, s, 32, )
7567 FLOAT_CONVS(si, d, 64, )
7568 FLOAT_CONVS(ui, s, 32, u)
7569 FLOAT_CONVS(ui, d, 64, u)
7570
7571 #undef CONV_ITOF
7572 #undef CONV_FTOI
7573 #undef FLOAT_CONVS
7574
7575 /* floating point conversion */
7576 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
7577 {
7578     float64 r = float32_to_float64(x, &env->vfp.fp_status);
7579     /* ARM requires that S<->D conversion of any kind of NaN generates
7580      * a quiet NaN by forcing the most significant frac bit to 1.
7581      */
7582     return float64_maybe_silence_nan(r);
7583 }
7584
7585 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
7586 {
7587     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
7588     /* ARM requires that S<->D conversion of any kind of NaN generates
7589      * a quiet NaN by forcing the most significant frac bit to 1.
7590      */
7591     return float32_maybe_silence_nan(r);
7592 }
7593
7594 /* VFP3 fixed point conversion.  */
7595 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
7596 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
7597                                      void *fpstp) \
7598 { \
7599     float_status *fpst = fpstp; \
7600     float##fsz tmp; \
7601     tmp = itype##_to_##float##fsz(x, fpst); \
7602     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
7603 }
7604
7605 /* Notice that we want only input-denormal exception flags from the
7606  * scalbn operation: the other possible flags (overflow+inexact if
7607  * we overflow to infinity, output-denormal) aren't correct for the
7608  * complete scale-and-convert operation.
7609  */
7610 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
7611 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
7612                                              uint32_t shift, \
7613                                              void *fpstp) \
7614 { \
7615     float_status *fpst = fpstp; \
7616     int old_exc_flags = get_float_exception_flags(fpst); \
7617     float##fsz tmp; \
7618     if (float##fsz##_is_any_nan(x)) { \
7619         float_raise(float_flag_invalid, fpst); \
7620         return 0; \
7621     } \
7622     tmp = float##fsz##_scalbn(x, shift, fpst); \
7623     old_exc_flags |= get_float_exception_flags(fpst) \
7624         & float_flag_input_denormal; \
7625     set_float_exception_flags(old_exc_flags, fpst); \
7626     return float##fsz##_to_##itype##round(tmp, fpst); \
7627 }
7628
7629 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
7630 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
7631 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
7632 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
7633
7634 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
7635 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
7636 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
7637
7638 VFP_CONV_FIX(sh, d, 64, 64, int16)
7639 VFP_CONV_FIX(sl, d, 64, 64, int32)
7640 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
7641 VFP_CONV_FIX(uh, d, 64, 64, uint16)
7642 VFP_CONV_FIX(ul, d, 64, 64, uint32)
7643 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
7644 VFP_CONV_FIX(sh, s, 32, 32, int16)
7645 VFP_CONV_FIX(sl, s, 32, 32, int32)
7646 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
7647 VFP_CONV_FIX(uh, s, 32, 32, uint16)
7648 VFP_CONV_FIX(ul, s, 32, 32, uint32)
7649 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
7650 #undef VFP_CONV_FIX
7651 #undef VFP_CONV_FIX_FLOAT
7652 #undef VFP_CONV_FLOAT_FIX_ROUND
7653
7654 /* Set the current fp rounding mode and return the old one.
7655  * The argument is a softfloat float_round_ value.
7656  */
7657 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
7658 {
7659     float_status *fp_status = &env->vfp.fp_status;
7660
7661     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
7662     set_float_rounding_mode(rmode, fp_status);
7663
7664     return prev_rmode;
7665 }
7666
7667 /* Set the current fp rounding mode in the standard fp status and return
7668  * the old one. This is for NEON instructions that need to change the
7669  * rounding mode but wish to use the standard FPSCR values for everything
7670  * else. Always set the rounding mode back to the correct value after
7671  * modifying it.
7672  * The argument is a softfloat float_round_ value.
7673  */
7674 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
7675 {
7676     float_status *fp_status = &env->vfp.standard_fp_status;
7677
7678     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
7679     set_float_rounding_mode(rmode, fp_status);
7680
7681     return prev_rmode;
7682 }
7683
7684 /* Half precision conversions.  */
7685 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
7686 {
7687     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7688     float32 r = float16_to_float32(make_float16(a), ieee, s);
7689     if (ieee) {
7690         return float32_maybe_silence_nan(r);
7691     }
7692     return r;
7693 }
7694
7695 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
7696 {
7697     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7698     float16 r = float32_to_float16(a, ieee, s);
7699     if (ieee) {
7700         r = float16_maybe_silence_nan(r);
7701     }
7702     return float16_val(r);
7703 }
7704
7705 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
7706 {
7707     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
7708 }
7709
7710 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
7711 {
7712     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
7713 }
7714
7715 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
7716 {
7717     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
7718 }
7719
7720 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
7721 {
7722     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
7723 }
7724
7725 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
7726 {
7727     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7728     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
7729     if (ieee) {
7730         return float64_maybe_silence_nan(r);
7731     }
7732     return r;
7733 }
7734
7735 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
7736 {
7737     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
7738     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
7739     if (ieee) {
7740         r = float16_maybe_silence_nan(r);
7741     }
7742     return float16_val(r);
7743 }
7744
7745 #define float32_two make_float32(0x40000000)
7746 #define float32_three make_float32(0x40400000)
7747 #define float32_one_point_five make_float32(0x3fc00000)
7748
7749 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
7750 {
7751     float_status *s = &env->vfp.standard_fp_status;
7752     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
7753         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
7754         if (!(float32_is_zero(a) || float32_is_zero(b))) {
7755             float_raise(float_flag_input_denormal, s);
7756         }
7757         return float32_two;
7758     }
7759     return float32_sub(float32_two, float32_mul(a, b, s), s);
7760 }
7761
7762 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
7763 {
7764     float_status *s = &env->vfp.standard_fp_status;
7765     float32 product;
7766     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
7767         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
7768         if (!(float32_is_zero(a) || float32_is_zero(b))) {
7769             float_raise(float_flag_input_denormal, s);
7770         }
7771         return float32_one_point_five;
7772     }
7773     product = float32_mul(a, b, s);
7774     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
7775 }
7776
7777 /* NEON helpers.  */
7778
7779 /* Constants 256 and 512 are used in some helpers; we avoid relying on
7780  * int->float conversions at run-time.  */
7781 #define float64_256 make_float64(0x4070000000000000LL)
7782 #define float64_512 make_float64(0x4080000000000000LL)
7783 #define float32_maxnorm make_float32(0x7f7fffff)
7784 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
7785
7786 /* Reciprocal functions
7787  *
7788  * The algorithm that must be used to calculate the estimate
7789  * is specified by the ARM ARM, see FPRecipEstimate()
7790  */
7791
7792 static float64 recip_estimate(float64 a, float_status *real_fp_status)
7793 {
7794     /* These calculations mustn't set any fp exception flags,
7795      * so we use a local copy of the fp_status.
7796      */
7797     float_status dummy_status = *real_fp_status;
7798     float_status *s = &dummy_status;
7799     /* q = (int)(a * 512.0) */
7800     float64 q = float64_mul(float64_512, a, s);
7801     int64_t q_int = float64_to_int64_round_to_zero(q, s);
7802
7803     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
7804     q = int64_to_float64(q_int, s);
7805     q = float64_add(q, float64_half, s);
7806     q = float64_div(q, float64_512, s);
7807     q = float64_div(float64_one, q, s);
7808
7809     /* s = (int)(256.0 * r + 0.5) */
7810     q = float64_mul(q, float64_256, s);
7811     q = float64_add(q, float64_half, s);
7812     q_int = float64_to_int64_round_to_zero(q, s);
7813
7814     /* return (double)s / 256.0 */
7815     return float64_div(int64_to_float64(q_int, s), float64_256, s);
7816 }
7817
7818 /* Common wrapper to call recip_estimate */
7819 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
7820 {
7821     uint64_t val64 = float64_val(num);
7822     uint64_t frac = extract64(val64, 0, 52);
7823     int64_t exp = extract64(val64, 52, 11);
7824     uint64_t sbit;
7825     float64 scaled, estimate;
7826
7827     /* Generate the scaled number for the estimate function */
7828     if (exp == 0) {
7829         if (extract64(frac, 51, 1) == 0) {
7830             exp = -1;
7831             frac = extract64(frac, 0, 50) << 2;
7832         } else {
7833             frac = extract64(frac, 0, 51) << 1;
7834         }
7835     }
7836
7837     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
7838     scaled = make_float64((0x3feULL << 52)
7839                           | extract64(frac, 44, 8) << 44);
7840
7841     estimate = recip_estimate(scaled, fpst);
7842
7843     /* Build new result */
7844     val64 = float64_val(estimate);
7845     sbit = 0x8000000000000000ULL & val64;
7846     exp = off - exp;
7847     frac = extract64(val64, 0, 52);
7848
7849     if (exp == 0) {
7850         frac = 1ULL << 51 | extract64(frac, 1, 51);
7851     } else if (exp == -1) {
7852         frac = 1ULL << 50 | extract64(frac, 2, 50);
7853         exp = 0;
7854     }
7855
7856     return make_float64(sbit | (exp << 52) | frac);
7857 }
7858
7859 static bool round_to_inf(float_status *fpst, bool sign_bit)
7860 {
7861     switch (fpst->float_rounding_mode) {
7862     case float_round_nearest_even: /* Round to Nearest */
7863         return true;
7864     case float_round_up: /* Round to +Inf */
7865         return !sign_bit;
7866     case float_round_down: /* Round to -Inf */
7867         return sign_bit;
7868     case float_round_to_zero: /* Round to Zero */
7869         return false;
7870     }
7871
7872     g_assert_not_reached();
7873 }
7874
7875 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
7876 {
7877     float_status *fpst = fpstp;
7878     float32 f32 = float32_squash_input_denormal(input, fpst);
7879     uint32_t f32_val = float32_val(f32);
7880     uint32_t f32_sbit = 0x80000000ULL & f32_val;
7881     int32_t f32_exp = extract32(f32_val, 23, 8);
7882     uint32_t f32_frac = extract32(f32_val, 0, 23);
7883     float64 f64, r64;
7884     uint64_t r64_val;
7885     int64_t r64_exp;
7886     uint64_t r64_frac;
7887
7888     if (float32_is_any_nan(f32)) {
7889         float32 nan = f32;
7890         if (float32_is_signaling_nan(f32)) {
7891             float_raise(float_flag_invalid, fpst);
7892             nan = float32_maybe_silence_nan(f32);
7893         }
7894         if (fpst->default_nan_mode) {
7895             nan =  float32_default_nan;
7896         }
7897         return nan;
7898     } else if (float32_is_infinity(f32)) {
7899         return float32_set_sign(float32_zero, float32_is_neg(f32));
7900     } else if (float32_is_zero(f32)) {
7901         float_raise(float_flag_divbyzero, fpst);
7902         return float32_set_sign(float32_infinity, float32_is_neg(f32));
7903     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
7904         /* Abs(value) < 2.0^-128 */
7905         float_raise(float_flag_overflow | float_flag_inexact, fpst);
7906         if (round_to_inf(fpst, f32_sbit)) {
7907             return float32_set_sign(float32_infinity, float32_is_neg(f32));
7908         } else {
7909             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
7910         }
7911     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
7912         float_raise(float_flag_underflow, fpst);
7913         return float32_set_sign(float32_zero, float32_is_neg(f32));
7914     }
7915
7916
7917     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
7918     r64 = call_recip_estimate(f64, 253, fpst);
7919     r64_val = float64_val(r64);
7920     r64_exp = extract64(r64_val, 52, 11);
7921     r64_frac = extract64(r64_val, 0, 52);
7922
7923     /* result = sign : result_exp<7:0> : fraction<51:29>; */
7924     return make_float32(f32_sbit |
7925                         (r64_exp & 0xff) << 23 |
7926                         extract64(r64_frac, 29, 24));
7927 }
7928
7929 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
7930 {
7931     float_status *fpst = fpstp;
7932     float64 f64 = float64_squash_input_denormal(input, fpst);
7933     uint64_t f64_val = float64_val(f64);
7934     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
7935     int64_t f64_exp = extract64(f64_val, 52, 11);
7936     float64 r64;
7937     uint64_t r64_val;
7938     int64_t r64_exp;
7939     uint64_t r64_frac;
7940
7941     /* Deal with any special cases */
7942     if (float64_is_any_nan(f64)) {
7943         float64 nan = f64;
7944         if (float64_is_signaling_nan(f64)) {
7945             float_raise(float_flag_invalid, fpst);
7946             nan = float64_maybe_silence_nan(f64);
7947         }
7948         if (fpst->default_nan_mode) {
7949             nan =  float64_default_nan;
7950         }
7951         return nan;
7952     } else if (float64_is_infinity(f64)) {
7953         return float64_set_sign(float64_zero, float64_is_neg(f64));
7954     } else if (float64_is_zero(f64)) {
7955         float_raise(float_flag_divbyzero, fpst);
7956         return float64_set_sign(float64_infinity, float64_is_neg(f64));
7957     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
7958         /* Abs(value) < 2.0^-1024 */
7959         float_raise(float_flag_overflow | float_flag_inexact, fpst);
7960         if (round_to_inf(fpst, f64_sbit)) {
7961             return float64_set_sign(float64_infinity, float64_is_neg(f64));
7962         } else {
7963             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
7964         }
7965     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
7966         float_raise(float_flag_underflow, fpst);
7967         return float64_set_sign(float64_zero, float64_is_neg(f64));
7968     }
7969
7970     r64 = call_recip_estimate(f64, 2045, fpst);
7971     r64_val = float64_val(r64);
7972     r64_exp = extract64(r64_val, 52, 11);
7973     r64_frac = extract64(r64_val, 0, 52);
7974
7975     /* result = sign : result_exp<10:0> : fraction<51:0> */
7976     return make_float64(f64_sbit |
7977                         ((r64_exp & 0x7ff) << 52) |
7978                         r64_frac);
7979 }
7980
7981 /* The algorithm that must be used to calculate the estimate
7982  * is specified by the ARM ARM.
7983  */
7984 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
7985 {
7986     /* These calculations mustn't set any fp exception flags,
7987      * so we use a local copy of the fp_status.
7988      */
7989     float_status dummy_status = *real_fp_status;
7990     float_status *s = &dummy_status;
7991     float64 q;
7992     int64_t q_int;
7993
7994     if (float64_lt(a, float64_half, s)) {
7995         /* range 0.25 <= a < 0.5 */
7996
7997         /* a in units of 1/512 rounded down */
7998         /* q0 = (int)(a * 512.0);  */
7999         q = float64_mul(float64_512, a, s);
8000         q_int = float64_to_int64_round_to_zero(q, s);
8001
8002         /* reciprocal root r */
8003         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
8004         q = int64_to_float64(q_int, s);
8005         q = float64_add(q, float64_half, s);
8006         q = float64_div(q, float64_512, s);
8007         q = float64_sqrt(q, s);
8008         q = float64_div(float64_one, q, s);
8009     } else {
8010         /* range 0.5 <= a < 1.0 */
8011
8012         /* a in units of 1/256 rounded down */
8013         /* q1 = (int)(a * 256.0); */
8014         q = float64_mul(float64_256, a, s);
8015         int64_t q_int = float64_to_int64_round_to_zero(q, s);
8016
8017         /* reciprocal root r */
8018         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8019         q = int64_to_float64(q_int, s);
8020         q = float64_add(q, float64_half, s);
8021         q = float64_div(q, float64_256, s);
8022         q = float64_sqrt(q, s);
8023         q = float64_div(float64_one, q, s);
8024     }
8025     /* r in units of 1/256 rounded to nearest */
8026     /* s = (int)(256.0 * r + 0.5); */
8027
8028     q = float64_mul(q, float64_256,s );
8029     q = float64_add(q, float64_half, s);
8030     q_int = float64_to_int64_round_to_zero(q, s);
8031
8032     /* return (double)s / 256.0;*/
8033     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8034 }
8035
8036 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8037 {
8038     float_status *s = fpstp;
8039     float32 f32 = float32_squash_input_denormal(input, s);
8040     uint32_t val = float32_val(f32);
8041     uint32_t f32_sbit = 0x80000000 & val;
8042     int32_t f32_exp = extract32(val, 23, 8);
8043     uint32_t f32_frac = extract32(val, 0, 23);
8044     uint64_t f64_frac;
8045     uint64_t val64;
8046     int result_exp;
8047     float64 f64;
8048
8049     if (float32_is_any_nan(f32)) {
8050         float32 nan = f32;
8051         if (float32_is_signaling_nan(f32)) {
8052             float_raise(float_flag_invalid, s);
8053             nan = float32_maybe_silence_nan(f32);
8054         }
8055         if (s->default_nan_mode) {
8056             nan =  float32_default_nan;
8057         }
8058         return nan;
8059     } else if (float32_is_zero(f32)) {
8060         float_raise(float_flag_divbyzero, s);
8061         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8062     } else if (float32_is_neg(f32)) {
8063         float_raise(float_flag_invalid, s);
8064         return float32_default_nan;
8065     } else if (float32_is_infinity(f32)) {
8066         return float32_zero;
8067     }
8068
8069     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8070      * preserving the parity of the exponent.  */
8071
8072     f64_frac = ((uint64_t) f32_frac) << 29;
8073     if (f32_exp == 0) {
8074         while (extract64(f64_frac, 51, 1) == 0) {
8075             f64_frac = f64_frac << 1;
8076             f32_exp = f32_exp-1;
8077         }
8078         f64_frac = extract64(f64_frac, 0, 51) << 1;
8079     }
8080
8081     if (extract64(f32_exp, 0, 1) == 0) {
8082         f64 = make_float64(((uint64_t) f32_sbit) << 32
8083                            | (0x3feULL << 52)
8084                            | f64_frac);
8085     } else {
8086         f64 = make_float64(((uint64_t) f32_sbit) << 32
8087                            | (0x3fdULL << 52)
8088                            | f64_frac);
8089     }
8090
8091     result_exp = (380 - f32_exp) / 2;
8092
8093     f64 = recip_sqrt_estimate(f64, s);
8094
8095     val64 = float64_val(f64);
8096
8097     val = ((result_exp & 0xff) << 23)
8098         | ((val64 >> 29)  & 0x7fffff);
8099     return make_float32(val);
8100 }
8101
8102 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8103 {
8104     float_status *s = fpstp;
8105     float64 f64 = float64_squash_input_denormal(input, s);
8106     uint64_t val = float64_val(f64);
8107     uint64_t f64_sbit = 0x8000000000000000ULL & val;
8108     int64_t f64_exp = extract64(val, 52, 11);
8109     uint64_t f64_frac = extract64(val, 0, 52);
8110     int64_t result_exp;
8111     uint64_t result_frac;
8112
8113     if (float64_is_any_nan(f64)) {
8114         float64 nan = f64;
8115         if (float64_is_signaling_nan(f64)) {
8116             float_raise(float_flag_invalid, s);
8117             nan = float64_maybe_silence_nan(f64);
8118         }
8119         if (s->default_nan_mode) {
8120             nan =  float64_default_nan;
8121         }
8122         return nan;
8123     } else if (float64_is_zero(f64)) {
8124         float_raise(float_flag_divbyzero, s);
8125         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8126     } else if (float64_is_neg(f64)) {
8127         float_raise(float_flag_invalid, s);
8128         return float64_default_nan;
8129     } else if (float64_is_infinity(f64)) {
8130         return float64_zero;
8131     }
8132
8133     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8134      * preserving the parity of the exponent.  */
8135
8136     if (f64_exp == 0) {
8137         while (extract64(f64_frac, 51, 1) == 0) {
8138             f64_frac = f64_frac << 1;
8139             f64_exp = f64_exp - 1;
8140         }
8141         f64_frac = extract64(f64_frac, 0, 51) << 1;
8142     }
8143
8144     if (extract64(f64_exp, 0, 1) == 0) {
8145         f64 = make_float64(f64_sbit
8146                            | (0x3feULL << 52)
8147                            | f64_frac);
8148     } else {
8149         f64 = make_float64(f64_sbit
8150                            | (0x3fdULL << 52)
8151                            | f64_frac);
8152     }
8153
8154     result_exp = (3068 - f64_exp) / 2;
8155
8156     f64 = recip_sqrt_estimate(f64, s);
8157
8158     result_frac = extract64(float64_val(f64), 0, 52);
8159
8160     return make_float64(f64_sbit |
8161                         ((result_exp & 0x7ff) << 52) |
8162                         result_frac);
8163 }
8164
8165 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8166 {
8167     float_status *s = fpstp;
8168     float64 f64;
8169
8170     if ((a & 0x80000000) == 0) {
8171         return 0xffffffff;
8172     }
8173
8174     f64 = make_float64((0x3feULL << 52)
8175                        | ((int64_t)(a & 0x7fffffff) << 21));
8176
8177     f64 = recip_estimate(f64, s);
8178
8179     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8180 }
8181
8182 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8183 {
8184     float_status *fpst = fpstp;
8185     float64 f64;
8186
8187     if ((a & 0xc0000000) == 0) {
8188         return 0xffffffff;
8189     }
8190
8191     if (a & 0x80000000) {
8192         f64 = make_float64((0x3feULL << 52)
8193                            | ((uint64_t)(a & 0x7fffffff) << 21));
8194     } else { /* bits 31-30 == '01' */
8195         f64 = make_float64((0x3fdULL << 52)
8196                            | ((uint64_t)(a & 0x3fffffff) << 22));
8197     }
8198
8199     f64 = recip_sqrt_estimate(f64, fpst);
8200
8201     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8202 }
8203
8204 /* VFPv4 fused multiply-accumulate */
8205 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8206 {
8207     float_status *fpst = fpstp;
8208     return float32_muladd(a, b, c, 0, fpst);
8209 }
8210
8211 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
8212 {
8213     float_status *fpst = fpstp;
8214     return float64_muladd(a, b, c, 0, fpst);
8215 }
8216
8217 /* ARMv8 round to integral */
8218 float32 HELPER(rints_exact)(float32 x, void *fp_status)
8219 {
8220     return float32_round_to_int(x, fp_status);
8221 }
8222
8223 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
8224 {
8225     return float64_round_to_int(x, fp_status);
8226 }
8227
8228 float32 HELPER(rints)(float32 x, void *fp_status)
8229 {
8230     int old_flags = get_float_exception_flags(fp_status), new_flags;
8231     float32 ret;
8232
8233     ret = float32_round_to_int(x, fp_status);
8234
8235     /* Suppress any inexact exceptions the conversion produced */
8236     if (!(old_flags & float_flag_inexact)) {
8237         new_flags = get_float_exception_flags(fp_status);
8238         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8239     }
8240
8241     return ret;
8242 }
8243
8244 float64 HELPER(rintd)(float64 x, void *fp_status)
8245 {
8246     int old_flags = get_float_exception_flags(fp_status), new_flags;
8247     float64 ret;
8248
8249     ret = float64_round_to_int(x, fp_status);
8250
8251     new_flags = get_float_exception_flags(fp_status);
8252
8253     /* Suppress any inexact exceptions the conversion produced */
8254     if (!(old_flags & float_flag_inexact)) {
8255         new_flags = get_float_exception_flags(fp_status);
8256         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8257     }
8258
8259     return ret;
8260 }
8261
8262 /* Convert ARM rounding mode to softfloat */
8263 int arm_rmode_to_sf(int rmode)
8264 {
8265     switch (rmode) {
8266     case FPROUNDING_TIEAWAY:
8267         rmode = float_round_ties_away;
8268         break;
8269     case FPROUNDING_ODD:
8270         /* FIXME: add support for TIEAWAY and ODD */
8271         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
8272                       rmode);
8273     case FPROUNDING_TIEEVEN:
8274     default:
8275         rmode = float_round_nearest_even;
8276         break;
8277     case FPROUNDING_POSINF:
8278         rmode = float_round_up;
8279         break;
8280     case FPROUNDING_NEGINF:
8281         rmode = float_round_down;
8282         break;
8283     case FPROUNDING_ZERO:
8284         rmode = float_round_to_zero;
8285         break;
8286     }
8287     return rmode;
8288 }
8289
8290 /* CRC helpers.
8291  * The upper bytes of val (above the number specified by 'bytes') must have
8292  * been zeroed out by the caller.
8293  */
8294 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
8295 {
8296     uint8_t buf[4];
8297
8298     stl_le_p(buf, val);
8299
8300     /* zlib crc32 converts the accumulator and output to one's complement.  */
8301     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
8302 }
8303
8304 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
8305 {
8306     uint8_t buf[4];
8307
8308     stl_le_p(buf, val);
8309
8310     /* Linux crc32c converts the output to one's complement.  */
8311     return crc32c(acc, buf, bytes) ^ 0xffffffff;
8312 }