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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / linux-user / main.c
blob7c8234fbc5d746713a48d35aea0e57ab49116bb0
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu.h"
25 #include "qemu-common.h"
26 #include "cpu.h"
27 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
28 #include "vsyscall.h"
29 #endif
30 #include "tcg.h"
31 #include "qemu/timer.h"
32 #include "qemu/envlist.h"
33 #include "elf.h"
34
35 char *exec_path;
36
37 int singlestep;
38 const char *filename;
39 const char *argv0;
40 int gdbstub_port;
41 envlist_t *envlist;
42 static const char *cpu_model;
43 unsigned long mmap_min_addr;
44 uintptr_t guest_base;
45 int have_guest_base;
46 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
47 /*
48 * When running 32-on-64 we should make sure we can fit all of the possible
49 * guest address space into a contiguous chunk of virtual host memory.
50 *
51 * This way we will never overlap with our own libraries or binaries or stack
52 * or anything else that QEMU maps.
53 */
54 # ifdef TARGET_MIPS
55 /* MIPS only supports 31 bits of virtual address space for user space */
56 uintptr_t reserved_va = 0x77000000;
57 # else
58 uintptr_t reserved_va = 0xf7000000;
59 # endif
60 #else
61 uintptr_t reserved_va;
62 #endif
63
64 static void usage(void);
65
66 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
67 const char *qemu_uname_release;
68
69 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
70 we allocate a bigger stack. Need a better solution, for example
71 by remapping the process stack directly at the right place */
72 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
73
74 void gemu_log(const char *fmt, ...)
75 {
76 va_list ap;
77
78 va_start(ap, fmt);
79 vfprintf(stderr, fmt, ap);
80 va_end(ap);
81 }
82
83 #if defined(TARGET_I386)
84 int cpu_get_pic_interrupt(CPUX86State *env)
85 {
86 return -1;
87 }
88 #endif
89
90 /***********************************************************/
91 /* Helper routines for implementing atomic operations. */
92
93 /* To implement exclusive operations we force all cpus to syncronise.
94 We don't require a full sync, only that no cpus are executing guest code.
95 The alternative is to map target atomic ops onto host equivalents,
96 which requires quite a lot of per host/target work. */
97 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
98 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
99 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
100 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
101 static int pending_cpus;
102
103 /* Make sure everything is in a consistent state for calling fork(). */
104 void fork_start(void)
105 {
106 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
107 pthread_mutex_lock(&exclusive_lock);
108 mmap_fork_start();
109 }
110
111 void fork_end(int child)
112 {
113 mmap_fork_end(child);
114 if (child) {
115 CPUState *cpu, *next_cpu;
116 /* Child processes created by fork() only have a single thread.
117 Discard information about the parent threads. */
118 CPU_FOREACH_SAFE(cpu, next_cpu) {
119 if (cpu != thread_cpu) {
120 QTAILQ_REMOVE(&cpus, thread_cpu, node);
121 }
122 }
123 pending_cpus = 0;
124 pthread_mutex_init(&exclusive_lock, NULL);
125 pthread_mutex_init(&cpu_list_mutex, NULL);
126 pthread_cond_init(&exclusive_cond, NULL);
127 pthread_cond_init(&exclusive_resume, NULL);
128 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
129 gdbserver_fork(thread_cpu);
130 } else {
131 pthread_mutex_unlock(&exclusive_lock);
132 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
133 }
134 }
135
136 /* Wait for pending exclusive operations to complete. The exclusive lock
137 must be held. */
138 static inline void exclusive_idle(void)
139 {
140 while (pending_cpus) {
141 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
142 }
143 }
144
145 /* Start an exclusive operation.
146 Must only be called from outside cpu_arm_exec. */
147 static inline void start_exclusive(void)
148 {
149 CPUState *other_cpu;
150
151 pthread_mutex_lock(&exclusive_lock);
152 exclusive_idle();
153
154 pending_cpus = 1;
155 /* Make all other cpus stop executing. */
156 CPU_FOREACH(other_cpu) {
157 if (other_cpu->running) {
158 pending_cpus++;
159 cpu_exit(other_cpu);
160 }
161 }
162 if (pending_cpus > 1) {
163 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
164 }
165 }
166
167 /* Finish an exclusive operation. */
168 static inline void __attribute__((unused)) end_exclusive(void)
169 {
170 pending_cpus = 0;
171 pthread_cond_broadcast(&exclusive_resume);
172 pthread_mutex_unlock(&exclusive_lock);
173 }
174
175 /* Wait for exclusive ops to finish, and begin cpu execution. */
176 static inline void cpu_exec_start(CPUState *cpu)
177 {
178 pthread_mutex_lock(&exclusive_lock);
179 exclusive_idle();
180 cpu->running = true;
181 pthread_mutex_unlock(&exclusive_lock);
182 }
183
184 /* Mark cpu as not executing, and release pending exclusive ops. */
185 static inline void cpu_exec_end(CPUState *cpu)
186 {
187 pthread_mutex_lock(&exclusive_lock);
188 cpu->running = false;
189 if (pending_cpus > 1) {
190 pending_cpus--;
191 if (pending_cpus == 1) {
192 pthread_cond_signal(&exclusive_cond);
193 }
194 }
195 exclusive_idle();
196 pthread_mutex_unlock(&exclusive_lock);
197 }
198
199 void cpu_list_lock(void)
200 {
201 pthread_mutex_lock(&cpu_list_mutex);
202 }
203
204 void cpu_list_unlock(void)
205 {
206 pthread_mutex_unlock(&cpu_list_mutex);
207 }
208
209
210 #ifdef TARGET_I386
211 /***********************************************************/
212 /* CPUX86 core interface */
213
214 uint64_t cpu_get_tsc(CPUX86State *env)
215 {
216 return cpu_get_real_ticks();
217 }
218
219 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
220 int flags)
221 {
222 unsigned int e1, e2;
223 uint32_t *p;
224 e1 = (addr << 16) | (limit & 0xffff);
225 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
226 e2 |= flags;
227 p = ptr;
228 p[0] = tswap32(e1);
229 p[1] = tswap32(e2);
230 }
231
232 static uint64_t *idt_table;
233 #ifdef TARGET_X86_64
234 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
235 uint64_t addr, unsigned int sel)
236 {
237 uint32_t *p, e1, e2;
238 e1 = (addr & 0xffff) | (sel << 16);
239 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
240 p = ptr;
241 p[0] = tswap32(e1);
242 p[1] = tswap32(e2);
243 p[2] = tswap32(addr >> 32);
244 p[3] = 0;
245 }
246 /* only dpl matters as we do only user space emulation */
247 static void set_idt(int n, unsigned int dpl)
248 {
249 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
250 }
251 #else
252 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
253 uint32_t addr, unsigned int sel)
254 {
255 uint32_t *p, e1, e2;
256 e1 = (addr & 0xffff) | (sel << 16);
257 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
258 p = ptr;
259 p[0] = tswap32(e1);
260 p[1] = tswap32(e2);
261 }
262
263 /* only dpl matters as we do only user space emulation */
264 static void set_idt(int n, unsigned int dpl)
265 {
266 set_gate(idt_table + n, 0, dpl, 0, 0);
267 }
268 #endif
269
270 void cpu_loop(CPUX86State *env)
271 {
272 CPUState *cs = CPU(x86_env_get_cpu(env));
273 int trapnr;
274 abi_ulong pc;
275 target_siginfo_t info;
276 #ifdef TARGET_X86_64
277 int syscall_num;
278 uint64_t val;
279 #endif
280
281 for(;;) {
282 cpu_exec_start(cs);
283 trapnr = cpu_x86_exec(cs);
284 cpu_exec_end(cs);
285 switch(trapnr) {
286 case 0x80:
287 /* linux syscall from int $0x80 */
288 env->regs[R_EAX] = do_syscall(env,
289 env->regs[R_EAX],
290 env->regs[R_EBX],
291 env->regs[R_ECX],
292 env->regs[R_EDX],
293 env->regs[R_ESI],
294 env->regs[R_EDI],
295 env->regs[R_EBP],
296 0, 0);
297 break;
298 #ifndef TARGET_ABI32
299 case EXCP_SYSCALL:
300 /* linux syscall from syscall instruction */
301 env->regs[R_EAX] = do_syscall(env,
302 env->regs[R_EAX],
303 env->regs[R_EDI],
304 env->regs[R_ESI],
305 env->regs[R_EDX],
306 env->regs[10],
307 env->regs[8],
308 env->regs[9],
309 0, 0);
310 break;
311 #endif
312 #ifdef TARGET_X86_64
313 case EXCP_VSYSCALL:
314 switch (env->eip) {
315 case TARGET_VSYSCALL_ADDR(__NR_vgettimeofday):
316 syscall_num = __NR_gettimeofday;
317 break;
318 case TARGET_VSYSCALL_ADDR(__NR_vtime):
319 #ifdef __NR_time
320 syscall_num = __NR_time;
321 #else
322 /* XXX: not yet implemented (arm eabi host) */
323 cpu_abort(cs, "Unimplemented vsyscall vtime");
324 #endif
325 break;
326 case TARGET_VSYSCALL_ADDR(__NR_vgetcpu):
327 /* XXX: not yet implemented */
328 cpu_abort(cs, "Unimplemented vsyscall vgetcpu");
329 break;
330 default:
331 cpu_abort(cs,
332 "Invalid vsyscall to address " TARGET_FMT_lx "\n",
333 env->eip);
334 }
335 env->regs[R_EAX] = do_syscall(env,
336 syscall_num,
337 env->regs[R_EDI],
338 env->regs[R_ESI],
339 env->regs[R_EDX],
340 env->regs[10],
341 env->regs[8],
342 env->regs[9],
343 0, 0);
344 /* simulate a ret */
345 get_user_u64(val, env->regs[R_ESP]);
346 env->eip = val;
347 env->regs[R_ESP] += 8;
348 break;
349 #endif
350 case EXCP0B_NOSEG:
351 case EXCP0C_STACK:
352 info.si_signo = TARGET_SIGBUS;
353 info.si_errno = 0;
354 info.si_code = TARGET_SI_KERNEL;
355 info._sifields._sigfault._addr = 0;
356 queue_signal(env, info.si_signo, &info);
357 break;
358 case EXCP0D_GPF:
359 /* XXX: potential problem if ABI32 */
360 #ifndef TARGET_X86_64
361 if (env->eflags & VM_MASK) {
362 handle_vm86_fault(env);
363 } else
364 #endif
365 {
366 info.si_signo = TARGET_SIGSEGV;
367 info.si_errno = 0;
368 info.si_code = TARGET_SI_KERNEL;
369 info._sifields._sigfault._addr = 0;
370 queue_signal(env, info.si_signo, &info);
371 }
372 break;
373 case EXCP0E_PAGE:
374 info.si_signo = TARGET_SIGSEGV;
375 info.si_errno = 0;
376 if (!(env->error_code & 1))
377 info.si_code = TARGET_SEGV_MAPERR;
378 else
379 info.si_code = TARGET_SEGV_ACCERR;
380 info._sifields._sigfault._addr = env->cr[2];
381 queue_signal(env, info.si_signo, &info);
382 break;
383 case EXCP00_DIVZ:
384 #ifndef TARGET_X86_64
385 if (env->eflags & VM_MASK) {
386 handle_vm86_trap(env, trapnr);
387 } else
388 #endif
389 {
390 /* division by zero */
391 info.si_signo = TARGET_SIGFPE;
392 info.si_errno = 0;
393 info.si_code = TARGET_FPE_INTDIV;
394 info._sifields._sigfault._addr = env->eip;
395 queue_signal(env, info.si_signo, &info);
396 }
397 break;
398 case EXCP01_DB:
399 case EXCP03_INT3:
400 #ifndef TARGET_X86_64
401 if (env->eflags & VM_MASK) {
402 handle_vm86_trap(env, trapnr);
403 } else
404 #endif
405 {
406 info.si_signo = TARGET_SIGTRAP;
407 info.si_errno = 0;
408 if (trapnr == EXCP01_DB) {
409 info.si_code = TARGET_TRAP_BRKPT;
410 info._sifields._sigfault._addr = env->eip;
411 } else {
412 info.si_code = TARGET_SI_KERNEL;
413 info._sifields._sigfault._addr = 0;
414 }
415 queue_signal(env, info.si_signo, &info);
416 }
417 break;
418 case EXCP04_INTO:
419 case EXCP05_BOUND:
420 #ifndef TARGET_X86_64
421 if (env->eflags & VM_MASK) {
422 handle_vm86_trap(env, trapnr);
423 } else
424 #endif
425 {
426 info.si_signo = TARGET_SIGSEGV;
427 info.si_errno = 0;
428 info.si_code = TARGET_SI_KERNEL;
429 info._sifields._sigfault._addr = 0;
430 queue_signal(env, info.si_signo, &info);
431 }
432 break;
433 case EXCP06_ILLOP:
434 info.si_signo = TARGET_SIGILL;
435 info.si_errno = 0;
436 info.si_code = TARGET_ILL_ILLOPN;
437 info._sifields._sigfault._addr = env->eip;
438 queue_signal(env, info.si_signo, &info);
439 break;
440 case EXCP_INTERRUPT:
441 /* just indicate that signals should be handled asap */
442 break;
443 case EXCP_DEBUG:
444 {
445 int sig;
446
447 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
448 if (sig)
449 {
450 info.si_signo = sig;
451 info.si_errno = 0;
452 info.si_code = TARGET_TRAP_BRKPT;
453 queue_signal(env, info.si_signo, &info);
454 }
455 }
456 break;
457 default:
458 pc = env->segs[R_CS].base + env->eip;
459 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
460 (long)pc, trapnr);
461 abort();
462 }
463 process_pending_signals(env);
464 }
465 }
466 #endif
467
468 #ifdef TARGET_ARM
469
470 #define get_user_code_u32(x, gaddr, doswap) \
471 ({ abi_long __r = get_user_u32((x), (gaddr)); \
472 if (!__r && (doswap)) { \
473 (x) = bswap32(x); \
474 } \
475 __r; \
476 })
477
478 #define get_user_code_u16(x, gaddr, doswap) \
479 ({ abi_long __r = get_user_u16((x), (gaddr)); \
480 if (!__r && (doswap)) { \
481 (x) = bswap16(x); \
482 } \
483 __r; \
484 })
485
486 #ifdef TARGET_ABI32
487 /* Commpage handling -- there is no commpage for AArch64 */
488
489 /*
490 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
491 * Input:
492 * r0 = pointer to oldval
493 * r1 = pointer to newval
494 * r2 = pointer to target value
495 *
496 * Output:
497 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
498 * C set if *ptr was changed, clear if no exchange happened
499 *
500 * Note segv's in kernel helpers are a bit tricky, we can set the
501 * data address sensibly but the PC address is just the entry point.
502 */
503 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
504 {
505 uint64_t oldval, newval, val;
506 uint32_t addr, cpsr;
507 target_siginfo_t info;
508
509 /* Based on the 32 bit code in do_kernel_trap */
510
511 /* XXX: This only works between threads, not between processes.
512 It's probably possible to implement this with native host
513 operations. However things like ldrex/strex are much harder so
514 there's not much point trying. */
515 start_exclusive();
516 cpsr = cpsr_read(env);
517 addr = env->regs[2];
518
519 if (get_user_u64(oldval, env->regs[0])) {
520 env->exception.vaddress = env->regs[0];
521 goto segv;
522 };
523
524 if (get_user_u64(newval, env->regs[1])) {
525 env->exception.vaddress = env->regs[1];
526 goto segv;
527 };
528
529 if (get_user_u64(val, addr)) {
530 env->exception.vaddress = addr;
531 goto segv;
532 }
533
534 if (val == oldval) {
535 val = newval;
536
537 if (put_user_u64(val, addr)) {
538 env->exception.vaddress = addr;
539 goto segv;
540 };
541
542 env->regs[0] = 0;
543 cpsr |= CPSR_C;
544 } else {
545 env->regs[0] = -1;
546 cpsr &= ~CPSR_C;
547 }
548 cpsr_write(env, cpsr, CPSR_C);
549 end_exclusive();
550 return;
551
552 segv:
553 end_exclusive();
554 /* We get the PC of the entry address - which is as good as anything,
555 on a real kernel what you get depends on which mode it uses. */
556 info.si_signo = TARGET_SIGSEGV;
557 info.si_errno = 0;
558 /* XXX: check env->error_code */
559 info.si_code = TARGET_SEGV_MAPERR;
560 info._sifields._sigfault._addr = env->exception.vaddress;
561 queue_signal(env, info.si_signo, &info);
562 }
563
564 /* Handle a jump to the kernel code page. */
565 static int
566 do_kernel_trap(CPUARMState *env)
567 {
568 uint32_t addr;
569 uint32_t cpsr;
570 uint32_t val;
571
572 switch (env->regs[15]) {
573 case 0xffff0fa0: /* __kernel_memory_barrier */
574 /* ??? No-op. Will need to do better for SMP. */
575 break;
576 case 0xffff0fc0: /* __kernel_cmpxchg */
577 /* XXX: This only works between threads, not between processes.
578 It's probably possible to implement this with native host
579 operations. However things like ldrex/strex are much harder so
580 there's not much point trying. */
581 start_exclusive();
582 cpsr = cpsr_read(env);
583 addr = env->regs[2];
584 /* FIXME: This should SEGV if the access fails. */
585 if (get_user_u32(val, addr))
586 val = ~env->regs[0];
587 if (val == env->regs[0]) {
588 val = env->regs[1];
589 /* FIXME: Check for segfaults. */
590 put_user_u32(val, addr);
591 env->regs[0] = 0;
592 cpsr |= CPSR_C;
593 } else {
594 env->regs[0] = -1;
595 cpsr &= ~CPSR_C;
596 }
597 cpsr_write(env, cpsr, CPSR_C);
598 end_exclusive();
599 break;
600 case 0xffff0fe0: /* __kernel_get_tls */
601 env->regs[0] = cpu_get_tls(env);
602 break;
603 case 0xffff0f60: /* __kernel_cmpxchg64 */
604 arm_kernel_cmpxchg64_helper(env);
605 break;
606
607 default:
608 return 1;
609 }
610 /* Jump back to the caller. */
611 addr = env->regs[14];
612 if (addr & 1) {
613 env->thumb = 1;
614 addr &= ~1;
615 }
616 env->regs[15] = addr;
617
618 return 0;
619 }
620
621 /* Store exclusive handling for AArch32 */
622 static int do_strex(CPUARMState *env)
623 {
624 uint64_t val;
625 int size;
626 int rc = 1;
627 int segv = 0;
628 uint32_t addr;
629 start_exclusive();
630 if (env->exclusive_addr != env->exclusive_test) {
631 goto fail;
632 }
633 /* We know we're always AArch32 so the address is in uint32_t range
634 * unless it was the -1 exclusive-monitor-lost value (which won't
635 * match exclusive_test above).
636 */
637 assert(extract64(env->exclusive_addr, 32, 32) == 0);
638 addr = env->exclusive_addr;
639 size = env->exclusive_info & 0xf;
640 switch (size) {
641 case 0:
642 segv = get_user_u8(val, addr);
643 break;
644 case 1:
645 segv = get_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = get_user_u32(val, addr);
650 break;
651 default:
652 abort();
653 }
654 if (segv) {
655 env->exception.vaddress = addr;
656 goto done;
657 }
658 if (size == 3) {
659 uint32_t valhi;
660 segv = get_user_u32(valhi, addr + 4);
661 if (segv) {
662 env->exception.vaddress = addr + 4;
663 goto done;
664 }
665 val = deposit64(val, 32, 32, valhi);
666 }
667 if (val != env->exclusive_val) {
668 goto fail;
669 }
670
671 val = env->regs[(env->exclusive_info >> 8) & 0xf];
672 switch (size) {
673 case 0:
674 segv = put_user_u8(val, addr);
675 break;
676 case 1:
677 segv = put_user_u16(val, addr);
678 break;
679 case 2:
680 case 3:
681 segv = put_user_u32(val, addr);
682 break;
683 }
684 if (segv) {
685 env->exception.vaddress = addr;
686 goto done;
687 }
688 if (size == 3) {
689 val = env->regs[(env->exclusive_info >> 12) & 0xf];
690 segv = put_user_u32(val, addr + 4);
691 if (segv) {
692 env->exception.vaddress = addr + 4;
693 goto done;
694 }
695 }
696 rc = 0;
697 fail:
698 env->regs[15] += 4;
699 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
700 done:
701 end_exclusive();
702 return segv;
703 }
704
705 void cpu_loop(CPUARMState *env)
706 {
707 CPUState *cs = CPU(arm_env_get_cpu(env));
708 int trapnr;
709 unsigned int n, insn;
710 target_siginfo_t info;
711 uint32_t addr;
712
713 for(;;) {
714 cpu_exec_start(cs);
715 trapnr = cpu_arm_exec(cs);
716 cpu_exec_end(cs);
717 switch(trapnr) {
718 case EXCP_UDEF:
719 {
720 TaskState *ts = cs->opaque;
721 uint32_t opcode;
722 int rc;
723
724 /* we handle the FPU emulation here, as Linux */
725 /* we get the opcode */
726 /* FIXME - what to do if get_user() fails? */
727 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
728
729 rc = EmulateAll(opcode, &ts->fpa, env);
730 if (rc == 0) { /* illegal instruction */
731 info.si_signo = TARGET_SIGILL;
732 info.si_errno = 0;
733 info.si_code = TARGET_ILL_ILLOPN;
734 info._sifields._sigfault._addr = env->regs[15];
735 queue_signal(env, info.si_signo, &info);
736 } else if (rc < 0) { /* FP exception */
737 int arm_fpe=0;
738
739 /* translate softfloat flags to FPSR flags */
740 if (-rc & float_flag_invalid)
741 arm_fpe |= BIT_IOC;
742 if (-rc & float_flag_divbyzero)
743 arm_fpe |= BIT_DZC;
744 if (-rc & float_flag_overflow)
745 arm_fpe |= BIT_OFC;
746 if (-rc & float_flag_underflow)
747 arm_fpe |= BIT_UFC;
748 if (-rc & float_flag_inexact)
749 arm_fpe |= BIT_IXC;
750
751 FPSR fpsr = ts->fpa.fpsr;
752 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
753
754 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
755 info.si_signo = TARGET_SIGFPE;
756 info.si_errno = 0;
757
758 /* ordered by priority, least first */
759 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
760 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
761 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
762 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
763 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
764
765 info._sifields._sigfault._addr = env->regs[15];
766 queue_signal(env, info.si_signo, &info);
767 } else {
768 env->regs[15] += 4;
769 }
770
771 /* accumulate unenabled exceptions */
772 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
773 fpsr |= BIT_IXC;
774 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
775 fpsr |= BIT_UFC;
776 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
777 fpsr |= BIT_OFC;
778 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
779 fpsr |= BIT_DZC;
780 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
781 fpsr |= BIT_IOC;
782 ts->fpa.fpsr=fpsr;
783 } else { /* everything OK */
784 /* increment PC */
785 env->regs[15] += 4;
786 }
787 }
788 break;
789 case EXCP_SWI:
790 case EXCP_BKPT:
791 {
792 env->eabi = 1;
793 /* system call */
794 if (trapnr == EXCP_BKPT) {
795 if (env->thumb) {
796 /* FIXME - what to do if get_user() fails? */
797 get_user_code_u16(insn, env->regs[15], env->bswap_code);
798 n = insn & 0xff;
799 env->regs[15] += 2;
800 } else {
801 /* FIXME - what to do if get_user() fails? */
802 get_user_code_u32(insn, env->regs[15], env->bswap_code);
803 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
804 env->regs[15] += 4;
805 }
806 } else {
807 if (env->thumb) {
808 /* FIXME - what to do if get_user() fails? */
809 get_user_code_u16(insn, env->regs[15] - 2,
810 env->bswap_code);
811 n = insn & 0xff;
812 } else {
813 /* FIXME - what to do if get_user() fails? */
814 get_user_code_u32(insn, env->regs[15] - 4,
815 env->bswap_code);
816 n = insn & 0xffffff;
817 }
818 }
819
820 if (n == ARM_NR_cacheflush) {
821 /* nop */
822 } else if (n == ARM_NR_semihosting
823 || n == ARM_NR_thumb_semihosting) {
824 env->regs[0] = do_arm_semihosting (env);
825 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
826 /* linux syscall */
827 if (env->thumb || n == 0) {
828 n = env->regs[7];
829 } else {
830 n -= ARM_SYSCALL_BASE;
831 env->eabi = 0;
832 }
833 if ( n > ARM_NR_BASE) {
834 switch (n) {
835 case ARM_NR_cacheflush:
836 /* nop */
837 break;
838 case ARM_NR_set_tls:
839 cpu_set_tls(env, env->regs[0]);
840 env->regs[0] = 0;
841 break;
842 case ARM_NR_breakpoint:
843 env->regs[15] -= env->thumb ? 2 : 4;
844 goto excp_debug;
845 default:
846 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
847 n);
848 env->regs[0] = -TARGET_ENOSYS;
849 break;
850 }
851 } else {
852 env->regs[0] = do_syscall(env,
853 n,
854 env->regs[0],
855 env->regs[1],
856 env->regs[2],
857 env->regs[3],
858 env->regs[4],
859 env->regs[5],
860 0, 0);
861 }
862 } else {
863 goto error;
864 }
865 }
866 break;
867 case EXCP_INTERRUPT:
868 /* just indicate that signals should be handled asap */
869 break;
870 case EXCP_STREX:
871 if (!do_strex(env)) {
872 break;
873 }
874 /* fall through for segv */
875 case EXCP_PREFETCH_ABORT:
876 case EXCP_DATA_ABORT:
877 addr = env->exception.vaddress;
878 {
879 info.si_signo = TARGET_SIGSEGV;
880 info.si_errno = 0;
881 /* XXX: check env->error_code */
882 info.si_code = TARGET_SEGV_MAPERR;
883 info._sifields._sigfault._addr = addr;
884 queue_signal(env, info.si_signo, &info);
885 }
886 break;
887 case EXCP_DEBUG:
888 excp_debug:
889 {
890 int sig;
891
892 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
893 if (sig)
894 {
895 info.si_signo = sig;
896 info.si_errno = 0;
897 info.si_code = TARGET_TRAP_BRKPT;
898 queue_signal(env, info.si_signo, &info);
899 }
900 }
901 break;
902 case EXCP_KERNEL_TRAP:
903 if (do_kernel_trap(env))
904 goto error;
905 break;
906 default:
907 error:
908 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
909 trapnr);
910 cpu_dump_state(cs, stderr, fprintf, 0);
911 abort();
912 }
913 process_pending_signals(env);
914 }
915 }
916
917 #else
918
919 /*
920 * Handle AArch64 store-release exclusive
921 *
922 * rs = gets the status result of store exclusive
923 * rt = is the register that is stored
924 * rt2 = is the second register store (in STP)
925 *
926 */
927 static int do_strex_a64(CPUARMState *env)
928 {
929 uint64_t val;
930 int size;
931 bool is_pair;
932 int rc = 1;
933 int segv = 0;
934 uint64_t addr;
935 int rs, rt, rt2;
936
937 start_exclusive();
938 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
939 size = extract32(env->exclusive_info, 0, 2);
940 is_pair = extract32(env->exclusive_info, 2, 1);
941 rs = extract32(env->exclusive_info, 4, 5);
942 rt = extract32(env->exclusive_info, 9, 5);
943 rt2 = extract32(env->exclusive_info, 14, 5);
944
945 addr = env->exclusive_addr;
946
947 if (addr != env->exclusive_test) {
948 goto finish;
949 }
950
951 switch (size) {
952 case 0:
953 segv = get_user_u8(val, addr);
954 break;
955 case 1:
956 segv = get_user_u16(val, addr);
957 break;
958 case 2:
959 segv = get_user_u32(val, addr);
960 break;
961 case 3:
962 segv = get_user_u64(val, addr);
963 break;
964 default:
965 abort();
966 }
967 if (segv) {
968 env->exception.vaddress = addr;
969 goto error;
970 }
971 if (val != env->exclusive_val) {
972 goto finish;
973 }
974 if (is_pair) {
975 if (size == 2) {
976 segv = get_user_u32(val, addr + 4);
977 } else {
978 segv = get_user_u64(val, addr + 8);
979 }
980 if (segv) {
981 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
982 goto error;
983 }
984 if (val != env->exclusive_high) {
985 goto finish;
986 }
987 }
988 /* handle the zero register */
989 val = rt == 31 ? 0 : env->xregs[rt];
990 switch (size) {
991 case 0:
992 segv = put_user_u8(val, addr);
993 break;
994 case 1:
995 segv = put_user_u16(val, addr);
996 break;
997 case 2:
998 segv = put_user_u32(val, addr);
999 break;
1000 case 3:
1001 segv = put_user_u64(val, addr);
1002 break;
1003 }
1004 if (segv) {
1005 goto error;
1006 }
1007 if (is_pair) {
1008 /* handle the zero register */
1009 val = rt2 == 31 ? 0 : env->xregs[rt2];
1010 if (size == 2) {
1011 segv = put_user_u32(val, addr + 4);
1012 } else {
1013 segv = put_user_u64(val, addr + 8);
1014 }
1015 if (segv) {
1016 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1017 goto error;
1018 }
1019 }
1020 rc = 0;
1021 finish:
1022 env->pc += 4;
1023 /* rs == 31 encodes a write to the ZR, thus throwing away
1024 * the status return. This is rather silly but valid.
1025 */
1026 if (rs < 31) {
1027 env->xregs[rs] = rc;
1028 }
1029 error:
1030 /* instruction faulted, PC does not advance */
1031 /* either way a strex releases any exclusive lock we have */
1032 env->exclusive_addr = -1;
1033 end_exclusive();
1034 return segv;
1035 }
1036
1037 /* AArch64 main loop */
1038 void cpu_loop(CPUARMState *env)
1039 {
1040 CPUState *cs = CPU(arm_env_get_cpu(env));
1041 int trapnr, sig;
1042 target_siginfo_t info;
1043
1044 for (;;) {
1045 cpu_exec_start(cs);
1046 trapnr = cpu_arm_exec(cs);
1047 cpu_exec_end(cs);
1048
1049 switch (trapnr) {
1050 case EXCP_SWI:
1051 env->xregs[0] = do_syscall(env,
1052 env->xregs[8],
1053 env->xregs[0],
1054 env->xregs[1],
1055 env->xregs[2],
1056 env->xregs[3],
1057 env->xregs[4],
1058 env->xregs[5],
1059 0, 0);
1060 break;
1061 case EXCP_INTERRUPT:
1062 /* just indicate that signals should be handled asap */
1063 break;
1064 case EXCP_UDEF:
1065 info.si_signo = TARGET_SIGILL;
1066 info.si_errno = 0;
1067 info.si_code = TARGET_ILL_ILLOPN;
1068 info._sifields._sigfault._addr = env->pc;
1069 queue_signal(env, info.si_signo, &info);
1070 break;
1071 case EXCP_STREX:
1072 if (!do_strex_a64(env)) {
1073 break;
1074 }
1075 /* fall through for segv */
1076 case EXCP_PREFETCH_ABORT:
1077 case EXCP_DATA_ABORT:
1078 info.si_signo = TARGET_SIGSEGV;
1079 info.si_errno = 0;
1080 /* XXX: check env->error_code */
1081 info.si_code = TARGET_SEGV_MAPERR;
1082 info._sifields._sigfault._addr = env->exception.vaddress;
1083 queue_signal(env, info.si_signo, &info);
1084 break;
1085 case EXCP_DEBUG:
1086 case EXCP_BKPT:
1087 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1088 if (sig) {
1089 info.si_signo = sig;
1090 info.si_errno = 0;
1091 info.si_code = TARGET_TRAP_BRKPT;
1092 queue_signal(env, info.si_signo, &info);
1093 }
1094 break;
1095 default:
1096 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1097 trapnr);
1098 cpu_dump_state(cs, stderr, fprintf, 0);
1099 abort();
1100 }
1101 process_pending_signals(env);
1102 /* Exception return on AArch64 always clears the exclusive monitor,
1103 * so any return to running guest code implies this.
1104 * A strex (successful or otherwise) also clears the monitor, so
1105 * we don't need to specialcase EXCP_STREX.
1106 */
1107 env->exclusive_addr = -1;
1108 }
1109 }
1110 #endif /* ndef TARGET_ABI32 */
1111
1112 #endif
1113
1114 #ifdef TARGET_UNICORE32
1115
1116 void cpu_loop(CPUUniCore32State *env)
1117 {
1118 CPUState *cs = CPU(uc32_env_get_cpu(env));
1119 int trapnr;
1120 unsigned int n, insn;
1121 target_siginfo_t info;
1122
1123 for (;;) {
1124 cpu_exec_start(cs);
1125 trapnr = uc32_cpu_exec(cs);
1126 cpu_exec_end(cs);
1127 switch (trapnr) {
1128 case UC32_EXCP_PRIV:
1129 {
1130 /* system call */
1131 get_user_u32(insn, env->regs[31] - 4);
1132 n = insn & 0xffffff;
1133
1134 if (n >= UC32_SYSCALL_BASE) {
1135 /* linux syscall */
1136 n -= UC32_SYSCALL_BASE;
1137 if (n == UC32_SYSCALL_NR_set_tls) {
1138 cpu_set_tls(env, env->regs[0]);
1139 env->regs[0] = 0;
1140 } else {
1141 env->regs[0] = do_syscall(env,
1142 n,
1143 env->regs[0],
1144 env->regs[1],
1145 env->regs[2],
1146 env->regs[3],
1147 env->regs[4],
1148 env->regs[5],
1149 0, 0);
1150 }
1151 } else {
1152 goto error;
1153 }
1154 }
1155 break;
1156 case UC32_EXCP_DTRAP:
1157 case UC32_EXCP_ITRAP:
1158 info.si_signo = TARGET_SIGSEGV;
1159 info.si_errno = 0;
1160 /* XXX: check env->error_code */
1161 info.si_code = TARGET_SEGV_MAPERR;
1162 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1163 queue_signal(env, info.si_signo, &info);
1164 break;
1165 case EXCP_INTERRUPT:
1166 /* just indicate that signals should be handled asap */
1167 break;
1168 case EXCP_DEBUG:
1169 {
1170 int sig;
1171
1172 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1173 if (sig) {
1174 info.si_signo = sig;
1175 info.si_errno = 0;
1176 info.si_code = TARGET_TRAP_BRKPT;
1177 queue_signal(env, info.si_signo, &info);
1178 }
1179 }
1180 break;
1181 default:
1182 goto error;
1183 }
1184 process_pending_signals(env);
1185 }
1186
1187 error:
1188 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1189 cpu_dump_state(cs, stderr, fprintf, 0);
1190 abort();
1191 }
1192 #endif
1193
1194 #ifdef TARGET_SPARC
1195 #define SPARC64_STACK_BIAS 2047
1196
1197 //#define DEBUG_WIN
1198
1199 /* WARNING: dealing with register windows _is_ complicated. More info
1200 can be found at http://www.sics.se/~psm/sparcstack.html */
1201 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1202 {
1203 index = (index + cwp * 16) % (16 * env->nwindows);
1204 /* wrap handling : if cwp is on the last window, then we use the
1205 registers 'after' the end */
1206 if (index < 8 && env->cwp == env->nwindows - 1)
1207 index += 16 * env->nwindows;
1208 return index;
1209 }
1210
1211 /* save the register window 'cwp1' */
1212 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1213 {
1214 unsigned int i;
1215 abi_ulong sp_ptr;
1216
1217 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1218 #ifdef TARGET_SPARC64
1219 if (sp_ptr & 3)
1220 sp_ptr += SPARC64_STACK_BIAS;
1221 #endif
1222 #if defined(DEBUG_WIN)
1223 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1224 sp_ptr, cwp1);
1225 #endif
1226 for(i = 0; i < 16; i++) {
1227 /* FIXME - what to do if put_user() fails? */
1228 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1229 sp_ptr += sizeof(abi_ulong);
1230 }
1231 }
1232
1233 static void save_window(CPUSPARCState *env)
1234 {
1235 #ifndef TARGET_SPARC64
1236 unsigned int new_wim;
1237 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1238 ((1LL << env->nwindows) - 1);
1239 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1240 env->wim = new_wim;
1241 #else
1242 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1243 env->cansave++;
1244 env->canrestore--;
1245 #endif
1246 }
1247
1248 static void restore_window(CPUSPARCState *env)
1249 {
1250 #ifndef TARGET_SPARC64
1251 unsigned int new_wim;
1252 #endif
1253 unsigned int i, cwp1;
1254 abi_ulong sp_ptr;
1255
1256 #ifndef TARGET_SPARC64
1257 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1258 ((1LL << env->nwindows) - 1);
1259 #endif
1260
1261 /* restore the invalid window */
1262 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1263 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1264 #ifdef TARGET_SPARC64
1265 if (sp_ptr & 3)
1266 sp_ptr += SPARC64_STACK_BIAS;
1267 #endif
1268 #if defined(DEBUG_WIN)
1269 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1270 sp_ptr, cwp1);
1271 #endif
1272 for(i = 0; i < 16; i++) {
1273 /* FIXME - what to do if get_user() fails? */
1274 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1275 sp_ptr += sizeof(abi_ulong);
1276 }
1277 #ifdef TARGET_SPARC64
1278 env->canrestore++;
1279 if (env->cleanwin < env->nwindows - 1)
1280 env->cleanwin++;
1281 env->cansave--;
1282 #else
1283 env->wim = new_wim;
1284 #endif
1285 }
1286
1287 static void flush_windows(CPUSPARCState *env)
1288 {
1289 int offset, cwp1;
1290
1291 offset = 1;
1292 for(;;) {
1293 /* if restore would invoke restore_window(), then we can stop */
1294 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1295 #ifndef TARGET_SPARC64
1296 if (env->wim & (1 << cwp1))
1297 break;
1298 #else
1299 if (env->canrestore == 0)
1300 break;
1301 env->cansave++;
1302 env->canrestore--;
1303 #endif
1304 save_window_offset(env, cwp1);
1305 offset++;
1306 }
1307 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1308 #ifndef TARGET_SPARC64
1309 /* set wim so that restore will reload the registers */
1310 env->wim = 1 << cwp1;
1311 #endif
1312 #if defined(DEBUG_WIN)
1313 printf("flush_windows: nb=%d\n", offset - 1);
1314 #endif
1315 }
1316
1317 void cpu_loop (CPUSPARCState *env)
1318 {
1319 CPUState *cs = CPU(sparc_env_get_cpu(env));
1320 int trapnr;
1321 abi_long ret;
1322 target_siginfo_t info;
1323
1324 while (1) {
1325 cpu_exec_start(cs);
1326 trapnr = cpu_sparc_exec(cs);
1327 cpu_exec_end(cs);
1328
1329 /* Compute PSR before exposing state. */
1330 if (env->cc_op != CC_OP_FLAGS) {
1331 cpu_get_psr(env);
1332 }
1333
1334 switch (trapnr) {
1335 #ifndef TARGET_SPARC64
1336 case 0x88:
1337 case 0x90:
1338 #else
1339 case 0x110:
1340 case 0x16d:
1341 #endif
1342 ret = do_syscall (env, env->gregs[1],
1343 env->regwptr[0], env->regwptr[1],
1344 env->regwptr[2], env->regwptr[3],
1345 env->regwptr[4], env->regwptr[5],
1346 0, 0);
1347 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1348 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1349 env->xcc |= PSR_CARRY;
1350 #else
1351 env->psr |= PSR_CARRY;
1352 #endif
1353 ret = -ret;
1354 } else {
1355 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1356 env->xcc &= ~PSR_CARRY;
1357 #else
1358 env->psr &= ~PSR_CARRY;
1359 #endif
1360 }
1361 env->regwptr[0] = ret;
1362 /* next instruction */
1363 env->pc = env->npc;
1364 env->npc = env->npc + 4;
1365 break;
1366 case 0x83: /* flush windows */
1367 #ifdef TARGET_ABI32
1368 case 0x103:
1369 #endif
1370 flush_windows(env);
1371 /* next instruction */
1372 env->pc = env->npc;
1373 env->npc = env->npc + 4;
1374 break;
1375 #ifndef TARGET_SPARC64
1376 case TT_WIN_OVF: /* window overflow */
1377 save_window(env);
1378 break;
1379 case TT_WIN_UNF: /* window underflow */
1380 restore_window(env);
1381 break;
1382 case TT_TFAULT:
1383 case TT_DFAULT:
1384 {
1385 info.si_signo = TARGET_SIGSEGV;
1386 info.si_errno = 0;
1387 /* XXX: check env->error_code */
1388 info.si_code = TARGET_SEGV_MAPERR;
1389 info._sifields._sigfault._addr = env->mmuregs[4];
1390 queue_signal(env, info.si_signo, &info);
1391 }
1392 break;
1393 #else
1394 case TT_SPILL: /* window overflow */
1395 save_window(env);
1396 break;
1397 case TT_FILL: /* window underflow */
1398 restore_window(env);
1399 break;
1400 case TT_TFAULT:
1401 case TT_DFAULT:
1402 {
1403 info.si_signo = TARGET_SIGSEGV;
1404 info.si_errno = 0;
1405 /* XXX: check env->error_code */
1406 info.si_code = TARGET_SEGV_MAPERR;
1407 if (trapnr == TT_DFAULT)
1408 info._sifields._sigfault._addr = env->dmmuregs[4];
1409 else
1410 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1411 queue_signal(env, info.si_signo, &info);
1412 }
1413 break;
1414 #ifndef TARGET_ABI32
1415 case 0x16e:
1416 flush_windows(env);
1417 sparc64_get_context(env);
1418 break;
1419 case 0x16f:
1420 flush_windows(env);
1421 sparc64_set_context(env);
1422 break;
1423 #endif
1424 #endif
1425 case EXCP_INTERRUPT:
1426 /* just indicate that signals should be handled asap */
1427 break;
1428 case TT_ILL_INSN:
1429 {
1430 info.si_signo = TARGET_SIGILL;
1431 info.si_errno = 0;
1432 info.si_code = TARGET_ILL_ILLOPC;
1433 info._sifields._sigfault._addr = env->pc;
1434 queue_signal(env, info.si_signo, &info);
1435 }
1436 break;
1437 case EXCP_DEBUG:
1438 {
1439 int sig;
1440
1441 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1442 if (sig)
1443 {
1444 info.si_signo = sig;
1445 info.si_errno = 0;
1446 info.si_code = TARGET_TRAP_BRKPT;
1447 queue_signal(env, info.si_signo, &info);
1448 }
1449 }
1450 break;
1451 default:
1452 printf ("Unhandled trap: 0x%x\n", trapnr);
1453 cpu_dump_state(cs, stderr, fprintf, 0);
1454 exit (1);
1455 }
1456 process_pending_signals (env);
1457 }
1458 }
1459
1460 #endif
1461
1462 #ifdef TARGET_PPC
1463 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1464 {
1465 return cpu_get_real_ticks();
1466 }
1467
1468 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1469 {
1470 return cpu_ppc_get_tb(env);
1471 }
1472
1473 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1474 {
1475 return cpu_ppc_get_tb(env) >> 32;
1476 }
1477
1478 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1479 {
1480 return cpu_ppc_get_tb(env);
1481 }
1482
1483 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1484 {
1485 return cpu_ppc_get_tb(env) >> 32;
1486 }
1487
1488 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1489 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1490
1491 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1492 {
1493 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1494 }
1495
1496 /* XXX: to be fixed */
1497 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1498 {
1499 return -1;
1500 }
1501
1502 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1503 {
1504 return -1;
1505 }
1506
1507 #define EXCP_DUMP(env, fmt, ...) \
1508 do { \
1509 CPUState *cs = ENV_GET_CPU(env); \
1510 fprintf(stderr, fmt , ## __VA_ARGS__); \
1511 cpu_dump_state(cs, stderr, fprintf, 0); \
1512 qemu_log(fmt, ## __VA_ARGS__); \
1513 if (qemu_log_enabled()) { \
1514 log_cpu_state(cs, 0); \
1515 } \
1516 } while (0)
1517
1518 static int do_store_exclusive(CPUPPCState *env)
1519 {
1520 target_ulong addr;
1521 target_ulong page_addr;
1522 target_ulong val, val2 __attribute__((unused)) = 0;
1523 int flags;
1524 int segv = 0;
1525
1526 addr = env->reserve_ea;
1527 page_addr = addr & TARGET_PAGE_MASK;
1528 start_exclusive();
1529 mmap_lock();
1530 flags = page_get_flags(page_addr);
1531 if ((flags & PAGE_READ) == 0) {
1532 segv = 1;
1533 } else {
1534 int reg = env->reserve_info & 0x1f;
1535 int size = env->reserve_info >> 5;
1536 int stored = 0;
1537
1538 if (addr == env->reserve_addr) {
1539 switch (size) {
1540 case 1: segv = get_user_u8(val, addr); break;
1541 case 2: segv = get_user_u16(val, addr); break;
1542 case 4: segv = get_user_u32(val, addr); break;
1543 #if defined(TARGET_PPC64)
1544 case 8: segv = get_user_u64(val, addr); break;
1545 case 16: {
1546 segv = get_user_u64(val, addr);
1547 if (!segv) {
1548 segv = get_user_u64(val2, addr + 8);
1549 }
1550 break;
1551 }
1552 #endif
1553 default: abort();
1554 }
1555 if (!segv && val == env->reserve_val) {
1556 val = env->gpr[reg];
1557 switch (size) {
1558 case 1: segv = put_user_u8(val, addr); break;
1559 case 2: segv = put_user_u16(val, addr); break;
1560 case 4: segv = put_user_u32(val, addr); break;
1561 #if defined(TARGET_PPC64)
1562 case 8: segv = put_user_u64(val, addr); break;
1563 case 16: {
1564 if (val2 == env->reserve_val2) {
1565 if (msr_le) {
1566 val2 = val;
1567 val = env->gpr[reg+1];
1568 } else {
1569 val2 = env->gpr[reg+1];
1570 }
1571 segv = put_user_u64(val, addr);
1572 if (!segv) {
1573 segv = put_user_u64(val2, addr + 8);
1574 }
1575 }
1576 break;
1577 }
1578 #endif
1579 default: abort();
1580 }
1581 if (!segv) {
1582 stored = 1;
1583 }
1584 }
1585 }
1586 env->crf[0] = (stored << 1) | xer_so;
1587 env->reserve_addr = (target_ulong)-1;
1588 }
1589 if (!segv) {
1590 env->nip += 4;
1591 }
1592 mmap_unlock();
1593 end_exclusive();
1594 return segv;
1595 }
1596
1597 void cpu_loop(CPUPPCState *env)
1598 {
1599 CPUState *cs = CPU(ppc_env_get_cpu(env));
1600 target_siginfo_t info;
1601 int trapnr;
1602 target_ulong ret;
1603
1604 for(;;) {
1605 cpu_exec_start(cs);
1606 trapnr = cpu_ppc_exec(cs);
1607 cpu_exec_end(cs);
1608 switch(trapnr) {
1609 case POWERPC_EXCP_NONE:
1610 /* Just go on */
1611 break;
1612 case POWERPC_EXCP_CRITICAL: /* Critical input */
1613 cpu_abort(cs, "Critical interrupt while in user mode. "
1614 "Aborting\n");
1615 break;
1616 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1617 cpu_abort(cs, "Machine check exception while in user mode. "
1618 "Aborting\n");
1619 break;
1620 case POWERPC_EXCP_DSI: /* Data storage exception */
1621 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1622 env->spr[SPR_DAR]);
1623 /* XXX: check this. Seems bugged */
1624 switch (env->error_code & 0xFF000000) {
1625 case 0x40000000:
1626 info.si_signo = TARGET_SIGSEGV;
1627 info.si_errno = 0;
1628 info.si_code = TARGET_SEGV_MAPERR;
1629 break;
1630 case 0x04000000:
1631 info.si_signo = TARGET_SIGILL;
1632 info.si_errno = 0;
1633 info.si_code = TARGET_ILL_ILLADR;
1634 break;
1635 case 0x08000000:
1636 info.si_signo = TARGET_SIGSEGV;
1637 info.si_errno = 0;
1638 info.si_code = TARGET_SEGV_ACCERR;
1639 break;
1640 default:
1641 /* Let's send a regular segfault... */
1642 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1643 env->error_code);
1644 info.si_signo = TARGET_SIGSEGV;
1645 info.si_errno = 0;
1646 info.si_code = TARGET_SEGV_MAPERR;
1647 break;
1648 }
1649 info._sifields._sigfault._addr = env->nip;
1650 queue_signal(env, info.si_signo, &info);
1651 break;
1652 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1653 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1654 "\n", env->spr[SPR_SRR0]);
1655 /* XXX: check this */
1656 switch (env->error_code & 0xFF000000) {
1657 case 0x40000000:
1658 info.si_signo = TARGET_SIGSEGV;
1659 info.si_errno = 0;
1660 info.si_code = TARGET_SEGV_MAPERR;
1661 break;
1662 case 0x10000000:
1663 case 0x08000000:
1664 info.si_signo = TARGET_SIGSEGV;
1665 info.si_errno = 0;
1666 info.si_code = TARGET_SEGV_ACCERR;
1667 break;
1668 default:
1669 /* Let's send a regular segfault... */
1670 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1671 env->error_code);
1672 info.si_signo = TARGET_SIGSEGV;
1673 info.si_errno = 0;
1674 info.si_code = TARGET_SEGV_MAPERR;
1675 break;
1676 }
1677 info._sifields._sigfault._addr = env->nip - 4;
1678 queue_signal(env, info.si_signo, &info);
1679 break;
1680 case POWERPC_EXCP_EXTERNAL: /* External input */
1681 cpu_abort(cs, "External interrupt while in user mode. "
1682 "Aborting\n");
1683 break;
1684 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1685 EXCP_DUMP(env, "Unaligned memory access\n");
1686 /* XXX: check this */
1687 info.si_signo = TARGET_SIGBUS;
1688 info.si_errno = 0;
1689 info.si_code = TARGET_BUS_ADRALN;
1690 info._sifields._sigfault._addr = env->nip - 4;
1691 queue_signal(env, info.si_signo, &info);
1692 break;
1693 case POWERPC_EXCP_PROGRAM: /* Program exception */
1694 /* XXX: check this */
1695 switch (env->error_code & ~0xF) {
1696 case POWERPC_EXCP_FP:
1697 EXCP_DUMP(env, "Floating point program exception\n");
1698 info.si_signo = TARGET_SIGFPE;
1699 info.si_errno = 0;
1700 switch (env->error_code & 0xF) {
1701 case POWERPC_EXCP_FP_OX:
1702 info.si_code = TARGET_FPE_FLTOVF;
1703 break;
1704 case POWERPC_EXCP_FP_UX:
1705 info.si_code = TARGET_FPE_FLTUND;
1706 break;
1707 case POWERPC_EXCP_FP_ZX:
1708 case POWERPC_EXCP_FP_VXZDZ:
1709 info.si_code = TARGET_FPE_FLTDIV;
1710 break;
1711 case POWERPC_EXCP_FP_XX:
1712 info.si_code = TARGET_FPE_FLTRES;
1713 break;
1714 case POWERPC_EXCP_FP_VXSOFT:
1715 info.si_code = TARGET_FPE_FLTINV;
1716 break;
1717 case POWERPC_EXCP_FP_VXSNAN:
1718 case POWERPC_EXCP_FP_VXISI:
1719 case POWERPC_EXCP_FP_VXIDI:
1720 case POWERPC_EXCP_FP_VXIMZ:
1721 case POWERPC_EXCP_FP_VXVC:
1722 case POWERPC_EXCP_FP_VXSQRT:
1723 case POWERPC_EXCP_FP_VXCVI:
1724 info.si_code = TARGET_FPE_FLTSUB;
1725 break;
1726 default:
1727 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1728 env->error_code);
1729 break;
1730 }
1731 break;
1732 case POWERPC_EXCP_INVAL:
1733 EXCP_DUMP(env, "Invalid instruction\n");
1734 info.si_signo = TARGET_SIGILL;
1735 info.si_errno = 0;
1736 switch (env->error_code & 0xF) {
1737 case POWERPC_EXCP_INVAL_INVAL:
1738 info.si_code = TARGET_ILL_ILLOPC;
1739 break;
1740 case POWERPC_EXCP_INVAL_LSWX:
1741 info.si_code = TARGET_ILL_ILLOPN;
1742 break;
1743 case POWERPC_EXCP_INVAL_SPR:
1744 info.si_code = TARGET_ILL_PRVREG;
1745 break;
1746 case POWERPC_EXCP_INVAL_FP:
1747 info.si_code = TARGET_ILL_COPROC;
1748 break;
1749 default:
1750 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1751 env->error_code & 0xF);
1752 info.si_code = TARGET_ILL_ILLADR;
1753 break;
1754 }
1755 break;
1756 case POWERPC_EXCP_PRIV:
1757 EXCP_DUMP(env, "Privilege violation\n");
1758 info.si_signo = TARGET_SIGILL;
1759 info.si_errno = 0;
1760 switch (env->error_code & 0xF) {
1761 case POWERPC_EXCP_PRIV_OPC:
1762 info.si_code = TARGET_ILL_PRVOPC;
1763 break;
1764 case POWERPC_EXCP_PRIV_REG:
1765 info.si_code = TARGET_ILL_PRVREG;
1766 break;
1767 default:
1768 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1769 env->error_code & 0xF);
1770 info.si_code = TARGET_ILL_PRVOPC;
1771 break;
1772 }
1773 break;
1774 case POWERPC_EXCP_TRAP:
1775 cpu_abort(cs, "Tried to call a TRAP\n");
1776 break;
1777 default:
1778 /* Should not happen ! */
1779 cpu_abort(cs, "Unknown program exception (%02x)\n",
1780 env->error_code);
1781 break;
1782 }
1783 info._sifields._sigfault._addr = env->nip - 4;
1784 queue_signal(env, info.si_signo, &info);
1785 break;
1786 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1787 EXCP_DUMP(env, "No floating point allowed\n");
1788 info.si_signo = TARGET_SIGILL;
1789 info.si_errno = 0;
1790 info.si_code = TARGET_ILL_COPROC;
1791 info._sifields._sigfault._addr = env->nip - 4;
1792 queue_signal(env, info.si_signo, &info);
1793 break;
1794 case POWERPC_EXCP_SYSCALL: /* System call exception */
1795 cpu_abort(cs, "Syscall exception while in user mode. "
1796 "Aborting\n");
1797 break;
1798 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1799 EXCP_DUMP(env, "No APU instruction allowed\n");
1800 info.si_signo = TARGET_SIGILL;
1801 info.si_errno = 0;
1802 info.si_code = TARGET_ILL_COPROC;
1803 info._sifields._sigfault._addr = env->nip - 4;
1804 queue_signal(env, info.si_signo, &info);
1805 break;
1806 case POWERPC_EXCP_DECR: /* Decrementer exception */
1807 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1808 "Aborting\n");
1809 break;
1810 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1811 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1812 "Aborting\n");
1813 break;
1814 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1815 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1816 "Aborting\n");
1817 break;
1818 case POWERPC_EXCP_DTLB: /* Data TLB error */
1819 cpu_abort(cs, "Data TLB exception while in user mode. "
1820 "Aborting\n");
1821 break;
1822 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1823 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1824 "Aborting\n");
1825 break;
1826 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1827 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1828 info.si_signo = TARGET_SIGILL;
1829 info.si_errno = 0;
1830 info.si_code = TARGET_ILL_COPROC;
1831 info._sifields._sigfault._addr = env->nip - 4;
1832 queue_signal(env, info.si_signo, &info);
1833 break;
1834 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1835 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1836 break;
1837 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1838 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1839 break;
1840 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1841 cpu_abort(cs, "Performance monitor exception not handled\n");
1842 break;
1843 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1844 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1845 "Aborting\n");
1846 break;
1847 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1848 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1849 "Aborting\n");
1850 break;
1851 case POWERPC_EXCP_RESET: /* System reset exception */
1852 cpu_abort(cs, "Reset interrupt while in user mode. "
1853 "Aborting\n");
1854 break;
1855 case POWERPC_EXCP_DSEG: /* Data segment exception */
1856 cpu_abort(cs, "Data segment exception while in user mode. "
1857 "Aborting\n");
1858 break;
1859 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1860 cpu_abort(cs, "Instruction segment exception "
1861 "while in user mode. Aborting\n");
1862 break;
1863 /* PowerPC 64 with hypervisor mode support */
1864 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1865 cpu_abort(cs, "Hypervisor decrementer interrupt "
1866 "while in user mode. Aborting\n");
1867 break;
1868 case POWERPC_EXCP_TRACE: /* Trace exception */
1869 /* Nothing to do:
1870 * we use this exception to emulate step-by-step execution mode.
1871 */
1872 break;
1873 /* PowerPC 64 with hypervisor mode support */
1874 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1875 cpu_abort(cs, "Hypervisor data storage exception "
1876 "while in user mode. Aborting\n");
1877 break;
1878 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1879 cpu_abort(cs, "Hypervisor instruction storage exception "
1880 "while in user mode. Aborting\n");
1881 break;
1882 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1883 cpu_abort(cs, "Hypervisor data segment exception "
1884 "while in user mode. Aborting\n");
1885 break;
1886 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1887 cpu_abort(cs, "Hypervisor instruction segment exception "
1888 "while in user mode. Aborting\n");
1889 break;
1890 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1891 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1892 info.si_signo = TARGET_SIGILL;
1893 info.si_errno = 0;
1894 info.si_code = TARGET_ILL_COPROC;
1895 info._sifields._sigfault._addr = env->nip - 4;
1896 queue_signal(env, info.si_signo, &info);
1897 break;
1898 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1899 cpu_abort(cs, "Programmable interval timer interrupt "
1900 "while in user mode. Aborting\n");
1901 break;
1902 case POWERPC_EXCP_IO: /* IO error exception */
1903 cpu_abort(cs, "IO error exception while in user mode. "
1904 "Aborting\n");
1905 break;
1906 case POWERPC_EXCP_RUNM: /* Run mode exception */
1907 cpu_abort(cs, "Run mode exception while in user mode. "
1908 "Aborting\n");
1909 break;
1910 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1911 cpu_abort(cs, "Emulation trap exception not handled\n");
1912 break;
1913 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1914 cpu_abort(cs, "Instruction fetch TLB exception "
1915 "while in user-mode. Aborting");
1916 break;
1917 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1918 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1919 "Aborting");
1920 break;
1921 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1922 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1923 "Aborting");
1924 break;
1925 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1926 cpu_abort(cs, "Floating-point assist exception not handled\n");
1927 break;
1928 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1929 cpu_abort(cs, "Instruction address breakpoint exception "
1930 "not handled\n");
1931 break;
1932 case POWERPC_EXCP_SMI: /* System management interrupt */
1933 cpu_abort(cs, "System management interrupt while in user mode. "
1934 "Aborting\n");
1935 break;
1936 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1937 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1938 "Aborting\n");
1939 break;
1940 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1941 cpu_abort(cs, "Performance monitor exception not handled\n");
1942 break;
1943 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1944 cpu_abort(cs, "Vector assist exception not handled\n");
1945 break;
1946 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1947 cpu_abort(cs, "Soft patch exception not handled\n");
1948 break;
1949 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1950 cpu_abort(cs, "Maintenance exception while in user mode. "
1951 "Aborting\n");
1952 break;
1953 case POWERPC_EXCP_STOP: /* stop translation */
1954 /* We did invalidate the instruction cache. Go on */
1955 break;
1956 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1957 /* We just stopped because of a branch. Go on */
1958 break;
1959 case POWERPC_EXCP_SYSCALL_USER:
1960 /* system call in user-mode emulation */
1961 /* WARNING:
1962 * PPC ABI uses overflow flag in cr0 to signal an error
1963 * in syscalls.
1964 */
1965 env->crf[0] &= ~0x1;
1966 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1967 env->gpr[5], env->gpr[6], env->gpr[7],
1968 env->gpr[8], 0, 0);
1969 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1970 /* Returning from a successful sigreturn syscall.
1971 Avoid corrupting register state. */
1972 break;
1973 }
1974 if (ret > (target_ulong)(-515)) {
1975 env->crf[0] |= 0x1;
1976 ret = -ret;
1977 }
1978 env->gpr[3] = ret;
1979 break;
1980 case POWERPC_EXCP_STCX:
1981 if (do_store_exclusive(env)) {
1982 info.si_signo = TARGET_SIGSEGV;
1983 info.si_errno = 0;
1984 info.si_code = TARGET_SEGV_MAPERR;
1985 info._sifields._sigfault._addr = env->nip;
1986 queue_signal(env, info.si_signo, &info);
1987 }
1988 break;
1989 case EXCP_DEBUG:
1990 {
1991 int sig;
1992
1993 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1994 if (sig) {
1995 info.si_signo = sig;
1996 info.si_errno = 0;
1997 info.si_code = TARGET_TRAP_BRKPT;
1998 queue_signal(env, info.si_signo, &info);
1999 }
2000 }
2001 break;
2002 case EXCP_INTERRUPT:
2003 /* just indicate that signals should be handled asap */
2004 break;
2005 default:
2006 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2007 break;
2008 }
2009 process_pending_signals(env);
2010 }
2011 }
2012 #endif
2013
2014 #ifdef TARGET_MIPS
2015
2016 # ifdef TARGET_ABI_MIPSO32
2017 # define MIPS_SYS(name, args) args,
2018 static const uint8_t mips_syscall_args[] = {
2019 MIPS_SYS(sys_syscall , 8) /* 4000 */
2020 MIPS_SYS(sys_exit , 1)
2021 MIPS_SYS(sys_fork , 0)
2022 MIPS_SYS(sys_read , 3)
2023 MIPS_SYS(sys_write , 3)
2024 MIPS_SYS(sys_open , 3) /* 4005 */
2025 MIPS_SYS(sys_close , 1)
2026 MIPS_SYS(sys_waitpid , 3)
2027 MIPS_SYS(sys_creat , 2)
2028 MIPS_SYS(sys_link , 2)
2029 MIPS_SYS(sys_unlink , 1) /* 4010 */
2030 MIPS_SYS(sys_execve , 0)
2031 MIPS_SYS(sys_chdir , 1)
2032 MIPS_SYS(sys_time , 1)
2033 MIPS_SYS(sys_mknod , 3)
2034 MIPS_SYS(sys_chmod , 2) /* 4015 */
2035 MIPS_SYS(sys_lchown , 3)
2036 MIPS_SYS(sys_ni_syscall , 0)
2037 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2038 MIPS_SYS(sys_lseek , 3)
2039 MIPS_SYS(sys_getpid , 0) /* 4020 */
2040 MIPS_SYS(sys_mount , 5)
2041 MIPS_SYS(sys_umount , 1)
2042 MIPS_SYS(sys_setuid , 1)
2043 MIPS_SYS(sys_getuid , 0)
2044 MIPS_SYS(sys_stime , 1) /* 4025 */
2045 MIPS_SYS(sys_ptrace , 4)
2046 MIPS_SYS(sys_alarm , 1)
2047 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2048 MIPS_SYS(sys_pause , 0)
2049 MIPS_SYS(sys_utime , 2) /* 4030 */
2050 MIPS_SYS(sys_ni_syscall , 0)
2051 MIPS_SYS(sys_ni_syscall , 0)
2052 MIPS_SYS(sys_access , 2)
2053 MIPS_SYS(sys_nice , 1)
2054 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2055 MIPS_SYS(sys_sync , 0)
2056 MIPS_SYS(sys_kill , 2)
2057 MIPS_SYS(sys_rename , 2)
2058 MIPS_SYS(sys_mkdir , 2)
2059 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2060 MIPS_SYS(sys_dup , 1)
2061 MIPS_SYS(sys_pipe , 0)
2062 MIPS_SYS(sys_times , 1)
2063 MIPS_SYS(sys_ni_syscall , 0)
2064 MIPS_SYS(sys_brk , 1) /* 4045 */
2065 MIPS_SYS(sys_setgid , 1)
2066 MIPS_SYS(sys_getgid , 0)
2067 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2068 MIPS_SYS(sys_geteuid , 0)
2069 MIPS_SYS(sys_getegid , 0) /* 4050 */
2070 MIPS_SYS(sys_acct , 0)
2071 MIPS_SYS(sys_umount2 , 2)
2072 MIPS_SYS(sys_ni_syscall , 0)
2073 MIPS_SYS(sys_ioctl , 3)
2074 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2075 MIPS_SYS(sys_ni_syscall , 2)
2076 MIPS_SYS(sys_setpgid , 2)
2077 MIPS_SYS(sys_ni_syscall , 0)
2078 MIPS_SYS(sys_olduname , 1)
2079 MIPS_SYS(sys_umask , 1) /* 4060 */
2080 MIPS_SYS(sys_chroot , 1)
2081 MIPS_SYS(sys_ustat , 2)
2082 MIPS_SYS(sys_dup2 , 2)
2083 MIPS_SYS(sys_getppid , 0)
2084 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2085 MIPS_SYS(sys_setsid , 0)
2086 MIPS_SYS(sys_sigaction , 3)
2087 MIPS_SYS(sys_sgetmask , 0)
2088 MIPS_SYS(sys_ssetmask , 1)
2089 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2090 MIPS_SYS(sys_setregid , 2)
2091 MIPS_SYS(sys_sigsuspend , 0)
2092 MIPS_SYS(sys_sigpending , 1)
2093 MIPS_SYS(sys_sethostname , 2)
2094 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2095 MIPS_SYS(sys_getrlimit , 2)
2096 MIPS_SYS(sys_getrusage , 2)
2097 MIPS_SYS(sys_gettimeofday, 2)
2098 MIPS_SYS(sys_settimeofday, 2)
2099 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2100 MIPS_SYS(sys_setgroups , 2)
2101 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2102 MIPS_SYS(sys_symlink , 2)
2103 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2104 MIPS_SYS(sys_readlink , 3) /* 4085 */
2105 MIPS_SYS(sys_uselib , 1)
2106 MIPS_SYS(sys_swapon , 2)
2107 MIPS_SYS(sys_reboot , 3)
2108 MIPS_SYS(old_readdir , 3)
2109 MIPS_SYS(old_mmap , 6) /* 4090 */
2110 MIPS_SYS(sys_munmap , 2)
2111 MIPS_SYS(sys_truncate , 2)
2112 MIPS_SYS(sys_ftruncate , 2)
2113 MIPS_SYS(sys_fchmod , 2)
2114 MIPS_SYS(sys_fchown , 3) /* 4095 */
2115 MIPS_SYS(sys_getpriority , 2)
2116 MIPS_SYS(sys_setpriority , 3)
2117 MIPS_SYS(sys_ni_syscall , 0)
2118 MIPS_SYS(sys_statfs , 2)
2119 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2120 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2121 MIPS_SYS(sys_socketcall , 2)
2122 MIPS_SYS(sys_syslog , 3)
2123 MIPS_SYS(sys_setitimer , 3)
2124 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2125 MIPS_SYS(sys_newstat , 2)
2126 MIPS_SYS(sys_newlstat , 2)
2127 MIPS_SYS(sys_newfstat , 2)
2128 MIPS_SYS(sys_uname , 1)
2129 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2130 MIPS_SYS(sys_vhangup , 0)
2131 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2132 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2133 MIPS_SYS(sys_wait4 , 4)
2134 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2135 MIPS_SYS(sys_sysinfo , 1)
2136 MIPS_SYS(sys_ipc , 6)
2137 MIPS_SYS(sys_fsync , 1)
2138 MIPS_SYS(sys_sigreturn , 0)
2139 MIPS_SYS(sys_clone , 6) /* 4120 */
2140 MIPS_SYS(sys_setdomainname, 2)
2141 MIPS_SYS(sys_newuname , 1)
2142 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2143 MIPS_SYS(sys_adjtimex , 1)
2144 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2145 MIPS_SYS(sys_sigprocmask , 3)
2146 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2147 MIPS_SYS(sys_init_module , 5)
2148 MIPS_SYS(sys_delete_module, 1)
2149 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2150 MIPS_SYS(sys_quotactl , 0)
2151 MIPS_SYS(sys_getpgid , 1)
2152 MIPS_SYS(sys_fchdir , 1)
2153 MIPS_SYS(sys_bdflush , 2)
2154 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2155 MIPS_SYS(sys_personality , 1)
2156 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2157 MIPS_SYS(sys_setfsuid , 1)
2158 MIPS_SYS(sys_setfsgid , 1)
2159 MIPS_SYS(sys_llseek , 5) /* 4140 */
2160 MIPS_SYS(sys_getdents , 3)
2161 MIPS_SYS(sys_select , 5)
2162 MIPS_SYS(sys_flock , 2)
2163 MIPS_SYS(sys_msync , 3)
2164 MIPS_SYS(sys_readv , 3) /* 4145 */
2165 MIPS_SYS(sys_writev , 3)
2166 MIPS_SYS(sys_cacheflush , 3)
2167 MIPS_SYS(sys_cachectl , 3)
2168 MIPS_SYS(sys_sysmips , 4)
2169 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2170 MIPS_SYS(sys_getsid , 1)
2171 MIPS_SYS(sys_fdatasync , 0)
2172 MIPS_SYS(sys_sysctl , 1)
2173 MIPS_SYS(sys_mlock , 2)
2174 MIPS_SYS(sys_munlock , 2) /* 4155 */
2175 MIPS_SYS(sys_mlockall , 1)
2176 MIPS_SYS(sys_munlockall , 0)
2177 MIPS_SYS(sys_sched_setparam, 2)
2178 MIPS_SYS(sys_sched_getparam, 2)
2179 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2180 MIPS_SYS(sys_sched_getscheduler, 1)
2181 MIPS_SYS(sys_sched_yield , 0)
2182 MIPS_SYS(sys_sched_get_priority_max, 1)
2183 MIPS_SYS(sys_sched_get_priority_min, 1)
2184 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2185 MIPS_SYS(sys_nanosleep, 2)
2186 MIPS_SYS(sys_mremap , 5)
2187 MIPS_SYS(sys_accept , 3)
2188 MIPS_SYS(sys_bind , 3)
2189 MIPS_SYS(sys_connect , 3) /* 4170 */
2190 MIPS_SYS(sys_getpeername , 3)
2191 MIPS_SYS(sys_getsockname , 3)
2192 MIPS_SYS(sys_getsockopt , 5)
2193 MIPS_SYS(sys_listen , 2)
2194 MIPS_SYS(sys_recv , 4) /* 4175 */
2195 MIPS_SYS(sys_recvfrom , 6)
2196 MIPS_SYS(sys_recvmsg , 3)
2197 MIPS_SYS(sys_send , 4)
2198 MIPS_SYS(sys_sendmsg , 3)
2199 MIPS_SYS(sys_sendto , 6) /* 4180 */
2200 MIPS_SYS(sys_setsockopt , 5)
2201 MIPS_SYS(sys_shutdown , 2)
2202 MIPS_SYS(sys_socket , 3)
2203 MIPS_SYS(sys_socketpair , 4)
2204 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2205 MIPS_SYS(sys_getresuid , 3)
2206 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2207 MIPS_SYS(sys_poll , 3)
2208 MIPS_SYS(sys_nfsservctl , 3)
2209 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2210 MIPS_SYS(sys_getresgid , 3)
2211 MIPS_SYS(sys_prctl , 5)
2212 MIPS_SYS(sys_rt_sigreturn, 0)
2213 MIPS_SYS(sys_rt_sigaction, 4)
2214 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2215 MIPS_SYS(sys_rt_sigpending, 2)
2216 MIPS_SYS(sys_rt_sigtimedwait, 4)
2217 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2218 MIPS_SYS(sys_rt_sigsuspend, 0)
2219 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2220 MIPS_SYS(sys_pwrite64 , 6)
2221 MIPS_SYS(sys_chown , 3)
2222 MIPS_SYS(sys_getcwd , 2)
2223 MIPS_SYS(sys_capget , 2)
2224 MIPS_SYS(sys_capset , 2) /* 4205 */
2225 MIPS_SYS(sys_sigaltstack , 2)
2226 MIPS_SYS(sys_sendfile , 4)
2227 MIPS_SYS(sys_ni_syscall , 0)
2228 MIPS_SYS(sys_ni_syscall , 0)
2229 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2230 MIPS_SYS(sys_truncate64 , 4)
2231 MIPS_SYS(sys_ftruncate64 , 4)
2232 MIPS_SYS(sys_stat64 , 2)
2233 MIPS_SYS(sys_lstat64 , 2)
2234 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2235 MIPS_SYS(sys_pivot_root , 2)
2236 MIPS_SYS(sys_mincore , 3)
2237 MIPS_SYS(sys_madvise , 3)
2238 MIPS_SYS(sys_getdents64 , 3)
2239 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2240 MIPS_SYS(sys_ni_syscall , 0)
2241 MIPS_SYS(sys_gettid , 0)
2242 MIPS_SYS(sys_readahead , 5)
2243 MIPS_SYS(sys_setxattr , 5)
2244 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2245 MIPS_SYS(sys_fsetxattr , 5)
2246 MIPS_SYS(sys_getxattr , 4)
2247 MIPS_SYS(sys_lgetxattr , 4)
2248 MIPS_SYS(sys_fgetxattr , 4)
2249 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2250 MIPS_SYS(sys_llistxattr , 3)
2251 MIPS_SYS(sys_flistxattr , 3)
2252 MIPS_SYS(sys_removexattr , 2)
2253 MIPS_SYS(sys_lremovexattr, 2)
2254 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2255 MIPS_SYS(sys_tkill , 2)
2256 MIPS_SYS(sys_sendfile64 , 5)
2257 MIPS_SYS(sys_futex , 6)
2258 MIPS_SYS(sys_sched_setaffinity, 3)
2259 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2260 MIPS_SYS(sys_io_setup , 2)
2261 MIPS_SYS(sys_io_destroy , 1)
2262 MIPS_SYS(sys_io_getevents, 5)
2263 MIPS_SYS(sys_io_submit , 3)
2264 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2265 MIPS_SYS(sys_exit_group , 1)
2266 MIPS_SYS(sys_lookup_dcookie, 3)
2267 MIPS_SYS(sys_epoll_create, 1)
2268 MIPS_SYS(sys_epoll_ctl , 4)
2269 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2270 MIPS_SYS(sys_remap_file_pages, 5)
2271 MIPS_SYS(sys_set_tid_address, 1)
2272 MIPS_SYS(sys_restart_syscall, 0)
2273 MIPS_SYS(sys_fadvise64_64, 7)
2274 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2275 MIPS_SYS(sys_fstatfs64 , 2)
2276 MIPS_SYS(sys_timer_create, 3)
2277 MIPS_SYS(sys_timer_settime, 4)
2278 MIPS_SYS(sys_timer_gettime, 2)
2279 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2280 MIPS_SYS(sys_timer_delete, 1)
2281 MIPS_SYS(sys_clock_settime, 2)
2282 MIPS_SYS(sys_clock_gettime, 2)
2283 MIPS_SYS(sys_clock_getres, 2)
2284 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2285 MIPS_SYS(sys_tgkill , 3)
2286 MIPS_SYS(sys_utimes , 2)
2287 MIPS_SYS(sys_mbind , 4)
2288 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2289 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2290 MIPS_SYS(sys_mq_open , 4)
2291 MIPS_SYS(sys_mq_unlink , 1)
2292 MIPS_SYS(sys_mq_timedsend, 5)
2293 MIPS_SYS(sys_mq_timedreceive, 5)
2294 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2295 MIPS_SYS(sys_mq_getsetattr, 3)
2296 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2297 MIPS_SYS(sys_waitid , 4)
2298 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2299 MIPS_SYS(sys_add_key , 5)
2300 MIPS_SYS(sys_request_key, 4)
2301 MIPS_SYS(sys_keyctl , 5)
2302 MIPS_SYS(sys_set_thread_area, 1)
2303 MIPS_SYS(sys_inotify_init, 0)
2304 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2305 MIPS_SYS(sys_inotify_rm_watch, 2)
2306 MIPS_SYS(sys_migrate_pages, 4)
2307 MIPS_SYS(sys_openat, 4)
2308 MIPS_SYS(sys_mkdirat, 3)
2309 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2310 MIPS_SYS(sys_fchownat, 5)
2311 MIPS_SYS(sys_futimesat, 3)
2312 MIPS_SYS(sys_fstatat64, 4)
2313 MIPS_SYS(sys_unlinkat, 3)
2314 MIPS_SYS(sys_renameat, 4) /* 4295 */
2315 MIPS_SYS(sys_linkat, 5)
2316 MIPS_SYS(sys_symlinkat, 3)
2317 MIPS_SYS(sys_readlinkat, 4)
2318 MIPS_SYS(sys_fchmodat, 3)
2319 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2320 MIPS_SYS(sys_pselect6, 6)
2321 MIPS_SYS(sys_ppoll, 5)
2322 MIPS_SYS(sys_unshare, 1)
2323 MIPS_SYS(sys_splice, 6)
2324 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2325 MIPS_SYS(sys_tee, 4)
2326 MIPS_SYS(sys_vmsplice, 4)
2327 MIPS_SYS(sys_move_pages, 6)
2328 MIPS_SYS(sys_set_robust_list, 2)
2329 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2330 MIPS_SYS(sys_kexec_load, 4)
2331 MIPS_SYS(sys_getcpu, 3)
2332 MIPS_SYS(sys_epoll_pwait, 6)
2333 MIPS_SYS(sys_ioprio_set, 3)
2334 MIPS_SYS(sys_ioprio_get, 2)
2335 MIPS_SYS(sys_utimensat, 4)
2336 MIPS_SYS(sys_signalfd, 3)
2337 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2338 MIPS_SYS(sys_eventfd, 1)
2339 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2340 MIPS_SYS(sys_timerfd_create, 2)
2341 MIPS_SYS(sys_timerfd_gettime, 2)
2342 MIPS_SYS(sys_timerfd_settime, 4)
2343 MIPS_SYS(sys_signalfd4, 4)
2344 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2345 MIPS_SYS(sys_epoll_create1, 1)
2346 MIPS_SYS(sys_dup3, 3)
2347 MIPS_SYS(sys_pipe2, 2)
2348 MIPS_SYS(sys_inotify_init1, 1)
2349 MIPS_SYS(sys_preadv, 6) /* 4330 */
2350 MIPS_SYS(sys_pwritev, 6)
2351 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2352 MIPS_SYS(sys_perf_event_open, 5)
2353 MIPS_SYS(sys_accept4, 4)
2354 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2355 MIPS_SYS(sys_fanotify_init, 2)
2356 MIPS_SYS(sys_fanotify_mark, 6)
2357 MIPS_SYS(sys_prlimit64, 4)
2358 MIPS_SYS(sys_name_to_handle_at, 5)
2359 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2360 MIPS_SYS(sys_clock_adjtime, 2)
2361 MIPS_SYS(sys_syncfs, 1)
2362 };
2363 # undef MIPS_SYS
2364 # endif /* O32 */
2365
2366 static int do_store_exclusive(CPUMIPSState *env)
2367 {
2368 target_ulong addr;
2369 target_ulong page_addr;
2370 target_ulong val;
2371 int flags;
2372 int segv = 0;
2373 int reg;
2374 int d;
2375
2376 addr = env->lladdr;
2377 page_addr = addr & TARGET_PAGE_MASK;
2378 start_exclusive();
2379 mmap_lock();
2380 flags = page_get_flags(page_addr);
2381 if ((flags & PAGE_READ) == 0) {
2382 segv = 1;
2383 } else {
2384 reg = env->llreg & 0x1f;
2385 d = (env->llreg & 0x20) != 0;
2386 if (d) {
2387 segv = get_user_s64(val, addr);
2388 } else {
2389 segv = get_user_s32(val, addr);
2390 }
2391 if (!segv) {
2392 if (val != env->llval) {
2393 env->active_tc.gpr[reg] = 0;
2394 } else {
2395 if (d) {
2396 segv = put_user_u64(env->llnewval, addr);
2397 } else {
2398 segv = put_user_u32(env->llnewval, addr);
2399 }
2400 if (!segv) {
2401 env->active_tc.gpr[reg] = 1;
2402 }
2403 }
2404 }
2405 }
2406 env->lladdr = -1;
2407 if (!segv) {
2408 env->active_tc.PC += 4;
2409 }
2410 mmap_unlock();
2411 end_exclusive();
2412 return segv;
2413 }
2414
2415 /* Break codes */
2416 enum {
2417 BRK_OVERFLOW = 6,
2418 BRK_DIVZERO = 7
2419 };
2420
2421 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2422 unsigned int code)
2423 {
2424 int ret = -1;
2425
2426 switch (code) {
2427 case BRK_OVERFLOW:
2428 case BRK_DIVZERO:
2429 info->si_signo = TARGET_SIGFPE;
2430 info->si_errno = 0;
2431 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2432 queue_signal(env, info->si_signo, &*info);
2433 ret = 0;
2434 break;
2435 default:
2436 info->si_signo = TARGET_SIGTRAP;
2437 info->si_errno = 0;
2438 queue_signal(env, info->si_signo, &*info);
2439 ret = 0;
2440 break;
2441 }
2442
2443 return ret;
2444 }
2445
2446 void cpu_loop(CPUMIPSState *env)
2447 {
2448 CPUState *cs = CPU(mips_env_get_cpu(env));
2449 target_siginfo_t info;
2450 int trapnr;
2451 abi_long ret;
2452 # ifdef TARGET_ABI_MIPSO32
2453 unsigned int syscall_num;
2454 # endif
2455
2456 for(;;) {
2457 cpu_exec_start(cs);
2458 trapnr = cpu_mips_exec(cs);
2459 cpu_exec_end(cs);
2460 switch(trapnr) {
2461 case EXCP_SYSCALL:
2462 env->active_tc.PC += 4;
2463 # ifdef TARGET_ABI_MIPSO32
2464 syscall_num = env->active_tc.gpr[2] - 4000;
2465 if (syscall_num >= sizeof(mips_syscall_args)) {
2466 ret = -TARGET_ENOSYS;
2467 } else {
2468 int nb_args;
2469 abi_ulong sp_reg;
2470 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2471
2472 nb_args = mips_syscall_args[syscall_num];
2473 sp_reg = env->active_tc.gpr[29];
2474 switch (nb_args) {
2475 /* these arguments are taken from the stack */
2476 case 8:
2477 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2478 goto done_syscall;
2479 }
2480 case 7:
2481 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2482 goto done_syscall;
2483 }
2484 case 6:
2485 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2486 goto done_syscall;
2487 }
2488 case 5:
2489 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2490 goto done_syscall;
2491 }
2492 default:
2493 break;
2494 }
2495 ret = do_syscall(env, env->active_tc.gpr[2],
2496 env->active_tc.gpr[4],
2497 env->active_tc.gpr[5],
2498 env->active_tc.gpr[6],
2499 env->active_tc.gpr[7],
2500 arg5, arg6, arg7, arg8);
2501 }
2502 done_syscall:
2503 # else
2504 ret = do_syscall(env, env->active_tc.gpr[2],
2505 env->active_tc.gpr[4], env->active_tc.gpr[5],
2506 env->active_tc.gpr[6], env->active_tc.gpr[7],
2507 env->active_tc.gpr[8], env->active_tc.gpr[9],
2508 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2509 # endif /* O32 */
2510 if (ret == -TARGET_QEMU_ESIGRETURN) {
2511 /* Returning from a successful sigreturn syscall.
2512 Avoid clobbering register state. */
2513 break;
2514 }
2515 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2516 env->active_tc.gpr[7] = 1; /* error flag */
2517 ret = -ret;
2518 } else {
2519 env->active_tc.gpr[7] = 0; /* error flag */
2520 }
2521 env->active_tc.gpr[2] = ret;
2522 break;
2523 case EXCP_TLBL:
2524 case EXCP_TLBS:
2525 case EXCP_AdEL:
2526 case EXCP_AdES:
2527 info.si_signo = TARGET_SIGSEGV;
2528 info.si_errno = 0;
2529 /* XXX: check env->error_code */
2530 info.si_code = TARGET_SEGV_MAPERR;
2531 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2532 queue_signal(env, info.si_signo, &info);
2533 break;
2534 case EXCP_CpU:
2535 case EXCP_RI:
2536 info.si_signo = TARGET_SIGILL;
2537 info.si_errno = 0;
2538 info.si_code = 0;
2539 queue_signal(env, info.si_signo, &info);
2540 break;
2541 case EXCP_INTERRUPT:
2542 /* just indicate that signals should be handled asap */
2543 break;
2544 case EXCP_DEBUG:
2545 {
2546 int sig;
2547
2548 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2549 if (sig)
2550 {
2551 info.si_signo = sig;
2552 info.si_errno = 0;
2553 info.si_code = TARGET_TRAP_BRKPT;
2554 queue_signal(env, info.si_signo, &info);
2555 }
2556 }
2557 break;
2558 case EXCP_SC:
2559 if (do_store_exclusive(env)) {
2560 info.si_signo = TARGET_SIGSEGV;
2561 info.si_errno = 0;
2562 info.si_code = TARGET_SEGV_MAPERR;
2563 info._sifields._sigfault._addr = env->active_tc.PC;
2564 queue_signal(env, info.si_signo, &info);
2565 }
2566 break;
2567 case EXCP_DSPDIS:
2568 info.si_signo = TARGET_SIGILL;
2569 info.si_errno = 0;
2570 info.si_code = TARGET_ILL_ILLOPC;
2571 queue_signal(env, info.si_signo, &info);
2572 break;
2573 /* The code below was inspired by the MIPS Linux kernel trap
2574 * handling code in arch/mips/kernel/traps.c.
2575 */
2576 case EXCP_BREAK:
2577 {
2578 abi_ulong trap_instr;
2579 unsigned int code;
2580
2581 if (env->hflags & MIPS_HFLAG_M16) {
2582 if (env->insn_flags & ASE_MICROMIPS) {
2583 /* microMIPS mode */
2584 ret = get_user_u16(trap_instr, env->active_tc.PC);
2585 if (ret != 0) {
2586 goto error;
2587 }
2588
2589 if ((trap_instr >> 10) == 0x11) {
2590 /* 16-bit instruction */
2591 code = trap_instr & 0xf;
2592 } else {
2593 /* 32-bit instruction */
2594 abi_ulong instr_lo;
2595
2596 ret = get_user_u16(instr_lo,
2597 env->active_tc.PC + 2);
2598 if (ret != 0) {
2599 goto error;
2600 }
2601 trap_instr = (trap_instr << 16) | instr_lo;
2602 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2603 /* Unfortunately, microMIPS also suffers from
2604 the old assembler bug... */
2605 if (code >= (1 << 10)) {
2606 code >>= 10;
2607 }
2608 }
2609 } else {
2610 /* MIPS16e mode */
2611 ret = get_user_u16(trap_instr, env->active_tc.PC);
2612 if (ret != 0) {
2613 goto error;
2614 }
2615 code = (trap_instr >> 6) & 0x3f;
2616 }
2617 } else {
2618 ret = get_user_u32(trap_instr, env->active_tc.PC);
2619 if (ret != 0) {
2620 goto error;
2621 }
2622
2623 /* As described in the original Linux kernel code, the
2624 * below checks on 'code' are to work around an old
2625 * assembly bug.
2626 */
2627 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2628 if (code >= (1 << 10)) {
2629 code >>= 10;
2630 }
2631 }
2632
2633 if (do_break(env, &info, code) != 0) {
2634 goto error;
2635 }
2636 }
2637 break;
2638 case EXCP_TRAP:
2639 {
2640 abi_ulong trap_instr;
2641 unsigned int code = 0;
2642
2643 if (env->hflags & MIPS_HFLAG_M16) {
2644 /* microMIPS mode */
2645 abi_ulong instr[2];
2646
2647 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2648 get_user_u16(instr[1], env->active_tc.PC + 2);
2649
2650 trap_instr = (instr[0] << 16) | instr[1];
2651 } else {
2652 ret = get_user_u32(trap_instr, env->active_tc.PC);
2653 }
2654
2655 if (ret != 0) {
2656 goto error;
2657 }
2658
2659 /* The immediate versions don't provide a code. */
2660 if (!(trap_instr & 0xFC000000)) {
2661 if (env->hflags & MIPS_HFLAG_M16) {
2662 /* microMIPS mode */
2663 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2664 } else {
2665 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2666 }
2667 }
2668
2669 if (do_break(env, &info, code) != 0) {
2670 goto error;
2671 }
2672 }
2673 break;
2674 default:
2675 error:
2676 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2677 trapnr);
2678 cpu_dump_state(cs, stderr, fprintf, 0);
2679 abort();
2680 }
2681 process_pending_signals(env);
2682 }
2683 }
2684 #endif
2685
2686 #ifdef TARGET_OPENRISC
2687
2688 void cpu_loop(CPUOpenRISCState *env)
2689 {
2690 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2691 int trapnr, gdbsig;
2692
2693 for (;;) {
2694 cpu_exec_start(cs);
2695 trapnr = cpu_openrisc_exec(cs);
2696 cpu_exec_end(cs);
2697 gdbsig = 0;
2698
2699 switch (trapnr) {
2700 case EXCP_RESET:
2701 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2702 exit(1);
2703 break;
2704 case EXCP_BUSERR:
2705 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2706 gdbsig = TARGET_SIGBUS;
2707 break;
2708 case EXCP_DPF:
2709 case EXCP_IPF:
2710 cpu_dump_state(cs, stderr, fprintf, 0);
2711 gdbsig = TARGET_SIGSEGV;
2712 break;
2713 case EXCP_TICK:
2714 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2715 break;
2716 case EXCP_ALIGN:
2717 qemu_log("\nAlignment pc is %#x\n", env->pc);
2718 gdbsig = TARGET_SIGBUS;
2719 break;
2720 case EXCP_ILLEGAL:
2721 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2722 gdbsig = TARGET_SIGILL;
2723 break;
2724 case EXCP_INT:
2725 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2726 break;
2727 case EXCP_DTLBMISS:
2728 case EXCP_ITLBMISS:
2729 qemu_log("\nTLB miss\n");
2730 break;
2731 case EXCP_RANGE:
2732 qemu_log("\nRange\n");
2733 gdbsig = TARGET_SIGSEGV;
2734 break;
2735 case EXCP_SYSCALL:
2736 env->pc += 4; /* 0xc00; */
2737 env->gpr[11] = do_syscall(env,
2738 env->gpr[11], /* return value */
2739 env->gpr[3], /* r3 - r7 are params */
2740 env->gpr[4],
2741 env->gpr[5],
2742 env->gpr[6],
2743 env->gpr[7],
2744 env->gpr[8], 0, 0);
2745 break;
2746 case EXCP_FPE:
2747 qemu_log("\nFloating point error\n");
2748 break;
2749 case EXCP_TRAP:
2750 qemu_log("\nTrap\n");
2751 gdbsig = TARGET_SIGTRAP;
2752 break;
2753 case EXCP_NR:
2754 qemu_log("\nNR\n");
2755 break;
2756 default:
2757 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2758 trapnr);
2759 cpu_dump_state(cs, stderr, fprintf, 0);
2760 gdbsig = TARGET_SIGILL;
2761 break;
2762 }
2763 if (gdbsig) {
2764 gdb_handlesig(cs, gdbsig);
2765 if (gdbsig != TARGET_SIGTRAP) {
2766 exit(1);
2767 }
2768 }
2769
2770 process_pending_signals(env);
2771 }
2772 }
2773
2774 #endif /* TARGET_OPENRISC */
2775
2776 #ifdef TARGET_SH4
2777 void cpu_loop(CPUSH4State *env)
2778 {
2779 CPUState *cs = CPU(sh_env_get_cpu(env));
2780 int trapnr, ret;
2781 target_siginfo_t info;
2782
2783 while (1) {
2784 cpu_exec_start(cs);
2785 trapnr = cpu_sh4_exec(cs);
2786 cpu_exec_end(cs);
2787
2788 switch (trapnr) {
2789 case 0x160:
2790 env->pc += 2;
2791 ret = do_syscall(env,
2792 env->gregs[3],
2793 env->gregs[4],
2794 env->gregs[5],
2795 env->gregs[6],
2796 env->gregs[7],
2797 env->gregs[0],
2798 env->gregs[1],
2799 0, 0);
2800 env->gregs[0] = ret;
2801 break;
2802 case EXCP_INTERRUPT:
2803 /* just indicate that signals should be handled asap */
2804 break;
2805 case EXCP_DEBUG:
2806 {
2807 int sig;
2808
2809 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2810 if (sig)
2811 {
2812 info.si_signo = sig;
2813 info.si_errno = 0;
2814 info.si_code = TARGET_TRAP_BRKPT;
2815 queue_signal(env, info.si_signo, &info);
2816 }
2817 }
2818 break;
2819 case 0xa0:
2820 case 0xc0:
2821 info.si_signo = TARGET_SIGSEGV;
2822 info.si_errno = 0;
2823 info.si_code = TARGET_SEGV_MAPERR;
2824 info._sifields._sigfault._addr = env->tea;
2825 queue_signal(env, info.si_signo, &info);
2826 break;
2827
2828 default:
2829 printf ("Unhandled trap: 0x%x\n", trapnr);
2830 cpu_dump_state(cs, stderr, fprintf, 0);
2831 exit (1);
2832 }
2833 process_pending_signals (env);
2834 }
2835 }
2836 #endif
2837
2838 #ifdef TARGET_CRIS
2839 void cpu_loop(CPUCRISState *env)
2840 {
2841 CPUState *cs = CPU(cris_env_get_cpu(env));
2842 int trapnr, ret;
2843 target_siginfo_t info;
2844
2845 while (1) {
2846 cpu_exec_start(cs);
2847 trapnr = cpu_cris_exec(cs);
2848 cpu_exec_end(cs);
2849 switch (trapnr) {
2850 case 0xaa:
2851 {
2852 info.si_signo = TARGET_SIGSEGV;
2853 info.si_errno = 0;
2854 /* XXX: check env->error_code */
2855 info.si_code = TARGET_SEGV_MAPERR;
2856 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2857 queue_signal(env, info.si_signo, &info);
2858 }
2859 break;
2860 case EXCP_INTERRUPT:
2861 /* just indicate that signals should be handled asap */
2862 break;
2863 case EXCP_BREAK:
2864 ret = do_syscall(env,
2865 env->regs[9],
2866 env->regs[10],
2867 env->regs[11],
2868 env->regs[12],
2869 env->regs[13],
2870 env->pregs[7],
2871 env->pregs[11],
2872 0, 0);
2873 env->regs[10] = ret;
2874 break;
2875 case EXCP_DEBUG:
2876 {
2877 int sig;
2878
2879 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2880 if (sig)
2881 {
2882 info.si_signo = sig;
2883 info.si_errno = 0;
2884 info.si_code = TARGET_TRAP_BRKPT;
2885 queue_signal(env, info.si_signo, &info);
2886 }
2887 }
2888 break;
2889 default:
2890 printf ("Unhandled trap: 0x%x\n", trapnr);
2891 cpu_dump_state(cs, stderr, fprintf, 0);
2892 exit (1);
2893 }
2894 process_pending_signals (env);
2895 }
2896 }
2897 #endif
2898
2899 #ifdef TARGET_MICROBLAZE
2900 void cpu_loop(CPUMBState *env)
2901 {
2902 CPUState *cs = CPU(mb_env_get_cpu(env));
2903 int trapnr, ret;
2904 target_siginfo_t info;
2905
2906 while (1) {
2907 cpu_exec_start(cs);
2908 trapnr = cpu_mb_exec(cs);
2909 cpu_exec_end(cs);
2910 switch (trapnr) {
2911 case 0xaa:
2912 {
2913 info.si_signo = TARGET_SIGSEGV;
2914 info.si_errno = 0;
2915 /* XXX: check env->error_code */
2916 info.si_code = TARGET_SEGV_MAPERR;
2917 info._sifields._sigfault._addr = 0;
2918 queue_signal(env, info.si_signo, &info);
2919 }
2920 break;
2921 case EXCP_INTERRUPT:
2922 /* just indicate that signals should be handled asap */
2923 break;
2924 case EXCP_BREAK:
2925 /* Return address is 4 bytes after the call. */
2926 env->regs[14] += 4;
2927 env->sregs[SR_PC] = env->regs[14];
2928 ret = do_syscall(env,
2929 env->regs[12],
2930 env->regs[5],
2931 env->regs[6],
2932 env->regs[7],
2933 env->regs[8],
2934 env->regs[9],
2935 env->regs[10],
2936 0, 0);
2937 env->regs[3] = ret;
2938 break;
2939 case EXCP_HW_EXCP:
2940 env->regs[17] = env->sregs[SR_PC] + 4;
2941 if (env->iflags & D_FLAG) {
2942 env->sregs[SR_ESR] |= 1 << 12;
2943 env->sregs[SR_PC] -= 4;
2944 /* FIXME: if branch was immed, replay the imm as well. */
2945 }
2946
2947 env->iflags &= ~(IMM_FLAG | D_FLAG);
2948
2949 switch (env->sregs[SR_ESR] & 31) {
2950 case ESR_EC_DIVZERO:
2951 info.si_signo = TARGET_SIGFPE;
2952 info.si_errno = 0;
2953 info.si_code = TARGET_FPE_FLTDIV;
2954 info._sifields._sigfault._addr = 0;
2955 queue_signal(env, info.si_signo, &info);
2956 break;
2957 case ESR_EC_FPU:
2958 info.si_signo = TARGET_SIGFPE;
2959 info.si_errno = 0;
2960 if (env->sregs[SR_FSR] & FSR_IO) {
2961 info.si_code = TARGET_FPE_FLTINV;
2962 }
2963 if (env->sregs[SR_FSR] & FSR_DZ) {
2964 info.si_code = TARGET_FPE_FLTDIV;
2965 }
2966 info._sifields._sigfault._addr = 0;
2967 queue_signal(env, info.si_signo, &info);
2968 break;
2969 default:
2970 printf ("Unhandled hw-exception: 0x%x\n",
2971 env->sregs[SR_ESR] & ESR_EC_MASK);
2972 cpu_dump_state(cs, stderr, fprintf, 0);
2973 exit (1);
2974 break;
2975 }
2976 break;
2977 case EXCP_DEBUG:
2978 {
2979 int sig;
2980
2981 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2982 if (sig)
2983 {
2984 info.si_signo = sig;
2985 info.si_errno = 0;
2986 info.si_code = TARGET_TRAP_BRKPT;
2987 queue_signal(env, info.si_signo, &info);
2988 }
2989 }
2990 break;
2991 default:
2992 printf ("Unhandled trap: 0x%x\n", trapnr);
2993 cpu_dump_state(cs, stderr, fprintf, 0);
2994 exit (1);
2995 }
2996 process_pending_signals (env);
2997 }
2998 }
2999 #endif
3000
3001 #ifdef TARGET_M68K
3002
3003 void cpu_loop(CPUM68KState *env)
3004 {
3005 CPUState *cs = CPU(m68k_env_get_cpu(env));
3006 int trapnr;
3007 unsigned int n;
3008 target_siginfo_t info;
3009 TaskState *ts = cs->opaque;
3010
3011 for(;;) {
3012 cpu_exec_start(cs);
3013 trapnr = cpu_m68k_exec(cs);
3014 cpu_exec_end(cs);
3015 switch(trapnr) {
3016 case EXCP_ILLEGAL:
3017 {
3018 if (ts->sim_syscalls) {
3019 uint16_t nr;
3020 get_user_u16(nr, env->pc + 2);
3021 env->pc += 4;
3022 do_m68k_simcall(env, nr);
3023 } else {
3024 goto do_sigill;
3025 }
3026 }
3027 break;
3028 case EXCP_HALT_INSN:
3029 /* Semihosing syscall. */
3030 env->pc += 4;
3031 do_m68k_semihosting(env, env->dregs[0]);
3032 break;
3033 case EXCP_LINEA:
3034 case EXCP_LINEF:
3035 case EXCP_UNSUPPORTED:
3036 do_sigill:
3037 info.si_signo = TARGET_SIGILL;
3038 info.si_errno = 0;
3039 info.si_code = TARGET_ILL_ILLOPN;
3040 info._sifields._sigfault._addr = env->pc;
3041 queue_signal(env, info.si_signo, &info);
3042 break;
3043 case EXCP_TRAP0:
3044 {
3045 ts->sim_syscalls = 0;
3046 n = env->dregs[0];
3047 env->pc += 2;
3048 env->dregs[0] = do_syscall(env,
3049 n,
3050 env->dregs[1],
3051 env->dregs[2],
3052 env->dregs[3],
3053 env->dregs[4],
3054 env->dregs[5],
3055 env->aregs[0],
3056 0, 0);
3057 }
3058 break;
3059 case EXCP_INTERRUPT:
3060 /* just indicate that signals should be handled asap */
3061 break;
3062 case EXCP_ACCESS:
3063 {
3064 info.si_signo = TARGET_SIGSEGV;
3065 info.si_errno = 0;
3066 /* XXX: check env->error_code */
3067 info.si_code = TARGET_SEGV_MAPERR;
3068 info._sifields._sigfault._addr = env->mmu.ar;
3069 queue_signal(env, info.si_signo, &info);
3070 }
3071 break;
3072 case EXCP_DEBUG:
3073 {
3074 int sig;
3075
3076 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3077 if (sig)
3078 {
3079 info.si_signo = sig;
3080 info.si_errno = 0;
3081 info.si_code = TARGET_TRAP_BRKPT;
3082 queue_signal(env, info.si_signo, &info);
3083 }
3084 }
3085 break;
3086 default:
3087 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3088 trapnr);
3089 cpu_dump_state(cs, stderr, fprintf, 0);
3090 abort();
3091 }
3092 process_pending_signals(env);
3093 }
3094 }
3095 #endif /* TARGET_M68K */
3096
3097 #ifdef TARGET_ALPHA
3098 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3099 {
3100 target_ulong addr, val, tmp;
3101 target_siginfo_t info;
3102 int ret = 0;
3103
3104 addr = env->lock_addr;
3105 tmp = env->lock_st_addr;
3106 env->lock_addr = -1;
3107 env->lock_st_addr = 0;
3108
3109 start_exclusive();
3110 mmap_lock();
3111
3112 if (addr == tmp) {
3113 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3114 goto do_sigsegv;
3115 }
3116
3117 if (val == env->lock_value) {
3118 tmp = env->ir[reg];
3119 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3120 goto do_sigsegv;
3121 }
3122 ret = 1;
3123 }
3124 }
3125 env->ir[reg] = ret;
3126 env->pc += 4;
3127
3128 mmap_unlock();
3129 end_exclusive();
3130 return;
3131
3132 do_sigsegv:
3133 mmap_unlock();
3134 end_exclusive();
3135
3136 info.si_signo = TARGET_SIGSEGV;
3137 info.si_errno = 0;
3138 info.si_code = TARGET_SEGV_MAPERR;
3139 info._sifields._sigfault._addr = addr;
3140 queue_signal(env, TARGET_SIGSEGV, &info);
3141 }
3142
3143 void cpu_loop(CPUAlphaState *env)
3144 {
3145 CPUState *cs = CPU(alpha_env_get_cpu(env));
3146 int trapnr;
3147 target_siginfo_t info;
3148 abi_long sysret;
3149
3150 while (1) {
3151 cpu_exec_start(cs);
3152 trapnr = cpu_alpha_exec(cs);
3153 cpu_exec_end(cs);
3154
3155 /* All of the traps imply a transition through PALcode, which
3156 implies an REI instruction has been executed. Which means
3157 that the intr_flag should be cleared. */
3158 env->intr_flag = 0;
3159
3160 switch (trapnr) {
3161 case EXCP_RESET:
3162 fprintf(stderr, "Reset requested. Exit\n");
3163 exit(1);
3164 break;
3165 case EXCP_MCHK:
3166 fprintf(stderr, "Machine check exception. Exit\n");
3167 exit(1);
3168 break;
3169 case EXCP_SMP_INTERRUPT:
3170 case EXCP_CLK_INTERRUPT:
3171 case EXCP_DEV_INTERRUPT:
3172 fprintf(stderr, "External interrupt. Exit\n");
3173 exit(1);
3174 break;
3175 case EXCP_MMFAULT:
3176 env->lock_addr = -1;
3177 info.si_signo = TARGET_SIGSEGV;
3178 info.si_errno = 0;
3179 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3180 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3181 info._sifields._sigfault._addr = env->trap_arg0;
3182 queue_signal(env, info.si_signo, &info);
3183 break;
3184 case EXCP_UNALIGN:
3185 env->lock_addr = -1;
3186 info.si_signo = TARGET_SIGBUS;
3187 info.si_errno = 0;
3188 info.si_code = TARGET_BUS_ADRALN;
3189 info._sifields._sigfault._addr = env->trap_arg0;
3190 queue_signal(env, info.si_signo, &info);
3191 break;
3192 case EXCP_OPCDEC:
3193 do_sigill:
3194 env->lock_addr = -1;
3195 info.si_signo = TARGET_SIGILL;
3196 info.si_errno = 0;
3197 info.si_code = TARGET_ILL_ILLOPC;
3198 info._sifields._sigfault._addr = env->pc;
3199 queue_signal(env, info.si_signo, &info);
3200 break;
3201 case EXCP_ARITH:
3202 env->lock_addr = -1;
3203 info.si_signo = TARGET_SIGFPE;
3204 info.si_errno = 0;
3205 info.si_code = TARGET_FPE_FLTINV;
3206 info._sifields._sigfault._addr = env->pc;
3207 queue_signal(env, info.si_signo, &info);
3208 break;
3209 case EXCP_FEN:
3210 /* No-op. Linux simply re-enables the FPU. */
3211 break;
3212 case EXCP_CALL_PAL:
3213 env->lock_addr = -1;
3214 switch (env->error_code) {
3215 case 0x80:
3216 /* BPT */
3217 info.si_signo = TARGET_SIGTRAP;
3218 info.si_errno = 0;
3219 info.si_code = TARGET_TRAP_BRKPT;
3220 info._sifields._sigfault._addr = env->pc;
3221 queue_signal(env, info.si_signo, &info);
3222 break;
3223 case 0x81:
3224 /* BUGCHK */
3225 info.si_signo = TARGET_SIGTRAP;
3226 info.si_errno = 0;
3227 info.si_code = 0;
3228 info._sifields._sigfault._addr = env->pc;
3229 queue_signal(env, info.si_signo, &info);
3230 break;
3231 case 0x83:
3232 /* CALLSYS */
3233 trapnr = env->ir[IR_V0];
3234 sysret = do_syscall(env, trapnr,
3235 env->ir[IR_A0], env->ir[IR_A1],
3236 env->ir[IR_A2], env->ir[IR_A3],
3237 env->ir[IR_A4], env->ir[IR_A5],
3238 0, 0);
3239 if (trapnr == TARGET_NR_sigreturn
3240 || trapnr == TARGET_NR_rt_sigreturn) {
3241 break;
3242 }
3243 /* Syscall writes 0 to V0 to bypass error check, similar
3244 to how this is handled internal to Linux kernel.
3245 (Ab)use trapnr temporarily as boolean indicating error. */
3246 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3247 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3248 env->ir[IR_A3] = trapnr;
3249 break;
3250 case 0x86:
3251 /* IMB */
3252 /* ??? We can probably elide the code using page_unprotect
3253 that is checking for self-modifying code. Instead we
3254 could simply call tb_flush here. Until we work out the
3255 changes required to turn off the extra write protection,
3256 this can be a no-op. */
3257 break;
3258 case 0x9E:
3259 /* RDUNIQUE */
3260 /* Handled in the translator for usermode. */
3261 abort();
3262 case 0x9F:
3263 /* WRUNIQUE */
3264 /* Handled in the translator for usermode. */
3265 abort();
3266 case 0xAA:
3267 /* GENTRAP */
3268 info.si_signo = TARGET_SIGFPE;
3269 switch (env->ir[IR_A0]) {
3270 case TARGET_GEN_INTOVF:
3271 info.si_code = TARGET_FPE_INTOVF;
3272 break;
3273 case TARGET_GEN_INTDIV:
3274 info.si_code = TARGET_FPE_INTDIV;
3275 break;
3276 case TARGET_GEN_FLTOVF:
3277 info.si_code = TARGET_FPE_FLTOVF;
3278 break;
3279 case TARGET_GEN_FLTUND:
3280 info.si_code = TARGET_FPE_FLTUND;
3281 break;
3282 case TARGET_GEN_FLTINV:
3283 info.si_code = TARGET_FPE_FLTINV;
3284 break;
3285 case TARGET_GEN_FLTINE:
3286 info.si_code = TARGET_FPE_FLTRES;
3287 break;
3288 case TARGET_GEN_ROPRAND:
3289 info.si_code = 0;
3290 break;
3291 default:
3292 info.si_signo = TARGET_SIGTRAP;
3293 info.si_code = 0;
3294 break;
3295 }
3296 info.si_errno = 0;
3297 info._sifields._sigfault._addr = env->pc;
3298 queue_signal(env, info.si_signo, &info);
3299 break;
3300 default:
3301 goto do_sigill;
3302 }
3303 break;
3304 case EXCP_DEBUG:
3305 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3306 if (info.si_signo) {
3307 env->lock_addr = -1;
3308 info.si_errno = 0;
3309 info.si_code = TARGET_TRAP_BRKPT;
3310 queue_signal(env, info.si_signo, &info);
3311 }
3312 break;
3313 case EXCP_STL_C:
3314 case EXCP_STQ_C:
3315 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3316 break;
3317 case EXCP_INTERRUPT:
3318 /* Just indicate that signals should be handled asap. */
3319 break;
3320 default:
3321 printf ("Unhandled trap: 0x%x\n", trapnr);
3322 cpu_dump_state(cs, stderr, fprintf, 0);
3323 exit (1);
3324 }
3325 process_pending_signals (env);
3326 }
3327 }
3328 #endif /* TARGET_ALPHA */
3329
3330 #ifdef TARGET_S390X
3331 void cpu_loop(CPUS390XState *env)
3332 {
3333 CPUState *cs = CPU(s390_env_get_cpu(env));
3334 int trapnr, n, sig;
3335 target_siginfo_t info;
3336 target_ulong addr;
3337
3338 while (1) {
3339 cpu_exec_start(cs);
3340 trapnr = cpu_s390x_exec(cs);
3341 cpu_exec_end(cs);
3342 switch (trapnr) {
3343 case EXCP_INTERRUPT:
3344 /* Just indicate that signals should be handled asap. */
3345 break;
3346
3347 case EXCP_SVC:
3348 n = env->int_svc_code;
3349 if (!n) {
3350 /* syscalls > 255 */
3351 n = env->regs[1];
3352 }
3353 env->psw.addr += env->int_svc_ilen;
3354 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3355 env->regs[4], env->regs[5],
3356 env->regs[6], env->regs[7], 0, 0);
3357 break;
3358
3359 case EXCP_DEBUG:
3360 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3361 if (sig) {
3362 n = TARGET_TRAP_BRKPT;
3363 goto do_signal_pc;
3364 }
3365 break;
3366 case EXCP_PGM:
3367 n = env->int_pgm_code;
3368 switch (n) {
3369 case PGM_OPERATION:
3370 case PGM_PRIVILEGED:
3371 sig = TARGET_SIGILL;
3372 n = TARGET_ILL_ILLOPC;
3373 goto do_signal_pc;
3374 case PGM_PROTECTION:
3375 case PGM_ADDRESSING:
3376 sig = TARGET_SIGSEGV;
3377 /* XXX: check env->error_code */
3378 n = TARGET_SEGV_MAPERR;
3379 addr = env->__excp_addr;
3380 goto do_signal;
3381 case PGM_EXECUTE:
3382 case PGM_SPECIFICATION:
3383 case PGM_SPECIAL_OP:
3384 case PGM_OPERAND:
3385 do_sigill_opn:
3386 sig = TARGET_SIGILL;
3387 n = TARGET_ILL_ILLOPN;
3388 goto do_signal_pc;
3389
3390 case PGM_FIXPT_OVERFLOW:
3391 sig = TARGET_SIGFPE;
3392 n = TARGET_FPE_INTOVF;
3393 goto do_signal_pc;
3394 case PGM_FIXPT_DIVIDE:
3395 sig = TARGET_SIGFPE;
3396 n = TARGET_FPE_INTDIV;
3397 goto do_signal_pc;
3398
3399 case PGM_DATA:
3400 n = (env->fpc >> 8) & 0xff;
3401 if (n == 0xff) {
3402 /* compare-and-trap */
3403 goto do_sigill_opn;
3404 } else {
3405 /* An IEEE exception, simulated or otherwise. */
3406 if (n & 0x80) {
3407 n = TARGET_FPE_FLTINV;
3408 } else if (n & 0x40) {
3409 n = TARGET_FPE_FLTDIV;
3410 } else if (n & 0x20) {
3411 n = TARGET_FPE_FLTOVF;
3412 } else if (n & 0x10) {
3413 n = TARGET_FPE_FLTUND;
3414 } else if (n & 0x08) {
3415 n = TARGET_FPE_FLTRES;
3416 } else {
3417 /* ??? Quantum exception; BFP, DFP error. */
3418 goto do_sigill_opn;
3419 }
3420 sig = TARGET_SIGFPE;
3421 goto do_signal_pc;
3422 }
3423
3424 default:
3425 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3426 cpu_dump_state(cs, stderr, fprintf, 0);
3427 exit(1);
3428 }
3429 break;
3430
3431 do_signal_pc:
3432 addr = env->psw.addr;
3433 do_signal:
3434 info.si_signo = sig;
3435 info.si_errno = 0;
3436 info.si_code = n;
3437 info._sifields._sigfault._addr = addr;
3438 queue_signal(env, info.si_signo, &info);
3439 break;
3440
3441 default:
3442 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3443 cpu_dump_state(cs, stderr, fprintf, 0);
3444 exit(1);
3445 }
3446 process_pending_signals (env);
3447 }
3448 }
3449
3450 #endif /* TARGET_S390X */
3451
3452 THREAD CPUState *thread_cpu;
3453
3454 void task_settid(TaskState *ts)
3455 {
3456 if (ts->ts_tid == 0) {
3457 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3458 }
3459 }
3460
3461 void stop_all_tasks(void)
3462 {
3463 /*
3464 * We trust that when using NPTL, start_exclusive()
3465 * handles thread stopping correctly.
3466 */
3467 start_exclusive();
3468 }
3469
3470 /* Assumes contents are already zeroed. */
3471 void init_task_state(TaskState *ts)
3472 {
3473 int i;
3474
3475 ts->used = 1;
3476 ts->first_free = ts->sigqueue_table;
3477 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3478 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3479 }
3480 ts->sigqueue_table[i].next = NULL;
3481 }
3482
3483 CPUArchState *cpu_copy(CPUArchState *env)
3484 {
3485 CPUState *cpu = ENV_GET_CPU(env);
3486 CPUState *new_cpu = cpu_init(cpu_model);
3487 CPUArchState *new_env = new_cpu->env_ptr;
3488 CPUBreakpoint *bp;
3489 CPUWatchpoint *wp;
3490
3491 /* Reset non arch specific state */
3492 cpu_reset(new_cpu);
3493
3494 memcpy(new_env, env, sizeof(CPUArchState));
3495
3496 /* Clone all break/watchpoints.
3497 Note: Once we support ptrace with hw-debug register access, make sure
3498 BP_CPU break/watchpoints are handled correctly on clone. */
3499 QTAILQ_INIT(&new_cpu->breakpoints);
3500 QTAILQ_INIT(&new_cpu->watchpoints);
3501 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3502 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3503 }
3504 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3505 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3506 }
3507
3508 return new_env;
3509 }
3510
3511 static void handle_arg_help(const char *arg)
3512 {
3513 usage();
3514 }
3515
3516 static void handle_arg_log(const char *arg)
3517 {
3518 int mask;
3519
3520 mask = qemu_str_to_log_mask(arg);
3521 if (!mask) {
3522 qemu_print_log_usage(stdout);
3523 exit(1);
3524 }
3525 qemu_set_log(mask);
3526 }
3527
3528 static void handle_arg_log_filename(const char *arg)
3529 {
3530 qemu_set_log_filename(arg);
3531 }
3532
3533 static void handle_arg_set_env(const char *arg)
3534 {
3535 char *r, *p, *token;
3536 r = p = strdup(arg);
3537 while ((token = strsep(&p, ",")) != NULL) {
3538 if (envlist_setenv(envlist, token) != 0) {
3539 usage();
3540 }
3541 }
3542 free(r);
3543 }
3544
3545 static void handle_arg_unset_env(const char *arg)
3546 {
3547 char *r, *p, *token;
3548 r = p = strdup(arg);
3549 while ((token = strsep(&p, ",")) != NULL) {
3550 if (envlist_unsetenv(envlist, token) != 0) {
3551 usage();
3552 }
3553 }
3554 free(r);
3555 }
3556
3557 static void handle_arg_argv0(const char *arg)
3558 {
3559 argv0 = strdup(arg);
3560 }
3561
3562 static void handle_arg_stack_size(const char *arg)
3563 {
3564 char *p;
3565 guest_stack_size = strtoul(arg, &p, 0);
3566 if (guest_stack_size == 0) {
3567 usage();
3568 }
3569
3570 if (*p == 'M') {
3571 guest_stack_size *= 1024 * 1024;
3572 } else if (*p == 'k' || *p == 'K') {
3573 guest_stack_size *= 1024;
3574 }
3575 }
3576
3577 static void handle_arg_ld_prefix(const char *arg)
3578 {
3579 interp_prefix = strdup(arg);
3580 }
3581
3582 static void handle_arg_pagesize(const char *arg)
3583 {
3584 qemu_host_page_size = atoi(arg);
3585 if (qemu_host_page_size == 0 ||
3586 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3587 fprintf(stderr, "page size must be a power of two\n");
3588 exit(1);
3589 }
3590 }
3591
3592 static void handle_arg_randseed(const char *arg)
3593 {
3594 unsigned long long seed;
3595
3596 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3597 fprintf(stderr, "Invalid seed number: %s\n", arg);
3598 exit(1);
3599 }
3600 srand(seed);
3601 }
3602
3603 static void handle_arg_gdb(const char *arg)
3604 {
3605 gdbstub_port = atoi(arg);
3606 }
3607
3608 static void handle_arg_uname(const char *arg)
3609 {
3610 qemu_uname_release = strdup(arg);
3611 }
3612
3613 static void handle_arg_cpu(const char *arg)
3614 {
3615 cpu_model = strdup(arg);
3616 if (cpu_model == NULL || is_help_option(cpu_model)) {
3617 /* XXX: implement xxx_cpu_list for targets that still miss it */
3618 #if defined(cpu_list_id)
3619 cpu_list_id(stdout, &fprintf, "");
3620 #elif defined(cpu_list)
3621 cpu_list(stdout, &fprintf); /* deprecated */
3622 #else
3623 /* TODO: add cpu selection for alpha, microblaze, unicore32, s390x. */
3624 printf("Target ignores cpu selection\n");
3625 #endif
3626 exit(1);
3627 }
3628 }
3629
3630 static void handle_arg_guest_base(const char *arg)
3631 {
3632 guest_base = strtol(arg, NULL, 0);
3633 have_guest_base = 1;
3634 }
3635
3636 static void handle_arg_reserved_va(const char *arg)
3637 {
3638 char *p;
3639 int shift = 0;
3640 reserved_va = strtoul(arg, &p, 0);
3641 switch (*p) {
3642 case 'k':
3643 case 'K':
3644 shift = 10;
3645 break;
3646 case 'M':
3647 shift = 20;
3648 break;
3649 case 'G':
3650 shift = 30;
3651 break;
3652 }
3653 if (shift) {
3654 unsigned long unshifted = reserved_va;
3655 p++;
3656 reserved_va <<= shift;
3657 if (((reserved_va >> shift) != unshifted)
3658 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3659 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3660 #endif
3661 ) {
3662 fprintf(stderr, "Reserved virtual address too big\n");
3663 exit(1);
3664 }
3665 }
3666 if (*p) {
3667 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3668 exit(1);
3669 }
3670 }
3671
3672 static void handle_arg_singlestep(const char *arg)
3673 {
3674 singlestep = 1;
3675 }
3676
3677 static void handle_arg_strace(const char *arg)
3678 {
3679 do_strace = 1;
3680 }
3681
3682 static void handle_arg_version(const char *arg)
3683 {
3684 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3685 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3686 exit(0);
3687 }
3688
3689 struct qemu_argument {
3690 const char *argv;
3691 const char *env;
3692 bool has_arg;
3693 void (*handle_opt)(const char *arg);
3694 const char *example;
3695 const char *help;
3696 };
3697
3698 static const struct qemu_argument arg_table[] = {
3699 {"h", "", false, handle_arg_help,
3700 "", "print this help"},
3701 {"g", "QEMU_GDB", true, handle_arg_gdb,
3702 "port", "wait gdb connection to 'port'"},
3703 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3704 "path", "set the elf interpreter prefix to 'path'"},
3705 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3706 "size", "set the stack size to 'size' bytes"},
3707 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3708 "model", "select CPU (-cpu help for list)"},
3709 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3710 "var=value", "sets targets environment variable (see below)"},
3711 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3712 "var", "unsets targets environment variable (see below)"},
3713 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3714 "argv0", "forces target process argv[0] to be 'argv0'"},
3715 {"r", "QEMU_UNAME", true, handle_arg_uname,
3716 "uname", "set qemu uname release string to 'uname'"},
3717 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3718 "address", "set guest_base address to 'address'"},
3719 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3720 "size", "reserve 'size' bytes for guest virtual address space"},
3721 {"d", "QEMU_LOG", true, handle_arg_log,
3722 "item[,...]", "enable logging of specified items "
3723 "(use '-d help' for a list of items)"},
3724 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3725 "logfile", "write logs to 'logfile' (default stderr)"},
3726 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3727 "pagesize", "set the host page size to 'pagesize'"},
3728 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3729 "", "run in singlestep mode"},
3730 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3731 "", "log system calls"},
3732 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3733 "", "Seed for pseudo-random number generator"},
3734 {"version", "QEMU_VERSION", false, handle_arg_version,
3735 "", "display version information and exit"},
3736 {NULL, NULL, false, NULL, NULL, NULL}
3737 };
3738
3739 static void QEMU_NORETURN usage(void)
3740 {
3741 const struct qemu_argument *arginfo;
3742 int maxarglen;
3743 int maxenvlen;
3744
3745 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3746 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3747 "\n"
3748 "Options and associated environment variables:\n"
3749 "\n");
3750
3751 /* Calculate column widths. We must always have at least enough space
3752 * for the column header.
3753 */
3754 maxarglen = strlen("Argument");
3755 maxenvlen = strlen("Env-variable");
3756
3757 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3758 int arglen = strlen(arginfo->argv);
3759 if (arginfo->has_arg) {
3760 arglen += strlen(arginfo->example) + 1;
3761 }
3762 if (strlen(arginfo->env) > maxenvlen) {
3763 maxenvlen = strlen(arginfo->env);
3764 }
3765 if (arglen > maxarglen) {
3766 maxarglen = arglen;
3767 }
3768 }
3769
3770 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3771 maxenvlen, "Env-variable");
3772
3773 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3774 if (arginfo->has_arg) {
3775 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3776 (int)(maxarglen - strlen(arginfo->argv) - 1),
3777 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3778 } else {
3779 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3780 maxenvlen, arginfo->env,
3781 arginfo->help);
3782 }
3783 }
3784
3785 printf("\n"
3786 "Defaults:\n"
3787 "QEMU_LD_PREFIX = %s\n"
3788 "QEMU_STACK_SIZE = %ld byte\n",
3789 interp_prefix,
3790 guest_stack_size);
3791
3792 printf("\n"
3793 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3794 "QEMU_UNSET_ENV environment variables to set and unset\n"
3795 "environment variables for the target process.\n"
3796 "It is possible to provide several variables by separating them\n"
3797 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3798 "provide the -E and -U options multiple times.\n"
3799 "The following lines are equivalent:\n"
3800 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3801 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3802 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3803 "Note that if you provide several changes to a single variable\n"
3804 "the last change will stay in effect.\n");
3805
3806 exit(1);
3807 }
3808
3809 static int parse_args(int argc, char **argv)
3810 {
3811 const char *r;
3812 int optind;
3813 const struct qemu_argument *arginfo;
3814
3815 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3816 if (arginfo->env == NULL) {
3817 continue;
3818 }
3819
3820 r = getenv(arginfo->env);
3821 if (r != NULL) {
3822 arginfo->handle_opt(r);
3823 }
3824 }
3825
3826 optind = 1;
3827 for (;;) {
3828 if (optind >= argc) {
3829 break;
3830 }
3831 r = argv[optind];
3832 if (r[0] != '-') {
3833 break;
3834 }
3835 optind++;
3836 r++;
3837 if (!strcmp(r, "-")) {
3838 break;
3839 }
3840
3841 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3842 if (!strcmp(r, arginfo->argv)) {
3843 if (arginfo->has_arg) {
3844 if (optind >= argc) {
3845 usage();
3846 }
3847 arginfo->handle_opt(argv[optind]);
3848 optind++;
3849 } else {
3850 arginfo->handle_opt(NULL);
3851 }
3852 break;
3853 }
3854 }
3855
3856 /* no option matched the current argv */
3857 if (arginfo->handle_opt == NULL) {
3858 usage();
3859 }
3860 }
3861
3862 if (optind >= argc) {
3863 usage();
3864 }
3865
3866 filename = argv[optind];
3867 exec_path = argv[optind];
3868
3869 return optind;
3870 }
3871
3872 int main(int argc, char **argv)
3873 {
3874 struct target_pt_regs regs1, *regs = &regs1;
3875 struct image_info info1, *info = &info1;
3876 struct linux_binprm bprm;
3877 TaskState *ts;
3878 CPUArchState *env;
3879 CPUState *cpu;
3880 int optind;
3881 char **target_environ, **wrk;
3882 char **target_argv;
3883 int target_argc;
3884 int i;
3885 int ret;
3886 int execfd;
3887
3888 module_call_init(MODULE_INIT_QOM);
3889
3890 if ((envlist = envlist_create()) == NULL) {
3891 (void) fprintf(stderr, "Unable to allocate envlist\n");
3892 exit(1);
3893 }
3894
3895 /* add current environment into the list */
3896 for (wrk = environ; *wrk != NULL; wrk++) {
3897 (void) envlist_setenv(envlist, *wrk);
3898 }
3899
3900 /* Read the stack limit from the kernel. If it's "unlimited",
3901 then we can do little else besides use the default. */
3902 {
3903 struct rlimit lim;
3904 if (getrlimit(RLIMIT_STACK, &lim) == 0
3905 && lim.rlim_cur != RLIM_INFINITY
3906 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3907 guest_stack_size = lim.rlim_cur;
3908 }
3909 }
3910
3911 cpu_model = NULL;
3912 #if defined(cpudef_setup)
3913 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3914 #endif
3915
3916 srand(time(NULL));
3917
3918 optind = parse_args(argc, argv);
3919
3920 /* Zero out regs */
3921 memset(regs, 0, sizeof(struct target_pt_regs));
3922
3923 /* Zero out image_info */
3924 memset(info, 0, sizeof(struct image_info));
3925
3926 memset(&bprm, 0, sizeof (bprm));
3927
3928 /* Scan interp_prefix dir for replacement files. */
3929 init_paths(interp_prefix);
3930
3931 init_qemu_uname_release();
3932
3933 if (cpu_model == NULL) {
3934 #if defined(TARGET_I386)
3935 #ifdef TARGET_X86_64
3936 cpu_model = "qemu64";
3937 #else
3938 cpu_model = "qemu32";
3939 #endif
3940 #elif defined(TARGET_ARM)
3941 cpu_model = "any";
3942 #elif defined(TARGET_UNICORE32)
3943 cpu_model = "any";
3944 #elif defined(TARGET_M68K)
3945 cpu_model = "any";
3946 #elif defined(TARGET_SPARC)
3947 #ifdef TARGET_SPARC64
3948 cpu_model = "TI UltraSparc II";
3949 #else
3950 cpu_model = "Fujitsu MB86904";
3951 #endif
3952 #elif defined(TARGET_MIPS)
3953 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3954 cpu_model = "5KEf";
3955 #else
3956 cpu_model = "24Kf";
3957 #endif
3958 #elif defined TARGET_OPENRISC
3959 cpu_model = "or1200";
3960 #elif defined(TARGET_PPC)
3961 # ifdef TARGET_PPC64
3962 cpu_model = "POWER7";
3963 # else
3964 cpu_model = "750";
3965 # endif
3966 #elif defined TARGET_SH4
3967 cpu_model = TYPE_SH7785_CPU;
3968 #else
3969 cpu_model = "any";
3970 #endif
3971 }
3972 tcg_exec_init(0);
3973 /* NOTE: we need to init the CPU at this stage to get
3974 qemu_host_page_size */
3975 cpu = cpu_init(cpu_model);
3976 if (!cpu) {
3977 fprintf(stderr, "Unable to find CPU definition\n");
3978 exit(1);
3979 }
3980 env = cpu->env_ptr;
3981 cpu_reset(cpu);
3982
3983 thread_cpu = cpu;
3984
3985 if (getenv("QEMU_STRACE")) {
3986 do_strace = 1;
3987 }
3988
3989 if (getenv("QEMU_RAND_SEED")) {
3990 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3991 }
3992
3993 target_environ = envlist_to_environ(envlist, NULL);
3994 envlist_free(envlist);
3995
3996 /*
3997 * Now that page sizes are configured in cpu_init() we can do
3998 * proper page alignment for guest_base.
3999 */
4000 guest_base = HOST_PAGE_ALIGN(guest_base);
4001
4002 if (reserved_va || have_guest_base) {
4003 guest_base = init_guest_space(guest_base, reserved_va, 0,
4004 have_guest_base);
4005 if (guest_base == (unsigned long)-1) {
4006 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4007 "space for use as guest address space (check your virtual "
4008 "memory ulimit setting or reserve less using -R option)\n",
4009 reserved_va);
4010 exit(1);
4011 }
4012
4013 if (reserved_va) {
4014 mmap_next_start = reserved_va;
4015 }
4016 }
4017
4018 /*
4019 * Read in mmap_min_addr kernel parameter. This value is used
4020 * When loading the ELF image to determine whether guest_base
4021 * is needed. It is also used in mmap_find_vma.
4022 */
4023 {
4024 FILE *fp;
4025
4026 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4027 unsigned long tmp;
4028 if (fscanf(fp, "%lu", &tmp) == 1) {
4029 mmap_min_addr = tmp;
4030 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
4031 }
4032 fclose(fp);
4033 }
4034 }
4035
4036 /*
4037 * Prepare copy of argv vector for target.
4038 */
4039 target_argc = argc - optind;
4040 target_argv = calloc(target_argc + 1, sizeof (char *));
4041 if (target_argv == NULL) {
4042 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4043 exit(1);
4044 }
4045
4046 /*
4047 * If argv0 is specified (using '-0' switch) we replace
4048 * argv[0] pointer with the given one.
4049 */
4050 i = 0;
4051 if (argv0 != NULL) {
4052 target_argv[i++] = strdup(argv0);
4053 }
4054 for (; i < target_argc; i++) {
4055 target_argv[i] = strdup(argv[optind + i]);
4056 }
4057 target_argv[target_argc] = NULL;
4058
4059 ts = g_malloc0 (sizeof(TaskState));
4060 init_task_state(ts);
4061 /* build Task State */
4062 ts->info = info;
4063 ts->bprm = &bprm;
4064 cpu->opaque = ts;
4065 task_settid(ts);
4066
4067 execfd = qemu_getauxval(AT_EXECFD);
4068 if (execfd == 0) {
4069 execfd = open(filename, O_RDONLY);
4070 if (execfd < 0) {
4071 printf("Error while loading %s: %s\n", filename, strerror(errno));
4072 _exit(1);
4073 }
4074 }
4075
4076 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4077 info, &bprm);
4078 if (ret != 0) {
4079 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4080 _exit(1);
4081 }
4082
4083 for (wrk = target_environ; *wrk; wrk++) {
4084 free(*wrk);
4085 }
4086
4087 free(target_environ);
4088
4089 if (qemu_log_enabled()) {
4090 qemu_log("guest_base 0x%" PRIxPTR "\n", guest_base);
4091 log_page_dump();
4092
4093 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4094 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4095 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4096 info->start_code);
4097 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4098 info->start_data);
4099 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4100 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4101 info->start_stack);
4102 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4103 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4104 }
4105
4106 target_set_brk(info->brk);
4107 syscall_init();
4108 signal_init();
4109
4110 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4111 generating the prologue until now so that the prologue can take
4112 the real value of GUEST_BASE into account. */
4113 tcg_prologue_init(&tcg_ctx);
4114
4115 #if defined(TARGET_I386)
4116 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4117 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4118 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4119 env->cr[4] |= CR4_OSFXSR_MASK;
4120 env->hflags |= HF_OSFXSR_MASK;
4121 }
4122 #ifndef TARGET_ABI32
4123 /* enable 64 bit mode if possible */
4124 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4125 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4126 exit(1);
4127 }
4128 env->cr[4] |= CR4_PAE_MASK;
4129 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4130 env->hflags |= HF_LMA_MASK;
4131 #endif
4132
4133 /* flags setup : we activate the IRQs by default as in user mode */
4134 env->eflags |= IF_MASK;
4135
4136 /* linux register setup */
4137 #ifndef TARGET_ABI32
4138 env->regs[R_EAX] = regs->rax;
4139 env->regs[R_EBX] = regs->rbx;
4140 env->regs[R_ECX] = regs->rcx;
4141 env->regs[R_EDX] = regs->rdx;
4142 env->regs[R_ESI] = regs->rsi;
4143 env->regs[R_EDI] = regs->rdi;
4144 env->regs[R_EBP] = regs->rbp;
4145 env->regs[R_ESP] = regs->rsp;
4146 env->eip = regs->rip;
4147 #else
4148 env->regs[R_EAX] = regs->eax;
4149 env->regs[R_EBX] = regs->ebx;
4150 env->regs[R_ECX] = regs->ecx;
4151 env->regs[R_EDX] = regs->edx;
4152 env->regs[R_ESI] = regs->esi;
4153 env->regs[R_EDI] = regs->edi;
4154 env->regs[R_EBP] = regs->ebp;
4155 env->regs[R_ESP] = regs->esp;
4156 env->eip = regs->eip;
4157 #endif
4158
4159 /* linux interrupt setup */
4160 #ifndef TARGET_ABI32
4161 env->idt.limit = 511;
4162 #else
4163 env->idt.limit = 255;
4164 #endif
4165 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4166 PROT_READ|PROT_WRITE,
4167 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4168 idt_table = g2h(env->idt.base);
4169 set_idt(0, 0);
4170 set_idt(1, 0);
4171 set_idt(2, 0);
4172 set_idt(3, 3);
4173 set_idt(4, 3);
4174 set_idt(5, 0);
4175 set_idt(6, 0);
4176 set_idt(7, 0);
4177 set_idt(8, 0);
4178 set_idt(9, 0);
4179 set_idt(10, 0);
4180 set_idt(11, 0);
4181 set_idt(12, 0);
4182 set_idt(13, 0);
4183 set_idt(14, 0);
4184 set_idt(15, 0);
4185 set_idt(16, 0);
4186 set_idt(17, 0);
4187 set_idt(18, 0);
4188 set_idt(19, 0);
4189 set_idt(0x80, 3);
4190
4191 /* linux segment setup */
4192 {
4193 uint64_t *gdt_table;
4194 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4195 PROT_READ|PROT_WRITE,
4196 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4197 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4198 gdt_table = g2h(env->gdt.base);
4199 #ifdef TARGET_ABI32
4200 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4201 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4202 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4203 #else
4204 /* 64 bit code segment */
4205 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4206 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4207 DESC_L_MASK |
4208 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4209 #endif
4210 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4211 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4212 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4213 }
4214 cpu_x86_load_seg(env, R_CS, __USER_CS);
4215 cpu_x86_load_seg(env, R_SS, __USER_DS);
4216 #ifdef TARGET_ABI32
4217 cpu_x86_load_seg(env, R_DS, __USER_DS);
4218 cpu_x86_load_seg(env, R_ES, __USER_DS);
4219 cpu_x86_load_seg(env, R_FS, __USER_DS);
4220 cpu_x86_load_seg(env, R_GS, __USER_DS);
4221 /* This hack makes Wine work... */
4222 env->segs[R_FS].selector = 0;
4223 #else
4224 cpu_x86_load_seg(env, R_DS, 0);
4225 cpu_x86_load_seg(env, R_ES, 0);
4226 cpu_x86_load_seg(env, R_FS, 0);
4227 cpu_x86_load_seg(env, R_GS, 0);
4228 #endif
4229 #elif defined(TARGET_AARCH64)
4230 {
4231 int i;
4232
4233 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4234 fprintf(stderr,
4235 "The selected ARM CPU does not support 64 bit mode\n");
4236 exit(1);
4237 }
4238
4239 for (i = 0; i < 31; i++) {
4240 env->xregs[i] = regs->regs[i];
4241 }
4242 env->pc = regs->pc;
4243 env->xregs[31] = regs->sp;
4244 }
4245 #elif defined(TARGET_ARM)
4246 {
4247 int i;
4248 cpsr_write(env, regs->uregs[16], 0xffffffff);
4249 for(i = 0; i < 16; i++) {
4250 env->regs[i] = regs->uregs[i];
4251 }
4252 #ifdef TARGET_WORDS_BIGENDIAN
4253 /* Enable BE8. */
4254 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4255 && (info->elf_flags & EF_ARM_BE8)) {
4256 env->bswap_code = 1;
4257 }
4258 #endif
4259 }
4260 #elif defined(TARGET_UNICORE32)
4261 {
4262 int i;
4263 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4264 for (i = 0; i < 32; i++) {
4265 env->regs[i] = regs->uregs[i];
4266 }
4267 }
4268 #elif defined(TARGET_SPARC)
4269 {
4270 int i;
4271 env->pc = regs->pc;
4272 env->npc = regs->npc;
4273 env->y = regs->y;
4274 for(i = 0; i < 8; i++)
4275 env->gregs[i] = regs->u_regs[i];
4276 for(i = 0; i < 8; i++)
4277 env->regwptr[i] = regs->u_regs[i + 8];
4278 }
4279 #elif defined(TARGET_PPC)
4280 {
4281 int i;
4282
4283 #if defined(TARGET_PPC64)
4284 #if defined(TARGET_ABI32)
4285 env->msr &= ~((target_ulong)1 << MSR_SF);
4286 #else
4287 env->msr |= (target_ulong)1 << MSR_SF;
4288 #endif
4289 #endif
4290 env->nip = regs->nip;
4291 for(i = 0; i < 32; i++) {
4292 env->gpr[i] = regs->gpr[i];
4293 }
4294 }
4295 #elif defined(TARGET_M68K)
4296 {
4297 env->pc = regs->pc;
4298 env->dregs[0] = regs->d0;
4299 env->dregs[1] = regs->d1;
4300 env->dregs[2] = regs->d2;
4301 env->dregs[3] = regs->d3;
4302 env->dregs[4] = regs->d4;
4303 env->dregs[5] = regs->d5;
4304 env->dregs[6] = regs->d6;
4305 env->dregs[7] = regs->d7;
4306 env->aregs[0] = regs->a0;
4307 env->aregs[1] = regs->a1;
4308 env->aregs[2] = regs->a2;
4309 env->aregs[3] = regs->a3;
4310 env->aregs[4] = regs->a4;
4311 env->aregs[5] = regs->a5;
4312 env->aregs[6] = regs->a6;
4313 env->aregs[7] = regs->usp;
4314 env->sr = regs->sr;
4315 ts->sim_syscalls = 1;
4316 }
4317 #elif defined(TARGET_MICROBLAZE)
4318 {
4319 env->regs[0] = regs->r0;
4320 env->regs[1] = regs->r1;
4321 env->regs[2] = regs->r2;
4322 env->regs[3] = regs->r3;
4323 env->regs[4] = regs->r4;
4324 env->regs[5] = regs->r5;
4325 env->regs[6] = regs->r6;
4326 env->regs[7] = regs->r7;
4327 env->regs[8] = regs->r8;
4328 env->regs[9] = regs->r9;
4329 env->regs[10] = regs->r10;
4330 env->regs[11] = regs->r11;
4331 env->regs[12] = regs->r12;
4332 env->regs[13] = regs->r13;
4333 env->regs[14] = regs->r14;
4334 env->regs[15] = regs->r15;
4335 env->regs[16] = regs->r16;
4336 env->regs[17] = regs->r17;
4337 env->regs[18] = regs->r18;
4338 env->regs[19] = regs->r19;
4339 env->regs[20] = regs->r20;
4340 env->regs[21] = regs->r21;
4341 env->regs[22] = regs->r22;
4342 env->regs[23] = regs->r23;
4343 env->regs[24] = regs->r24;
4344 env->regs[25] = regs->r25;
4345 env->regs[26] = regs->r26;
4346 env->regs[27] = regs->r27;
4347 env->regs[28] = regs->r28;
4348 env->regs[29] = regs->r29;
4349 env->regs[30] = regs->r30;
4350 env->regs[31] = regs->r31;
4351 env->sregs[SR_PC] = regs->pc;
4352 }
4353 #elif defined(TARGET_MIPS)
4354 {
4355 int i;
4356
4357 for(i = 0; i < 32; i++) {
4358 env->active_tc.gpr[i] = regs->regs[i];
4359 }
4360 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4361 if (regs->cp0_epc & 1) {
4362 env->hflags |= MIPS_HFLAG_M16;
4363 }
4364 }
4365 #elif defined(TARGET_OPENRISC)
4366 {
4367 int i;
4368
4369 for (i = 0; i < 32; i++) {
4370 env->gpr[i] = regs->gpr[i];
4371 }
4372
4373 env->sr = regs->sr;
4374 env->pc = regs->pc;
4375 }
4376 #elif defined(TARGET_SH4)
4377 {
4378 int i;
4379
4380 for(i = 0; i < 16; i++) {
4381 env->gregs[i] = regs->regs[i];
4382 }
4383 env->pc = regs->pc;
4384 }
4385 #elif defined(TARGET_ALPHA)
4386 {
4387 int i;
4388
4389 for(i = 0; i < 28; i++) {
4390 env->ir[i] = ((abi_ulong *)regs)[i];
4391 }
4392 env->ir[IR_SP] = regs->usp;
4393 env->pc = regs->pc;
4394 }
4395 #elif defined(TARGET_CRIS)
4396 {
4397 env->regs[0] = regs->r0;
4398 env->regs[1] = regs->r1;
4399 env->regs[2] = regs->r2;
4400 env->regs[3] = regs->r3;
4401 env->regs[4] = regs->r4;
4402 env->regs[5] = regs->r5;
4403 env->regs[6] = regs->r6;
4404 env->regs[7] = regs->r7;
4405 env->regs[8] = regs->r8;
4406 env->regs[9] = regs->r9;
4407 env->regs[10] = regs->r10;
4408 env->regs[11] = regs->r11;
4409 env->regs[12] = regs->r12;
4410 env->regs[13] = regs->r13;
4411 env->regs[14] = info->start_stack;
4412 env->regs[15] = regs->acr;
4413 env->pc = regs->erp;
4414 }
4415 #elif defined(TARGET_S390X)
4416 {
4417 int i;
4418 for (i = 0; i < 16; i++) {
4419 env->regs[i] = regs->gprs[i];
4420 }
4421 env->psw.mask = regs->psw.mask;
4422 env->psw.addr = regs->psw.addr;
4423 }
4424 #else
4425 #error unsupported target CPU
4426 #endif
4427
4428 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4429 ts->stack_base = info->start_stack;
4430 ts->heap_base = info->brk;
4431 /* This will be filled in on the first SYS_HEAPINFO call. */
4432 ts->heap_limit = 0;
4433 #endif
4434
4435 if (gdbstub_port) {
4436 if (gdbserver_start(gdbstub_port) < 0) {
4437 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4438 gdbstub_port);
4439 exit(1);
4440 }
4441 gdb_handlesig(cpu, 0);
4442 }
4443 cpu_loop(env);
4444 /* never exits */
4445 return 0;
4446 }
AR7 emulation for QEMU