include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include <signal.h>
  24 #include <setjmp.h>
  25 #include "hw/qdev-core.h"
  26 #include "disas/bfd.h"
  27 #include "exec/hwaddr.h"
  28 #include "exec/memattrs.h"
  29 #include "qemu/queue.h"
  30 #include "qemu/thread.h"
  31 #include "qemu/tls.h"
  32 #include "qemu/typedefs.h"
  33
  34 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  35                                      void *opaque);
  36
  37 /**
  38  * vaddr:
  39  * Type wide enough to contain any #target_ulong virtual address.
  40  */
  41 typedef uint64_t vaddr;
  42 #define VADDR_PRId PRId64
  43 #define VADDR_PRIu PRIu64
  44 #define VADDR_PRIo PRIo64
  45 #define VADDR_PRIx PRIx64
  46 #define VADDR_PRIX PRIX64
  47 #define VADDR_MAX UINT64_MAX
  48
  49 /**
  50  * SECTION:cpu
  51  * @section_id: QEMU-cpu
  52  * @title: CPU Class
  53  * @short_description: Base class for all CPUs
  54  */
  55
  56 #define TYPE_CPU "cpu"
  57
  58 /* Since this macro is used a lot in hot code paths and in conjunction with
  59  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
  60  * an unchecked cast.
  61  */
  62 #define CPU(obj) ((CPUState *)(obj))
  63
  64 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  65 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  66
  67 typedef struct CPUState CPUState;
  68
  69 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  70                                     bool is_write, bool is_exec, int opaque,
  71                                     unsigned size);
  72
  73 struct TranslationBlock;
  74
  75 /**
  76  * CPUClass:
  77  * @class_by_name: Callback to map -cpu command line model name to an
  78  * instantiatable CPU type.
  79  * @parse_features: Callback to parse command line arguments.
  80  * @reset: Callback to reset the #CPUState to its initial state.
  81  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  82  * @has_work: Callback for checking if there is work to do.
  83  * @do_interrupt: Callback for interrupt handling.
  84  * @do_unassigned_access: Callback for unassigned access handling.
  85  * @do_unaligned_access: Callback for unaligned access handling, if
  86  * the target defines #ALIGNED_ONLY.
  87  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  88  * runtime configurable endianness is currently big-endian. Non-configurable
  89  * CPUs can use the default implementation of this method. This method should
  90  * not be used by any callers other than the pre-1.0 virtio devices.
  91  * @memory_rw_debug: Callback for GDB memory access.
  92  * @dump_state: Callback for dumping state.
  93  * @dump_statistics: Callback for dumping statistics.
  94  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  95  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  96  * @get_memory_mapping: Callback for obtaining the memory mappings.
  97  * @set_pc: Callback for setting the Program Counter register.
  98  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  99  * #TranslationBlock.
 100  * @handle_mmu_fault: Callback for handling an MMU fault.
 101  * @get_phys_page_debug: Callback for obtaining a physical address.
 102  * @gdb_read_register: Callback for letting GDB read a register.
 103  * @gdb_write_register: Callback for letting GDB write a register.
 104  * @debug_excp_handler: Callback for handling debug exceptions.
 105  * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
 106  * 64-bit VM coredump.
 107  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 108  * note to a 32-bit VM coredump.
 109  * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
 110  * 32-bit VM coredump.
 111  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 112  * note to a 32-bit VM coredump.
 113  * @vmsd: State description for migration.
 114  * @gdb_num_core_regs: Number of core registers accessible to GDB.
 115  * @gdb_core_xml_file: File name for core registers GDB XML description.
 116  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
 117  *           before the insn which triggers a watchpoint rather than after it.
 118  * @cpu_exec_enter: Callback for cpu_exec preparation.
 119  * @cpu_exec_exit: Callback for cpu_exec cleanup.
 120  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
 121  * @disas_set_info: Setup architecture specific components of disassembly info
 122  *
 123  * Represents a CPU family or model.
 124  */
 125 typedef struct CPUClass {
 126     /*< private >*/
 127     DeviceClass parent_class;
 128     /*< public >*/
 129
 130     ObjectClass *(*class_by_name)(const char *cpu_model);
 131     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 132
 133     void (*reset)(CPUState *cpu);
 134     int reset_dump_flags;
 135     bool (*has_work)(CPUState *cpu);
 136     void (*do_interrupt)(CPUState *cpu);
 137     CPUUnassignedAccess do_unassigned_access;
 138     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
 139                                 int is_write, int is_user, uintptr_t retaddr);
 140     bool (*virtio_is_big_endian)(CPUState *cpu);
 141     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 142                            uint8_t *buf, int len, bool is_write);
 143     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 144                        int flags);
 145     void (*dump_statistics)(CPUState *cpu, FILE *f,
 146                             fprintf_function cpu_fprintf, int flags);
 147     int64_t (*get_arch_id)(CPUState *cpu);
 148     bool (*get_paging_enabled)(const CPUState *cpu);
 149     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 150                                Error **errp);
 151     void (*set_pc)(CPUState *cpu, vaddr value);
 152     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 153     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 154                             int mmu_index);
 155     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 156     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 157     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 158     void (*debug_excp_handler)(CPUState *cpu);
 159
 160     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 161                             int cpuid, void *opaque);
 162     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 163                                 void *opaque);
 164     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 165                             int cpuid, void *opaque);
 166     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 167                                 void *opaque);
 168
 169     const struct VMStateDescription *vmsd;
 170     int gdb_num_core_regs;
 171     const char *gdb_core_xml_file;
 172     bool gdb_stop_before_watchpoint;
 173
 174     void (*cpu_exec_enter)(CPUState *cpu);
 175     void (*cpu_exec_exit)(CPUState *cpu);
 176     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 177
 178     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
 179 } CPUClass;
 180
 181 #ifdef HOST_WORDS_BIGENDIAN
 182 typedef struct icount_decr_u16 {
 183     uint16_t high;
 184     uint16_t low;
 185 } icount_decr_u16;
 186 #else
 187 typedef struct icount_decr_u16 {
 188     uint16_t low;
 189     uint16_t high;
 190 } icount_decr_u16;
 191 #endif
 192
 193 typedef struct CPUBreakpoint {
 194     vaddr pc;
 195     int flags; /* BP_* */
 196     QTAILQ_ENTRY(CPUBreakpoint) entry;
 197 } CPUBreakpoint;
 198
 199 typedef struct CPUWatchpoint {
 200     vaddr vaddr;
 201     vaddr len;
 202     vaddr hitaddr;
 203     MemTxAttrs hitattrs;
 204     int flags; /* BP_* */
 205     QTAILQ_ENTRY(CPUWatchpoint) entry;
 206 } CPUWatchpoint;
 207
 208 struct KVMState;
 209 struct kvm_run;
 210
 211 #define TB_JMP_CACHE_BITS 12
 212 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 213
 214 /**
 215  * CPUState:
 216  * @cpu_index: CPU index (informative).
 217  * @nr_cores: Number of cores within this CPU package.
 218  * @nr_threads: Number of threads within this CPU.
 219  * @numa_node: NUMA node this CPU is belonging to.
 220  * @host_tid: Host thread ID.
 221  * @running: #true if CPU is currently running (usermode).
 222  * @created: Indicates whether the CPU thread has been successfully created.
 223  * @interrupt_request: Indicates a pending interrupt request.
 224  * @halted: Nonzero if the CPU is in suspended state.
 225  * @stop: Indicates a pending stop request.
 226  * @stopped: Indicates the CPU has been artificially stopped.
 227  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 228  *           CPU and return to its top level loop.
 229  * @singlestep_enabled: Flags for single-stepping.
 230  * @icount_extra: Instructions until next timer event.
 231  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 232  * This allows a single read-compare-cbranch-write sequence to test
 233  * for both decrementer underflow and exceptions.
 234  * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
 235  * requires that IO only be performed on the last instruction of a TB
 236  * so that interrupts take effect immediately.
 237  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 238  * @current_tb: Currently executing TB.
 239  * @gdb_regs: Additional GDB registers.
 240  * @gdb_num_regs: Number of total registers accessible to GDB.
 241  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 242  * @next_cpu: Next CPU sharing TB cache.
 243  * @opaque: User data.
 244  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 245  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 246  * @kvm_fd: vCPU file descriptor for KVM.
 247  *
 248  * State of one CPU core or thread.
 249  */
 250 struct CPUState {
 251     /*< private >*/
 252     DeviceState parent_obj;
 253     /*< public >*/
 254
 255     int nr_cores;
 256     int nr_threads;
 257     int numa_node;
 258
 259     struct QemuThread *thread;
 260 #ifdef _WIN32
 261     HANDLE hThread;
 262 #endif
 263     int thread_id;
 264     uint32_t host_tid;
 265     bool running;
 266     struct QemuCond *halt_cond;
 267     struct qemu_work_item *queued_work_first, *queued_work_last;
 268     bool thread_kicked;
 269     bool created;
 270     bool stop;
 271     bool stopped;
 272     /* Endianness, false = little endian, true = big endian. */
 273     bool bigendian;
 274     volatile sig_atomic_t exit_request;
 275     uint32_t interrupt_request;
 276     int singlestep_enabled;
 277     int64_t icount_extra;
 278     sigjmp_buf jmp_env;
 279
 280     AddressSpace *as;
 281     struct AddressSpaceDispatch *memory_dispatch;
 282     MemoryListener *tcg_as_listener;
 283
 284     void *env_ptr; /* CPUArchState */
 285     struct TranslationBlock *current_tb;
 286     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 287     struct GDBRegisterState *gdb_regs;
 288     int gdb_num_regs;
 289     int gdb_num_g_regs;
 290     QTAILQ_ENTRY(CPUState) node;
 291
 292     /* ice debug support */
 293     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
 294
 295     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 296     CPUWatchpoint *watchpoint_hit;
 297
 298     void *opaque;
 299
 300     /* In order to avoid passing too many arguments to the MMIO helpers,
 301      * we store some rarely used information in the CPU context.
 302      */
 303     uintptr_t mem_io_pc;
 304     vaddr mem_io_vaddr;
 305
 306     int kvm_fd;
 307     bool kvm_vcpu_dirty;
 308     struct KVMState *kvm_state;
 309     struct kvm_run *kvm_run;
 310
 311     /* TODO Move common fields from CPUArchState here. */
 312     int cpu_index; /* used by alpha TCG */
 313     uint32_t halted; /* used by alpha, cris, ppc TCG */
 314     union {
 315         uint32_t u32;
 316         icount_decr_u16 u16;
 317     } icount_decr;
 318     uint32_t can_do_io;
 319     int32_t exception_index; /* used by m68k TCG */
 320
 321     /* Note that this is accessed at the start of every TB via a negative
 322        offset from AREG0.  Leave this field at the end so as to make the
 323        (absolute value) offset as small as possible.  This reduces code
 324        size, especially for hosts without large memory offsets.  */
 325     volatile sig_atomic_t tcg_exit_req;
 326 };
 327
 328 QTAILQ_HEAD(CPUTailQ, CPUState);
 329 extern struct CPUTailQ cpus;
 330 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 331 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 332 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 333     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 334 #define CPU_FOREACH_REVERSE(cpu) \
 335     QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node)
 336 #define first_cpu QTAILQ_FIRST(&cpus)
 337
 338 DECLARE_TLS(CPUState *, current_cpu);
 339 #define current_cpu tls_var(current_cpu)
 340
 341 /**
 342  * cpu_paging_enabled:
 343  * @cpu: The CPU whose state is to be inspected.
 344  *
 345  * Returns: %true if paging is enabled, %false otherwise.
 346  */
 347 bool cpu_paging_enabled(const CPUState *cpu);
 348
 349 /**
 350  * cpu_get_memory_mapping:
 351  * @cpu: The CPU whose memory mappings are to be obtained.
 352  * @list: Where to write the memory mappings to.
 353  * @errp: Pointer for reporting an #Error.
 354  */
 355 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 356                             Error **errp);
 357
 358 /**
 359  * cpu_write_elf64_note:
 360  * @f: pointer to a function that writes memory to a file
 361  * @cpu: The CPU whose memory is to be dumped
 362  * @cpuid: ID number of the CPU
 363  * @opaque: pointer to the CPUState struct
 364  */
 365 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 366                          int cpuid, void *opaque);
 367
 368 /**
 369  * cpu_write_elf64_qemunote:
 370  * @f: pointer to a function that writes memory to a file
 371  * @cpu: The CPU whose memory is to be dumped
 372  * @cpuid: ID number of the CPU
 373  * @opaque: pointer to the CPUState struct
 374  */
 375 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 376                              void *opaque);
 377
 378 /**
 379  * cpu_write_elf32_note:
 380  * @f: pointer to a function that writes memory to a file
 381  * @cpu: The CPU whose memory is to be dumped
 382  * @cpuid: ID number of the CPU
 383  * @opaque: pointer to the CPUState struct
 384  */
 385 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 386                          int cpuid, void *opaque);
 387
 388 /**
 389  * cpu_write_elf32_qemunote:
 390  * @f: pointer to a function that writes memory to a file
 391  * @cpu: The CPU whose memory is to be dumped
 392  * @cpuid: ID number of the CPU
 393  * @opaque: pointer to the CPUState struct
 394  */
 395 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 396                              void *opaque);
 397
 398 /**
 399  * CPUDumpFlags:
 400  * @CPU_DUMP_CODE:
 401  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 402  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 403  */
 404 enum CPUDumpFlags {
 405     CPU_DUMP_CODE = 0x00010000,
 406     CPU_DUMP_FPU  = 0x00020000,
 407     CPU_DUMP_CCOP = 0x00040000,
 408 };
 409
 410 /**
 411  * cpu_dump_state:
 412  * @cpu: The CPU whose state is to be dumped.
 413  * @f: File to dump to.
 414  * @cpu_fprintf: Function to dump with.
 415  * @flags: Flags what to dump.
 416  *
 417  * Dumps CPU state.
 418  */
 419 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 420                     int flags);
 421
 422 /**
 423  * cpu_dump_statistics:
 424  * @cpu: The CPU whose state is to be dumped.
 425  * @f: File to dump to.
 426  * @cpu_fprintf: Function to dump with.
 427  * @flags: Flags what to dump.
 428  *
 429  * Dumps CPU statistics.
 430  */
 431 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 432                          int flags);
 433
 434 #ifndef CONFIG_USER_ONLY
 435 /**
 436  * cpu_get_phys_page_debug:
 437  * @cpu: The CPU to obtain the physical page address for.
 438  * @addr: The virtual address.
 439  *
 440  * Obtains the physical page corresponding to a virtual one.
 441  * Use it only for debugging because no protection checks are done.
 442  *
 443  * Returns: Corresponding physical page address or -1 if no page found.
 444  */
 445 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 446 {
 447     CPUClass *cc = CPU_GET_CLASS(cpu);
 448
 449     return cc->get_phys_page_debug(cpu, addr);
 450 }
 451 #endif
 452
 453 /**
 454  * cpu_reset:
 455  * @cpu: The CPU whose state is to be reset.
 456  */
 457 void cpu_reset(CPUState *cpu);
 458
 459 /**
 460  * cpu_class_by_name:
 461  * @typename: The CPU base type.
 462  * @cpu_model: The model string without any parameters.
 463  *
 464  * Looks up a CPU #ObjectClass matching name @cpu_model.
 465  *
 466  * Returns: A #CPUClass or %NULL if not matching class is found.
 467  */
 468 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 469
 470 /**
 471  * cpu_generic_init:
 472  * @typename: The CPU base type.
 473  * @cpu_model: The model string including optional parameters.
 474  *
 475  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 476  *
 477  * Returns: A #CPUState or %NULL if an error occurred.
 478  */
 479 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 480
 481 /**
 482  * cpu_has_work:
 483  * @cpu: The vCPU to check.
 484  *
 485  * Checks whether the CPU has work to do.
 486  *
 487  * Returns: %true if the CPU has work, %false otherwise.
 488  */
 489 static inline bool cpu_has_work(CPUState *cpu)
 490 {
 491     CPUClass *cc = CPU_GET_CLASS(cpu);
 492
 493     g_assert(cc->has_work);
 494     return cc->has_work(cpu);
 495 }
 496
 497 /**
 498  * qemu_cpu_is_self:
 499  * @cpu: The vCPU to check against.
 500  *
 501  * Checks whether the caller is executing on the vCPU thread.
 502  *
 503  * Returns: %true if called from @cpu's thread, %false otherwise.
 504  */
 505 bool qemu_cpu_is_self(CPUState *cpu);
 506
 507 /**
 508  * qemu_cpu_kick:
 509  * @cpu: The vCPU to kick.
 510  *
 511  * Kicks @cpu's thread.
 512  */
 513 void qemu_cpu_kick(CPUState *cpu);
 514
 515 /**
 516  * cpu_is_stopped:
 517  * @cpu: The CPU to check.
 518  *
 519  * Checks whether the CPU is stopped.
 520  *
 521  * Returns: %true if run state is not running or if artificially stopped;
 522  * %false otherwise.
 523  */
 524 bool cpu_is_stopped(CPUState *cpu);
 525
 526 /**
 527  * run_on_cpu:
 528  * @cpu: The vCPU to run on.
 529  * @func: The function to be executed.
 530  * @data: Data to pass to the function.
 531  *
 532  * Schedules the function @func for execution on the vCPU @cpu.
 533  */
 534 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 535
 536 /**
 537  * async_run_on_cpu:
 538  * @cpu: The vCPU to run on.
 539  * @func: The function to be executed.
 540  * @data: Data to pass to the function.
 541  *
 542  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 543  */
 544 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 545
 546 /**
 547  * qemu_get_cpu:
 548  * @index: The CPUState@cpu_index value of the CPU to obtain.
 549  *
 550  * Gets a CPU matching @index.
 551  *
 552  * Returns: The CPU or %NULL if there is no matching CPU.
 553  */
 554 CPUState *qemu_get_cpu(int index);
 555
 556 /**
 557  * cpu_exists:
 558  * @id: Guest-exposed CPU ID to lookup.
 559  *
 560  * Search for CPU with specified ID.
 561  *
 562  * Returns: %true - CPU is found, %false - CPU isn't found.
 563  */
 564 bool cpu_exists(int64_t id);
 565
 566 #ifndef CONFIG_USER_ONLY
 567
 568 typedef void (*CPUInterruptHandler)(CPUState *, int);
 569
 570 extern CPUInterruptHandler cpu_interrupt_handler;
 571
 572 /**
 573  * cpu_interrupt:
 574  * @cpu: The CPU to set an interrupt on.
 575  * @mask: The interupts to set.
 576  *
 577  * Invokes the interrupt handler.
 578  */
 579 static inline void cpu_interrupt(CPUState *cpu, int mask)
 580 {
 581     cpu_interrupt_handler(cpu, mask);
 582 }
 583
 584 #else /* USER_ONLY */
 585
 586 void cpu_interrupt(CPUState *cpu, int mask);
 587
 588 #endif /* USER_ONLY */
 589
 590 #ifdef CONFIG_SOFTMMU
 591 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 592                                          bool is_write, bool is_exec,
 593                                          int opaque, unsigned size)
 594 {
 595     CPUClass *cc = CPU_GET_CLASS(cpu);
 596
 597     if (cc->do_unassigned_access) {
 598         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 599     }
 600 }
 601
 602 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 603                                         int is_write, int is_user,
 604                                         uintptr_t retaddr)
 605 {
 606     CPUClass *cc = CPU_GET_CLASS(cpu);
 607
 608     cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
 609 }
 610 #endif
 611
 612 /**
 613  * cpu_set_pc:
 614  * @cpu: The CPU to set the program counter for.
 615  * @addr: Program counter value.
 616  *
 617  * Sets the program counter for a CPU.
 618  */
 619 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
 620 {
 621     CPUClass *cc = CPU_GET_CLASS(cpu);
 622
 623     cc->set_pc(cpu, addr);
 624 }
 625
 626 /**
 627  * cpu_reset_interrupt:
 628  * @cpu: The CPU to clear the interrupt on.
 629  * @mask: The interrupt mask to clear.
 630  *
 631  * Resets interrupts on the vCPU @cpu.
 632  */
 633 void cpu_reset_interrupt(CPUState *cpu, int mask);
 634
 635 /**
 636  * cpu_exit:
 637  * @cpu: The CPU to exit.
 638  *
 639  * Requests the CPU @cpu to exit execution.
 640  */
 641 void cpu_exit(CPUState *cpu);
 642
 643 /**
 644  * cpu_resume:
 645  * @cpu: The CPU to resume.
 646  *
 647  * Resumes CPU, i.e. puts CPU into runnable state.
 648  */
 649 void cpu_resume(CPUState *cpu);
 650
 651 /**
 652  * qemu_init_vcpu:
 653  * @cpu: The vCPU to initialize.
 654  *
 655  * Initializes a vCPU.
 656  */
 657 void qemu_init_vcpu(CPUState *cpu);
 658
 659 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 660 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 661 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 662
 663 /**
 664  * cpu_single_step:
 665  * @cpu: CPU to the flags for.
 666  * @enabled: Flags to enable.
 667  *
 668  * Enables or disables single-stepping for @cpu.
 669  */
 670 void cpu_single_step(CPUState *cpu, int enabled);
 671
 672 /* Breakpoint/watchpoint flags */
 673 #define BP_MEM_READ           0x01
 674 #define BP_MEM_WRITE          0x02
 675 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 676 #define BP_STOP_BEFORE_ACCESS 0x04
 677 /* 0x08 currently unused */
 678 #define BP_GDB                0x10
 679 #define BP_CPU                0x20
 680 #define BP_WATCHPOINT_HIT_READ 0x40
 681 #define BP_WATCHPOINT_HIT_WRITE 0x80
 682 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
 683
 684 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 685                           CPUBreakpoint **breakpoint);
 686 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
 687 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
 688 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
 689
 690 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
 691                           int flags, CPUWatchpoint **watchpoint);
 692 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
 693                           vaddr len, int flags);
 694 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
 695 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
 696
 697 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
 698     GCC_FMT_ATTR(2, 3);
 699 void cpu_exec_exit(CPUState *cpu);
 700
 701 #ifdef CONFIG_SOFTMMU
 702 extern const struct VMStateDescription vmstate_cpu_common;
 703 #else
 704 #define vmstate_cpu_common vmstate_dummy
 705 #endif
 706
 707 #define VMSTATE_CPU() {                                                     \
 708     .name = "parent_obj",                                                   \
 709     .size = sizeof(CPUState),                                               \
 710     .vmsd = &vmstate_cpu_common,                                            \
 711     .flags = VMS_STRUCT,                                                    \
 712     .offset = 0,                                                            \
 713 }
 714
 715 #endif