include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 /* Maximum size a TCG op can expand to.  This is complicated because a
  66    single op may require several host instructions and register reloads.
  67    For now take a wild guess at 192 bytes, which should allow at least
  68    a couple of fixup instructions per argument.  */
  69 #define TCG_MAX_OP_SIZE 192
  70
  71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  72
  73 #include "qemu/log.h"
  74
  75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
  77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  78                           int pc_pos);
  79
  80 /* Get a backtrace for the guest code. */
  81 const char *qemu_sprint_backtrace(char *buffer, size_t length);
  82
  83 void cpu_gen_init(void);
  84 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
  85                  int *gen_code_size_ptr);
  86 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  87 void page_size_init(void);
  88
  89 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  90 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  91 TranslationBlock *tb_gen_code(CPUState *cpu,
  92                               target_ulong pc, target_ulong cs_base, int flags,
  93                               int cflags);
  94 void cpu_exec_init(CPUState *cpu, Error **errp);
  95 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  96
  97 #if !defined(CONFIG_USER_ONLY)
  98 bool qemu_in_vcpu_thread(void);
  99 void cpu_reload_memory_map(CPUState *cpu);
 100 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
 101 /* cputlb.c */
 102 /**
 103  * tlb_flush_page:
 104  * @cpu: CPU whose TLB should be flushed
 105  * @addr: virtual address of page to be flushed
 106  *
 107  * Flush one page from the TLB of the specified CPU, for all
 108  * MMU indexes.
 109  */
 110 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 111 /**
 112  * tlb_flush:
 113  * @cpu: CPU whose TLB should be flushed
 114  * @flush_global: ignored
 115  *
 116  * Flush the entire TLB for the specified CPU.
 117  * The flush_global flag is in theory an indicator of whether the whole
 118  * TLB should be flushed, or only those entries not marked global.
 119  * In practice QEMU does not implement any global/not global flag for
 120  * TLB entries, and the argument is ignored.
 121  */
 122 void tlb_flush(CPUState *cpu, int flush_global);
 123 /**
 124  * tlb_flush_page_by_mmuidx:
 125  * @cpu: CPU whose TLB should be flushed
 126  * @addr: virtual address of page to be flushed
 127  * @...: list of MMU indexes to flush, terminated by a negative value
 128  *
 129  * Flush one page from the TLB of the specified CPU, for the specified
 130  * MMU indexes.
 131  */
 132 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
 133 /**
 134  * tlb_flush_by_mmuidx:
 135  * @cpu: CPU whose TLB should be flushed
 136  * @...: list of MMU indexes to flush, terminated by a negative value
 137  *
 138  * Flush all entries from the TLB of the specified CPU, for the specified
 139  * MMU indexes.
 140  */
 141 void tlb_flush_by_mmuidx(CPUState *cpu, ...);
 142 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 143                   hwaddr paddr, int prot,
 144                   int mmu_idx, target_ulong size);
 145 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 146                              hwaddr paddr, MemTxAttrs attrs,
 147                              int prot, int mmu_idx, target_ulong size);
 148 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 149 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 150                  uintptr_t retaddr);
 151 #else
 152 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 153 {
 154 }
 155
 156 static inline void tlb_flush(CPUState *cpu, int flush_global)
 157 {
 158 }
 159
 160 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 161                                             target_ulong addr, ...)
 162 {
 163 }
 164
 165 static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...)
 166 {
 167 }
 168 #endif
 169
 170 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 171
 172 #define CODE_GEN_PHYS_HASH_BITS     15
 173 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 174
 175 /* estimated block size for TB allocation */
 176 /* XXX: use a per code average code fragment size and modulate it
 177    according to the host CPU */
 178 #if defined(CONFIG_SOFTMMU)
 179 #define CODE_GEN_AVG_BLOCK_SIZE 128
 180 #else
 181 #define CODE_GEN_AVG_BLOCK_SIZE 64
 182 #endif
 183
 184 #if defined(__arm__) || defined(_ARCH_PPC) \
 185     || defined(__x86_64__) || defined(__i386__) \
 186     || defined(__sparc__) || defined(__aarch64__) \
 187     || defined(__s390x__) || defined(__mips__) \
 188     || defined(CONFIG_TCG_INTERPRETER)
 189 #define USE_DIRECT_JUMP
 190 #endif
 191
 192 struct TranslationBlock {
 193     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 194     target_ulong cs_base; /* CS base for this block */
 195     uint64_t flags; /* flags defining in which context the code was generated */
 196     uint16_t size;      /* size of target code for this block (1 <=
 197                            size <= TARGET_PAGE_SIZE) */
 198     uint16_t icount;
 199     uint32_t cflags;    /* compile flags */
 200 #define CF_COUNT_MASK  0x7fff
 201 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 202 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 203 #define CF_USE_ICOUNT  0x20000
 204
 205     void *tc_ptr;    /* pointer to the translated code */
 206     /* next matching tb for physical address. */
 207     struct TranslationBlock *phys_hash_next;
 208     /* original tb when cflags has CF_NOCACHE */
 209     struct TranslationBlock *orig_tb;
 210     /* first and second physical page containing code. The lower bit
 211        of the pointer tells the index in page_next[] */
 212     struct TranslationBlock *page_next[2];
 213     tb_page_addr_t page_addr[2];
 214
 215     /* the following data are used to directly call another TB from
 216        the code of this one. */
 217     uint16_t tb_next_offset[2]; /* offset of original jump target */
 218 #ifdef USE_DIRECT_JUMP
 219     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 220 #else
 221     uintptr_t tb_next[2]; /* address of jump generated code */
 222 #endif
 223     /* list of TBs jumping to this one. This is a circular list using
 224        the two least significant bits of the pointers to tell what is
 225        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 226        jmp_first */
 227     struct TranslationBlock *jmp_next[2];
 228     struct TranslationBlock *jmp_first;
 229 };
 230
 231 #include "exec/spinlock.h"
 232
 233 typedef struct TBContext TBContext;
 234
 235 struct TBContext {
 236
 237     TranslationBlock *tbs;
 238     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 239     int nb_tbs;
 240     /* any access to the tbs or the page table must use this lock */
 241     spinlock_t tb_lock;
 242
 243     /* statistics */
 244     int tb_flush_count;
 245     int tb_phys_invalidate_count;
 246
 247     int tb_invalidated_flag;
 248 };
 249
 250 void tb_free(TranslationBlock *tb);
 251 void tb_flush(CPUState *cpu);
 252 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 253
 254 #if defined(USE_DIRECT_JUMP)
 255
 256 #if defined(CONFIG_TCG_INTERPRETER)
 257 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 258 {
 259     /* patch the branch destination */
 260     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 261     /* no need to flush icache explicitly */
 262 }
 263 #elif defined(_ARCH_PPC)
 264 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 265 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 266 #elif defined(__i386__) || defined(__x86_64__)
 267 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 268 {
 269     /* patch the branch destination */
 270     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 271     /* no need to flush icache explicitly */
 272 }
 273 #elif defined(__s390x__)
 274 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 275 {
 276     /* patch the branch destination */
 277     intptr_t disp = addr - (jmp_addr - 2);
 278     stl_be_p((void*)jmp_addr, disp / 2);
 279     /* no need to flush icache explicitly */
 280 }
 281 #elif defined(__aarch64__)
 282 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 283 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 284 #elif defined(__arm__)
 285 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 286 {
 287 #if !QEMU_GNUC_PREREQ(4, 1)
 288     register unsigned long _beg __asm ("a1");
 289     register unsigned long _end __asm ("a2");
 290     register unsigned long _flg __asm ("a3");
 291 #endif
 292
 293     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 294     *(uint32_t *)jmp_addr =
 295         (*(uint32_t *)jmp_addr & ~0xffffff)
 296         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 297
 298 #if QEMU_GNUC_PREREQ(4, 1)
 299     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 300 #else
 301     /* flush icache */
 302     _beg = jmp_addr;
 303     _end = jmp_addr + 4;
 304     _flg = 0;
 305     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 306 #endif
 307 }
 308 #elif defined(__sparc__) || defined(__mips__)
 309 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 310 #else
 311 #error tb_set_jmp_target1 is missing
 312 #endif
 313
 314 static inline void tb_set_jmp_target(TranslationBlock *tb,
 315                                      int n, uintptr_t addr)
 316 {
 317     uint16_t offset = tb->tb_jmp_offset[n];
 318     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 319 }
 320
 321 #else
 322
 323 /* set the jump target */
 324 static inline void tb_set_jmp_target(TranslationBlock *tb,
 325                                      int n, uintptr_t addr)
 326 {
 327     tb->tb_next[n] = addr;
 328 }
 329
 330 #endif
 331
 332 static inline void tb_add_jump(TranslationBlock *tb, int n,
 333                                TranslationBlock *tb_next)
 334 {
 335     /* NOTE: this test is only needed for thread safety */
 336     if (!tb->jmp_next[n]) {
 337         /* patch the native jump address */
 338         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 339
 340         /* add in TB jmp circular list */
 341         tb->jmp_next[n] = tb_next->jmp_first;
 342         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 343     }
 344 }
 345
 346 /* GETRA is the true target of the return instruction that we'll execute,
 347    defined here for simplicity of defining the follow-up macros.  */
 348 #if defined(CONFIG_TCG_INTERPRETER)
 349 extern uintptr_t tci_tb_ptr;
 350 # define GETRA() tci_tb_ptr
 351 #else
 352 # define GETRA() \
 353     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 354 #endif
 355
 356 /* The true return address will often point to a host insn that is part of
 357    the next translated guest insn.  Adjust the address backward to point to
 358    the middle of the call insn.  Subtracting one would do the job except for
 359    several compressed mode architectures (arm, mips) which set the low bit
 360    to indicate the compressed mode; subtracting two works around that.  It
 361    is also the case that there are no host isas that contain a call insn
 362    smaller than 4 bytes, so we don't worry about special-casing this.  */
 363 #define GETPC_ADJ   2
 364
 365 #define GETPC()  (GETRA() - GETPC_ADJ)
 366
 367 #if !defined(CONFIG_USER_ONLY)
 368
 369 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
 370
 371 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 372                                      hwaddr index);
 373
 374 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 375               uintptr_t retaddr);
 376
 377 #endif
 378
 379 #if defined(CONFIG_USER_ONLY)
 380 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 381 {
 382     return addr;
 383 }
 384 #else
 385 /* cputlb.c */
 386 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 387 #endif
 388
 389 /* vl.c */
 390 extern int singlestep;
 391
 392 /* cpu-exec.c */
 393 extern volatile sig_atomic_t exit_request;
 394
 395 #if !defined(CONFIG_USER_ONLY)
 396 void migration_bitmap_extend(ram_addr_t old, ram_addr_t new);
 397 #endif
 398 #endif