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Revert "kernel-doc: Handle function typedefs that return pointers"
[qemu/ar7.git] / hw / arm / npcm7xx.c
blob47e2b6fc400de2c7355203728d8a02bccac22505
1 /*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18
19 #include "exec/address-spaces.h"
20 #include "hw/arm/boot.h"
21 #include "hw/arm/npcm7xx.h"
22 #include "hw/char/serial.h"
23 #include "hw/loader.h"
24 #include "hw/misc/unimp.h"
25 #include "hw/qdev-properties.h"
26 #include "qapi/error.h"
27 #include "qemu/units.h"
28 #include "sysemu/sysemu.h"
29
30 /*
31 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
32 * that aren't handled by any device.
33 */
34 #define NPCM7XX_MMIO_BA (0x80000000)
35 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
36
37 /* OTP key storage and fuse strap array */
38 #define NPCM7XX_OTP1_BA (0xf0189000)
39 #define NPCM7XX_OTP2_BA (0xf018a000)
40
41 /* Core system modules. */
42 #define NPCM7XX_L2C_BA (0xf03fc000)
43 #define NPCM7XX_CPUP_BA (0xf03fe000)
44 #define NPCM7XX_GCR_BA (0xf0800000)
45 #define NPCM7XX_CLK_BA (0xf0801000)
46 #define NPCM7XX_MC_BA (0xf0824000)
47 #define NPCM7XX_RNG_BA (0xf000b000)
48
49 /* USB Host modules */
50 #define NPCM7XX_EHCI_BA (0xf0806000)
51 #define NPCM7XX_OHCI_BA (0xf0807000)
52
53 /* Internal AHB SRAM */
54 #define NPCM7XX_RAM3_BA (0xc0008000)
55 #define NPCM7XX_RAM3_SZ (4 * KiB)
56
57 /* Memory blocks at the end of the address space */
58 #define NPCM7XX_RAM2_BA (0xfffd0000)
59 #define NPCM7XX_RAM2_SZ (128 * KiB)
60 #define NPCM7XX_ROM_BA (0xffff0000)
61 #define NPCM7XX_ROM_SZ (64 * KiB)
62
63 /* Clock configuration values to be fixed up when bypassing bootloader */
64
65 /* Run PLL1 at 1600 MHz */
66 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
67 /* Run the CPU from PLL1 and UART from PLL2 */
68 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
69
70 /*
71 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
72 * interrupts.
73 */
74 enum NPCM7xxInterrupt {
75 NPCM7XX_UART0_IRQ = 2,
76 NPCM7XX_UART1_IRQ,
77 NPCM7XX_UART2_IRQ,
78 NPCM7XX_UART3_IRQ,
79 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
80 NPCM7XX_TIMER1_IRQ,
81 NPCM7XX_TIMER2_IRQ,
82 NPCM7XX_TIMER3_IRQ,
83 NPCM7XX_TIMER4_IRQ,
84 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
85 NPCM7XX_TIMER6_IRQ,
86 NPCM7XX_TIMER7_IRQ,
87 NPCM7XX_TIMER8_IRQ,
88 NPCM7XX_TIMER9_IRQ,
89 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
90 NPCM7XX_TIMER11_IRQ,
91 NPCM7XX_TIMER12_IRQ,
92 NPCM7XX_TIMER13_IRQ,
93 NPCM7XX_TIMER14_IRQ,
94 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
95 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
96 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
97 NPCM7XX_EHCI_IRQ = 61,
98 NPCM7XX_OHCI_IRQ = 62,
99 NPCM7XX_GPIO0_IRQ = 116,
100 NPCM7XX_GPIO1_IRQ,
101 NPCM7XX_GPIO2_IRQ,
102 NPCM7XX_GPIO3_IRQ,
103 NPCM7XX_GPIO4_IRQ,
104 NPCM7XX_GPIO5_IRQ,
105 NPCM7XX_GPIO6_IRQ,
106 NPCM7XX_GPIO7_IRQ,
107 };
108
109 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
110 #define NPCM7XX_NUM_IRQ (160)
111
112 /* Register base address for each Timer Module */
113 static const hwaddr npcm7xx_tim_addr[] = {
114 0xf0008000,
115 0xf0009000,
116 0xf000a000,
117 };
118
119 /* Register base address for each 16550 UART */
120 static const hwaddr npcm7xx_uart_addr[] = {
121 0xf0001000,
122 0xf0002000,
123 0xf0003000,
124 0xf0004000,
125 };
126
127 /* Direct memory-mapped access to SPI0 CS0-1. */
128 static const hwaddr npcm7xx_fiu0_flash_addr[] = {
129 0x80000000, /* CS0 */
130 0x88000000, /* CS1 */
131 };
132
133 /* Direct memory-mapped access to SPI3 CS0-3. */
134 static const hwaddr npcm7xx_fiu3_flash_addr[] = {
135 0xa0000000, /* CS0 */
136 0xa8000000, /* CS1 */
137 0xb0000000, /* CS2 */
138 0xb8000000, /* CS3 */
139 };
140
141 static const struct {
142 hwaddr regs_addr;
143 uint32_t unconnected_pins;
144 uint32_t reset_pu;
145 uint32_t reset_pd;
146 uint32_t reset_osrc;
147 uint32_t reset_odsc;
148 } npcm7xx_gpio[] = {
149 {
150 .regs_addr = 0xf0010000,
151 .reset_pu = 0xff03ffff,
152 .reset_pd = 0x00fc0000,
153 }, {
154 .regs_addr = 0xf0011000,
155 .unconnected_pins = 0x0000001e,
156 .reset_pu = 0xfefffe07,
157 .reset_pd = 0x010001e0,
158 }, {
159 .regs_addr = 0xf0012000,
160 .reset_pu = 0x780fffff,
161 .reset_pd = 0x07f00000,
162 .reset_odsc = 0x00700000,
163 }, {
164 .regs_addr = 0xf0013000,
165 .reset_pu = 0x00fc0000,
166 .reset_pd = 0xff000000,
167 }, {
168 .regs_addr = 0xf0014000,
169 .reset_pu = 0xffffffff,
170 }, {
171 .regs_addr = 0xf0015000,
172 .reset_pu = 0xbf83f801,
173 .reset_pd = 0x007c0000,
174 .reset_osrc = 0x000000f1,
175 .reset_odsc = 0x3f9f80f1,
176 }, {
177 .regs_addr = 0xf0016000,
178 .reset_pu = 0xfc00f801,
179 .reset_pd = 0x000007fe,
180 .reset_odsc = 0x00000800,
181 }, {
182 .regs_addr = 0xf0017000,
183 .unconnected_pins = 0xffffff00,
184 .reset_pu = 0x0000007f,
185 .reset_osrc = 0x0000007f,
186 .reset_odsc = 0x0000007f,
187 },
188 };
189
190 static const struct {
191 const char *name;
192 hwaddr regs_addr;
193 int cs_count;
194 const hwaddr *flash_addr;
195 } npcm7xx_fiu[] = {
196 {
197 .name = "fiu0",
198 .regs_addr = 0xfb000000,
199 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
200 .flash_addr = npcm7xx_fiu0_flash_addr,
201 }, {
202 .name = "fiu3",
203 .regs_addr = 0xc0000000,
204 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
205 .flash_addr = npcm7xx_fiu3_flash_addr,
206 },
207 };
208
209 static void npcm7xx_write_board_setup(ARMCPU *cpu,
210 const struct arm_boot_info *info)
211 {
212 uint32_t board_setup[] = {
213 0xe59f0010, /* ldr r0, clk_base_addr */
214 0xe59f1010, /* ldr r1, pllcon1_value */
215 0xe5801010, /* str r1, [r0, #16] */
216 0xe59f100c, /* ldr r1, clksel_value */
217 0xe5801004, /* str r1, [r0, #4] */
218 0xe12fff1e, /* bx lr */
219 NPCM7XX_CLK_BA,
220 NPCM7XX_PLLCON1_FIXUP_VAL,
221 NPCM7XX_CLKSEL_FIXUP_VAL,
222 };
223 int i;
224
225 for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
226 board_setup[i] = tswap32(board_setup[i]);
227 }
228 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
229 info->board_setup_addr);
230 }
231
232 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
233 const struct arm_boot_info *info)
234 {
235 /*
236 * The default smpboot stub halts the secondary CPU with a 'wfi'
237 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
238 * does not send an IPI to wake it up, so the second CPU fails to boot. So
239 * we need to provide our own smpboot stub that can not use 'wfi', it has
240 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
241 */
242 uint32_t smpboot[] = {
243 0xe59f2018, /* ldr r2, bootreg_addr */
244 0xe3a00000, /* mov r0, #0 */
245 0xe5820000, /* str r0, [r2] */
246 0xe320f002, /* wfe */
247 0xe5921000, /* ldr r1, [r2] */
248 0xe1110001, /* tst r1, r1 */
249 0x0afffffb, /* beq <wfe> */
250 0xe12fff11, /* bx r1 */
251 NPCM7XX_SMP_BOOTREG_ADDR,
252 };
253 int i;
254
255 for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
256 smpboot[i] = tswap32(smpboot[i]);
257 }
258
259 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
260 NPCM7XX_SMP_LOADER_START);
261 }
262
263 static struct arm_boot_info npcm7xx_binfo = {
264 .loader_start = NPCM7XX_LOADER_START,
265 .smp_loader_start = NPCM7XX_SMP_LOADER_START,
266 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
267 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
268 .write_secondary_boot = npcm7xx_write_secondary_boot,
269 .board_id = -1,
270 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR,
271 .write_board_setup = npcm7xx_write_board_setup,
272 };
273
274 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
275 {
276 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
277
278 npcm7xx_binfo.ram_size = machine->ram_size;
279 npcm7xx_binfo.nb_cpus = sc->num_cpus;
280
281 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
282 }
283
284 static void npcm7xx_init_fuses(NPCM7xxState *s)
285 {
286 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
287 uint32_t value;
288
289 /*
290 * The initial mask of disabled modules indicates the chip derivative (e.g.
291 * NPCM750 or NPCM730).
292 */
293 value = tswap32(nc->disabled_modules);
294 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
295 sizeof(value));
296 }
297
298 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
299 {
300 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
301 }
302
303 static void npcm7xx_init(Object *obj)
304 {
305 NPCM7xxState *s = NPCM7XX(obj);
306 int i;
307
308 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
309 object_initialize_child(obj, "cpu[*]", &s->cpu[i],
310 ARM_CPU_TYPE_NAME("cortex-a9"));
311 }
312
313 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
314 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
315 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
316 "power-on-straps");
317 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
318 object_initialize_child(obj, "otp1", &s->key_storage,
319 TYPE_NPCM7XX_KEY_STORAGE);
320 object_initialize_child(obj, "otp2", &s->fuse_array,
321 TYPE_NPCM7XX_FUSE_ARRAY);
322 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
323 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
324
325 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
326 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
327 }
328
329 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
330 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
331 }
332
333 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
334 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
335
336 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
337 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
338 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
339 TYPE_NPCM7XX_FIU);
340 }
341 }
342
343 static void npcm7xx_realize(DeviceState *dev, Error **errp)
344 {
345 NPCM7xxState *s = NPCM7XX(dev);
346 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
347 int i;
348
349 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
350 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
351 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
352 return;
353 }
354
355 /* CPUs */
356 for (i = 0; i < nc->num_cpus; i++) {
357 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
358 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
359 &error_abort);
360 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
361 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
362 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
363 &error_abort);
364
365 /* Disable security extensions. */
366 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
367 &error_abort);
368
369 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
370 return;
371 }
372 }
373
374 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
375 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
376 &error_abort);
377 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
378 &error_abort);
379 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
380 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
381
382 for (i = 0; i < nc->num_cpus; i++) {
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
384 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
386 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
387 }
388
389 /* L2 cache controller */
390 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
391
392 /* System Global Control Registers (GCR). Can fail due to user input. */
393 object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
394 nc->disabled_modules, &error_abort);
395 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
396 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
397 return;
398 }
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
400
401 /* Clock Control Registers (CLK). Cannot fail. */
402 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
403 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
404
405 /* OTP key storage and fuse strap array. Cannot fail. */
406 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
408 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
410 npcm7xx_init_fuses(s);
411
412 /* Fake Memory Controller (MC). Cannot fail. */
413 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
414 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
415
416 /* Timer Modules (TIM). Cannot fail. */
417 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
418 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
419 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
420 int first_irq;
421 int j;
422
423 sysbus_realize(sbd, &error_abort);
424 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
425
426 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
427 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
428 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
429 sysbus_connect_irq(sbd, j, irq);
430 }
431
432 /* IRQ for watchdogs */
433 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
434 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
435 /* GPIO that connects clk module with watchdog */
436 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
437 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
438 qdev_get_gpio_in_named(DEVICE(&s->clk),
439 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
440 }
441
442 /* UART0..3 (16550 compatible) */
443 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
444 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
445 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
446 serial_hd(i), DEVICE_LITTLE_ENDIAN);
447 }
448
449 /* Random Number Generator. Cannot fail. */
450 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
451 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
452
453 /* GPIO modules. Cannot fail. */
454 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
455 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
456 Object *obj = OBJECT(&s->gpio[i]);
457
458 object_property_set_uint(obj, "reset-pullup",
459 npcm7xx_gpio[i].reset_pu, &error_abort);
460 object_property_set_uint(obj, "reset-pulldown",
461 npcm7xx_gpio[i].reset_pd, &error_abort);
462 object_property_set_uint(obj, "reset-osrc",
463 npcm7xx_gpio[i].reset_osrc, &error_abort);
464 object_property_set_uint(obj, "reset-odsc",
465 npcm7xx_gpio[i].reset_odsc, &error_abort);
466 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
467 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
468 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
469 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
470 }
471
472 /* USB Host */
473 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
474 &error_abort);
475 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
476 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
478 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
479
480 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
481 &error_abort);
482 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
483 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
484 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
486 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
487
488 /*
489 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
490 * specified, but this is a programming error.
491 */
492 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
493 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
494 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
495 int j;
496
497 object_property_set_int(OBJECT(sbd), "cs-count",
498 npcm7xx_fiu[i].cs_count, &error_abort);
499 sysbus_realize(sbd, &error_abort);
500
501 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
502 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
503 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
504 }
505 }
506
507 /* RAM2 (SRAM) */
508 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
509 NPCM7XX_RAM2_SZ, &error_abort);
510 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
511
512 /* RAM3 (SRAM) */
513 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
514 NPCM7XX_RAM3_SZ, &error_abort);
515 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
516
517 /* Internal ROM */
518 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
519 &error_abort);
520 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
521
522 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
523 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
524 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
525 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
526 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
527 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
528 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
529 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
530 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB);
531 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB);
532 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB);
533 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB);
534 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB);
535 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB);
536 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB);
537 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB);
538 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB);
539 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB);
540 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB);
541 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB);
542 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB);
543 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB);
544 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB);
545 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB);
546 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB);
547 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB);
548 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB);
549 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB);
550 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB);
551 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB);
552 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB);
553 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
554 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
555 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
556 create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
557 create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
558 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
559 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
560 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
561 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB);
562 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB);
563 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB);
564 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB);
565 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB);
566 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
567 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
568 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
569 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
570 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
571 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
572 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
573 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
574 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
575 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB);
576 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB);
577 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB);
578 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB);
579 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB);
580 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB);
581 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB);
582 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB);
583 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB);
584 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB);
585 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB);
586 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB);
587 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB);
588 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB);
589 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB);
590 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB);
591 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB);
592 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB);
593 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB);
594 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB);
595 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB);
596 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB);
597 }
598
599 static Property npcm7xx_properties[] = {
600 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
601 MemoryRegion *),
602 DEFINE_PROP_END_OF_LIST(),
603 };
604
605 static void npcm7xx_class_init(ObjectClass *oc, void *data)
606 {
607 DeviceClass *dc = DEVICE_CLASS(oc);
608
609 dc->realize = npcm7xx_realize;
610 dc->user_creatable = false;
611 device_class_set_props(dc, npcm7xx_properties);
612 }
613
614 static void npcm730_class_init(ObjectClass *oc, void *data)
615 {
616 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
617
618 /* NPCM730 is optimized for data center use, so no graphics, etc. */
619 nc->disabled_modules = 0x00300395;
620 nc->num_cpus = 2;
621 }
622
623 static void npcm750_class_init(ObjectClass *oc, void *data)
624 {
625 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
626
627 /* NPCM750 has 2 cores and a full set of peripherals */
628 nc->disabled_modules = 0x00000000;
629 nc->num_cpus = 2;
630 }
631
632 static const TypeInfo npcm7xx_soc_types[] = {
633 {
634 .name = TYPE_NPCM7XX,
635 .parent = TYPE_DEVICE,
636 .instance_size = sizeof(NPCM7xxState),
637 .instance_init = npcm7xx_init,
638 .class_size = sizeof(NPCM7xxClass),
639 .class_init = npcm7xx_class_init,
640 .abstract = true,
641 }, {
642 .name = TYPE_NPCM730,
643 .parent = TYPE_NPCM7XX,
644 .class_init = npcm730_class_init,
645 }, {
646 .name = TYPE_NPCM750,
647 .parent = TYPE_NPCM7XX,
648 .class_init = npcm750_class_init,
649 },
650 };
651
652 DEFINE_TYPES(npcm7xx_soc_types);
AR7 emulation for QEMU