hw/intc/riscv_aclint.c

   1 /*
   2  * RISC-V ACLINT (Advanced Core Local Interruptor)
   3  * URL: https://github.com/riscv/riscv-aclint
   4  *
   5  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   6  * Copyright (c) 2017 SiFive, Inc.
   7  * Copyright (c) 2021 Western Digital Corporation or its affiliates.
   8  *
   9  * This provides real-time clock, timer and interprocessor interrupts.
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2 or later, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program.  If not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/log.h"
  28 #include "qemu/module.h"
  29 #include "hw/sysbus.h"
  30 #include "target/riscv/cpu.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/intc/riscv_aclint.h"
  33 #include "qemu/timer.h"
  34 #include "hw/irq.h"
  35 #include "migration/vmstate.h"
  36
  37 typedef struct riscv_aclint_mtimer_callback {
  38     RISCVAclintMTimerState *s;
  39     int num;
  40 } riscv_aclint_mtimer_callback;
  41
  42 static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq)
  43 {
  44     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
  45         timebase_freq, NANOSECONDS_PER_SECOND);
  46 }
  47
  48 static uint64_t cpu_riscv_read_rtc(void *opaque)
  49 {
  50     RISCVAclintMTimerState *mtimer = opaque;
  51     return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta;
  52 }
  53
  54 /*
  55  * Called when timecmp is written to update the QEMU timer or immediately
  56  * trigger timer interrupt if mtimecmp <= current timer value.
  57  */
  58 static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
  59                                               RISCVCPU *cpu,
  60                                               int hartid,
  61                                               uint64_t value)
  62 {
  63     uint32_t timebase_freq = mtimer->timebase_freq;
  64     uint64_t next;
  65     uint64_t diff;
  66
  67     uint64_t rtc = cpu_riscv_read_rtc(mtimer);
  68
  69     /* Compute the relative hartid w.r.t the socket */
  70     hartid = hartid - mtimer->hartid_base;
  71
  72     mtimer->timecmp[hartid] = value;
  73     if (mtimer->timecmp[hartid] <= rtc) {
  74         /*
  75          * If we're setting an MTIMECMP value in the "past",
  76          * immediately raise the timer interrupt
  77          */
  78         qemu_irq_raise(mtimer->timer_irqs[hartid]);
  79         return;
  80     }
  81
  82     /* otherwise, set up the future timer interrupt */
  83     qemu_irq_lower(mtimer->timer_irqs[hartid]);
  84     diff = mtimer->timecmp[hartid] - rtc;
  85     /* back to ns (note args switched in muldiv64) */
  86     uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
  87
  88     /*
  89      * check if ns_diff overflowed and check if the addition would potentially
  90      * overflow
  91      */
  92     if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) ||
  93         ns_diff > INT64_MAX) {
  94         next = INT64_MAX;
  95     } else {
  96         /*
  97          * as it is very unlikely qemu_clock_get_ns will return a value
  98          * greater than INT64_MAX, no additional check is needed for an
  99          * unsigned integer overflow.
 100          */
 101         next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
 102         /*
 103          * if ns_diff is INT64_MAX next may still be outside the range
 104          * of a signed integer.
 105          */
 106         next = MIN(next, INT64_MAX);
 107     }
 108
 109     timer_mod(mtimer->timers[hartid], next);
 110 }
 111
 112 /*
 113  * Callback used when the timer set using timer_mod expires.
 114  * Should raise the timer interrupt line
 115  */
 116 static void riscv_aclint_mtimer_cb(void *opaque)
 117 {
 118     riscv_aclint_mtimer_callback *state = opaque;
 119
 120     qemu_irq_raise(state->s->timer_irqs[state->num]);
 121 }
 122
 123 /* CPU read MTIMER register */
 124 static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
 125     unsigned size)
 126 {
 127     RISCVAclintMTimerState *mtimer = opaque;
 128
 129     if (addr >= mtimer->timecmp_base &&
 130         addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
 131         size_t hartid = mtimer->hartid_base +
 132                         ((addr - mtimer->timecmp_base) >> 3);
 133         CPUState *cpu = cpu_by_arch_id(hartid);
 134         CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
 135         if (!env) {
 136             qemu_log_mask(LOG_GUEST_ERROR,
 137                           "aclint-mtimer: invalid hartid: %zu", hartid);
 138         } else if ((addr & 0x7) == 0) {
 139             /* timecmp_lo for RV32/RV64 or timecmp for RV64 */
 140             uint64_t timecmp = mtimer->timecmp[hartid];
 141             return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;
 142         } else if ((addr & 0x7) == 4) {
 143             /* timecmp_hi */
 144             uint64_t timecmp = mtimer->timecmp[hartid];
 145             return (timecmp >> 32) & 0xFFFFFFFF;
 146         } else {
 147             qemu_log_mask(LOG_UNIMP,
 148                           "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
 149             return 0;
 150         }
 151     } else if (addr == mtimer->time_base) {
 152         /* time_lo for RV32/RV64 or timecmp for RV64 */
 153         uint64_t rtc = cpu_riscv_read_rtc(mtimer);
 154         return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc;
 155     } else if (addr == mtimer->time_base + 4) {
 156         /* time_hi */
 157         return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF;
 158     }
 159
 160     qemu_log_mask(LOG_UNIMP,
 161                   "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
 162     return 0;
 163 }
 164
 165 /* CPU write MTIMER register */
 166 static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
 167     uint64_t value, unsigned size)
 168 {
 169     RISCVAclintMTimerState *mtimer = opaque;
 170     int i;
 171
 172     if (addr >= mtimer->timecmp_base &&
 173         addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
 174         size_t hartid = mtimer->hartid_base +
 175                         ((addr - mtimer->timecmp_base) >> 3);
 176         CPUState *cpu = cpu_by_arch_id(hartid);
 177         CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
 178         if (!env) {
 179             qemu_log_mask(LOG_GUEST_ERROR,
 180                           "aclint-mtimer: invalid hartid: %zu", hartid);
 181         } else if ((addr & 0x7) == 0) {
 182             if (size == 4) {
 183                 /* timecmp_lo for RV32/RV64 */
 184                 uint64_t timecmp_hi = mtimer->timecmp[hartid] >> 32;
 185                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
 186                     timecmp_hi << 32 | (value & 0xFFFFFFFF));
 187             } else {
 188                 /* timecmp for RV64 */
 189                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
 190                                                   value);
 191             }
 192         } else if ((addr & 0x7) == 4) {
 193             if (size == 4) {
 194                 /* timecmp_hi for RV32/RV64 */
 195                 uint64_t timecmp_lo = mtimer->timecmp[hartid];
 196                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
 197                     value << 32 | (timecmp_lo & 0xFFFFFFFF));
 198             } else {
 199                 qemu_log_mask(LOG_GUEST_ERROR,
 200                               "aclint-mtimer: invalid timecmp_hi write: %08x",
 201                               (uint32_t)addr);
 202             }
 203         } else {
 204             qemu_log_mask(LOG_UNIMP,
 205                           "aclint-mtimer: invalid timecmp write: %08x",
 206                           (uint32_t)addr);
 207         }
 208         return;
 209     } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
 210         uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
 211         uint64_t rtc = cpu_riscv_read_rtc(mtimer);
 212
 213         if (addr == mtimer->time_base) {
 214             if (size == 4) {
 215                 /* time_lo for RV32/RV64 */
 216                 mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
 217             } else {
 218                 /* time for RV64 */
 219                 mtimer->time_delta = value - rtc_r;
 220             }
 221         } else {
 222             if (size == 4) {
 223                 /* time_hi for RV32/RV64 */
 224                 mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;
 225             } else {
 226                 qemu_log_mask(LOG_GUEST_ERROR,
 227                               "aclint-mtimer: invalid time_hi write: %08x",
 228                               (uint32_t)addr);
 229                 return;
 230             }
 231         }
 232
 233         /* Check if timer interrupt is triggered for each hart. */
 234         for (i = 0; i < mtimer->num_harts; i++) {
 235             CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);
 236             CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
 237             if (!env) {
 238                 continue;
 239             }
 240             riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
 241                                               mtimer->hartid_base + i,
 242                                               mtimer->timecmp[i]);
 243         }
 244         return;
 245     }
 246
 247     qemu_log_mask(LOG_UNIMP,
 248                   "aclint-mtimer: invalid write: %08x", (uint32_t)addr);
 249 }
 250
 251 static const MemoryRegionOps riscv_aclint_mtimer_ops = {
 252     .read = riscv_aclint_mtimer_read,
 253     .write = riscv_aclint_mtimer_write,
 254     .endianness = DEVICE_LITTLE_ENDIAN,
 255     .valid = {
 256         .min_access_size = 4,
 257         .max_access_size = 8
 258     },
 259     .impl = {
 260         .min_access_size = 4,
 261         .max_access_size = 8,
 262     }
 263 };
 264
 265 static Property riscv_aclint_mtimer_properties[] = {
 266     DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState,
 267         hartid_base, 0),
 268     DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
 269     DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState,
 270         timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP),
 271     DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState,
 272         time_base, RISCV_ACLINT_DEFAULT_MTIME),
 273     DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState,
 274         aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE),
 275     DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState,
 276         timebase_freq, 0),
 277     DEFINE_PROP_END_OF_LIST(),
 278 };
 279
 280 static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
 281 {
 282     RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
 283     int i;
 284
 285     memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops,
 286                           s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size);
 287     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 288
 289     s->timer_irqs = g_new(qemu_irq, s->num_harts);
 290     qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);
 291
 292     s->timers = g_new0(QEMUTimer *, s->num_harts);
 293     s->timecmp = g_new0(uint64_t, s->num_harts);
 294     /* Claim timer interrupt bits */
 295     for (i = 0; i < s->num_harts; i++) {
 296         RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));
 297         if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
 298             error_report("MTIP already claimed");
 299             exit(1);
 300         }
 301     }
 302 }
 303
 304 static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
 305 {
 306     /*
 307      * According to RISC-V ACLINT spec:
 308      *   - On MTIMER device reset, the MTIME register is cleared to zero.
 309      *   - On MTIMER device reset, the MTIMECMP registers are in unknown state.
 310      */
 311     RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj);
 312
 313     /*
 314      * Clear mtime register by writing to 0 it.
 315      * Pending mtime interrupts will also be cleared at the same time.
 316      */
 317     riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
 318 }
 319
 320 static const VMStateDescription vmstate_riscv_mtimer = {
 321     .name = "riscv_mtimer",
 322     .version_id = 1,
 323     .minimum_version_id = 1,
 324     .fields = (const VMStateField[]) {
 325             VMSTATE_VARRAY_UINT32(timecmp, RISCVAclintMTimerState,
 326                                   num_harts, 0,
 327                                   vmstate_info_uint64, uint64_t),
 328             VMSTATE_END_OF_LIST()
 329         }
 330 };
 331
 332 static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
 333 {
 334     DeviceClass *dc = DEVICE_CLASS(klass);
 335     dc->realize = riscv_aclint_mtimer_realize;
 336     device_class_set_props(dc, riscv_aclint_mtimer_properties);
 337     ResettableClass *rc = RESETTABLE_CLASS(klass);
 338     rc->phases.enter = riscv_aclint_mtimer_reset_enter;
 339     dc->vmsd = &vmstate_riscv_mtimer;
 340 }
 341
 342 static const TypeInfo riscv_aclint_mtimer_info = {
 343     .name          = TYPE_RISCV_ACLINT_MTIMER,
 344     .parent        = TYPE_SYS_BUS_DEVICE,
 345     .instance_size = sizeof(RISCVAclintMTimerState),
 346     .class_init    = riscv_aclint_mtimer_class_init,
 347 };
 348
 349 /*
 350  * Create ACLINT MTIMER device.
 351  */
 352 DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
 353     uint32_t hartid_base, uint32_t num_harts,
 354     uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
 355     bool provide_rdtime)
 356 {
 357     int i;
 358     DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);
 359     RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
 360
 361     assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
 362     assert(!(addr & 0x7));
 363     assert(!(timecmp_base & 0x7));
 364     assert(!(time_base & 0x7));
 365
 366     qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
 367     qdev_prop_set_uint32(dev, "num-harts", num_harts);
 368     qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
 369     qdev_prop_set_uint32(dev, "time-base", time_base);
 370     qdev_prop_set_uint32(dev, "aperture-size", size);
 371     qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
 372     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 373     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 374
 375     for (i = 0; i < num_harts; i++) {
 376         CPUState *cpu = cpu_by_arch_id(hartid_base + i);
 377         RISCVCPU *rvcpu = RISCV_CPU(cpu);
 378         CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
 379         riscv_aclint_mtimer_callback *cb =
 380             g_new0(riscv_aclint_mtimer_callback, 1);
 381
 382         if (!env) {
 383             g_free(cb);
 384             continue;
 385         }
 386         if (provide_rdtime) {
 387             riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev);
 388         }
 389
 390         cb->s = s;
 391         cb->num = i;
 392         s->timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 393                                   &riscv_aclint_mtimer_cb, cb);
 394         s->timecmp[i] = 0;
 395
 396         qdev_connect_gpio_out(dev, i,
 397                               qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
 398     }
 399
 400     return dev;
 401 }
 402
 403 /* CPU read [M|S]SWI register */
 404 static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
 405     unsigned size)
 406 {
 407     RISCVAclintSwiState *swi = opaque;
 408
 409     if (addr < (swi->num_harts << 2)) {
 410         size_t hartid = swi->hartid_base + (addr >> 2);
 411         CPUState *cpu = cpu_by_arch_id(hartid);
 412         CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
 413         if (!env) {
 414             qemu_log_mask(LOG_GUEST_ERROR,
 415                           "aclint-swi: invalid hartid: %zu", hartid);
 416         } else if ((addr & 0x3) == 0) {
 417             return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0);
 418         }
 419     }
 420
 421     qemu_log_mask(LOG_UNIMP,
 422                   "aclint-swi: invalid read: %08x", (uint32_t)addr);
 423     return 0;
 424 }
 425
 426 /* CPU write [M|S]SWI register */
 427 static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
 428         unsigned size)
 429 {
 430     RISCVAclintSwiState *swi = opaque;
 431
 432     if (addr < (swi->num_harts << 2)) {
 433         size_t hartid = swi->hartid_base + (addr >> 2);
 434         CPUState *cpu = cpu_by_arch_id(hartid);
 435         CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
 436         if (!env) {
 437             qemu_log_mask(LOG_GUEST_ERROR,
 438                           "aclint-swi: invalid hartid: %zu", hartid);
 439         } else if ((addr & 0x3) == 0) {
 440             if (value & 0x1) {
 441                 qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);
 442             } else {
 443                 if (!swi->sswi) {
 444                     qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);
 445                 }
 446             }
 447             return;
 448         }
 449     }
 450
 451     qemu_log_mask(LOG_UNIMP,
 452                   "aclint-swi: invalid write: %08x", (uint32_t)addr);
 453 }
 454
 455 static const MemoryRegionOps riscv_aclint_swi_ops = {
 456     .read = riscv_aclint_swi_read,
 457     .write = riscv_aclint_swi_write,
 458     .endianness = DEVICE_LITTLE_ENDIAN,
 459     .valid = {
 460         .min_access_size = 4,
 461         .max_access_size = 4
 462     }
 463 };
 464
 465 static Property riscv_aclint_swi_properties[] = {
 466     DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
 467     DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
 468     DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false),
 469     DEFINE_PROP_END_OF_LIST(),
 470 };
 471
 472 static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
 473 {
 474     RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev);
 475     int i;
 476
 477     memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi,
 478                           TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE);
 479     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);
 480
 481     swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
 482     qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);
 483
 484     /* Claim software interrupt bits */
 485     for (i = 0; i < swi->num_harts; i++) {
 486         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
 487         /* We don't claim mip.SSIP because it is writable by software */
 488         if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
 489             error_report("MSIP already claimed");
 490             exit(1);
 491         }
 492     }
 493 }
 494
 495 static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)
 496 {
 497     /*
 498      * According to RISC-V ACLINT spec:
 499      *   - On MSWI device reset, each MSIP register is cleared to zero.
 500      *
 501      * p.s. SSWI device reset does nothing since SETSIP register always reads 0.
 502      */
 503     RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj);
 504     int i;
 505
 506     if (!swi->sswi) {
 507         for (i = 0; i < swi->num_harts; i++) {
 508             /* Clear MSIP registers by lowering software interrupts. */
 509             qemu_irq_lower(swi->soft_irqs[i]);
 510         }
 511     }
 512 }
 513
 514 static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
 515 {
 516     DeviceClass *dc = DEVICE_CLASS(klass);
 517     dc->realize = riscv_aclint_swi_realize;
 518     device_class_set_props(dc, riscv_aclint_swi_properties);
 519     ResettableClass *rc = RESETTABLE_CLASS(klass);
 520     rc->phases.enter = riscv_aclint_swi_reset_enter;
 521 }
 522
 523 static const TypeInfo riscv_aclint_swi_info = {
 524     .name          = TYPE_RISCV_ACLINT_SWI,
 525     .parent        = TYPE_SYS_BUS_DEVICE,
 526     .instance_size = sizeof(RISCVAclintSwiState),
 527     .class_init    = riscv_aclint_swi_class_init,
 528 };
 529
 530 /*
 531  * Create ACLINT [M|S]SWI device.
 532  */
 533 DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
 534     uint32_t num_harts, bool sswi)
 535 {
 536     int i;
 537     DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI);
 538
 539     assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
 540     assert(!(addr & 0x3));
 541
 542     qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
 543     qdev_prop_set_uint32(dev, "num-harts", num_harts);
 544     qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
 545     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 546     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 547
 548     for (i = 0; i < num_harts; i++) {
 549         CPUState *cpu = cpu_by_arch_id(hartid_base + i);
 550         RISCVCPU *rvcpu = RISCV_CPU(cpu);
 551
 552         qdev_connect_gpio_out(dev, i,
 553                               qdev_get_gpio_in(DEVICE(rvcpu),
 554                                   (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT));
 555     }
 556
 557     return dev;
 558 }
 559
 560 static void riscv_aclint_register_types(void)
 561 {
 562     type_register_static(&riscv_aclint_mtimer_info);
 563     type_register_static(&riscv_aclint_swi_info);
 564 }
 565
 566 type_init(riscv_aclint_register_types)