hw/timer/i8254_common.c

   1 /*
   2  * QEMU 8253/8254 - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2012      Jan Kiszka, Siemens AG
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/isa/isa.h"
  28 #include "qemu/timer.h"
  29 #include "hw/timer/i8254.h"
  30 #include "hw/timer/i8254_internal.h"
  31
  32 /* val must be 0 or 1 */
  33 void pit_set_gate(ISADevice *dev, int channel, int val)
  34 {
  35     PITCommonState *pit = PIT_COMMON(dev);
  36     PITChannelState *s = &pit->channels[channel];
  37     PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
  38
  39     c->set_channel_gate(pit, s, val);
  40 }
  41
  42 /* get pit output bit */
  43 int pit_get_out(PITChannelState *s, int64_t current_time)
  44 {
  45     uint64_t d;
  46     int out;
  47
  48     d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
  49                  get_ticks_per_sec());
  50     switch (s->mode) {
  51     default:
  52     case 0:
  53         out = (d >= s->count);
  54         break;
  55     case 1:
  56         out = (d < s->count);
  57         break;
  58     case 2:
  59         if ((d % s->count) == 0 && d != 0) {
  60             out = 1;
  61         } else {
  62             out = 0;
  63         }
  64         break;
  65     case 3:
  66         out = (d % s->count) < ((s->count + 1) >> 1);
  67         break;
  68     case 4:
  69     case 5:
  70         out = (d == s->count);
  71         break;
  72     }
  73     return out;
  74 }
  75
  76 /* return -1 if no transition will occur.  */
  77 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
  78 {
  79     uint64_t d, next_time, base;
  80     int period2;
  81
  82     d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
  83                  get_ticks_per_sec());
  84     switch (s->mode) {
  85     default:
  86     case 0:
  87     case 1:
  88         if (d < s->count) {
  89             next_time = s->count;
  90         } else {
  91             return -1;
  92         }
  93         break;
  94     case 2:
  95         base = (d / s->count) * s->count;
  96         if ((d - base) == 0 && d != 0) {
  97             next_time = base + s->count;
  98         } else {
  99             next_time = base + s->count + 1;
 100         }
 101         break;
 102     case 3:
 103         base = (d / s->count) * s->count;
 104         period2 = ((s->count + 1) >> 1);
 105         if ((d - base) < period2) {
 106             next_time = base + period2;
 107         } else {
 108             next_time = base + s->count;
 109         }
 110         break;
 111     case 4:
 112     case 5:
 113         if (d < s->count) {
 114             next_time = s->count;
 115         } else if (d == s->count) {
 116             next_time = s->count + 1;
 117         } else {
 118             return -1;
 119         }
 120         break;
 121     }
 122     /* convert to timer units */
 123     next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
 124                                               PIT_FREQ);
 125     /* fix potential rounding problems */
 126     /* XXX: better solution: use a clock at PIT_FREQ Hz */
 127     if (next_time <= current_time) {
 128         next_time = current_time + 1;
 129     }
 130     return next_time;
 131 }
 132
 133 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
 134                                  PITChannelInfo *info)
 135 {
 136     info->gate = sc->gate;
 137     info->mode = sc->mode;
 138     info->initial_count = sc->count;
 139     info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 140 }
 141
 142 void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
 143 {
 144     PITCommonState *pit = PIT_COMMON(dev);
 145     PITChannelState *s = &pit->channels[channel];
 146     PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
 147
 148     c->get_channel_info(pit, s, info);
 149 }
 150
 151 void pit_reset_common(PITCommonState *pit)
 152 {
 153     PITChannelState *s;
 154     int i;
 155
 156     for (i = 0; i < 3; i++) {
 157         s = &pit->channels[i];
 158         s->mode = 3;
 159         s->gate = (i != 2);
 160         s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 161         s->count = 0x10000;
 162         if (i == 0 && !s->irq_disabled) {
 163             s->next_transition_time =
 164                 pit_get_next_transition_time(s, s->count_load_time);
 165         }
 166     }
 167 }
 168
 169 static void pit_common_realize(DeviceState *dev, Error **errp)
 170 {
 171     ISADevice *isadev = ISA_DEVICE(dev);
 172     PITCommonState *pit = PIT_COMMON(dev);
 173
 174     isa_register_ioport(isadev, &pit->ioports, pit->iobase);
 175
 176     qdev_set_legacy_instance_id(dev, pit->iobase, 2);
 177 }
 178
 179 static const VMStateDescription vmstate_pit_channel = {
 180     .name = "pit channel",
 181     .version_id = 2,
 182     .minimum_version_id = 2,
 183     .minimum_version_id_old = 2,
 184     .fields = (VMStateField[]) {
 185         VMSTATE_INT32(count, PITChannelState),
 186         VMSTATE_UINT16(latched_count, PITChannelState),
 187         VMSTATE_UINT8(count_latched, PITChannelState),
 188         VMSTATE_UINT8(status_latched, PITChannelState),
 189         VMSTATE_UINT8(status, PITChannelState),
 190         VMSTATE_UINT8(read_state, PITChannelState),
 191         VMSTATE_UINT8(write_state, PITChannelState),
 192         VMSTATE_UINT8(write_latch, PITChannelState),
 193         VMSTATE_UINT8(rw_mode, PITChannelState),
 194         VMSTATE_UINT8(mode, PITChannelState),
 195         VMSTATE_UINT8(bcd, PITChannelState),
 196         VMSTATE_UINT8(gate, PITChannelState),
 197         VMSTATE_INT64(count_load_time, PITChannelState),
 198         VMSTATE_INT64(next_transition_time, PITChannelState),
 199         VMSTATE_END_OF_LIST()
 200     }
 201 };
 202
 203 static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
 204 {
 205     PITCommonState *pit = opaque;
 206     PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
 207     PITChannelState *s;
 208     int i;
 209
 210     if (version_id != 1) {
 211         return -EINVAL;
 212     }
 213
 214     for (i = 0; i < 3; i++) {
 215         s = &pit->channels[i];
 216         s->count = qemu_get_be32(f);
 217         qemu_get_be16s(f, &s->latched_count);
 218         qemu_get_8s(f, &s->count_latched);
 219         qemu_get_8s(f, &s->status_latched);
 220         qemu_get_8s(f, &s->status);
 221         qemu_get_8s(f, &s->read_state);
 222         qemu_get_8s(f, &s->write_state);
 223         qemu_get_8s(f, &s->write_latch);
 224         qemu_get_8s(f, &s->rw_mode);
 225         qemu_get_8s(f, &s->mode);
 226         qemu_get_8s(f, &s->bcd);
 227         qemu_get_8s(f, &s->gate);
 228         s->count_load_time = qemu_get_be64(f);
 229         s->irq_disabled = 0;
 230         if (i == 0) {
 231             s->next_transition_time = qemu_get_be64(f);
 232         }
 233     }
 234     if (c->post_load) {
 235         c->post_load(pit);
 236     }
 237     return 0;
 238 }
 239
 240 static void pit_dispatch_pre_save(void *opaque)
 241 {
 242     PITCommonState *s = opaque;
 243     PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
 244
 245     if (c->pre_save) {
 246         c->pre_save(s);
 247     }
 248 }
 249
 250 static int pit_dispatch_post_load(void *opaque, int version_id)
 251 {
 252     PITCommonState *s = opaque;
 253     PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
 254
 255     if (c->post_load) {
 256         c->post_load(s);
 257     }
 258     return 0;
 259 }
 260
 261 static const VMStateDescription vmstate_pit_common = {
 262     .name = "i8254",
 263     .version_id = 3,
 264     .minimum_version_id = 2,
 265     .minimum_version_id_old = 1,
 266     .load_state_old = pit_load_old,
 267     .pre_save = pit_dispatch_pre_save,
 268     .post_load = pit_dispatch_post_load,
 269     .fields = (VMStateField[]) {
 270         VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
 271         VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
 272                              vmstate_pit_channel, PITChannelState),
 273         VMSTATE_INT64(channels[0].next_transition_time,
 274                       PITCommonState), /* formerly irq_timer */
 275         VMSTATE_END_OF_LIST()
 276     }
 277 };
 278
 279 static void pit_common_class_init(ObjectClass *klass, void *data)
 280 {
 281     DeviceClass *dc = DEVICE_CLASS(klass);
 282
 283     dc->realize = pit_common_realize;
 284     dc->vmsd = &vmstate_pit_common;
 285     dc->no_user = 1;
 286 }
 287
 288 static const TypeInfo pit_common_type = {
 289     .name          = TYPE_PIT_COMMON,
 290     .parent        = TYPE_ISA_DEVICE,
 291     .instance_size = sizeof(PITCommonState),
 292     .class_size    = sizeof(PITCommonClass),
 293     .class_init    = pit_common_class_init,
 294     .abstract      = true,
 295 };
 296
 297 static void register_devices(void)
 298 {
 299     type_register_static(&pit_common_type);
 300 }
 301
 302 type_init(register_devices);