4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #define DPRINTF(fmt, ...) \
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
67 #define BUS_MCEERR_AR 4
70 #define BUS_MCEERR_AO 5
73 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR
),
75 KVM_CAP_INFO(EXT_CPUID
),
76 KVM_CAP_INFO(MP_STATE
),
80 static bool has_msr_star
;
81 static bool has_msr_hsave_pa
;
82 static bool has_msr_tsc_aux
;
83 static bool has_msr_tsc_adjust
;
84 static bool has_msr_tsc_deadline
;
85 static bool has_msr_feature_control
;
86 static bool has_msr_async_pf_en
;
87 static bool has_msr_pv_eoi_en
;
88 static bool has_msr_misc_enable
;
89 static bool has_msr_smbase
;
90 static bool has_msr_bndcfgs
;
91 static bool has_msr_kvm_steal_time
;
92 static int lm_capable_kernel
;
93 static bool has_msr_hv_hypercall
;
94 static bool has_msr_hv_crash
;
95 static bool has_msr_hv_reset
;
96 static bool has_msr_hv_vpindex
;
97 static bool has_msr_hv_runtime
;
98 static bool has_msr_hv_synic
;
99 static bool has_msr_hv_stimer
;
100 static bool has_msr_xss
;
102 static bool has_msr_architectural_pmu
;
103 static uint32_t num_architectural_pmu_counters
;
105 static int has_xsave
;
107 static int has_pit_state2
;
109 static bool has_msr_mcg_ext_ctl
;
111 static struct kvm_cpuid2
*cpuid_cache
;
113 int kvm_has_pit_state2(void)
115 return has_pit_state2
;
118 bool kvm_has_smm(void)
120 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
123 bool kvm_allows_irq0_override(void)
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
128 static int kvm_get_tsc(CPUState
*cs
)
130 X86CPU
*cpu
= X86_CPU(cs
);
131 CPUX86State
*env
= &cpu
->env
;
133 struct kvm_msrs info
;
134 struct kvm_msr_entry entries
[1];
138 if (env
->tsc_valid
) {
142 msr_data
.info
.nmsrs
= 1;
143 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
144 env
->tsc_valid
= !runstate_is_running();
146 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
152 env
->tsc
= msr_data
.entries
[0].data
;
156 static inline void do_kvm_synchronize_tsc(void *arg
)
163 void kvm_synchronize_all_tsc(void)
169 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, cpu
);
174 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
176 struct kvm_cpuid2
*cpuid
;
179 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
180 cpuid
= g_malloc0(size
);
182 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
183 if (r
== 0 && cpuid
->nent
>= max
) {
191 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
199 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
202 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
204 struct kvm_cpuid2
*cpuid
;
207 if (cpuid_cache
!= NULL
) {
210 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
217 static const struct kvm_para_features
{
220 } para_features
[] = {
221 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
222 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
223 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
224 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
227 static int get_para_features(KVMState
*s
)
231 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
232 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
233 features
|= (1 << para_features
[i
].feature
);
241 /* Returns the value for a specific register on the cpuid entry
243 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
263 /* Find matching entry for function/index on kvm_cpuid2 struct
265 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
270 for (i
= 0; i
< cpuid
->nent
; ++i
) {
271 if (cpuid
->entries
[i
].function
== function
&&
272 cpuid
->entries
[i
].index
== index
) {
273 return &cpuid
->entries
[i
];
280 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
281 uint32_t index
, int reg
)
283 struct kvm_cpuid2
*cpuid
;
285 uint32_t cpuid_1_edx
;
288 cpuid
= get_supported_cpuid(s
);
290 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
293 ret
= cpuid_entry_get_reg(entry
, reg
);
296 /* Fixups for the data returned by KVM, below */
298 if (function
== 1 && reg
== R_EDX
) {
299 /* KVM before 2.6.30 misreports the following features */
300 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
301 } else if (function
== 1 && reg
== R_ECX
) {
302 /* We can set the hypervisor flag, even if KVM does not return it on
303 * GET_SUPPORTED_CPUID
305 ret
|= CPUID_EXT_HYPERVISOR
;
306 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
307 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
308 * and the irqchip is in the kernel.
310 if (kvm_irqchip_in_kernel() &&
311 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
312 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
315 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
316 * without the in-kernel irqchip
318 if (!kvm_irqchip_in_kernel()) {
319 ret
&= ~CPUID_EXT_X2APIC
;
321 } else if (function
== 6 && reg
== R_EAX
) {
322 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
323 } else if (function
== 0x80000001 && reg
== R_EDX
) {
324 /* On Intel, kvm returns cpuid according to the Intel spec,
325 * so add missing bits according to the AMD spec:
327 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
328 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
329 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EAX
) {
330 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
331 * be enabled without the in-kernel irqchip
333 if (!kvm_irqchip_in_kernel()) {
334 ret
&= ~(1U << KVM_FEATURE_PV_UNHALT
);
338 /* fallback for older kernels */
339 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
340 ret
= get_para_features(s
);
346 typedef struct HWPoisonPage
{
348 QLIST_ENTRY(HWPoisonPage
) list
;
351 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
352 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
354 static void kvm_unpoison_all(void *param
)
356 HWPoisonPage
*page
, *next_page
;
358 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
359 QLIST_REMOVE(page
, list
);
360 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
365 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
369 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
370 if (page
->ram_addr
== ram_addr
) {
374 page
= g_new(HWPoisonPage
, 1);
375 page
->ram_addr
= ram_addr
;
376 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
379 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
384 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
387 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
392 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
394 CPUState
*cs
= CPU(cpu
);
395 CPUX86State
*env
= &cpu
->env
;
396 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
397 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
398 uint64_t mcg_status
= MCG_STATUS_MCIP
;
401 if (code
== BUS_MCEERR_AR
) {
402 status
|= MCI_STATUS_AR
| 0x134;
403 mcg_status
|= MCG_STATUS_EIPV
;
406 mcg_status
|= MCG_STATUS_RIPV
;
409 flags
= cpu_x86_support_mca_broadcast(env
) ? MCE_INJECT_BROADCAST
: 0;
410 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
411 * guest kernel back into env->mcg_ext_ctl.
413 cpu_synchronize_state(cs
);
414 if (env
->mcg_ext_ctl
& MCG_EXT_CTL_LMCE_EN
) {
415 mcg_status
|= MCG_STATUS_LMCE
;
419 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
420 (MCM_ADDR_PHYS
<< 6) | 0xc, flags
);
423 static void hardware_memory_error(void)
425 fprintf(stderr
, "Hardware memory error!\n");
429 int kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
431 X86CPU
*cpu
= X86_CPU(c
);
432 CPUX86State
*env
= &cpu
->env
;
436 if ((env
->mcg_cap
& MCG_SER_P
) && addr
437 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
438 ram_addr
= qemu_ram_addr_from_host(addr
);
439 if (ram_addr
== RAM_ADDR_INVALID
||
440 !kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
441 fprintf(stderr
, "Hardware memory error for memory used by "
442 "QEMU itself instead of guest system!\n");
443 /* Hope we are lucky for AO MCE */
444 if (code
== BUS_MCEERR_AO
) {
447 hardware_memory_error();
450 kvm_hwpoison_page_add(ram_addr
);
451 kvm_mce_inject(cpu
, paddr
, code
);
453 if (code
== BUS_MCEERR_AO
) {
455 } else if (code
== BUS_MCEERR_AR
) {
456 hardware_memory_error();
464 int kvm_arch_on_sigbus(int code
, void *addr
)
466 X86CPU
*cpu
= X86_CPU(first_cpu
);
468 if ((cpu
->env
.mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
472 /* Hope we are lucky for AO MCE */
473 ram_addr
= qemu_ram_addr_from_host(addr
);
474 if (ram_addr
== RAM_ADDR_INVALID
||
475 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
,
477 fprintf(stderr
, "Hardware memory error for memory used by "
478 "QEMU itself instead of guest system!: %p\n", addr
);
481 kvm_hwpoison_page_add(ram_addr
);
482 kvm_mce_inject(X86_CPU(first_cpu
), paddr
, code
);
484 if (code
== BUS_MCEERR_AO
) {
486 } else if (code
== BUS_MCEERR_AR
) {
487 hardware_memory_error();
495 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
497 CPUX86State
*env
= &cpu
->env
;
499 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
500 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
501 struct kvm_x86_mce mce
;
503 env
->exception_injected
= -1;
506 * There must be at least one bank in use if an MCE is pending.
507 * Find it and use its values for the event injection.
509 for (bank
= 0; bank
< bank_num
; bank
++) {
510 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
514 assert(bank
< bank_num
);
517 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
518 mce
.mcg_status
= env
->mcg_status
;
519 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
520 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
522 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
527 static void cpu_update_state(void *opaque
, int running
, RunState state
)
529 CPUX86State
*env
= opaque
;
532 env
->tsc_valid
= false;
536 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
538 X86CPU
*cpu
= X86_CPU(cs
);
542 #ifndef KVM_CPUID_SIGNATURE_NEXT
543 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
546 static bool hyperv_hypercall_available(X86CPU
*cpu
)
548 return cpu
->hyperv_vapic
||
549 (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
);
552 static bool hyperv_enabled(X86CPU
*cpu
)
554 CPUState
*cs
= CPU(cpu
);
555 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
556 (hyperv_hypercall_available(cpu
) ||
558 cpu
->hyperv_relaxed_timing
||
561 cpu
->hyperv_vpindex
||
562 cpu
->hyperv_runtime
||
567 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
569 X86CPU
*cpu
= X86_CPU(cs
);
570 CPUX86State
*env
= &cpu
->env
;
577 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
578 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
581 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
582 * TSC frequency doesn't match the one we want.
584 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
585 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
587 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
588 error_report("warning: TSC frequency mismatch between "
589 "VM (%" PRId64
" kHz) and host (%d kHz), "
590 "and TSC scaling unavailable",
591 env
->tsc_khz
, cur_freq
);
599 static int hyperv_handle_properties(CPUState
*cs
)
601 X86CPU
*cpu
= X86_CPU(cs
);
602 CPUX86State
*env
= &cpu
->env
;
604 if (cpu
->hyperv_time
&&
605 kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) <= 0) {
606 cpu
->hyperv_time
= false;
609 if (cpu
->hyperv_relaxed_timing
) {
610 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_HYPERCALL_AVAILABLE
;
612 if (cpu
->hyperv_vapic
) {
613 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_HYPERCALL_AVAILABLE
;
614 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
616 if (cpu
->hyperv_time
) {
617 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_HYPERCALL_AVAILABLE
;
618 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE
;
619 env
->features
[FEAT_HYPERV_EAX
] |= 0x200;
621 if (cpu
->hyperv_crash
&& has_msr_hv_crash
) {
622 env
->features
[FEAT_HYPERV_EDX
] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE
;
624 env
->features
[FEAT_HYPERV_EDX
] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
625 if (cpu
->hyperv_reset
&& has_msr_hv_reset
) {
626 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_RESET_AVAILABLE
;
628 if (cpu
->hyperv_vpindex
&& has_msr_hv_vpindex
) {
629 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_VP_INDEX_AVAILABLE
;
631 if (cpu
->hyperv_runtime
&& has_msr_hv_runtime
) {
632 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE
;
634 if (cpu
->hyperv_synic
) {
637 if (!has_msr_hv_synic
||
638 kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_SYNIC
, 0)) {
639 fprintf(stderr
, "Hyper-V SynIC is not supported by kernel\n");
643 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_SYNIC_AVAILABLE
;
644 env
->msr_hv_synic_version
= HV_SYNIC_VERSION_1
;
645 for (sint
= 0; sint
< ARRAY_SIZE(env
->msr_hv_synic_sint
); sint
++) {
646 env
->msr_hv_synic_sint
[sint
] = HV_SYNIC_SINT_MASKED
;
649 if (cpu
->hyperv_stimer
) {
650 if (!has_msr_hv_stimer
) {
651 fprintf(stderr
, "Hyper-V timers aren't supported by kernel\n");
654 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_SYNTIMER_AVAILABLE
;
659 static Error
*invtsc_mig_blocker
;
661 #define KVM_MAX_CPUID_ENTRIES 100
663 int kvm_arch_init_vcpu(CPUState
*cs
)
666 struct kvm_cpuid2 cpuid
;
667 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
668 } QEMU_PACKED cpuid_data
;
669 X86CPU
*cpu
= X86_CPU(cs
);
670 CPUX86State
*env
= &cpu
->env
;
671 uint32_t limit
, i
, j
, cpuid_i
;
673 struct kvm_cpuid_entry2
*c
;
674 uint32_t signature
[3];
675 int kvm_base
= KVM_CPUID_SIGNATURE
;
678 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
682 /* Paravirtualization CPUIDs */
683 if (hyperv_enabled(cpu
)) {
684 c
= &cpuid_data
.entries
[cpuid_i
++];
685 c
->function
= HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
686 if (!cpu
->hyperv_vendor_id
) {
687 memcpy(signature
, "Microsoft Hv", 12);
689 size_t len
= strlen(cpu
->hyperv_vendor_id
);
692 error_report("hv-vendor-id truncated to 12 characters");
695 memset(signature
, 0, 12);
696 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
698 c
->eax
= HYPERV_CPUID_MIN
;
699 c
->ebx
= signature
[0];
700 c
->ecx
= signature
[1];
701 c
->edx
= signature
[2];
703 c
= &cpuid_data
.entries
[cpuid_i
++];
704 c
->function
= HYPERV_CPUID_INTERFACE
;
705 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
706 c
->eax
= signature
[0];
711 c
= &cpuid_data
.entries
[cpuid_i
++];
712 c
->function
= HYPERV_CPUID_VERSION
;
716 c
= &cpuid_data
.entries
[cpuid_i
++];
717 c
->function
= HYPERV_CPUID_FEATURES
;
718 r
= hyperv_handle_properties(cs
);
722 c
->eax
= env
->features
[FEAT_HYPERV_EAX
];
723 c
->ebx
= env
->features
[FEAT_HYPERV_EBX
];
724 c
->edx
= env
->features
[FEAT_HYPERV_EDX
];
726 c
= &cpuid_data
.entries
[cpuid_i
++];
727 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
728 if (cpu
->hyperv_relaxed_timing
) {
729 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
731 if (cpu
->hyperv_vapic
) {
732 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
734 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
736 c
= &cpuid_data
.entries
[cpuid_i
++];
737 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
741 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
742 has_msr_hv_hypercall
= true;
745 if (cpu
->expose_kvm
) {
746 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
747 c
= &cpuid_data
.entries
[cpuid_i
++];
748 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
749 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
750 c
->ebx
= signature
[0];
751 c
->ecx
= signature
[1];
752 c
->edx
= signature
[2];
754 c
= &cpuid_data
.entries
[cpuid_i
++];
755 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
756 c
->eax
= env
->features
[FEAT_KVM
];
758 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
760 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
762 has_msr_kvm_steal_time
= c
->eax
& (1 << KVM_FEATURE_STEAL_TIME
);
765 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
767 for (i
= 0; i
<= limit
; i
++) {
768 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
769 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
772 c
= &cpuid_data
.entries
[cpuid_i
++];
776 /* Keep reading function 2 till all the input is received */
780 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
781 KVM_CPUID_FLAG_STATE_READ_NEXT
;
782 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
783 times
= c
->eax
& 0xff;
785 for (j
= 1; j
< times
; ++j
) {
786 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
787 fprintf(stderr
, "cpuid_data is full, no space for "
788 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
791 c
= &cpuid_data
.entries
[cpuid_i
++];
793 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
794 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
802 if (i
== 0xd && j
== 64) {
806 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
808 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
810 if (i
== 4 && c
->eax
== 0) {
813 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
816 if (i
== 0xd && c
->eax
== 0) {
819 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
820 fprintf(stderr
, "cpuid_data is full, no space for "
821 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
824 c
= &cpuid_data
.entries
[cpuid_i
++];
830 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
838 cpu_x86_cpuid(env
, 0x0a, 0, &ver
, &unused
, &unused
, &unused
);
839 if ((ver
& 0xff) > 0) {
840 has_msr_architectural_pmu
= true;
841 num_architectural_pmu_counters
= (ver
& 0xff00) >> 8;
843 /* Shouldn't be more than 32, since that's the number of bits
844 * available in EBX to tell us _which_ counters are available.
847 if (num_architectural_pmu_counters
> MAX_GP_COUNTERS
) {
848 num_architectural_pmu_counters
= MAX_GP_COUNTERS
;
853 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
855 for (i
= 0x80000000; i
<= limit
; i
++) {
856 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
857 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
860 c
= &cpuid_data
.entries
[cpuid_i
++];
864 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
867 /* Call Centaur's CPUID instructions they are supported. */
868 if (env
->cpuid_xlevel2
> 0) {
869 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
871 for (i
= 0xC0000000; i
<= limit
; i
++) {
872 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
873 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
876 c
= &cpuid_data
.entries
[cpuid_i
++];
880 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
884 cpuid_data
.cpuid
.nent
= cpuid_i
;
886 if (((env
->cpuid_version
>> 8)&0xF) >= 6
887 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
888 (CPUID_MCE
| CPUID_MCA
)
889 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
890 uint64_t mcg_cap
, unsupported_caps
;
894 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
896 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
900 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
901 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
902 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
906 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
907 if (unsupported_caps
) {
908 if (unsupported_caps
& MCG_LMCE_P
) {
909 error_report("kvm: LMCE not supported");
912 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64
,
916 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
917 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
919 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
924 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
926 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
928 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
929 !!(c
->ecx
& CPUID_EXT_SMX
);
932 if (env
->mcg_cap
& MCG_LMCE_P
) {
933 has_msr_mcg_ext_ctl
= has_msr_feature_control
= true;
936 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 0x80000007, 0);
937 if (c
&& (c
->edx
& 1<<8) && invtsc_mig_blocker
== NULL
) {
939 error_setg(&invtsc_mig_blocker
,
940 "State blocked by non-migratable CPU device"
942 migrate_add_blocker(invtsc_mig_blocker
);
944 vmstate_x86_cpu
.unmigratable
= 1;
947 cpuid_data
.cpuid
.padding
= 0;
948 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
953 r
= kvm_arch_set_tsc_khz(cs
);
958 /* vcpu's TSC frequency is either specified by user, or following
959 * the value used by KVM if the former is not present. In the
960 * latter case, we query it from KVM and record in env->tsc_khz,
961 * so that vcpu's TSC frequency can be migrated later via this field.
964 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
965 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
973 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
975 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
977 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
978 has_msr_tsc_aux
= false;
984 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
986 CPUX86State
*env
= &cpu
->env
;
988 env
->exception_injected
= -1;
989 env
->interrupt_injected
= -1;
991 if (kvm_irqchip_in_kernel()) {
992 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
993 KVM_MP_STATE_UNINITIALIZED
;
995 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
999 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
1001 CPUX86State
*env
= &cpu
->env
;
1003 /* APs get directly into wait-for-SIPI state. */
1004 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
1005 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1009 static int kvm_get_supported_msrs(KVMState
*s
)
1011 static int kvm_supported_msrs
;
1015 if (kvm_supported_msrs
== 0) {
1016 struct kvm_msr_list msr_list
, *kvm_msr_list
;
1018 kvm_supported_msrs
= -1;
1020 /* Obtain MSR list from KVM. These are the MSRs that we must
1023 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
1024 if (ret
< 0 && ret
!= -E2BIG
) {
1027 /* Old kernel modules had a bug and could write beyond the provided
1028 memory. Allocate at least a safe amount of 1K. */
1029 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
1031 sizeof(msr_list
.indices
[0])));
1033 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
1034 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
1038 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
1039 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
1040 has_msr_star
= true;
1043 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
1044 has_msr_hsave_pa
= true;
1047 if (kvm_msr_list
->indices
[i
] == MSR_TSC_AUX
) {
1048 has_msr_tsc_aux
= true;
1051 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
1052 has_msr_tsc_adjust
= true;
1055 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
1056 has_msr_tsc_deadline
= true;
1059 if (kvm_msr_list
->indices
[i
] == MSR_IA32_SMBASE
) {
1060 has_msr_smbase
= true;
1063 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
1064 has_msr_misc_enable
= true;
1067 if (kvm_msr_list
->indices
[i
] == MSR_IA32_BNDCFGS
) {
1068 has_msr_bndcfgs
= true;
1071 if (kvm_msr_list
->indices
[i
] == MSR_IA32_XSS
) {
1075 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_CRASH_CTL
) {
1076 has_msr_hv_crash
= true;
1079 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_RESET
) {
1080 has_msr_hv_reset
= true;
1083 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_VP_INDEX
) {
1084 has_msr_hv_vpindex
= true;
1087 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_VP_RUNTIME
) {
1088 has_msr_hv_runtime
= true;
1091 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_SCONTROL
) {
1092 has_msr_hv_synic
= true;
1095 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_STIMER0_CONFIG
) {
1096 has_msr_hv_stimer
= true;
1102 g_free(kvm_msr_list
);
1108 static Notifier smram_machine_done
;
1109 static KVMMemoryListener smram_listener
;
1110 static AddressSpace smram_address_space
;
1111 static MemoryRegion smram_as_root
;
1112 static MemoryRegion smram_as_mem
;
1114 static void register_smram_listener(Notifier
*n
, void *unused
)
1116 MemoryRegion
*smram
=
1117 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
1119 /* Outer container... */
1120 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
1121 memory_region_set_enabled(&smram_as_root
, true);
1123 /* ... with two regions inside: normal system memory with low
1126 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
1127 get_system_memory(), 0, ~0ull);
1128 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
1129 memory_region_set_enabled(&smram_as_mem
, true);
1132 /* ... SMRAM with higher priority */
1133 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
1134 memory_region_set_enabled(smram
, true);
1137 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
1138 kvm_memory_listener_register(kvm_state
, &smram_listener
,
1139 &smram_address_space
, 1);
1142 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
1144 uint64_t identity_base
= 0xfffbc000;
1145 uint64_t shadow_mem
;
1147 struct utsname utsname
;
1149 #ifdef KVM_CAP_XSAVE
1150 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
1154 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
1157 #ifdef KVM_CAP_PIT_STATE2
1158 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
1161 ret
= kvm_get_supported_msrs(s
);
1167 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
1170 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1171 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1172 * Since these must be part of guest physical memory, we need to allocate
1173 * them, both by setting their start addresses in the kernel and by
1174 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1176 * Older KVM versions may not support setting the identity map base. In
1177 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1180 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
1181 /* Allows up to 16M BIOSes. */
1182 identity_base
= 0xfeffc000;
1184 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
1190 /* Set TSS base one page after EPT identity map. */
1191 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
1196 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1197 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
1199 fprintf(stderr
, "e820_add_entry() table is full\n");
1202 qemu_register_reset(kvm_unpoison_all
, NULL
);
1204 shadow_mem
= machine_kvm_shadow_mem(ms
);
1205 if (shadow_mem
!= -1) {
1207 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
1213 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
)) {
1214 smram_machine_done
.notify
= register_smram_listener
;
1215 qemu_add_machine_init_done_notifier(&smram_machine_done
);
1220 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1222 lhs
->selector
= rhs
->selector
;
1223 lhs
->base
= rhs
->base
;
1224 lhs
->limit
= rhs
->limit
;
1236 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1238 unsigned flags
= rhs
->flags
;
1239 lhs
->selector
= rhs
->selector
;
1240 lhs
->base
= rhs
->base
;
1241 lhs
->limit
= rhs
->limit
;
1242 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
1243 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
1244 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
1245 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
1246 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
1247 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
1248 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
1249 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
1250 lhs
->unusable
= !lhs
->present
;
1254 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
1256 lhs
->selector
= rhs
->selector
;
1257 lhs
->base
= rhs
->base
;
1258 lhs
->limit
= rhs
->limit
;
1259 if (rhs
->unusable
) {
1262 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
1263 (rhs
->present
* DESC_P_MASK
) |
1264 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
1265 (rhs
->db
<< DESC_B_SHIFT
) |
1266 (rhs
->s
* DESC_S_MASK
) |
1267 (rhs
->l
<< DESC_L_SHIFT
) |
1268 (rhs
->g
* DESC_G_MASK
) |
1269 (rhs
->avl
* DESC_AVL_MASK
);
1273 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
1276 *kvm_reg
= *qemu_reg
;
1278 *qemu_reg
= *kvm_reg
;
1282 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
1284 CPUX86State
*env
= &cpu
->env
;
1285 struct kvm_regs regs
;
1289 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
1295 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
1296 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
1297 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
1298 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
1299 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
1300 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
1301 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
1302 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
1303 #ifdef TARGET_X86_64
1304 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
1305 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
1306 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
1307 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
1308 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
1309 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
1310 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
1311 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
1314 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
1315 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
1318 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
1324 static int kvm_put_fpu(X86CPU
*cpu
)
1326 CPUX86State
*env
= &cpu
->env
;
1330 memset(&fpu
, 0, sizeof fpu
);
1331 fpu
.fsw
= env
->fpus
& ~(7 << 11);
1332 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
1333 fpu
.fcw
= env
->fpuc
;
1334 fpu
.last_opcode
= env
->fpop
;
1335 fpu
.last_ip
= env
->fpip
;
1336 fpu
.last_dp
= env
->fpdp
;
1337 for (i
= 0; i
< 8; ++i
) {
1338 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
1340 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
1341 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1342 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
1343 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
1345 fpu
.mxcsr
= env
->mxcsr
;
1347 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
1350 #define XSAVE_FCW_FSW 0
1351 #define XSAVE_FTW_FOP 1
1352 #define XSAVE_CWD_RIP 2
1353 #define XSAVE_CWD_RDP 4
1354 #define XSAVE_MXCSR 6
1355 #define XSAVE_ST_SPACE 8
1356 #define XSAVE_XMM_SPACE 40
1357 #define XSAVE_XSTATE_BV 128
1358 #define XSAVE_YMMH_SPACE 144
1359 #define XSAVE_BNDREGS 240
1360 #define XSAVE_BNDCSR 256
1361 #define XSAVE_OPMASK 272
1362 #define XSAVE_ZMM_Hi256 288
1363 #define XSAVE_Hi16_ZMM 416
1364 #define XSAVE_PKRU 672
1366 #define XSAVE_BYTE_OFFSET(word_offset) \
1367 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1369 #define ASSERT_OFFSET(word_offset, field) \
1370 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1371 offsetof(X86XSaveArea, field))
1373 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
1374 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
1375 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
1376 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
1377 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
1378 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
1379 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
1380 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
1381 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
1382 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
1383 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
1384 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
1385 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
1386 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
1387 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
1389 static int kvm_put_xsave(X86CPU
*cpu
)
1391 CPUX86State
*env
= &cpu
->env
;
1392 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1393 uint16_t cwd
, swd
, twd
;
1397 return kvm_put_fpu(cpu
);
1400 memset(xsave
, 0, sizeof(struct kvm_xsave
));
1402 swd
= env
->fpus
& ~(7 << 11);
1403 swd
|= (env
->fpstt
& 7) << 11;
1405 for (i
= 0; i
< 8; ++i
) {
1406 twd
|= (!env
->fptags
[i
]) << i
;
1408 xsave
->legacy
.fcw
= cwd
;
1409 xsave
->legacy
.fsw
= swd
;
1410 xsave
->legacy
.ftw
= twd
;
1411 xsave
->legacy
.fpop
= env
->fpop
;
1412 xsave
->legacy
.fpip
= env
->fpip
;
1413 xsave
->legacy
.fpdp
= env
->fpdp
;
1414 memcpy(&xsave
->legacy
.fpregs
, env
->fpregs
,
1415 sizeof env
->fpregs
);
1416 xsave
->legacy
.mxcsr
= env
->mxcsr
;
1417 xsave
->header
.xstate_bv
= env
->xstate_bv
;
1418 memcpy(&xsave
->bndreg_state
.bnd_regs
, env
->bnd_regs
,
1419 sizeof env
->bnd_regs
);
1420 xsave
->bndcsr_state
.bndcsr
= env
->bndcs_regs
;
1421 memcpy(&xsave
->opmask_state
.opmask_regs
, env
->opmask_regs
,
1422 sizeof env
->opmask_regs
);
1424 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1425 uint8_t *xmm
= xsave
->legacy
.xmm_regs
[i
];
1426 uint8_t *ymmh
= xsave
->avx_state
.ymmh
[i
];
1427 uint8_t *zmmh
= xsave
->zmm_hi256_state
.zmm_hi256
[i
];
1428 stq_p(xmm
, env
->xmm_regs
[i
].ZMM_Q(0));
1429 stq_p(xmm
+8, env
->xmm_regs
[i
].ZMM_Q(1));
1430 stq_p(ymmh
, env
->xmm_regs
[i
].ZMM_Q(2));
1431 stq_p(ymmh
+8, env
->xmm_regs
[i
].ZMM_Q(3));
1432 stq_p(zmmh
, env
->xmm_regs
[i
].ZMM_Q(4));
1433 stq_p(zmmh
+8, env
->xmm_regs
[i
].ZMM_Q(5));
1434 stq_p(zmmh
+16, env
->xmm_regs
[i
].ZMM_Q(6));
1435 stq_p(zmmh
+24, env
->xmm_regs
[i
].ZMM_Q(7));
1438 #ifdef TARGET_X86_64
1439 memcpy(&xsave
->hi16_zmm_state
.hi16_zmm
, &env
->xmm_regs
[16],
1440 16 * sizeof env
->xmm_regs
[16]);
1441 memcpy(&xsave
->pkru_state
, &env
->pkru
, sizeof env
->pkru
);
1443 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
1446 static int kvm_put_xcrs(X86CPU
*cpu
)
1448 CPUX86State
*env
= &cpu
->env
;
1449 struct kvm_xcrs xcrs
= {};
1457 xcrs
.xcrs
[0].xcr
= 0;
1458 xcrs
.xcrs
[0].value
= env
->xcr0
;
1459 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
1462 static int kvm_put_sregs(X86CPU
*cpu
)
1464 CPUX86State
*env
= &cpu
->env
;
1465 struct kvm_sregs sregs
;
1467 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
1468 if (env
->interrupt_injected
>= 0) {
1469 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
1470 (uint64_t)1 << (env
->interrupt_injected
% 64);
1473 if ((env
->eflags
& VM_MASK
)) {
1474 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1475 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1476 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1477 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1478 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1479 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1481 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1482 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1483 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1484 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1485 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1486 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1489 set_seg(&sregs
.tr
, &env
->tr
);
1490 set_seg(&sregs
.ldt
, &env
->ldt
);
1492 sregs
.idt
.limit
= env
->idt
.limit
;
1493 sregs
.idt
.base
= env
->idt
.base
;
1494 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
1495 sregs
.gdt
.limit
= env
->gdt
.limit
;
1496 sregs
.gdt
.base
= env
->gdt
.base
;
1497 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
1499 sregs
.cr0
= env
->cr
[0];
1500 sregs
.cr2
= env
->cr
[2];
1501 sregs
.cr3
= env
->cr
[3];
1502 sregs
.cr4
= env
->cr
[4];
1504 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
1505 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
1507 sregs
.efer
= env
->efer
;
1509 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1512 static void kvm_msr_buf_reset(X86CPU
*cpu
)
1514 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
1517 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
1519 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
1520 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
1521 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
1523 assert((void *)(entry
+ 1) <= limit
);
1525 entry
->index
= index
;
1526 entry
->reserved
= 0;
1527 entry
->data
= value
;
1531 static int kvm_put_one_msr(X86CPU
*cpu
, int index
, uint64_t value
)
1533 kvm_msr_buf_reset(cpu
);
1534 kvm_msr_entry_add(cpu
, index
, value
);
1536 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1539 void kvm_put_apicbase(X86CPU
*cpu
, uint64_t value
)
1543 ret
= kvm_put_one_msr(cpu
, MSR_IA32_APICBASE
, value
);
1547 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
1549 CPUX86State
*env
= &cpu
->env
;
1552 if (!has_msr_tsc_deadline
) {
1556 ret
= kvm_put_one_msr(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1566 * Provide a separate write service for the feature control MSR in order to
1567 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1568 * before writing any other state because forcibly leaving nested mode
1569 * invalidates the VCPU state.
1571 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
1575 if (!has_msr_feature_control
) {
1579 ret
= kvm_put_one_msr(cpu
, MSR_IA32_FEATURE_CONTROL
,
1580 cpu
->env
.msr_ia32_feature_control
);
1589 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1591 CPUX86State
*env
= &cpu
->env
;
1595 kvm_msr_buf_reset(cpu
);
1597 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1598 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1599 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1600 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
1602 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
1604 if (has_msr_hsave_pa
) {
1605 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1607 if (has_msr_tsc_aux
) {
1608 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
1610 if (has_msr_tsc_adjust
) {
1611 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
1613 if (has_msr_misc_enable
) {
1614 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
1615 env
->msr_ia32_misc_enable
);
1617 if (has_msr_smbase
) {
1618 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
1620 if (has_msr_bndcfgs
) {
1621 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
1624 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
1626 #ifdef TARGET_X86_64
1627 if (lm_capable_kernel
) {
1628 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
1629 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
1630 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
1631 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
1635 * The following MSRs have side effects on the guest or are too heavy
1636 * for normal writeback. Limit them to reset or full state updates.
1638 if (level
>= KVM_PUT_RESET_STATE
) {
1639 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
1640 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
1641 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1642 if (has_msr_async_pf_en
) {
1643 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
1645 if (has_msr_pv_eoi_en
) {
1646 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
1648 if (has_msr_kvm_steal_time
) {
1649 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
1651 if (has_msr_architectural_pmu
) {
1652 /* Stop the counter. */
1653 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1654 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1656 /* Set the counter values. */
1657 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1658 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
1659 env
->msr_fixed_counters
[i
]);
1661 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1662 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
1663 env
->msr_gp_counters
[i
]);
1664 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
1665 env
->msr_gp_evtsel
[i
]);
1667 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
1668 env
->msr_global_status
);
1669 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
1670 env
->msr_global_ovf_ctrl
);
1672 /* Now start the PMU. */
1673 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
1674 env
->msr_fixed_ctr_ctrl
);
1675 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
1676 env
->msr_global_ctrl
);
1678 if (has_msr_hv_hypercall
) {
1679 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
1680 env
->msr_hv_guest_os_id
);
1681 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
1682 env
->msr_hv_hypercall
);
1684 if (cpu
->hyperv_vapic
) {
1685 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
1688 if (cpu
->hyperv_time
) {
1689 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, env
->msr_hv_tsc
);
1691 if (has_msr_hv_crash
) {
1694 for (j
= 0; j
< HV_X64_MSR_CRASH_PARAMS
; j
++)
1695 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
1696 env
->msr_hv_crash_params
[j
]);
1698 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
,
1699 HV_X64_MSR_CRASH_CTL_NOTIFY
);
1701 if (has_msr_hv_runtime
) {
1702 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
1704 if (cpu
->hyperv_synic
) {
1707 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
1708 env
->msr_hv_synic_control
);
1709 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
,
1710 env
->msr_hv_synic_version
);
1711 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
1712 env
->msr_hv_synic_evt_page
);
1713 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
1714 env
->msr_hv_synic_msg_page
);
1716 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
1717 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
1718 env
->msr_hv_synic_sint
[j
]);
1721 if (has_msr_hv_stimer
) {
1724 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
1725 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
1726 env
->msr_hv_stimer_config
[j
]);
1729 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
1730 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
1731 env
->msr_hv_stimer_count
[j
]);
1734 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
1735 uint64_t phys_mask
= MAKE_64BIT_MASK(0, cpu
->phys_bits
);
1737 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
1738 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
1739 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
1740 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
1741 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
1742 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
1743 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
1744 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
1745 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
1746 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
1747 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
1748 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
1749 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
1750 /* The CPU GPs if we write to a bit above the physical limit of
1751 * the host CPU (and KVM emulates that)
1753 uint64_t mask
= env
->mtrr_var
[i
].mask
;
1756 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
1757 env
->mtrr_var
[i
].base
);
1758 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), mask
);
1762 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1763 * kvm_put_msr_feature_control. */
1768 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
1769 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
1770 if (has_msr_mcg_ext_ctl
) {
1771 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, env
->mcg_ext_ctl
);
1773 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1774 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1778 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1783 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
1788 static int kvm_get_fpu(X86CPU
*cpu
)
1790 CPUX86State
*env
= &cpu
->env
;
1794 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
1799 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1800 env
->fpus
= fpu
.fsw
;
1801 env
->fpuc
= fpu
.fcw
;
1802 env
->fpop
= fpu
.last_opcode
;
1803 env
->fpip
= fpu
.last_ip
;
1804 env
->fpdp
= fpu
.last_dp
;
1805 for (i
= 0; i
< 8; ++i
) {
1806 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1808 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1809 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1810 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
1811 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
1813 env
->mxcsr
= fpu
.mxcsr
;
1818 static int kvm_get_xsave(X86CPU
*cpu
)
1820 CPUX86State
*env
= &cpu
->env
;
1821 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1823 uint16_t cwd
, swd
, twd
;
1826 return kvm_get_fpu(cpu
);
1829 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
1834 cwd
= xsave
->legacy
.fcw
;
1835 swd
= xsave
->legacy
.fsw
;
1836 twd
= xsave
->legacy
.ftw
;
1837 env
->fpop
= xsave
->legacy
.fpop
;
1838 env
->fpstt
= (swd
>> 11) & 7;
1841 for (i
= 0; i
< 8; ++i
) {
1842 env
->fptags
[i
] = !((twd
>> i
) & 1);
1844 env
->fpip
= xsave
->legacy
.fpip
;
1845 env
->fpdp
= xsave
->legacy
.fpdp
;
1846 env
->mxcsr
= xsave
->legacy
.mxcsr
;
1847 memcpy(env
->fpregs
, &xsave
->legacy
.fpregs
,
1848 sizeof env
->fpregs
);
1849 env
->xstate_bv
= xsave
->header
.xstate_bv
;
1850 memcpy(env
->bnd_regs
, &xsave
->bndreg_state
.bnd_regs
,
1851 sizeof env
->bnd_regs
);
1852 env
->bndcs_regs
= xsave
->bndcsr_state
.bndcsr
;
1853 memcpy(env
->opmask_regs
, &xsave
->opmask_state
.opmask_regs
,
1854 sizeof env
->opmask_regs
);
1856 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1857 uint8_t *xmm
= xsave
->legacy
.xmm_regs
[i
];
1858 uint8_t *ymmh
= xsave
->avx_state
.ymmh
[i
];
1859 uint8_t *zmmh
= xsave
->zmm_hi256_state
.zmm_hi256
[i
];
1860 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(xmm
);
1861 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(xmm
+8);
1862 env
->xmm_regs
[i
].ZMM_Q(2) = ldq_p(ymmh
);
1863 env
->xmm_regs
[i
].ZMM_Q(3) = ldq_p(ymmh
+8);
1864 env
->xmm_regs
[i
].ZMM_Q(4) = ldq_p(zmmh
);
1865 env
->xmm_regs
[i
].ZMM_Q(5) = ldq_p(zmmh
+8);
1866 env
->xmm_regs
[i
].ZMM_Q(6) = ldq_p(zmmh
+16);
1867 env
->xmm_regs
[i
].ZMM_Q(7) = ldq_p(zmmh
+24);
1870 #ifdef TARGET_X86_64
1871 memcpy(&env
->xmm_regs
[16], &xsave
->hi16_zmm_state
.hi16_zmm
,
1872 16 * sizeof env
->xmm_regs
[16]);
1873 memcpy(&env
->pkru
, &xsave
->pkru_state
, sizeof env
->pkru
);
1878 static int kvm_get_xcrs(X86CPU
*cpu
)
1880 CPUX86State
*env
= &cpu
->env
;
1882 struct kvm_xcrs xcrs
;
1888 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
1893 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1894 /* Only support xcr0 now */
1895 if (xcrs
.xcrs
[i
].xcr
== 0) {
1896 env
->xcr0
= xcrs
.xcrs
[i
].value
;
1903 static int kvm_get_sregs(X86CPU
*cpu
)
1905 CPUX86State
*env
= &cpu
->env
;
1906 struct kvm_sregs sregs
;
1910 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1915 /* There can only be one pending IRQ set in the bitmap at a time, so try
1916 to find it and save its number instead (-1 for none). */
1917 env
->interrupt_injected
= -1;
1918 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1919 if (sregs
.interrupt_bitmap
[i
]) {
1920 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1921 env
->interrupt_injected
= i
* 64 + bit
;
1926 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1927 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1928 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1929 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1930 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1931 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1933 get_seg(&env
->tr
, &sregs
.tr
);
1934 get_seg(&env
->ldt
, &sregs
.ldt
);
1936 env
->idt
.limit
= sregs
.idt
.limit
;
1937 env
->idt
.base
= sregs
.idt
.base
;
1938 env
->gdt
.limit
= sregs
.gdt
.limit
;
1939 env
->gdt
.base
= sregs
.gdt
.base
;
1941 env
->cr
[0] = sregs
.cr0
;
1942 env
->cr
[2] = sregs
.cr2
;
1943 env
->cr
[3] = sregs
.cr3
;
1944 env
->cr
[4] = sregs
.cr4
;
1946 env
->efer
= sregs
.efer
;
1948 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1950 #define HFLAG_COPY_MASK \
1951 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1952 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1953 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1954 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1956 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
1957 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1958 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1959 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1960 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1961 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1963 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
1964 hflags
|= HF_OSFXSR_MASK
;
1967 if (env
->efer
& MSR_EFER_LMA
) {
1968 hflags
|= HF_LMA_MASK
;
1971 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1972 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1974 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1975 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1976 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1977 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1978 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1979 !(hflags
& HF_CS32_MASK
)) {
1980 hflags
|= HF_ADDSEG_MASK
;
1982 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1983 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1986 env
->hflags
= hflags
;
1991 static int kvm_get_msrs(X86CPU
*cpu
)
1993 CPUX86State
*env
= &cpu
->env
;
1994 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
1996 uint64_t mtrr_top_bits
;
1998 kvm_msr_buf_reset(cpu
);
2000 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
2001 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
2002 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
2003 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
2005 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
2007 if (has_msr_hsave_pa
) {
2008 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
2010 if (has_msr_tsc_aux
) {
2011 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
2013 if (has_msr_tsc_adjust
) {
2014 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
2016 if (has_msr_tsc_deadline
) {
2017 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
2019 if (has_msr_misc_enable
) {
2020 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
2022 if (has_msr_smbase
) {
2023 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
2025 if (has_msr_feature_control
) {
2026 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
2028 if (has_msr_bndcfgs
) {
2029 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
2032 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
2036 if (!env
->tsc_valid
) {
2037 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
2038 env
->tsc_valid
= !runstate_is_running();
2041 #ifdef TARGET_X86_64
2042 if (lm_capable_kernel
) {
2043 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
2044 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
2045 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
2046 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
2049 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
2050 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
2051 if (has_msr_async_pf_en
) {
2052 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
2054 if (has_msr_pv_eoi_en
) {
2055 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
2057 if (has_msr_kvm_steal_time
) {
2058 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
2060 if (has_msr_architectural_pmu
) {
2061 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
2062 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2063 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
2064 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
2065 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
2066 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
2068 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
2069 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
2070 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
2075 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
2076 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
2077 if (has_msr_mcg_ext_ctl
) {
2078 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, 0);
2080 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2081 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
2085 if (has_msr_hv_hypercall
) {
2086 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
2087 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
2089 if (cpu
->hyperv_vapic
) {
2090 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
2092 if (cpu
->hyperv_time
) {
2093 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
2095 if (has_msr_hv_crash
) {
2098 for (j
= 0; j
< HV_X64_MSR_CRASH_PARAMS
; j
++) {
2099 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
2102 if (has_msr_hv_runtime
) {
2103 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
2105 if (cpu
->hyperv_synic
) {
2108 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
2109 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, 0);
2110 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
2111 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
2112 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
2113 kvm_msr_entry_add(cpu
, msr
, 0);
2116 if (has_msr_hv_stimer
) {
2119 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
2121 kvm_msr_entry_add(cpu
, msr
, 0);
2124 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
2125 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
2126 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
2127 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
2128 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
2129 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
2130 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
2131 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
2132 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
2133 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
2134 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
2135 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
2136 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
2137 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2138 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
2139 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
2143 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
2148 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2150 * MTRR masks: Each mask consists of 5 parts
2151 * a 10..0: must be zero
2153 * c n-1.12: actual mask bits
2154 * d 51..n: reserved must be zero
2155 * e 63.52: reserved must be zero
2157 * 'n' is the number of physical bits supported by the CPU and is
2158 * apparently always <= 52. We know our 'n' but don't know what
2159 * the destinations 'n' is; it might be smaller, in which case
2160 * it masks (c) on loading. It might be larger, in which case
2161 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2162 * we're migrating to.
2165 if (cpu
->fill_mtrr_mask
) {
2166 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS
> 52);
2167 assert(cpu
->phys_bits
<= TARGET_PHYS_ADDR_SPACE_BITS
);
2168 mtrr_top_bits
= MAKE_64BIT_MASK(cpu
->phys_bits
, 52 - cpu
->phys_bits
);
2173 for (i
= 0; i
< ret
; i
++) {
2174 uint32_t index
= msrs
[i
].index
;
2176 case MSR_IA32_SYSENTER_CS
:
2177 env
->sysenter_cs
= msrs
[i
].data
;
2179 case MSR_IA32_SYSENTER_ESP
:
2180 env
->sysenter_esp
= msrs
[i
].data
;
2182 case MSR_IA32_SYSENTER_EIP
:
2183 env
->sysenter_eip
= msrs
[i
].data
;
2186 env
->pat
= msrs
[i
].data
;
2189 env
->star
= msrs
[i
].data
;
2191 #ifdef TARGET_X86_64
2193 env
->cstar
= msrs
[i
].data
;
2195 case MSR_KERNELGSBASE
:
2196 env
->kernelgsbase
= msrs
[i
].data
;
2199 env
->fmask
= msrs
[i
].data
;
2202 env
->lstar
= msrs
[i
].data
;
2206 env
->tsc
= msrs
[i
].data
;
2209 env
->tsc_aux
= msrs
[i
].data
;
2211 case MSR_TSC_ADJUST
:
2212 env
->tsc_adjust
= msrs
[i
].data
;
2214 case MSR_IA32_TSCDEADLINE
:
2215 env
->tsc_deadline
= msrs
[i
].data
;
2217 case MSR_VM_HSAVE_PA
:
2218 env
->vm_hsave
= msrs
[i
].data
;
2220 case MSR_KVM_SYSTEM_TIME
:
2221 env
->system_time_msr
= msrs
[i
].data
;
2223 case MSR_KVM_WALL_CLOCK
:
2224 env
->wall_clock_msr
= msrs
[i
].data
;
2226 case MSR_MCG_STATUS
:
2227 env
->mcg_status
= msrs
[i
].data
;
2230 env
->mcg_ctl
= msrs
[i
].data
;
2232 case MSR_MCG_EXT_CTL
:
2233 env
->mcg_ext_ctl
= msrs
[i
].data
;
2235 case MSR_IA32_MISC_ENABLE
:
2236 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
2238 case MSR_IA32_SMBASE
:
2239 env
->smbase
= msrs
[i
].data
;
2241 case MSR_IA32_FEATURE_CONTROL
:
2242 env
->msr_ia32_feature_control
= msrs
[i
].data
;
2244 case MSR_IA32_BNDCFGS
:
2245 env
->msr_bndcfgs
= msrs
[i
].data
;
2248 env
->xss
= msrs
[i
].data
;
2251 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
2252 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
2253 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
2256 case MSR_KVM_ASYNC_PF_EN
:
2257 env
->async_pf_en_msr
= msrs
[i
].data
;
2259 case MSR_KVM_PV_EOI_EN
:
2260 env
->pv_eoi_en_msr
= msrs
[i
].data
;
2262 case MSR_KVM_STEAL_TIME
:
2263 env
->steal_time_msr
= msrs
[i
].data
;
2265 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
2266 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
2268 case MSR_CORE_PERF_GLOBAL_CTRL
:
2269 env
->msr_global_ctrl
= msrs
[i
].data
;
2271 case MSR_CORE_PERF_GLOBAL_STATUS
:
2272 env
->msr_global_status
= msrs
[i
].data
;
2274 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
2275 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
2277 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
2278 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
2280 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
2281 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
2283 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
2284 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
2286 case HV_X64_MSR_HYPERCALL
:
2287 env
->msr_hv_hypercall
= msrs
[i
].data
;
2289 case HV_X64_MSR_GUEST_OS_ID
:
2290 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
2292 case HV_X64_MSR_APIC_ASSIST_PAGE
:
2293 env
->msr_hv_vapic
= msrs
[i
].data
;
2295 case HV_X64_MSR_REFERENCE_TSC
:
2296 env
->msr_hv_tsc
= msrs
[i
].data
;
2298 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
2299 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
2301 case HV_X64_MSR_VP_RUNTIME
:
2302 env
->msr_hv_runtime
= msrs
[i
].data
;
2304 case HV_X64_MSR_SCONTROL
:
2305 env
->msr_hv_synic_control
= msrs
[i
].data
;
2307 case HV_X64_MSR_SVERSION
:
2308 env
->msr_hv_synic_version
= msrs
[i
].data
;
2310 case HV_X64_MSR_SIEFP
:
2311 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
2313 case HV_X64_MSR_SIMP
:
2314 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
2316 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
2317 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
2319 case HV_X64_MSR_STIMER0_CONFIG
:
2320 case HV_X64_MSR_STIMER1_CONFIG
:
2321 case HV_X64_MSR_STIMER2_CONFIG
:
2322 case HV_X64_MSR_STIMER3_CONFIG
:
2323 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
2326 case HV_X64_MSR_STIMER0_COUNT
:
2327 case HV_X64_MSR_STIMER1_COUNT
:
2328 case HV_X64_MSR_STIMER2_COUNT
:
2329 case HV_X64_MSR_STIMER3_COUNT
:
2330 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
2333 case MSR_MTRRdefType
:
2334 env
->mtrr_deftype
= msrs
[i
].data
;
2336 case MSR_MTRRfix64K_00000
:
2337 env
->mtrr_fixed
[0] = msrs
[i
].data
;
2339 case MSR_MTRRfix16K_80000
:
2340 env
->mtrr_fixed
[1] = msrs
[i
].data
;
2342 case MSR_MTRRfix16K_A0000
:
2343 env
->mtrr_fixed
[2] = msrs
[i
].data
;
2345 case MSR_MTRRfix4K_C0000
:
2346 env
->mtrr_fixed
[3] = msrs
[i
].data
;
2348 case MSR_MTRRfix4K_C8000
:
2349 env
->mtrr_fixed
[4] = msrs
[i
].data
;
2351 case MSR_MTRRfix4K_D0000
:
2352 env
->mtrr_fixed
[5] = msrs
[i
].data
;
2354 case MSR_MTRRfix4K_D8000
:
2355 env
->mtrr_fixed
[6] = msrs
[i
].data
;
2357 case MSR_MTRRfix4K_E0000
:
2358 env
->mtrr_fixed
[7] = msrs
[i
].data
;
2360 case MSR_MTRRfix4K_E8000
:
2361 env
->mtrr_fixed
[8] = msrs
[i
].data
;
2363 case MSR_MTRRfix4K_F0000
:
2364 env
->mtrr_fixed
[9] = msrs
[i
].data
;
2366 case MSR_MTRRfix4K_F8000
:
2367 env
->mtrr_fixed
[10] = msrs
[i
].data
;
2369 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
2371 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
|
2374 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
2383 static int kvm_put_mp_state(X86CPU
*cpu
)
2385 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
2387 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
2390 static int kvm_get_mp_state(X86CPU
*cpu
)
2392 CPUState
*cs
= CPU(cpu
);
2393 CPUX86State
*env
= &cpu
->env
;
2394 struct kvm_mp_state mp_state
;
2397 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
2401 env
->mp_state
= mp_state
.mp_state
;
2402 if (kvm_irqchip_in_kernel()) {
2403 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
2408 static int kvm_get_apic(X86CPU
*cpu
)
2410 DeviceState
*apic
= cpu
->apic_state
;
2411 struct kvm_lapic_state kapic
;
2414 if (apic
&& kvm_irqchip_in_kernel()) {
2415 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
2420 kvm_get_apic_state(apic
, &kapic
);
2425 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
2427 CPUState
*cs
= CPU(cpu
);
2428 CPUX86State
*env
= &cpu
->env
;
2429 struct kvm_vcpu_events events
= {};
2431 if (!kvm_has_vcpu_events()) {
2435 events
.exception
.injected
= (env
->exception_injected
>= 0);
2436 events
.exception
.nr
= env
->exception_injected
;
2437 events
.exception
.has_error_code
= env
->has_error_code
;
2438 events
.exception
.error_code
= env
->error_code
;
2439 events
.exception
.pad
= 0;
2441 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
2442 events
.interrupt
.nr
= env
->interrupt_injected
;
2443 events
.interrupt
.soft
= env
->soft_interrupt
;
2445 events
.nmi
.injected
= env
->nmi_injected
;
2446 events
.nmi
.pending
= env
->nmi_pending
;
2447 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
2450 events
.sipi_vector
= env
->sipi_vector
;
2453 if (has_msr_smbase
) {
2454 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
2455 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
2456 if (kvm_irqchip_in_kernel()) {
2457 /* As soon as these are moved to the kernel, remove them
2458 * from cs->interrupt_request.
2460 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
2461 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
2462 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
2464 /* Keep these in cs->interrupt_request. */
2465 events
.smi
.pending
= 0;
2466 events
.smi
.latched_init
= 0;
2468 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
2471 if (level
>= KVM_PUT_RESET_STATE
) {
2473 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
2476 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
2479 static int kvm_get_vcpu_events(X86CPU
*cpu
)
2481 CPUX86State
*env
= &cpu
->env
;
2482 struct kvm_vcpu_events events
;
2485 if (!kvm_has_vcpu_events()) {
2489 memset(&events
, 0, sizeof(events
));
2490 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
2494 env
->exception_injected
=
2495 events
.exception
.injected
? events
.exception
.nr
: -1;
2496 env
->has_error_code
= events
.exception
.has_error_code
;
2497 env
->error_code
= events
.exception
.error_code
;
2499 env
->interrupt_injected
=
2500 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
2501 env
->soft_interrupt
= events
.interrupt
.soft
;
2503 env
->nmi_injected
= events
.nmi
.injected
;
2504 env
->nmi_pending
= events
.nmi
.pending
;
2505 if (events
.nmi
.masked
) {
2506 env
->hflags2
|= HF2_NMI_MASK
;
2508 env
->hflags2
&= ~HF2_NMI_MASK
;
2511 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
2512 if (events
.smi
.smm
) {
2513 env
->hflags
|= HF_SMM_MASK
;
2515 env
->hflags
&= ~HF_SMM_MASK
;
2517 if (events
.smi
.pending
) {
2518 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2520 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2522 if (events
.smi
.smm_inside_nmi
) {
2523 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
2525 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
2527 if (events
.smi
.latched_init
) {
2528 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2530 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2534 env
->sipi_vector
= events
.sipi_vector
;
2539 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
2541 CPUState
*cs
= CPU(cpu
);
2542 CPUX86State
*env
= &cpu
->env
;
2544 unsigned long reinject_trap
= 0;
2546 if (!kvm_has_vcpu_events()) {
2547 if (env
->exception_injected
== 1) {
2548 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
2549 } else if (env
->exception_injected
== 3) {
2550 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
2552 env
->exception_injected
= -1;
2556 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2557 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2558 * by updating the debug state once again if single-stepping is on.
2559 * Another reason to call kvm_update_guest_debug here is a pending debug
2560 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2561 * reinject them via SET_GUEST_DEBUG.
2563 if (reinject_trap
||
2564 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
2565 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
2570 static int kvm_put_debugregs(X86CPU
*cpu
)
2572 CPUX86State
*env
= &cpu
->env
;
2573 struct kvm_debugregs dbgregs
;
2576 if (!kvm_has_debugregs()) {
2580 for (i
= 0; i
< 4; i
++) {
2581 dbgregs
.db
[i
] = env
->dr
[i
];
2583 dbgregs
.dr6
= env
->dr
[6];
2584 dbgregs
.dr7
= env
->dr
[7];
2587 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
2590 static int kvm_get_debugregs(X86CPU
*cpu
)
2592 CPUX86State
*env
= &cpu
->env
;
2593 struct kvm_debugregs dbgregs
;
2596 if (!kvm_has_debugregs()) {
2600 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
2604 for (i
= 0; i
< 4; i
++) {
2605 env
->dr
[i
] = dbgregs
.db
[i
];
2607 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
2608 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
2613 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
2615 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2618 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
2620 if (level
>= KVM_PUT_RESET_STATE
) {
2621 ret
= kvm_put_msr_feature_control(x86_cpu
);
2627 if (level
== KVM_PUT_FULL_STATE
) {
2628 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2629 * because TSC frequency mismatch shouldn't abort migration,
2630 * unless the user explicitly asked for a more strict TSC
2631 * setting (e.g. using an explicit "tsc-freq" option).
2633 kvm_arch_set_tsc_khz(cpu
);
2636 ret
= kvm_getput_regs(x86_cpu
, 1);
2640 ret
= kvm_put_xsave(x86_cpu
);
2644 ret
= kvm_put_xcrs(x86_cpu
);
2648 ret
= kvm_put_sregs(x86_cpu
);
2652 /* must be before kvm_put_msrs */
2653 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
2657 ret
= kvm_put_msrs(x86_cpu
, level
);
2661 if (level
>= KVM_PUT_RESET_STATE
) {
2662 ret
= kvm_put_mp_state(x86_cpu
);
2668 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
2673 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
2677 ret
= kvm_put_debugregs(x86_cpu
);
2682 ret
= kvm_guest_debug_workarounds(x86_cpu
);
2689 int kvm_arch_get_registers(CPUState
*cs
)
2691 X86CPU
*cpu
= X86_CPU(cs
);
2694 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
2696 ret
= kvm_getput_regs(cpu
, 0);
2700 ret
= kvm_get_xsave(cpu
);
2704 ret
= kvm_get_xcrs(cpu
);
2708 ret
= kvm_get_sregs(cpu
);
2712 ret
= kvm_get_msrs(cpu
);
2716 ret
= kvm_get_mp_state(cpu
);
2720 ret
= kvm_get_apic(cpu
);
2724 ret
= kvm_get_vcpu_events(cpu
);
2728 ret
= kvm_get_debugregs(cpu
);
2734 cpu_sync_bndcs_hflags(&cpu
->env
);
2738 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
2740 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2741 CPUX86State
*env
= &x86_cpu
->env
;
2745 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
2746 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
2747 qemu_mutex_lock_iothread();
2748 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
2749 qemu_mutex_unlock_iothread();
2750 DPRINTF("injected NMI\n");
2751 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
2753 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
2757 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
2758 qemu_mutex_lock_iothread();
2759 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
2760 qemu_mutex_unlock_iothread();
2761 DPRINTF("injected SMI\n");
2762 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
2764 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
2770 if (!kvm_pic_in_kernel()) {
2771 qemu_mutex_lock_iothread();
2774 /* Force the VCPU out of its inner loop to process any INIT requests
2775 * or (for userspace APIC, but it is cheap to combine the checks here)
2776 * pending TPR access reports.
2778 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
2779 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
2780 !(env
->hflags
& HF_SMM_MASK
)) {
2781 cpu
->exit_request
= 1;
2783 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2784 cpu
->exit_request
= 1;
2788 if (!kvm_pic_in_kernel()) {
2789 /* Try to inject an interrupt if the guest can accept it */
2790 if (run
->ready_for_interrupt_injection
&&
2791 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2792 (env
->eflags
& IF_MASK
)) {
2795 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
2796 irq
= cpu_get_pic_interrupt(env
);
2798 struct kvm_interrupt intr
;
2801 DPRINTF("injected interrupt %d\n", irq
);
2802 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
2805 "KVM: injection failed, interrupt lost (%s)\n",
2811 /* If we have an interrupt but the guest is not ready to receive an
2812 * interrupt, request an interrupt window exit. This will
2813 * cause a return to userspace as soon as the guest is ready to
2814 * receive interrupts. */
2815 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
2816 run
->request_interrupt_window
= 1;
2818 run
->request_interrupt_window
= 0;
2821 DPRINTF("setting tpr\n");
2822 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
2824 qemu_mutex_unlock_iothread();
2828 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
2830 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2831 CPUX86State
*env
= &x86_cpu
->env
;
2833 if (run
->flags
& KVM_RUN_X86_SMM
) {
2834 env
->hflags
|= HF_SMM_MASK
;
2836 env
->hflags
&= HF_SMM_MASK
;
2839 env
->eflags
|= IF_MASK
;
2841 env
->eflags
&= ~IF_MASK
;
2844 /* We need to protect the apic state against concurrent accesses from
2845 * different threads in case the userspace irqchip is used. */
2846 if (!kvm_irqchip_in_kernel()) {
2847 qemu_mutex_lock_iothread();
2849 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
2850 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
2851 if (!kvm_irqchip_in_kernel()) {
2852 qemu_mutex_unlock_iothread();
2854 return cpu_get_mem_attrs(env
);
2857 int kvm_arch_process_async_events(CPUState
*cs
)
2859 X86CPU
*cpu
= X86_CPU(cs
);
2860 CPUX86State
*env
= &cpu
->env
;
2862 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
2863 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2864 assert(env
->mcg_cap
);
2866 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
2868 kvm_cpu_synchronize_state(cs
);
2870 if (env
->exception_injected
== EXCP08_DBLE
) {
2871 /* this means triple fault */
2872 qemu_system_reset_request();
2873 cs
->exit_request
= 1;
2876 env
->exception_injected
= EXCP12_MCHK
;
2877 env
->has_error_code
= 0;
2880 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
2881 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
2885 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
2886 !(env
->hflags
& HF_SMM_MASK
)) {
2887 kvm_cpu_synchronize_state(cs
);
2891 if (kvm_irqchip_in_kernel()) {
2895 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
2896 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
2897 apic_poll_irq(cpu
->apic_state
);
2899 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2900 (env
->eflags
& IF_MASK
)) ||
2901 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2904 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
2905 kvm_cpu_synchronize_state(cs
);
2908 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2909 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
2910 kvm_cpu_synchronize_state(cs
);
2911 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
2912 env
->tpr_access_type
);
2918 static int kvm_handle_halt(X86CPU
*cpu
)
2920 CPUState
*cs
= CPU(cpu
);
2921 CPUX86State
*env
= &cpu
->env
;
2923 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2924 (env
->eflags
& IF_MASK
)) &&
2925 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2933 static int kvm_handle_tpr_access(X86CPU
*cpu
)
2935 CPUState
*cs
= CPU(cpu
);
2936 struct kvm_run
*run
= cs
->kvm_run
;
2938 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
2939 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
2944 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2946 static const uint8_t int3
= 0xcc;
2948 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
2949 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
2955 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2959 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
2960 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
2972 static int nb_hw_breakpoint
;
2974 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
2978 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2979 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
2980 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
2987 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
2988 target_ulong len
, int type
)
2991 case GDB_BREAKPOINT_HW
:
2994 case GDB_WATCHPOINT_WRITE
:
2995 case GDB_WATCHPOINT_ACCESS
:
3002 if (addr
& (len
- 1)) {
3014 if (nb_hw_breakpoint
== 4) {
3017 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
3020 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
3021 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
3022 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
3028 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
3029 target_ulong len
, int type
)
3033 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
3038 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
3043 void kvm_arch_remove_all_hw_breakpoints(void)
3045 nb_hw_breakpoint
= 0;
3048 static CPUWatchpoint hw_watchpoint
;
3050 static int kvm_handle_debug(X86CPU
*cpu
,
3051 struct kvm_debug_exit_arch
*arch_info
)
3053 CPUState
*cs
= CPU(cpu
);
3054 CPUX86State
*env
= &cpu
->env
;
3058 if (arch_info
->exception
== 1) {
3059 if (arch_info
->dr6
& (1 << 14)) {
3060 if (cs
->singlestep_enabled
) {
3064 for (n
= 0; n
< 4; n
++) {
3065 if (arch_info
->dr6
& (1 << n
)) {
3066 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
3072 cs
->watchpoint_hit
= &hw_watchpoint
;
3073 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
3074 hw_watchpoint
.flags
= BP_MEM_WRITE
;
3078 cs
->watchpoint_hit
= &hw_watchpoint
;
3079 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
3080 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
3086 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
3090 cpu_synchronize_state(cs
);
3091 assert(env
->exception_injected
== -1);
3094 env
->exception_injected
= arch_info
->exception
;
3095 env
->has_error_code
= 0;
3101 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
3103 const uint8_t type_code
[] = {
3104 [GDB_BREAKPOINT_HW
] = 0x0,
3105 [GDB_WATCHPOINT_WRITE
] = 0x1,
3106 [GDB_WATCHPOINT_ACCESS
] = 0x3
3108 const uint8_t len_code
[] = {
3109 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3113 if (kvm_sw_breakpoints_active(cpu
)) {
3114 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
3116 if (nb_hw_breakpoint
> 0) {
3117 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
3118 dbg
->arch
.debugreg
[7] = 0x0600;
3119 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
3120 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
3121 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
3122 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
3123 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
3128 static bool host_supports_vmx(void)
3130 uint32_t ecx
, unused
;
3132 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
3133 return ecx
& CPUID_EXT_VMX
;
3136 #define VMX_INVALID_GUEST_STATE 0x80000021
3138 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
3140 X86CPU
*cpu
= X86_CPU(cs
);
3144 switch (run
->exit_reason
) {
3146 DPRINTF("handle_hlt\n");
3147 qemu_mutex_lock_iothread();
3148 ret
= kvm_handle_halt(cpu
);
3149 qemu_mutex_unlock_iothread();
3151 case KVM_EXIT_SET_TPR
:
3154 case KVM_EXIT_TPR_ACCESS
:
3155 qemu_mutex_lock_iothread();
3156 ret
= kvm_handle_tpr_access(cpu
);
3157 qemu_mutex_unlock_iothread();
3159 case KVM_EXIT_FAIL_ENTRY
:
3160 code
= run
->fail_entry
.hardware_entry_failure_reason
;
3161 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
3163 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
3165 "\nIf you're running a guest on an Intel machine without "
3166 "unrestricted mode\n"
3167 "support, the failure can be most likely due to the guest "
3168 "entering an invalid\n"
3169 "state for Intel VT. For example, the guest maybe running "
3170 "in big real mode\n"
3171 "which is not supported on less recent Intel processors."
3176 case KVM_EXIT_EXCEPTION
:
3177 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
3178 run
->ex
.exception
, run
->ex
.error_code
);
3181 case KVM_EXIT_DEBUG
:
3182 DPRINTF("kvm_exit_debug\n");
3183 qemu_mutex_lock_iothread();
3184 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
3185 qemu_mutex_unlock_iothread();
3187 case KVM_EXIT_HYPERV
:
3188 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
3190 case KVM_EXIT_IOAPIC_EOI
:
3191 ioapic_eoi_broadcast(run
->eoi
.vector
);
3195 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
3203 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
3205 X86CPU
*cpu
= X86_CPU(cs
);
3206 CPUX86State
*env
= &cpu
->env
;
3208 kvm_cpu_synchronize_state(cs
);
3209 return !(env
->cr
[0] & CR0_PE_MASK
) ||
3210 ((env
->segs
[R_CS
].selector
& 3) != 3);
3213 void kvm_arch_init_irq_routing(KVMState
*s
)
3215 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
3216 /* If kernel can't do irq routing, interrupt source
3217 * override 0->2 cannot be set up as required by HPET.
3218 * So we have to disable it.
3222 /* We know at this point that we're using the in-kernel
3223 * irqchip, so we can use irqfds, and on x86 we know
3224 * we can use msi via irqfd and GSI routing.
3226 kvm_msi_via_irqfd_allowed
= true;
3227 kvm_gsi_routing_allowed
= true;
3229 if (kvm_irqchip_is_split()) {
3232 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3233 MSI routes for signaling interrupts to the local apics. */
3234 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
3235 if (kvm_irqchip_add_msi_route(s
, 0, NULL
) < 0) {
3236 error_report("Could not enable split IRQ mode.");
3243 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
3246 if (machine_kernel_irqchip_split(ms
)) {
3247 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
3249 error_report("Could not enable split irqchip mode: %s",
3253 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3254 kvm_split_irqchip
= true;
3262 /* Classic KVM device assignment interface. Will remain x86 only. */
3263 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
3264 uint32_t flags
, uint32_t *dev_id
)
3266 struct kvm_assigned_pci_dev dev_data
= {
3267 .segnr
= dev_addr
->domain
,
3268 .busnr
= dev_addr
->bus
,
3269 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
3274 dev_data
.assigned_dev_id
=
3275 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
3277 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
3282 *dev_id
= dev_data
.assigned_dev_id
;
3287 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
3289 struct kvm_assigned_pci_dev dev_data
= {
3290 .assigned_dev_id
= dev_id
,
3293 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
3296 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3297 uint32_t irq_type
, uint32_t guest_irq
)
3299 struct kvm_assigned_irq assigned_irq
= {
3300 .assigned_dev_id
= dev_id
,
3301 .guest_irq
= guest_irq
,
3305 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
3306 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
3308 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
3312 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
3315 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
3316 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
3318 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
3321 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
3323 struct kvm_assigned_pci_dev dev_data
= {
3324 .assigned_dev_id
= dev_id
,
3325 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
3328 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
3331 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3334 struct kvm_assigned_irq assigned_irq
= {
3335 .assigned_dev_id
= dev_id
,
3339 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
3342 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
3344 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
3345 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
3348 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
3350 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
3351 KVM_DEV_IRQ_GUEST_MSI
, virq
);
3354 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
3356 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
3357 KVM_DEV_IRQ_HOST_MSI
);
3360 bool kvm_device_msix_supported(KVMState
*s
)
3362 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3363 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3364 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
3367 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
3368 uint32_t nr_vectors
)
3370 struct kvm_assigned_msix_nr msix_nr
= {
3371 .assigned_dev_id
= dev_id
,
3372 .entry_nr
= nr_vectors
,
3375 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
3378 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
3381 struct kvm_assigned_msix_entry msix_entry
= {
3382 .assigned_dev_id
= dev_id
,
3387 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
3390 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
3392 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
3393 KVM_DEV_IRQ_GUEST_MSIX
, 0);
3396 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
3398 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
3399 KVM_DEV_IRQ_HOST_MSIX
);
3402 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
3403 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
3405 X86IOMMUState
*iommu
= x86_iommu_get_default();
3409 MSIMessage src
, dst
;
3410 X86IOMMUClass
*class = X86_IOMMU_GET_CLASS(iommu
);
3412 src
.address
= route
->u
.msi
.address_hi
;
3413 src
.address
<<= VTD_MSI_ADDR_HI_SHIFT
;
3414 src
.address
|= route
->u
.msi
.address_lo
;
3415 src
.data
= route
->u
.msi
.data
;
3417 ret
= class->int_remap(iommu
, &src
, &dst
, dev
? \
3418 pci_requester_id(dev
) : \
3419 X86_IOMMU_SID_INVALID
);
3421 trace_kvm_x86_fixup_msi_error(route
->gsi
);
3425 route
->u
.msi
.address_hi
= dst
.address
>> VTD_MSI_ADDR_HI_SHIFT
;
3426 route
->u
.msi
.address_lo
= dst
.address
& VTD_MSI_ADDR_LO_MASK
;
3427 route
->u
.msi
.data
= dst
.data
;
3433 typedef struct MSIRouteEntry MSIRouteEntry
;
3435 struct MSIRouteEntry
{
3436 PCIDevice
*dev
; /* Device pointer */
3437 int vector
; /* MSI/MSIX vector index */
3438 int virq
; /* Virtual IRQ index */
3439 QLIST_ENTRY(MSIRouteEntry
) list
;
3442 /* List of used GSI routes */
3443 static QLIST_HEAD(, MSIRouteEntry
) msi_route_list
= \
3444 QLIST_HEAD_INITIALIZER(msi_route_list
);
3446 static void kvm_update_msi_routes_all(void *private, bool global
,
3447 uint32_t index
, uint32_t mask
)
3450 MSIRouteEntry
*entry
;
3452 /* TODO: explicit route update */
3453 QLIST_FOREACH(entry
, &msi_route_list
, list
) {
3455 msg
= pci_get_msi_message(entry
->dev
, entry
->vector
);
3456 kvm_irqchip_update_msi_route(kvm_state
, entry
->virq
,
3459 kvm_irqchip_commit_routes(kvm_state
);
3460 trace_kvm_x86_update_msi_routes(cnt
);
3463 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
3464 int vector
, PCIDevice
*dev
)
3466 static bool notify_list_inited
= false;
3467 MSIRouteEntry
*entry
;
3470 /* These are (possibly) IOAPIC routes only used for split
3471 * kernel irqchip mode, while what we are housekeeping are
3472 * PCI devices only. */
3476 entry
= g_new0(MSIRouteEntry
, 1);
3478 entry
->vector
= vector
;
3479 entry
->virq
= route
->gsi
;
3480 QLIST_INSERT_HEAD(&msi_route_list
, entry
, list
);
3482 trace_kvm_x86_add_msi_route(route
->gsi
);
3484 if (!notify_list_inited
) {
3485 /* For the first time we do add route, add ourselves into
3486 * IOMMU's IEC notify list if needed. */
3487 X86IOMMUState
*iommu
= x86_iommu_get_default();
3489 x86_iommu_iec_register_notifier(iommu
,
3490 kvm_update_msi_routes_all
,
3493 notify_list_inited
= true;
3498 int kvm_arch_release_virq_post(int virq
)
3500 MSIRouteEntry
*entry
, *next
;
3501 QLIST_FOREACH_SAFE(entry
, &msi_route_list
, list
, next
) {
3502 if (entry
->virq
== virq
) {
3503 trace_kvm_x86_remove_msi_route(virq
);
3504 QLIST_REMOVE(entry
, list
);
3511 int kvm_arch_msi_data_to_gsi(uint32_t data
)