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target-i386: Remove has_msr_hv_tsc global variable
[qemu/ar7.git] / target-i386 / kvm.c
blob40460309496c9e30016057b15c87305544df82d2
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
40
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
47 #include "trace.h"
48
49 //#define DEBUG_KVM
50
51 #ifdef DEBUG_KVM
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF(fmt, ...) \
56 do { } while (0)
57 #endif
58
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
61
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
65
66 #ifndef BUS_MCEERR_AR
67 #define BUS_MCEERR_AR 4
68 #endif
69 #ifndef BUS_MCEERR_AO
70 #define BUS_MCEERR_AO 5
71 #endif
72
73 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78 };
79
80 static bool has_msr_star;
81 static bool has_msr_hsave_pa;
82 static bool has_msr_tsc_aux;
83 static bool has_msr_tsc_adjust;
84 static bool has_msr_tsc_deadline;
85 static bool has_msr_feature_control;
86 static bool has_msr_async_pf_en;
87 static bool has_msr_pv_eoi_en;
88 static bool has_msr_misc_enable;
89 static bool has_msr_smbase;
90 static bool has_msr_bndcfgs;
91 static bool has_msr_kvm_steal_time;
92 static int lm_capable_kernel;
93 static bool has_msr_hv_hypercall;
94 static bool has_msr_hv_crash;
95 static bool has_msr_hv_reset;
96 static bool has_msr_hv_vpindex;
97 static bool has_msr_hv_runtime;
98 static bool has_msr_hv_synic;
99 static bool has_msr_hv_stimer;
100 static bool has_msr_xss;
101
102 static bool has_msr_architectural_pmu;
103 static uint32_t num_architectural_pmu_counters;
104
105 static int has_xsave;
106 static int has_xcrs;
107 static int has_pit_state2;
108
109 static bool has_msr_mcg_ext_ctl;
110
111 static struct kvm_cpuid2 *cpuid_cache;
112
113 int kvm_has_pit_state2(void)
114 {
115 return has_pit_state2;
116 }
117
118 bool kvm_has_smm(void)
119 {
120 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
121 }
122
123 bool kvm_allows_irq0_override(void)
124 {
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
126 }
127
128 static int kvm_get_tsc(CPUState *cs)
129 {
130 X86CPU *cpu = X86_CPU(cs);
131 CPUX86State *env = &cpu->env;
132 struct {
133 struct kvm_msrs info;
134 struct kvm_msr_entry entries[1];
135 } msr_data;
136 int ret;
137
138 if (env->tsc_valid) {
139 return 0;
140 }
141
142 msr_data.info.nmsrs = 1;
143 msr_data.entries[0].index = MSR_IA32_TSC;
144 env->tsc_valid = !runstate_is_running();
145
146 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
147 if (ret < 0) {
148 return ret;
149 }
150
151 assert(ret == 1);
152 env->tsc = msr_data.entries[0].data;
153 return 0;
154 }
155
156 static inline void do_kvm_synchronize_tsc(void *arg)
157 {
158 CPUState *cpu = arg;
159
160 kvm_get_tsc(cpu);
161 }
162
163 void kvm_synchronize_all_tsc(void)
164 {
165 CPUState *cpu;
166
167 if (kvm_enabled()) {
168 CPU_FOREACH(cpu) {
169 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
170 }
171 }
172 }
173
174 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
175 {
176 struct kvm_cpuid2 *cpuid;
177 int r, size;
178
179 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
180 cpuid = g_malloc0(size);
181 cpuid->nent = max;
182 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
183 if (r == 0 && cpuid->nent >= max) {
184 r = -E2BIG;
185 }
186 if (r < 0) {
187 if (r == -E2BIG) {
188 g_free(cpuid);
189 return NULL;
190 } else {
191 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
192 strerror(-r));
193 exit(1);
194 }
195 }
196 return cpuid;
197 }
198
199 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
200 * for all entries.
201 */
202 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
203 {
204 struct kvm_cpuid2 *cpuid;
205 int max = 1;
206
207 if (cpuid_cache != NULL) {
208 return cpuid_cache;
209 }
210 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
211 max *= 2;
212 }
213 cpuid_cache = cpuid;
214 return cpuid;
215 }
216
217 static const struct kvm_para_features {
218 int cap;
219 int feature;
220 } para_features[] = {
221 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
222 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
223 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
224 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
225 };
226
227 static int get_para_features(KVMState *s)
228 {
229 int i, features = 0;
230
231 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
232 if (kvm_check_extension(s, para_features[i].cap)) {
233 features |= (1 << para_features[i].feature);
234 }
235 }
236
237 return features;
238 }
239
240
241 /* Returns the value for a specific register on the cpuid entry
242 */
243 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
244 {
245 uint32_t ret = 0;
246 switch (reg) {
247 case R_EAX:
248 ret = entry->eax;
249 break;
250 case R_EBX:
251 ret = entry->ebx;
252 break;
253 case R_ECX:
254 ret = entry->ecx;
255 break;
256 case R_EDX:
257 ret = entry->edx;
258 break;
259 }
260 return ret;
261 }
262
263 /* Find matching entry for function/index on kvm_cpuid2 struct
264 */
265 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
266 uint32_t function,
267 uint32_t index)
268 {
269 int i;
270 for (i = 0; i < cpuid->nent; ++i) {
271 if (cpuid->entries[i].function == function &&
272 cpuid->entries[i].index == index) {
273 return &cpuid->entries[i];
274 }
275 }
276 /* not found: */
277 return NULL;
278 }
279
280 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
281 uint32_t index, int reg)
282 {
283 struct kvm_cpuid2 *cpuid;
284 uint32_t ret = 0;
285 uint32_t cpuid_1_edx;
286 bool found = false;
287
288 cpuid = get_supported_cpuid(s);
289
290 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
291 if (entry) {
292 found = true;
293 ret = cpuid_entry_get_reg(entry, reg);
294 }
295
296 /* Fixups for the data returned by KVM, below */
297
298 if (function == 1 && reg == R_EDX) {
299 /* KVM before 2.6.30 misreports the following features */
300 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
301 } else if (function == 1 && reg == R_ECX) {
302 /* We can set the hypervisor flag, even if KVM does not return it on
303 * GET_SUPPORTED_CPUID
304 */
305 ret |= CPUID_EXT_HYPERVISOR;
306 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
307 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
308 * and the irqchip is in the kernel.
309 */
310 if (kvm_irqchip_in_kernel() &&
311 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
312 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
313 }
314
315 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
316 * without the in-kernel irqchip
317 */
318 if (!kvm_irqchip_in_kernel()) {
319 ret &= ~CPUID_EXT_X2APIC;
320 }
321 } else if (function == 6 && reg == R_EAX) {
322 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
323 } else if (function == 0x80000001 && reg == R_EDX) {
324 /* On Intel, kvm returns cpuid according to the Intel spec,
325 * so add missing bits according to the AMD spec:
326 */
327 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
328 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
329 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
330 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
331 * be enabled without the in-kernel irqchip
332 */
333 if (!kvm_irqchip_in_kernel()) {
334 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
335 }
336 }
337
338 /* fallback for older kernels */
339 if ((function == KVM_CPUID_FEATURES) && !found) {
340 ret = get_para_features(s);
341 }
342
343 return ret;
344 }
345
346 typedef struct HWPoisonPage {
347 ram_addr_t ram_addr;
348 QLIST_ENTRY(HWPoisonPage) list;
349 } HWPoisonPage;
350
351 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
352 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
353
354 static void kvm_unpoison_all(void *param)
355 {
356 HWPoisonPage *page, *next_page;
357
358 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
359 QLIST_REMOVE(page, list);
360 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
361 g_free(page);
362 }
363 }
364
365 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
366 {
367 HWPoisonPage *page;
368
369 QLIST_FOREACH(page, &hwpoison_page_list, list) {
370 if (page->ram_addr == ram_addr) {
371 return;
372 }
373 }
374 page = g_new(HWPoisonPage, 1);
375 page->ram_addr = ram_addr;
376 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
377 }
378
379 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
380 int *max_banks)
381 {
382 int r;
383
384 r = kvm_check_extension(s, KVM_CAP_MCE);
385 if (r > 0) {
386 *max_banks = r;
387 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
388 }
389 return -ENOSYS;
390 }
391
392 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
393 {
394 CPUState *cs = CPU(cpu);
395 CPUX86State *env = &cpu->env;
396 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
397 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
398 uint64_t mcg_status = MCG_STATUS_MCIP;
399 int flags = 0;
400
401 if (code == BUS_MCEERR_AR) {
402 status |= MCI_STATUS_AR | 0x134;
403 mcg_status |= MCG_STATUS_EIPV;
404 } else {
405 status |= 0xc0;
406 mcg_status |= MCG_STATUS_RIPV;
407 }
408
409 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
410 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
411 * guest kernel back into env->mcg_ext_ctl.
412 */
413 cpu_synchronize_state(cs);
414 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
415 mcg_status |= MCG_STATUS_LMCE;
416 flags = 0;
417 }
418
419 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
420 (MCM_ADDR_PHYS << 6) | 0xc, flags);
421 }
422
423 static void hardware_memory_error(void)
424 {
425 fprintf(stderr, "Hardware memory error!\n");
426 exit(1);
427 }
428
429 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
430 {
431 X86CPU *cpu = X86_CPU(c);
432 CPUX86State *env = &cpu->env;
433 ram_addr_t ram_addr;
434 hwaddr paddr;
435
436 if ((env->mcg_cap & MCG_SER_P) && addr
437 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
438 ram_addr = qemu_ram_addr_from_host(addr);
439 if (ram_addr == RAM_ADDR_INVALID ||
440 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
441 fprintf(stderr, "Hardware memory error for memory used by "
442 "QEMU itself instead of guest system!\n");
443 /* Hope we are lucky for AO MCE */
444 if (code == BUS_MCEERR_AO) {
445 return 0;
446 } else {
447 hardware_memory_error();
448 }
449 }
450 kvm_hwpoison_page_add(ram_addr);
451 kvm_mce_inject(cpu, paddr, code);
452 } else {
453 if (code == BUS_MCEERR_AO) {
454 return 0;
455 } else if (code == BUS_MCEERR_AR) {
456 hardware_memory_error();
457 } else {
458 return 1;
459 }
460 }
461 return 0;
462 }
463
464 int kvm_arch_on_sigbus(int code, void *addr)
465 {
466 X86CPU *cpu = X86_CPU(first_cpu);
467
468 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
469 ram_addr_t ram_addr;
470 hwaddr paddr;
471
472 /* Hope we are lucky for AO MCE */
473 ram_addr = qemu_ram_addr_from_host(addr);
474 if (ram_addr == RAM_ADDR_INVALID ||
475 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
476 addr, &paddr)) {
477 fprintf(stderr, "Hardware memory error for memory used by "
478 "QEMU itself instead of guest system!: %p\n", addr);
479 return 0;
480 }
481 kvm_hwpoison_page_add(ram_addr);
482 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
483 } else {
484 if (code == BUS_MCEERR_AO) {
485 return 0;
486 } else if (code == BUS_MCEERR_AR) {
487 hardware_memory_error();
488 } else {
489 return 1;
490 }
491 }
492 return 0;
493 }
494
495 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
496 {
497 CPUX86State *env = &cpu->env;
498
499 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
500 unsigned int bank, bank_num = env->mcg_cap & 0xff;
501 struct kvm_x86_mce mce;
502
503 env->exception_injected = -1;
504
505 /*
506 * There must be at least one bank in use if an MCE is pending.
507 * Find it and use its values for the event injection.
508 */
509 for (bank = 0; bank < bank_num; bank++) {
510 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
511 break;
512 }
513 }
514 assert(bank < bank_num);
515
516 mce.bank = bank;
517 mce.status = env->mce_banks[bank * 4 + 1];
518 mce.mcg_status = env->mcg_status;
519 mce.addr = env->mce_banks[bank * 4 + 2];
520 mce.misc = env->mce_banks[bank * 4 + 3];
521
522 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
523 }
524 return 0;
525 }
526
527 static void cpu_update_state(void *opaque, int running, RunState state)
528 {
529 CPUX86State *env = opaque;
530
531 if (running) {
532 env->tsc_valid = false;
533 }
534 }
535
536 unsigned long kvm_arch_vcpu_id(CPUState *cs)
537 {
538 X86CPU *cpu = X86_CPU(cs);
539 return cpu->apic_id;
540 }
541
542 #ifndef KVM_CPUID_SIGNATURE_NEXT
543 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
544 #endif
545
546 static bool hyperv_hypercall_available(X86CPU *cpu)
547 {
548 return cpu->hyperv_vapic ||
549 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
550 }
551
552 static bool hyperv_enabled(X86CPU *cpu)
553 {
554 CPUState *cs = CPU(cpu);
555 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
556 (hyperv_hypercall_available(cpu) ||
557 cpu->hyperv_time ||
558 cpu->hyperv_relaxed_timing ||
559 cpu->hyperv_crash ||
560 cpu->hyperv_reset ||
561 cpu->hyperv_vpindex ||
562 cpu->hyperv_runtime ||
563 cpu->hyperv_synic ||
564 cpu->hyperv_stimer);
565 }
566
567 static int kvm_arch_set_tsc_khz(CPUState *cs)
568 {
569 X86CPU *cpu = X86_CPU(cs);
570 CPUX86State *env = &cpu->env;
571 int r;
572
573 if (!env->tsc_khz) {
574 return 0;
575 }
576
577 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
578 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
579 -ENOTSUP;
580 if (r < 0) {
581 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
582 * TSC frequency doesn't match the one we want.
583 */
584 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
585 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
586 -ENOTSUP;
587 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
588 error_report("warning: TSC frequency mismatch between "
589 "VM (%" PRId64 " kHz) and host (%d kHz), "
590 "and TSC scaling unavailable",
591 env->tsc_khz, cur_freq);
592 return r;
593 }
594 }
595
596 return 0;
597 }
598
599 static int hyperv_handle_properties(CPUState *cs)
600 {
601 X86CPU *cpu = X86_CPU(cs);
602 CPUX86State *env = &cpu->env;
603
604 if (cpu->hyperv_time &&
605 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
606 cpu->hyperv_time = false;
607 }
608
609 if (cpu->hyperv_relaxed_timing) {
610 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
611 }
612 if (cpu->hyperv_vapic) {
613 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
614 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
615 }
616 if (cpu->hyperv_time) {
617 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
618 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
619 env->features[FEAT_HYPERV_EAX] |= 0x200;
620 }
621 if (cpu->hyperv_crash && has_msr_hv_crash) {
622 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
623 }
624 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
625 if (cpu->hyperv_reset && has_msr_hv_reset) {
626 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
627 }
628 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
629 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
630 }
631 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
632 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
633 }
634 if (cpu->hyperv_synic) {
635 int sint;
636
637 if (!has_msr_hv_synic ||
638 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
639 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
640 return -ENOSYS;
641 }
642
643 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
644 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
645 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
646 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
647 }
648 }
649 if (cpu->hyperv_stimer) {
650 if (!has_msr_hv_stimer) {
651 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
652 return -ENOSYS;
653 }
654 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
655 }
656 return 0;
657 }
658
659 static Error *invtsc_mig_blocker;
660
661 #define KVM_MAX_CPUID_ENTRIES 100
662
663 int kvm_arch_init_vcpu(CPUState *cs)
664 {
665 struct {
666 struct kvm_cpuid2 cpuid;
667 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
668 } QEMU_PACKED cpuid_data;
669 X86CPU *cpu = X86_CPU(cs);
670 CPUX86State *env = &cpu->env;
671 uint32_t limit, i, j, cpuid_i;
672 uint32_t unused;
673 struct kvm_cpuid_entry2 *c;
674 uint32_t signature[3];
675 int kvm_base = KVM_CPUID_SIGNATURE;
676 int r;
677
678 memset(&cpuid_data, 0, sizeof(cpuid_data));
679
680 cpuid_i = 0;
681
682 /* Paravirtualization CPUIDs */
683 if (hyperv_enabled(cpu)) {
684 c = &cpuid_data.entries[cpuid_i++];
685 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
686 if (!cpu->hyperv_vendor_id) {
687 memcpy(signature, "Microsoft Hv", 12);
688 } else {
689 size_t len = strlen(cpu->hyperv_vendor_id);
690
691 if (len > 12) {
692 error_report("hv-vendor-id truncated to 12 characters");
693 len = 12;
694 }
695 memset(signature, 0, 12);
696 memcpy(signature, cpu->hyperv_vendor_id, len);
697 }
698 c->eax = HYPERV_CPUID_MIN;
699 c->ebx = signature[0];
700 c->ecx = signature[1];
701 c->edx = signature[2];
702
703 c = &cpuid_data.entries[cpuid_i++];
704 c->function = HYPERV_CPUID_INTERFACE;
705 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
706 c->eax = signature[0];
707 c->ebx = 0;
708 c->ecx = 0;
709 c->edx = 0;
710
711 c = &cpuid_data.entries[cpuid_i++];
712 c->function = HYPERV_CPUID_VERSION;
713 c->eax = 0x00001bbc;
714 c->ebx = 0x00060001;
715
716 c = &cpuid_data.entries[cpuid_i++];
717 c->function = HYPERV_CPUID_FEATURES;
718 r = hyperv_handle_properties(cs);
719 if (r) {
720 return r;
721 }
722 c->eax = env->features[FEAT_HYPERV_EAX];
723 c->ebx = env->features[FEAT_HYPERV_EBX];
724 c->edx = env->features[FEAT_HYPERV_EDX];
725
726 c = &cpuid_data.entries[cpuid_i++];
727 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
728 if (cpu->hyperv_relaxed_timing) {
729 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
730 }
731 if (cpu->hyperv_vapic) {
732 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
733 }
734 c->ebx = cpu->hyperv_spinlock_attempts;
735
736 c = &cpuid_data.entries[cpuid_i++];
737 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
738 c->eax = 0x40;
739 c->ebx = 0x40;
740
741 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
742 has_msr_hv_hypercall = true;
743 }
744
745 if (cpu->expose_kvm) {
746 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
747 c = &cpuid_data.entries[cpuid_i++];
748 c->function = KVM_CPUID_SIGNATURE | kvm_base;
749 c->eax = KVM_CPUID_FEATURES | kvm_base;
750 c->ebx = signature[0];
751 c->ecx = signature[1];
752 c->edx = signature[2];
753
754 c = &cpuid_data.entries[cpuid_i++];
755 c->function = KVM_CPUID_FEATURES | kvm_base;
756 c->eax = env->features[FEAT_KVM];
757
758 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
759
760 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
761
762 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
763 }
764
765 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
766
767 for (i = 0; i <= limit; i++) {
768 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
769 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
770 abort();
771 }
772 c = &cpuid_data.entries[cpuid_i++];
773
774 switch (i) {
775 case 2: {
776 /* Keep reading function 2 till all the input is received */
777 int times;
778
779 c->function = i;
780 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
781 KVM_CPUID_FLAG_STATE_READ_NEXT;
782 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
783 times = c->eax & 0xff;
784
785 for (j = 1; j < times; ++j) {
786 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
787 fprintf(stderr, "cpuid_data is full, no space for "
788 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
789 abort();
790 }
791 c = &cpuid_data.entries[cpuid_i++];
792 c->function = i;
793 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
794 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
795 }
796 break;
797 }
798 case 4:
799 case 0xb:
800 case 0xd:
801 for (j = 0; ; j++) {
802 if (i == 0xd && j == 64) {
803 break;
804 }
805 c->function = i;
806 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
807 c->index = j;
808 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
809
810 if (i == 4 && c->eax == 0) {
811 break;
812 }
813 if (i == 0xb && !(c->ecx & 0xff00)) {
814 break;
815 }
816 if (i == 0xd && c->eax == 0) {
817 continue;
818 }
819 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
820 fprintf(stderr, "cpuid_data is full, no space for "
821 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
822 abort();
823 }
824 c = &cpuid_data.entries[cpuid_i++];
825 }
826 break;
827 default:
828 c->function = i;
829 c->flags = 0;
830 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
831 break;
832 }
833 }
834
835 if (limit >= 0x0a) {
836 uint32_t ver;
837
838 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
839 if ((ver & 0xff) > 0) {
840 has_msr_architectural_pmu = true;
841 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
842
843 /* Shouldn't be more than 32, since that's the number of bits
844 * available in EBX to tell us _which_ counters are available.
845 * Play it safe.
846 */
847 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
848 num_architectural_pmu_counters = MAX_GP_COUNTERS;
849 }
850 }
851 }
852
853 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
854
855 for (i = 0x80000000; i <= limit; i++) {
856 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
857 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
858 abort();
859 }
860 c = &cpuid_data.entries[cpuid_i++];
861
862 c->function = i;
863 c->flags = 0;
864 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
865 }
866
867 /* Call Centaur's CPUID instructions they are supported. */
868 if (env->cpuid_xlevel2 > 0) {
869 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
870
871 for (i = 0xC0000000; i <= limit; i++) {
872 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
873 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
874 abort();
875 }
876 c = &cpuid_data.entries[cpuid_i++];
877
878 c->function = i;
879 c->flags = 0;
880 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
881 }
882 }
883
884 cpuid_data.cpuid.nent = cpuid_i;
885
886 if (((env->cpuid_version >> 8)&0xF) >= 6
887 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
888 (CPUID_MCE | CPUID_MCA)
889 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
890 uint64_t mcg_cap, unsupported_caps;
891 int banks;
892 int ret;
893
894 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
895 if (ret < 0) {
896 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
897 return ret;
898 }
899
900 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
901 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
902 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
903 return -ENOTSUP;
904 }
905
906 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
907 if (unsupported_caps) {
908 if (unsupported_caps & MCG_LMCE_P) {
909 error_report("kvm: LMCE not supported");
910 return -ENOTSUP;
911 }
912 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
913 unsupported_caps);
914 }
915
916 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
917 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
918 if (ret < 0) {
919 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
920 return ret;
921 }
922 }
923
924 qemu_add_vm_change_state_handler(cpu_update_state, env);
925
926 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
927 if (c) {
928 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
929 !!(c->ecx & CPUID_EXT_SMX);
930 }
931
932 if (env->mcg_cap & MCG_LMCE_P) {
933 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
934 }
935
936 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
937 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
938 /* for migration */
939 error_setg(&invtsc_mig_blocker,
940 "State blocked by non-migratable CPU device"
941 " (invtsc flag)");
942 migrate_add_blocker(invtsc_mig_blocker);
943 /* for savevm */
944 vmstate_x86_cpu.unmigratable = 1;
945 }
946
947 cpuid_data.cpuid.padding = 0;
948 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
949 if (r) {
950 return r;
951 }
952
953 r = kvm_arch_set_tsc_khz(cs);
954 if (r < 0) {
955 return r;
956 }
957
958 /* vcpu's TSC frequency is either specified by user, or following
959 * the value used by KVM if the former is not present. In the
960 * latter case, we query it from KVM and record in env->tsc_khz,
961 * so that vcpu's TSC frequency can be migrated later via this field.
962 */
963 if (!env->tsc_khz) {
964 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
965 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
966 -ENOTSUP;
967 if (r > 0) {
968 env->tsc_khz = r;
969 }
970 }
971
972 if (has_xsave) {
973 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
974 }
975 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
976
977 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
978 has_msr_tsc_aux = false;
979 }
980
981 return 0;
982 }
983
984 void kvm_arch_reset_vcpu(X86CPU *cpu)
985 {
986 CPUX86State *env = &cpu->env;
987
988 env->exception_injected = -1;
989 env->interrupt_injected = -1;
990 env->xcr0 = 1;
991 if (kvm_irqchip_in_kernel()) {
992 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
993 KVM_MP_STATE_UNINITIALIZED;
994 } else {
995 env->mp_state = KVM_MP_STATE_RUNNABLE;
996 }
997 }
998
999 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1000 {
1001 CPUX86State *env = &cpu->env;
1002
1003 /* APs get directly into wait-for-SIPI state. */
1004 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1005 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1006 }
1007 }
1008
1009 static int kvm_get_supported_msrs(KVMState *s)
1010 {
1011 static int kvm_supported_msrs;
1012 int ret = 0;
1013
1014 /* first time */
1015 if (kvm_supported_msrs == 0) {
1016 struct kvm_msr_list msr_list, *kvm_msr_list;
1017
1018 kvm_supported_msrs = -1;
1019
1020 /* Obtain MSR list from KVM. These are the MSRs that we must
1021 * save/restore */
1022 msr_list.nmsrs = 0;
1023 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1024 if (ret < 0 && ret != -E2BIG) {
1025 return ret;
1026 }
1027 /* Old kernel modules had a bug and could write beyond the provided
1028 memory. Allocate at least a safe amount of 1K. */
1029 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1030 msr_list.nmsrs *
1031 sizeof(msr_list.indices[0])));
1032
1033 kvm_msr_list->nmsrs = msr_list.nmsrs;
1034 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1035 if (ret >= 0) {
1036 int i;
1037
1038 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1039 if (kvm_msr_list->indices[i] == MSR_STAR) {
1040 has_msr_star = true;
1041 continue;
1042 }
1043 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1044 has_msr_hsave_pa = true;
1045 continue;
1046 }
1047 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1048 has_msr_tsc_aux = true;
1049 continue;
1050 }
1051 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1052 has_msr_tsc_adjust = true;
1053 continue;
1054 }
1055 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1056 has_msr_tsc_deadline = true;
1057 continue;
1058 }
1059 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1060 has_msr_smbase = true;
1061 continue;
1062 }
1063 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1064 has_msr_misc_enable = true;
1065 continue;
1066 }
1067 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1068 has_msr_bndcfgs = true;
1069 continue;
1070 }
1071 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1072 has_msr_xss = true;
1073 continue;
1074 }
1075 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1076 has_msr_hv_crash = true;
1077 continue;
1078 }
1079 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1080 has_msr_hv_reset = true;
1081 continue;
1082 }
1083 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1084 has_msr_hv_vpindex = true;
1085 continue;
1086 }
1087 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1088 has_msr_hv_runtime = true;
1089 continue;
1090 }
1091 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1092 has_msr_hv_synic = true;
1093 continue;
1094 }
1095 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1096 has_msr_hv_stimer = true;
1097 continue;
1098 }
1099 }
1100 }
1101
1102 g_free(kvm_msr_list);
1103 }
1104
1105 return ret;
1106 }
1107
1108 static Notifier smram_machine_done;
1109 static KVMMemoryListener smram_listener;
1110 static AddressSpace smram_address_space;
1111 static MemoryRegion smram_as_root;
1112 static MemoryRegion smram_as_mem;
1113
1114 static void register_smram_listener(Notifier *n, void *unused)
1115 {
1116 MemoryRegion *smram =
1117 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1118
1119 /* Outer container... */
1120 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1121 memory_region_set_enabled(&smram_as_root, true);
1122
1123 /* ... with two regions inside: normal system memory with low
1124 * priority, and...
1125 */
1126 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1127 get_system_memory(), 0, ~0ull);
1128 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1129 memory_region_set_enabled(&smram_as_mem, true);
1130
1131 if (smram) {
1132 /* ... SMRAM with higher priority */
1133 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1134 memory_region_set_enabled(smram, true);
1135 }
1136
1137 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1138 kvm_memory_listener_register(kvm_state, &smram_listener,
1139 &smram_address_space, 1);
1140 }
1141
1142 int kvm_arch_init(MachineState *ms, KVMState *s)
1143 {
1144 uint64_t identity_base = 0xfffbc000;
1145 uint64_t shadow_mem;
1146 int ret;
1147 struct utsname utsname;
1148
1149 #ifdef KVM_CAP_XSAVE
1150 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1151 #endif
1152
1153 #ifdef KVM_CAP_XCRS
1154 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1155 #endif
1156
1157 #ifdef KVM_CAP_PIT_STATE2
1158 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1159 #endif
1160
1161 ret = kvm_get_supported_msrs(s);
1162 if (ret < 0) {
1163 return ret;
1164 }
1165
1166 uname(&utsname);
1167 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1168
1169 /*
1170 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1171 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1172 * Since these must be part of guest physical memory, we need to allocate
1173 * them, both by setting their start addresses in the kernel and by
1174 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1175 *
1176 * Older KVM versions may not support setting the identity map base. In
1177 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1178 * size.
1179 */
1180 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1181 /* Allows up to 16M BIOSes. */
1182 identity_base = 0xfeffc000;
1183
1184 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1185 if (ret < 0) {
1186 return ret;
1187 }
1188 }
1189
1190 /* Set TSS base one page after EPT identity map. */
1191 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1192 if (ret < 0) {
1193 return ret;
1194 }
1195
1196 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1197 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1198 if (ret < 0) {
1199 fprintf(stderr, "e820_add_entry() table is full\n");
1200 return ret;
1201 }
1202 qemu_register_reset(kvm_unpoison_all, NULL);
1203
1204 shadow_mem = machine_kvm_shadow_mem(ms);
1205 if (shadow_mem != -1) {
1206 shadow_mem /= 4096;
1207 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1208 if (ret < 0) {
1209 return ret;
1210 }
1211 }
1212
1213 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1214 smram_machine_done.notify = register_smram_listener;
1215 qemu_add_machine_init_done_notifier(&smram_machine_done);
1216 }
1217 return 0;
1218 }
1219
1220 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1221 {
1222 lhs->selector = rhs->selector;
1223 lhs->base = rhs->base;
1224 lhs->limit = rhs->limit;
1225 lhs->type = 3;
1226 lhs->present = 1;
1227 lhs->dpl = 3;
1228 lhs->db = 0;
1229 lhs->s = 1;
1230 lhs->l = 0;
1231 lhs->g = 0;
1232 lhs->avl = 0;
1233 lhs->unusable = 0;
1234 }
1235
1236 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1237 {
1238 unsigned flags = rhs->flags;
1239 lhs->selector = rhs->selector;
1240 lhs->base = rhs->base;
1241 lhs->limit = rhs->limit;
1242 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1243 lhs->present = (flags & DESC_P_MASK) != 0;
1244 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1245 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1246 lhs->s = (flags & DESC_S_MASK) != 0;
1247 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1248 lhs->g = (flags & DESC_G_MASK) != 0;
1249 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1250 lhs->unusable = !lhs->present;
1251 lhs->padding = 0;
1252 }
1253
1254 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1255 {
1256 lhs->selector = rhs->selector;
1257 lhs->base = rhs->base;
1258 lhs->limit = rhs->limit;
1259 if (rhs->unusable) {
1260 lhs->flags = 0;
1261 } else {
1262 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1263 (rhs->present * DESC_P_MASK) |
1264 (rhs->dpl << DESC_DPL_SHIFT) |
1265 (rhs->db << DESC_B_SHIFT) |
1266 (rhs->s * DESC_S_MASK) |
1267 (rhs->l << DESC_L_SHIFT) |
1268 (rhs->g * DESC_G_MASK) |
1269 (rhs->avl * DESC_AVL_MASK);
1270 }
1271 }
1272
1273 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1274 {
1275 if (set) {
1276 *kvm_reg = *qemu_reg;
1277 } else {
1278 *qemu_reg = *kvm_reg;
1279 }
1280 }
1281
1282 static int kvm_getput_regs(X86CPU *cpu, int set)
1283 {
1284 CPUX86State *env = &cpu->env;
1285 struct kvm_regs regs;
1286 int ret = 0;
1287
1288 if (!set) {
1289 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1290 if (ret < 0) {
1291 return ret;
1292 }
1293 }
1294
1295 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1296 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1297 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1298 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1299 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1300 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1301 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1302 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1303 #ifdef TARGET_X86_64
1304 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1305 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1306 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1307 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1308 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1309 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1310 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1311 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1312 #endif
1313
1314 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1315 kvm_getput_reg(&regs.rip, &env->eip, set);
1316
1317 if (set) {
1318 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1319 }
1320
1321 return ret;
1322 }
1323
1324 static int kvm_put_fpu(X86CPU *cpu)
1325 {
1326 CPUX86State *env = &cpu->env;
1327 struct kvm_fpu fpu;
1328 int i;
1329
1330 memset(&fpu, 0, sizeof fpu);
1331 fpu.fsw = env->fpus & ~(7 << 11);
1332 fpu.fsw |= (env->fpstt & 7) << 11;
1333 fpu.fcw = env->fpuc;
1334 fpu.last_opcode = env->fpop;
1335 fpu.last_ip = env->fpip;
1336 fpu.last_dp = env->fpdp;
1337 for (i = 0; i < 8; ++i) {
1338 fpu.ftwx |= (!env->fptags[i]) << i;
1339 }
1340 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1341 for (i = 0; i < CPU_NB_REGS; i++) {
1342 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1343 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1344 }
1345 fpu.mxcsr = env->mxcsr;
1346
1347 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1348 }
1349
1350 #define XSAVE_FCW_FSW 0
1351 #define XSAVE_FTW_FOP 1
1352 #define XSAVE_CWD_RIP 2
1353 #define XSAVE_CWD_RDP 4
1354 #define XSAVE_MXCSR 6
1355 #define XSAVE_ST_SPACE 8
1356 #define XSAVE_XMM_SPACE 40
1357 #define XSAVE_XSTATE_BV 128
1358 #define XSAVE_YMMH_SPACE 144
1359 #define XSAVE_BNDREGS 240
1360 #define XSAVE_BNDCSR 256
1361 #define XSAVE_OPMASK 272
1362 #define XSAVE_ZMM_Hi256 288
1363 #define XSAVE_Hi16_ZMM 416
1364 #define XSAVE_PKRU 672
1365
1366 #define XSAVE_BYTE_OFFSET(word_offset) \
1367 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1368
1369 #define ASSERT_OFFSET(word_offset, field) \
1370 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1371 offsetof(X86XSaveArea, field))
1372
1373 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1374 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1375 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1376 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1377 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1378 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1379 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1380 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1381 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1382 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1383 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1384 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1385 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1386 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1387 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1388
1389 static int kvm_put_xsave(X86CPU *cpu)
1390 {
1391 CPUX86State *env = &cpu->env;
1392 X86XSaveArea *xsave = env->kvm_xsave_buf;
1393 uint16_t cwd, swd, twd;
1394 int i;
1395
1396 if (!has_xsave) {
1397 return kvm_put_fpu(cpu);
1398 }
1399
1400 memset(xsave, 0, sizeof(struct kvm_xsave));
1401 twd = 0;
1402 swd = env->fpus & ~(7 << 11);
1403 swd |= (env->fpstt & 7) << 11;
1404 cwd = env->fpuc;
1405 for (i = 0; i < 8; ++i) {
1406 twd |= (!env->fptags[i]) << i;
1407 }
1408 xsave->legacy.fcw = cwd;
1409 xsave->legacy.fsw = swd;
1410 xsave->legacy.ftw = twd;
1411 xsave->legacy.fpop = env->fpop;
1412 xsave->legacy.fpip = env->fpip;
1413 xsave->legacy.fpdp = env->fpdp;
1414 memcpy(&xsave->legacy.fpregs, env->fpregs,
1415 sizeof env->fpregs);
1416 xsave->legacy.mxcsr = env->mxcsr;
1417 xsave->header.xstate_bv = env->xstate_bv;
1418 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1419 sizeof env->bnd_regs);
1420 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1421 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1422 sizeof env->opmask_regs);
1423
1424 for (i = 0; i < CPU_NB_REGS; i++) {
1425 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1426 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1427 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1428 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1429 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1430 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1431 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1432 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1433 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1434 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1435 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1436 }
1437
1438 #ifdef TARGET_X86_64
1439 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1440 16 * sizeof env->xmm_regs[16]);
1441 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1442 #endif
1443 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1444 }
1445
1446 static int kvm_put_xcrs(X86CPU *cpu)
1447 {
1448 CPUX86State *env = &cpu->env;
1449 struct kvm_xcrs xcrs = {};
1450
1451 if (!has_xcrs) {
1452 return 0;
1453 }
1454
1455 xcrs.nr_xcrs = 1;
1456 xcrs.flags = 0;
1457 xcrs.xcrs[0].xcr = 0;
1458 xcrs.xcrs[0].value = env->xcr0;
1459 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1460 }
1461
1462 static int kvm_put_sregs(X86CPU *cpu)
1463 {
1464 CPUX86State *env = &cpu->env;
1465 struct kvm_sregs sregs;
1466
1467 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1468 if (env->interrupt_injected >= 0) {
1469 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1470 (uint64_t)1 << (env->interrupt_injected % 64);
1471 }
1472
1473 if ((env->eflags & VM_MASK)) {
1474 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1475 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1476 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1477 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1478 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1479 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1480 } else {
1481 set_seg(&sregs.cs, &env->segs[R_CS]);
1482 set_seg(&sregs.ds, &env->segs[R_DS]);
1483 set_seg(&sregs.es, &env->segs[R_ES]);
1484 set_seg(&sregs.fs, &env->segs[R_FS]);
1485 set_seg(&sregs.gs, &env->segs[R_GS]);
1486 set_seg(&sregs.ss, &env->segs[R_SS]);
1487 }
1488
1489 set_seg(&sregs.tr, &env->tr);
1490 set_seg(&sregs.ldt, &env->ldt);
1491
1492 sregs.idt.limit = env->idt.limit;
1493 sregs.idt.base = env->idt.base;
1494 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1495 sregs.gdt.limit = env->gdt.limit;
1496 sregs.gdt.base = env->gdt.base;
1497 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1498
1499 sregs.cr0 = env->cr[0];
1500 sregs.cr2 = env->cr[2];
1501 sregs.cr3 = env->cr[3];
1502 sregs.cr4 = env->cr[4];
1503
1504 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1505 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1506
1507 sregs.efer = env->efer;
1508
1509 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1510 }
1511
1512 static void kvm_msr_buf_reset(X86CPU *cpu)
1513 {
1514 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1515 }
1516
1517 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1518 {
1519 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1520 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1521 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1522
1523 assert((void *)(entry + 1) <= limit);
1524
1525 entry->index = index;
1526 entry->reserved = 0;
1527 entry->data = value;
1528 msrs->nmsrs++;
1529 }
1530
1531 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1532 {
1533 kvm_msr_buf_reset(cpu);
1534 kvm_msr_entry_add(cpu, index, value);
1535
1536 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1537 }
1538
1539 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1540 {
1541 int ret;
1542
1543 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1544 assert(ret == 1);
1545 }
1546
1547 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1548 {
1549 CPUX86State *env = &cpu->env;
1550 int ret;
1551
1552 if (!has_msr_tsc_deadline) {
1553 return 0;
1554 }
1555
1556 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1557 if (ret < 0) {
1558 return ret;
1559 }
1560
1561 assert(ret == 1);
1562 return 0;
1563 }
1564
1565 /*
1566 * Provide a separate write service for the feature control MSR in order to
1567 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1568 * before writing any other state because forcibly leaving nested mode
1569 * invalidates the VCPU state.
1570 */
1571 static int kvm_put_msr_feature_control(X86CPU *cpu)
1572 {
1573 int ret;
1574
1575 if (!has_msr_feature_control) {
1576 return 0;
1577 }
1578
1579 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1580 cpu->env.msr_ia32_feature_control);
1581 if (ret < 0) {
1582 return ret;
1583 }
1584
1585 assert(ret == 1);
1586 return 0;
1587 }
1588
1589 static int kvm_put_msrs(X86CPU *cpu, int level)
1590 {
1591 CPUX86State *env = &cpu->env;
1592 int i;
1593 int ret;
1594
1595 kvm_msr_buf_reset(cpu);
1596
1597 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1598 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1599 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1600 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1601 if (has_msr_star) {
1602 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1603 }
1604 if (has_msr_hsave_pa) {
1605 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1606 }
1607 if (has_msr_tsc_aux) {
1608 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1609 }
1610 if (has_msr_tsc_adjust) {
1611 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1612 }
1613 if (has_msr_misc_enable) {
1614 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1615 env->msr_ia32_misc_enable);
1616 }
1617 if (has_msr_smbase) {
1618 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1619 }
1620 if (has_msr_bndcfgs) {
1621 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1622 }
1623 if (has_msr_xss) {
1624 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1625 }
1626 #ifdef TARGET_X86_64
1627 if (lm_capable_kernel) {
1628 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1629 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1630 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1631 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1632 }
1633 #endif
1634 /*
1635 * The following MSRs have side effects on the guest or are too heavy
1636 * for normal writeback. Limit them to reset or full state updates.
1637 */
1638 if (level >= KVM_PUT_RESET_STATE) {
1639 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1640 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1641 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1642 if (has_msr_async_pf_en) {
1643 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1644 }
1645 if (has_msr_pv_eoi_en) {
1646 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1647 }
1648 if (has_msr_kvm_steal_time) {
1649 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1650 }
1651 if (has_msr_architectural_pmu) {
1652 /* Stop the counter. */
1653 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1654 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1655
1656 /* Set the counter values. */
1657 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1659 env->msr_fixed_counters[i]);
1660 }
1661 for (i = 0; i < num_architectural_pmu_counters; i++) {
1662 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1663 env->msr_gp_counters[i]);
1664 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1665 env->msr_gp_evtsel[i]);
1666 }
1667 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1668 env->msr_global_status);
1669 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1670 env->msr_global_ovf_ctrl);
1671
1672 /* Now start the PMU. */
1673 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1674 env->msr_fixed_ctr_ctrl);
1675 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1676 env->msr_global_ctrl);
1677 }
1678 if (has_msr_hv_hypercall) {
1679 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1680 env->msr_hv_guest_os_id);
1681 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1682 env->msr_hv_hypercall);
1683 }
1684 if (cpu->hyperv_vapic) {
1685 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1686 env->msr_hv_vapic);
1687 }
1688 if (cpu->hyperv_time) {
1689 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1690 }
1691 if (has_msr_hv_crash) {
1692 int j;
1693
1694 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1695 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1696 env->msr_hv_crash_params[j]);
1697
1698 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1699 HV_X64_MSR_CRASH_CTL_NOTIFY);
1700 }
1701 if (has_msr_hv_runtime) {
1702 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1703 }
1704 if (cpu->hyperv_synic) {
1705 int j;
1706
1707 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1708 env->msr_hv_synic_control);
1709 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1710 env->msr_hv_synic_version);
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1712 env->msr_hv_synic_evt_page);
1713 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1714 env->msr_hv_synic_msg_page);
1715
1716 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1717 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1718 env->msr_hv_synic_sint[j]);
1719 }
1720 }
1721 if (has_msr_hv_stimer) {
1722 int j;
1723
1724 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1725 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1726 env->msr_hv_stimer_config[j]);
1727 }
1728
1729 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1730 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1731 env->msr_hv_stimer_count[j]);
1732 }
1733 }
1734 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1735 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1736
1737 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1738 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1739 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1740 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1741 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1742 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1743 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1744 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1745 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1746 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1747 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1748 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1749 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1750 /* The CPU GPs if we write to a bit above the physical limit of
1751 * the host CPU (and KVM emulates that)
1752 */
1753 uint64_t mask = env->mtrr_var[i].mask;
1754 mask &= phys_mask;
1755
1756 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1757 env->mtrr_var[i].base);
1758 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1759 }
1760 }
1761
1762 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1763 * kvm_put_msr_feature_control. */
1764 }
1765 if (env->mcg_cap) {
1766 int i;
1767
1768 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1769 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1770 if (has_msr_mcg_ext_ctl) {
1771 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1772 }
1773 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1774 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1775 }
1776 }
1777
1778 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1779 if (ret < 0) {
1780 return ret;
1781 }
1782
1783 assert(ret == cpu->kvm_msr_buf->nmsrs);
1784 return 0;
1785 }
1786
1787
1788 static int kvm_get_fpu(X86CPU *cpu)
1789 {
1790 CPUX86State *env = &cpu->env;
1791 struct kvm_fpu fpu;
1792 int i, ret;
1793
1794 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1795 if (ret < 0) {
1796 return ret;
1797 }
1798
1799 env->fpstt = (fpu.fsw >> 11) & 7;
1800 env->fpus = fpu.fsw;
1801 env->fpuc = fpu.fcw;
1802 env->fpop = fpu.last_opcode;
1803 env->fpip = fpu.last_ip;
1804 env->fpdp = fpu.last_dp;
1805 for (i = 0; i < 8; ++i) {
1806 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1807 }
1808 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1809 for (i = 0; i < CPU_NB_REGS; i++) {
1810 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1811 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1812 }
1813 env->mxcsr = fpu.mxcsr;
1814
1815 return 0;
1816 }
1817
1818 static int kvm_get_xsave(X86CPU *cpu)
1819 {
1820 CPUX86State *env = &cpu->env;
1821 X86XSaveArea *xsave = env->kvm_xsave_buf;
1822 int ret, i;
1823 uint16_t cwd, swd, twd;
1824
1825 if (!has_xsave) {
1826 return kvm_get_fpu(cpu);
1827 }
1828
1829 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1830 if (ret < 0) {
1831 return ret;
1832 }
1833
1834 cwd = xsave->legacy.fcw;
1835 swd = xsave->legacy.fsw;
1836 twd = xsave->legacy.ftw;
1837 env->fpop = xsave->legacy.fpop;
1838 env->fpstt = (swd >> 11) & 7;
1839 env->fpus = swd;
1840 env->fpuc = cwd;
1841 for (i = 0; i < 8; ++i) {
1842 env->fptags[i] = !((twd >> i) & 1);
1843 }
1844 env->fpip = xsave->legacy.fpip;
1845 env->fpdp = xsave->legacy.fpdp;
1846 env->mxcsr = xsave->legacy.mxcsr;
1847 memcpy(env->fpregs, &xsave->legacy.fpregs,
1848 sizeof env->fpregs);
1849 env->xstate_bv = xsave->header.xstate_bv;
1850 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1851 sizeof env->bnd_regs);
1852 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1853 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1854 sizeof env->opmask_regs);
1855
1856 for (i = 0; i < CPU_NB_REGS; i++) {
1857 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1858 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1859 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1860 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1861 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1862 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1863 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1864 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1865 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1866 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1867 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1868 }
1869
1870 #ifdef TARGET_X86_64
1871 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1872 16 * sizeof env->xmm_regs[16]);
1873 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1874 #endif
1875 return 0;
1876 }
1877
1878 static int kvm_get_xcrs(X86CPU *cpu)
1879 {
1880 CPUX86State *env = &cpu->env;
1881 int i, ret;
1882 struct kvm_xcrs xcrs;
1883
1884 if (!has_xcrs) {
1885 return 0;
1886 }
1887
1888 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1889 if (ret < 0) {
1890 return ret;
1891 }
1892
1893 for (i = 0; i < xcrs.nr_xcrs; i++) {
1894 /* Only support xcr0 now */
1895 if (xcrs.xcrs[i].xcr == 0) {
1896 env->xcr0 = xcrs.xcrs[i].value;
1897 break;
1898 }
1899 }
1900 return 0;
1901 }
1902
1903 static int kvm_get_sregs(X86CPU *cpu)
1904 {
1905 CPUX86State *env = &cpu->env;
1906 struct kvm_sregs sregs;
1907 uint32_t hflags;
1908 int bit, i, ret;
1909
1910 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1911 if (ret < 0) {
1912 return ret;
1913 }
1914
1915 /* There can only be one pending IRQ set in the bitmap at a time, so try
1916 to find it and save its number instead (-1 for none). */
1917 env->interrupt_injected = -1;
1918 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1919 if (sregs.interrupt_bitmap[i]) {
1920 bit = ctz64(sregs.interrupt_bitmap[i]);
1921 env->interrupt_injected = i * 64 + bit;
1922 break;
1923 }
1924 }
1925
1926 get_seg(&env->segs[R_CS], &sregs.cs);
1927 get_seg(&env->segs[R_DS], &sregs.ds);
1928 get_seg(&env->segs[R_ES], &sregs.es);
1929 get_seg(&env->segs[R_FS], &sregs.fs);
1930 get_seg(&env->segs[R_GS], &sregs.gs);
1931 get_seg(&env->segs[R_SS], &sregs.ss);
1932
1933 get_seg(&env->tr, &sregs.tr);
1934 get_seg(&env->ldt, &sregs.ldt);
1935
1936 env->idt.limit = sregs.idt.limit;
1937 env->idt.base = sregs.idt.base;
1938 env->gdt.limit = sregs.gdt.limit;
1939 env->gdt.base = sregs.gdt.base;
1940
1941 env->cr[0] = sregs.cr0;
1942 env->cr[2] = sregs.cr2;
1943 env->cr[3] = sregs.cr3;
1944 env->cr[4] = sregs.cr4;
1945
1946 env->efer = sregs.efer;
1947
1948 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1949
1950 #define HFLAG_COPY_MASK \
1951 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1952 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1953 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1954 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1955
1956 hflags = env->hflags & HFLAG_COPY_MASK;
1957 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1958 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1959 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1960 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1961 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1962
1963 if (env->cr[4] & CR4_OSFXSR_MASK) {
1964 hflags |= HF_OSFXSR_MASK;
1965 }
1966
1967 if (env->efer & MSR_EFER_LMA) {
1968 hflags |= HF_LMA_MASK;
1969 }
1970
1971 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1972 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1973 } else {
1974 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1975 (DESC_B_SHIFT - HF_CS32_SHIFT);
1976 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1977 (DESC_B_SHIFT - HF_SS32_SHIFT);
1978 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1979 !(hflags & HF_CS32_MASK)) {
1980 hflags |= HF_ADDSEG_MASK;
1981 } else {
1982 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1983 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1984 }
1985 }
1986 env->hflags = hflags;
1987
1988 return 0;
1989 }
1990
1991 static int kvm_get_msrs(X86CPU *cpu)
1992 {
1993 CPUX86State *env = &cpu->env;
1994 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1995 int ret, i;
1996 uint64_t mtrr_top_bits;
1997
1998 kvm_msr_buf_reset(cpu);
1999
2000 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2001 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2002 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2003 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2004 if (has_msr_star) {
2005 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2006 }
2007 if (has_msr_hsave_pa) {
2008 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2009 }
2010 if (has_msr_tsc_aux) {
2011 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2012 }
2013 if (has_msr_tsc_adjust) {
2014 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2015 }
2016 if (has_msr_tsc_deadline) {
2017 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2018 }
2019 if (has_msr_misc_enable) {
2020 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2021 }
2022 if (has_msr_smbase) {
2023 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2024 }
2025 if (has_msr_feature_control) {
2026 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2027 }
2028 if (has_msr_bndcfgs) {
2029 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2030 }
2031 if (has_msr_xss) {
2032 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2033 }
2034
2035
2036 if (!env->tsc_valid) {
2037 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2038 env->tsc_valid = !runstate_is_running();
2039 }
2040
2041 #ifdef TARGET_X86_64
2042 if (lm_capable_kernel) {
2043 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2044 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2045 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2046 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2047 }
2048 #endif
2049 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2050 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2051 if (has_msr_async_pf_en) {
2052 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2053 }
2054 if (has_msr_pv_eoi_en) {
2055 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2056 }
2057 if (has_msr_kvm_steal_time) {
2058 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2059 }
2060 if (has_msr_architectural_pmu) {
2061 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2062 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2063 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2064 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2065 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2066 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2067 }
2068 for (i = 0; i < num_architectural_pmu_counters; i++) {
2069 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2070 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2071 }
2072 }
2073
2074 if (env->mcg_cap) {
2075 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2076 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2077 if (has_msr_mcg_ext_ctl) {
2078 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2079 }
2080 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2081 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2082 }
2083 }
2084
2085 if (has_msr_hv_hypercall) {
2086 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2087 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2088 }
2089 if (cpu->hyperv_vapic) {
2090 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2091 }
2092 if (cpu->hyperv_time) {
2093 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2094 }
2095 if (has_msr_hv_crash) {
2096 int j;
2097
2098 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2099 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2100 }
2101 }
2102 if (has_msr_hv_runtime) {
2103 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2104 }
2105 if (cpu->hyperv_synic) {
2106 uint32_t msr;
2107
2108 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2109 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2110 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2111 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2112 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2113 kvm_msr_entry_add(cpu, msr, 0);
2114 }
2115 }
2116 if (has_msr_hv_stimer) {
2117 uint32_t msr;
2118
2119 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2120 msr++) {
2121 kvm_msr_entry_add(cpu, msr, 0);
2122 }
2123 }
2124 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2125 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2126 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2127 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2128 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2129 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2130 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2131 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2132 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2133 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2134 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2135 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2136 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2137 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2138 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2139 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2140 }
2141 }
2142
2143 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2144 if (ret < 0) {
2145 return ret;
2146 }
2147
2148 assert(ret == cpu->kvm_msr_buf->nmsrs);
2149 /*
2150 * MTRR masks: Each mask consists of 5 parts
2151 * a 10..0: must be zero
2152 * b 11 : valid bit
2153 * c n-1.12: actual mask bits
2154 * d 51..n: reserved must be zero
2155 * e 63.52: reserved must be zero
2156 *
2157 * 'n' is the number of physical bits supported by the CPU and is
2158 * apparently always <= 52. We know our 'n' but don't know what
2159 * the destinations 'n' is; it might be smaller, in which case
2160 * it masks (c) on loading. It might be larger, in which case
2161 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2162 * we're migrating to.
2163 */
2164
2165 if (cpu->fill_mtrr_mask) {
2166 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2167 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2168 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2169 } else {
2170 mtrr_top_bits = 0;
2171 }
2172
2173 for (i = 0; i < ret; i++) {
2174 uint32_t index = msrs[i].index;
2175 switch (index) {
2176 case MSR_IA32_SYSENTER_CS:
2177 env->sysenter_cs = msrs[i].data;
2178 break;
2179 case MSR_IA32_SYSENTER_ESP:
2180 env->sysenter_esp = msrs[i].data;
2181 break;
2182 case MSR_IA32_SYSENTER_EIP:
2183 env->sysenter_eip = msrs[i].data;
2184 break;
2185 case MSR_PAT:
2186 env->pat = msrs[i].data;
2187 break;
2188 case MSR_STAR:
2189 env->star = msrs[i].data;
2190 break;
2191 #ifdef TARGET_X86_64
2192 case MSR_CSTAR:
2193 env->cstar = msrs[i].data;
2194 break;
2195 case MSR_KERNELGSBASE:
2196 env->kernelgsbase = msrs[i].data;
2197 break;
2198 case MSR_FMASK:
2199 env->fmask = msrs[i].data;
2200 break;
2201 case MSR_LSTAR:
2202 env->lstar = msrs[i].data;
2203 break;
2204 #endif
2205 case MSR_IA32_TSC:
2206 env->tsc = msrs[i].data;
2207 break;
2208 case MSR_TSC_AUX:
2209 env->tsc_aux = msrs[i].data;
2210 break;
2211 case MSR_TSC_ADJUST:
2212 env->tsc_adjust = msrs[i].data;
2213 break;
2214 case MSR_IA32_TSCDEADLINE:
2215 env->tsc_deadline = msrs[i].data;
2216 break;
2217 case MSR_VM_HSAVE_PA:
2218 env->vm_hsave = msrs[i].data;
2219 break;
2220 case MSR_KVM_SYSTEM_TIME:
2221 env->system_time_msr = msrs[i].data;
2222 break;
2223 case MSR_KVM_WALL_CLOCK:
2224 env->wall_clock_msr = msrs[i].data;
2225 break;
2226 case MSR_MCG_STATUS:
2227 env->mcg_status = msrs[i].data;
2228 break;
2229 case MSR_MCG_CTL:
2230 env->mcg_ctl = msrs[i].data;
2231 break;
2232 case MSR_MCG_EXT_CTL:
2233 env->mcg_ext_ctl = msrs[i].data;
2234 break;
2235 case MSR_IA32_MISC_ENABLE:
2236 env->msr_ia32_misc_enable = msrs[i].data;
2237 break;
2238 case MSR_IA32_SMBASE:
2239 env->smbase = msrs[i].data;
2240 break;
2241 case MSR_IA32_FEATURE_CONTROL:
2242 env->msr_ia32_feature_control = msrs[i].data;
2243 break;
2244 case MSR_IA32_BNDCFGS:
2245 env->msr_bndcfgs = msrs[i].data;
2246 break;
2247 case MSR_IA32_XSS:
2248 env->xss = msrs[i].data;
2249 break;
2250 default:
2251 if (msrs[i].index >= MSR_MC0_CTL &&
2252 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2253 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2254 }
2255 break;
2256 case MSR_KVM_ASYNC_PF_EN:
2257 env->async_pf_en_msr = msrs[i].data;
2258 break;
2259 case MSR_KVM_PV_EOI_EN:
2260 env->pv_eoi_en_msr = msrs[i].data;
2261 break;
2262 case MSR_KVM_STEAL_TIME:
2263 env->steal_time_msr = msrs[i].data;
2264 break;
2265 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2266 env->msr_fixed_ctr_ctrl = msrs[i].data;
2267 break;
2268 case MSR_CORE_PERF_GLOBAL_CTRL:
2269 env->msr_global_ctrl = msrs[i].data;
2270 break;
2271 case MSR_CORE_PERF_GLOBAL_STATUS:
2272 env->msr_global_status = msrs[i].data;
2273 break;
2274 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2275 env->msr_global_ovf_ctrl = msrs[i].data;
2276 break;
2277 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2278 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2279 break;
2280 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2281 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2282 break;
2283 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2284 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2285 break;
2286 case HV_X64_MSR_HYPERCALL:
2287 env->msr_hv_hypercall = msrs[i].data;
2288 break;
2289 case HV_X64_MSR_GUEST_OS_ID:
2290 env->msr_hv_guest_os_id = msrs[i].data;
2291 break;
2292 case HV_X64_MSR_APIC_ASSIST_PAGE:
2293 env->msr_hv_vapic = msrs[i].data;
2294 break;
2295 case HV_X64_MSR_REFERENCE_TSC:
2296 env->msr_hv_tsc = msrs[i].data;
2297 break;
2298 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2299 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2300 break;
2301 case HV_X64_MSR_VP_RUNTIME:
2302 env->msr_hv_runtime = msrs[i].data;
2303 break;
2304 case HV_X64_MSR_SCONTROL:
2305 env->msr_hv_synic_control = msrs[i].data;
2306 break;
2307 case HV_X64_MSR_SVERSION:
2308 env->msr_hv_synic_version = msrs[i].data;
2309 break;
2310 case HV_X64_MSR_SIEFP:
2311 env->msr_hv_synic_evt_page = msrs[i].data;
2312 break;
2313 case HV_X64_MSR_SIMP:
2314 env->msr_hv_synic_msg_page = msrs[i].data;
2315 break;
2316 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2317 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2318 break;
2319 case HV_X64_MSR_STIMER0_CONFIG:
2320 case HV_X64_MSR_STIMER1_CONFIG:
2321 case HV_X64_MSR_STIMER2_CONFIG:
2322 case HV_X64_MSR_STIMER3_CONFIG:
2323 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2324 msrs[i].data;
2325 break;
2326 case HV_X64_MSR_STIMER0_COUNT:
2327 case HV_X64_MSR_STIMER1_COUNT:
2328 case HV_X64_MSR_STIMER2_COUNT:
2329 case HV_X64_MSR_STIMER3_COUNT:
2330 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2331 msrs[i].data;
2332 break;
2333 case MSR_MTRRdefType:
2334 env->mtrr_deftype = msrs[i].data;
2335 break;
2336 case MSR_MTRRfix64K_00000:
2337 env->mtrr_fixed[0] = msrs[i].data;
2338 break;
2339 case MSR_MTRRfix16K_80000:
2340 env->mtrr_fixed[1] = msrs[i].data;
2341 break;
2342 case MSR_MTRRfix16K_A0000:
2343 env->mtrr_fixed[2] = msrs[i].data;
2344 break;
2345 case MSR_MTRRfix4K_C0000:
2346 env->mtrr_fixed[3] = msrs[i].data;
2347 break;
2348 case MSR_MTRRfix4K_C8000:
2349 env->mtrr_fixed[4] = msrs[i].data;
2350 break;
2351 case MSR_MTRRfix4K_D0000:
2352 env->mtrr_fixed[5] = msrs[i].data;
2353 break;
2354 case MSR_MTRRfix4K_D8000:
2355 env->mtrr_fixed[6] = msrs[i].data;
2356 break;
2357 case MSR_MTRRfix4K_E0000:
2358 env->mtrr_fixed[7] = msrs[i].data;
2359 break;
2360 case MSR_MTRRfix4K_E8000:
2361 env->mtrr_fixed[8] = msrs[i].data;
2362 break;
2363 case MSR_MTRRfix4K_F0000:
2364 env->mtrr_fixed[9] = msrs[i].data;
2365 break;
2366 case MSR_MTRRfix4K_F8000:
2367 env->mtrr_fixed[10] = msrs[i].data;
2368 break;
2369 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2370 if (index & 1) {
2371 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2372 mtrr_top_bits;
2373 } else {
2374 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2375 }
2376 break;
2377 }
2378 }
2379
2380 return 0;
2381 }
2382
2383 static int kvm_put_mp_state(X86CPU *cpu)
2384 {
2385 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2386
2387 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2388 }
2389
2390 static int kvm_get_mp_state(X86CPU *cpu)
2391 {
2392 CPUState *cs = CPU(cpu);
2393 CPUX86State *env = &cpu->env;
2394 struct kvm_mp_state mp_state;
2395 int ret;
2396
2397 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2398 if (ret < 0) {
2399 return ret;
2400 }
2401 env->mp_state = mp_state.mp_state;
2402 if (kvm_irqchip_in_kernel()) {
2403 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2404 }
2405 return 0;
2406 }
2407
2408 static int kvm_get_apic(X86CPU *cpu)
2409 {
2410 DeviceState *apic = cpu->apic_state;
2411 struct kvm_lapic_state kapic;
2412 int ret;
2413
2414 if (apic && kvm_irqchip_in_kernel()) {
2415 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2416 if (ret < 0) {
2417 return ret;
2418 }
2419
2420 kvm_get_apic_state(apic, &kapic);
2421 }
2422 return 0;
2423 }
2424
2425 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2426 {
2427 CPUState *cs = CPU(cpu);
2428 CPUX86State *env = &cpu->env;
2429 struct kvm_vcpu_events events = {};
2430
2431 if (!kvm_has_vcpu_events()) {
2432 return 0;
2433 }
2434
2435 events.exception.injected = (env->exception_injected >= 0);
2436 events.exception.nr = env->exception_injected;
2437 events.exception.has_error_code = env->has_error_code;
2438 events.exception.error_code = env->error_code;
2439 events.exception.pad = 0;
2440
2441 events.interrupt.injected = (env->interrupt_injected >= 0);
2442 events.interrupt.nr = env->interrupt_injected;
2443 events.interrupt.soft = env->soft_interrupt;
2444
2445 events.nmi.injected = env->nmi_injected;
2446 events.nmi.pending = env->nmi_pending;
2447 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2448 events.nmi.pad = 0;
2449
2450 events.sipi_vector = env->sipi_vector;
2451 events.flags = 0;
2452
2453 if (has_msr_smbase) {
2454 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2455 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2456 if (kvm_irqchip_in_kernel()) {
2457 /* As soon as these are moved to the kernel, remove them
2458 * from cs->interrupt_request.
2459 */
2460 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2461 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2462 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2463 } else {
2464 /* Keep these in cs->interrupt_request. */
2465 events.smi.pending = 0;
2466 events.smi.latched_init = 0;
2467 }
2468 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2469 }
2470
2471 if (level >= KVM_PUT_RESET_STATE) {
2472 events.flags |=
2473 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2474 }
2475
2476 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2477 }
2478
2479 static int kvm_get_vcpu_events(X86CPU *cpu)
2480 {
2481 CPUX86State *env = &cpu->env;
2482 struct kvm_vcpu_events events;
2483 int ret;
2484
2485 if (!kvm_has_vcpu_events()) {
2486 return 0;
2487 }
2488
2489 memset(&events, 0, sizeof(events));
2490 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2491 if (ret < 0) {
2492 return ret;
2493 }
2494 env->exception_injected =
2495 events.exception.injected ? events.exception.nr : -1;
2496 env->has_error_code = events.exception.has_error_code;
2497 env->error_code = events.exception.error_code;
2498
2499 env->interrupt_injected =
2500 events.interrupt.injected ? events.interrupt.nr : -1;
2501 env->soft_interrupt = events.interrupt.soft;
2502
2503 env->nmi_injected = events.nmi.injected;
2504 env->nmi_pending = events.nmi.pending;
2505 if (events.nmi.masked) {
2506 env->hflags2 |= HF2_NMI_MASK;
2507 } else {
2508 env->hflags2 &= ~HF2_NMI_MASK;
2509 }
2510
2511 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2512 if (events.smi.smm) {
2513 env->hflags |= HF_SMM_MASK;
2514 } else {
2515 env->hflags &= ~HF_SMM_MASK;
2516 }
2517 if (events.smi.pending) {
2518 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2519 } else {
2520 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2521 }
2522 if (events.smi.smm_inside_nmi) {
2523 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2524 } else {
2525 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2526 }
2527 if (events.smi.latched_init) {
2528 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2529 } else {
2530 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2531 }
2532 }
2533
2534 env->sipi_vector = events.sipi_vector;
2535
2536 return 0;
2537 }
2538
2539 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2540 {
2541 CPUState *cs = CPU(cpu);
2542 CPUX86State *env = &cpu->env;
2543 int ret = 0;
2544 unsigned long reinject_trap = 0;
2545
2546 if (!kvm_has_vcpu_events()) {
2547 if (env->exception_injected == 1) {
2548 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2549 } else if (env->exception_injected == 3) {
2550 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2551 }
2552 env->exception_injected = -1;
2553 }
2554
2555 /*
2556 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2557 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2558 * by updating the debug state once again if single-stepping is on.
2559 * Another reason to call kvm_update_guest_debug here is a pending debug
2560 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2561 * reinject them via SET_GUEST_DEBUG.
2562 */
2563 if (reinject_trap ||
2564 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2565 ret = kvm_update_guest_debug(cs, reinject_trap);
2566 }
2567 return ret;
2568 }
2569
2570 static int kvm_put_debugregs(X86CPU *cpu)
2571 {
2572 CPUX86State *env = &cpu->env;
2573 struct kvm_debugregs dbgregs;
2574 int i;
2575
2576 if (!kvm_has_debugregs()) {
2577 return 0;
2578 }
2579
2580 for (i = 0; i < 4; i++) {
2581 dbgregs.db[i] = env->dr[i];
2582 }
2583 dbgregs.dr6 = env->dr[6];
2584 dbgregs.dr7 = env->dr[7];
2585 dbgregs.flags = 0;
2586
2587 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2588 }
2589
2590 static int kvm_get_debugregs(X86CPU *cpu)
2591 {
2592 CPUX86State *env = &cpu->env;
2593 struct kvm_debugregs dbgregs;
2594 int i, ret;
2595
2596 if (!kvm_has_debugregs()) {
2597 return 0;
2598 }
2599
2600 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2601 if (ret < 0) {
2602 return ret;
2603 }
2604 for (i = 0; i < 4; i++) {
2605 env->dr[i] = dbgregs.db[i];
2606 }
2607 env->dr[4] = env->dr[6] = dbgregs.dr6;
2608 env->dr[5] = env->dr[7] = dbgregs.dr7;
2609
2610 return 0;
2611 }
2612
2613 int kvm_arch_put_registers(CPUState *cpu, int level)
2614 {
2615 X86CPU *x86_cpu = X86_CPU(cpu);
2616 int ret;
2617
2618 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2619
2620 if (level >= KVM_PUT_RESET_STATE) {
2621 ret = kvm_put_msr_feature_control(x86_cpu);
2622 if (ret < 0) {
2623 return ret;
2624 }
2625 }
2626
2627 if (level == KVM_PUT_FULL_STATE) {
2628 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2629 * because TSC frequency mismatch shouldn't abort migration,
2630 * unless the user explicitly asked for a more strict TSC
2631 * setting (e.g. using an explicit "tsc-freq" option).
2632 */
2633 kvm_arch_set_tsc_khz(cpu);
2634 }
2635
2636 ret = kvm_getput_regs(x86_cpu, 1);
2637 if (ret < 0) {
2638 return ret;
2639 }
2640 ret = kvm_put_xsave(x86_cpu);
2641 if (ret < 0) {
2642 return ret;
2643 }
2644 ret = kvm_put_xcrs(x86_cpu);
2645 if (ret < 0) {
2646 return ret;
2647 }
2648 ret = kvm_put_sregs(x86_cpu);
2649 if (ret < 0) {
2650 return ret;
2651 }
2652 /* must be before kvm_put_msrs */
2653 ret = kvm_inject_mce_oldstyle(x86_cpu);
2654 if (ret < 0) {
2655 return ret;
2656 }
2657 ret = kvm_put_msrs(x86_cpu, level);
2658 if (ret < 0) {
2659 return ret;
2660 }
2661 if (level >= KVM_PUT_RESET_STATE) {
2662 ret = kvm_put_mp_state(x86_cpu);
2663 if (ret < 0) {
2664 return ret;
2665 }
2666 }
2667
2668 ret = kvm_put_tscdeadline_msr(x86_cpu);
2669 if (ret < 0) {
2670 return ret;
2671 }
2672
2673 ret = kvm_put_vcpu_events(x86_cpu, level);
2674 if (ret < 0) {
2675 return ret;
2676 }
2677 ret = kvm_put_debugregs(x86_cpu);
2678 if (ret < 0) {
2679 return ret;
2680 }
2681 /* must be last */
2682 ret = kvm_guest_debug_workarounds(x86_cpu);
2683 if (ret < 0) {
2684 return ret;
2685 }
2686 return 0;
2687 }
2688
2689 int kvm_arch_get_registers(CPUState *cs)
2690 {
2691 X86CPU *cpu = X86_CPU(cs);
2692 int ret;
2693
2694 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2695
2696 ret = kvm_getput_regs(cpu, 0);
2697 if (ret < 0) {
2698 goto out;
2699 }
2700 ret = kvm_get_xsave(cpu);
2701 if (ret < 0) {
2702 goto out;
2703 }
2704 ret = kvm_get_xcrs(cpu);
2705 if (ret < 0) {
2706 goto out;
2707 }
2708 ret = kvm_get_sregs(cpu);
2709 if (ret < 0) {
2710 goto out;
2711 }
2712 ret = kvm_get_msrs(cpu);
2713 if (ret < 0) {
2714 goto out;
2715 }
2716 ret = kvm_get_mp_state(cpu);
2717 if (ret < 0) {
2718 goto out;
2719 }
2720 ret = kvm_get_apic(cpu);
2721 if (ret < 0) {
2722 goto out;
2723 }
2724 ret = kvm_get_vcpu_events(cpu);
2725 if (ret < 0) {
2726 goto out;
2727 }
2728 ret = kvm_get_debugregs(cpu);
2729 if (ret < 0) {
2730 goto out;
2731 }
2732 ret = 0;
2733 out:
2734 cpu_sync_bndcs_hflags(&cpu->env);
2735 return ret;
2736 }
2737
2738 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2739 {
2740 X86CPU *x86_cpu = X86_CPU(cpu);
2741 CPUX86State *env = &x86_cpu->env;
2742 int ret;
2743
2744 /* Inject NMI */
2745 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2746 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2747 qemu_mutex_lock_iothread();
2748 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2749 qemu_mutex_unlock_iothread();
2750 DPRINTF("injected NMI\n");
2751 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2752 if (ret < 0) {
2753 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2754 strerror(-ret));
2755 }
2756 }
2757 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2758 qemu_mutex_lock_iothread();
2759 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2760 qemu_mutex_unlock_iothread();
2761 DPRINTF("injected SMI\n");
2762 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2763 if (ret < 0) {
2764 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2765 strerror(-ret));
2766 }
2767 }
2768 }
2769
2770 if (!kvm_pic_in_kernel()) {
2771 qemu_mutex_lock_iothread();
2772 }
2773
2774 /* Force the VCPU out of its inner loop to process any INIT requests
2775 * or (for userspace APIC, but it is cheap to combine the checks here)
2776 * pending TPR access reports.
2777 */
2778 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2779 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2780 !(env->hflags & HF_SMM_MASK)) {
2781 cpu->exit_request = 1;
2782 }
2783 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2784 cpu->exit_request = 1;
2785 }
2786 }
2787
2788 if (!kvm_pic_in_kernel()) {
2789 /* Try to inject an interrupt if the guest can accept it */
2790 if (run->ready_for_interrupt_injection &&
2791 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2792 (env->eflags & IF_MASK)) {
2793 int irq;
2794
2795 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2796 irq = cpu_get_pic_interrupt(env);
2797 if (irq >= 0) {
2798 struct kvm_interrupt intr;
2799
2800 intr.irq = irq;
2801 DPRINTF("injected interrupt %d\n", irq);
2802 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2803 if (ret < 0) {
2804 fprintf(stderr,
2805 "KVM: injection failed, interrupt lost (%s)\n",
2806 strerror(-ret));
2807 }
2808 }
2809 }
2810
2811 /* If we have an interrupt but the guest is not ready to receive an
2812 * interrupt, request an interrupt window exit. This will
2813 * cause a return to userspace as soon as the guest is ready to
2814 * receive interrupts. */
2815 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2816 run->request_interrupt_window = 1;
2817 } else {
2818 run->request_interrupt_window = 0;
2819 }
2820
2821 DPRINTF("setting tpr\n");
2822 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2823
2824 qemu_mutex_unlock_iothread();
2825 }
2826 }
2827
2828 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2829 {
2830 X86CPU *x86_cpu = X86_CPU(cpu);
2831 CPUX86State *env = &x86_cpu->env;
2832
2833 if (run->flags & KVM_RUN_X86_SMM) {
2834 env->hflags |= HF_SMM_MASK;
2835 } else {
2836 env->hflags &= HF_SMM_MASK;
2837 }
2838 if (run->if_flag) {
2839 env->eflags |= IF_MASK;
2840 } else {
2841 env->eflags &= ~IF_MASK;
2842 }
2843
2844 /* We need to protect the apic state against concurrent accesses from
2845 * different threads in case the userspace irqchip is used. */
2846 if (!kvm_irqchip_in_kernel()) {
2847 qemu_mutex_lock_iothread();
2848 }
2849 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2850 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2851 if (!kvm_irqchip_in_kernel()) {
2852 qemu_mutex_unlock_iothread();
2853 }
2854 return cpu_get_mem_attrs(env);
2855 }
2856
2857 int kvm_arch_process_async_events(CPUState *cs)
2858 {
2859 X86CPU *cpu = X86_CPU(cs);
2860 CPUX86State *env = &cpu->env;
2861
2862 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2863 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2864 assert(env->mcg_cap);
2865
2866 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2867
2868 kvm_cpu_synchronize_state(cs);
2869
2870 if (env->exception_injected == EXCP08_DBLE) {
2871 /* this means triple fault */
2872 qemu_system_reset_request();
2873 cs->exit_request = 1;
2874 return 0;
2875 }
2876 env->exception_injected = EXCP12_MCHK;
2877 env->has_error_code = 0;
2878
2879 cs->halted = 0;
2880 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2881 env->mp_state = KVM_MP_STATE_RUNNABLE;
2882 }
2883 }
2884
2885 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2886 !(env->hflags & HF_SMM_MASK)) {
2887 kvm_cpu_synchronize_state(cs);
2888 do_cpu_init(cpu);
2889 }
2890
2891 if (kvm_irqchip_in_kernel()) {
2892 return 0;
2893 }
2894
2895 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2896 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2897 apic_poll_irq(cpu->apic_state);
2898 }
2899 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2900 (env->eflags & IF_MASK)) ||
2901 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2902 cs->halted = 0;
2903 }
2904 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2905 kvm_cpu_synchronize_state(cs);
2906 do_cpu_sipi(cpu);
2907 }
2908 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2909 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2910 kvm_cpu_synchronize_state(cs);
2911 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2912 env->tpr_access_type);
2913 }
2914
2915 return cs->halted;
2916 }
2917
2918 static int kvm_handle_halt(X86CPU *cpu)
2919 {
2920 CPUState *cs = CPU(cpu);
2921 CPUX86State *env = &cpu->env;
2922
2923 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2924 (env->eflags & IF_MASK)) &&
2925 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2926 cs->halted = 1;
2927 return EXCP_HLT;
2928 }
2929
2930 return 0;
2931 }
2932
2933 static int kvm_handle_tpr_access(X86CPU *cpu)
2934 {
2935 CPUState *cs = CPU(cpu);
2936 struct kvm_run *run = cs->kvm_run;
2937
2938 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2939 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2940 : TPR_ACCESS_READ);
2941 return 1;
2942 }
2943
2944 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2945 {
2946 static const uint8_t int3 = 0xcc;
2947
2948 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2949 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2950 return -EINVAL;
2951 }
2952 return 0;
2953 }
2954
2955 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2956 {
2957 uint8_t int3;
2958
2959 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2960 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2961 return -EINVAL;
2962 }
2963 return 0;
2964 }
2965
2966 static struct {
2967 target_ulong addr;
2968 int len;
2969 int type;
2970 } hw_breakpoint[4];
2971
2972 static int nb_hw_breakpoint;
2973
2974 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2975 {
2976 int n;
2977
2978 for (n = 0; n < nb_hw_breakpoint; n++) {
2979 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2980 (hw_breakpoint[n].len == len || len == -1)) {
2981 return n;
2982 }
2983 }
2984 return -1;
2985 }
2986
2987 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2988 target_ulong len, int type)
2989 {
2990 switch (type) {
2991 case GDB_BREAKPOINT_HW:
2992 len = 1;
2993 break;
2994 case GDB_WATCHPOINT_WRITE:
2995 case GDB_WATCHPOINT_ACCESS:
2996 switch (len) {
2997 case 1:
2998 break;
2999 case 2:
3000 case 4:
3001 case 8:
3002 if (addr & (len - 1)) {
3003 return -EINVAL;
3004 }
3005 break;
3006 default:
3007 return -EINVAL;
3008 }
3009 break;
3010 default:
3011 return -ENOSYS;
3012 }
3013
3014 if (nb_hw_breakpoint == 4) {
3015 return -ENOBUFS;
3016 }
3017 if (find_hw_breakpoint(addr, len, type) >= 0) {
3018 return -EEXIST;
3019 }
3020 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3021 hw_breakpoint[nb_hw_breakpoint].len = len;
3022 hw_breakpoint[nb_hw_breakpoint].type = type;
3023 nb_hw_breakpoint++;
3024
3025 return 0;
3026 }
3027
3028 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3029 target_ulong len, int type)
3030 {
3031 int n;
3032
3033 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3034 if (n < 0) {
3035 return -ENOENT;
3036 }
3037 nb_hw_breakpoint--;
3038 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3039
3040 return 0;
3041 }
3042
3043 void kvm_arch_remove_all_hw_breakpoints(void)
3044 {
3045 nb_hw_breakpoint = 0;
3046 }
3047
3048 static CPUWatchpoint hw_watchpoint;
3049
3050 static int kvm_handle_debug(X86CPU *cpu,
3051 struct kvm_debug_exit_arch *arch_info)
3052 {
3053 CPUState *cs = CPU(cpu);
3054 CPUX86State *env = &cpu->env;
3055 int ret = 0;
3056 int n;
3057
3058 if (arch_info->exception == 1) {
3059 if (arch_info->dr6 & (1 << 14)) {
3060 if (cs->singlestep_enabled) {
3061 ret = EXCP_DEBUG;
3062 }
3063 } else {
3064 for (n = 0; n < 4; n++) {
3065 if (arch_info->dr6 & (1 << n)) {
3066 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3067 case 0x0:
3068 ret = EXCP_DEBUG;
3069 break;
3070 case 0x1:
3071 ret = EXCP_DEBUG;
3072 cs->watchpoint_hit = &hw_watchpoint;
3073 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3074 hw_watchpoint.flags = BP_MEM_WRITE;
3075 break;
3076 case 0x3:
3077 ret = EXCP_DEBUG;
3078 cs->watchpoint_hit = &hw_watchpoint;
3079 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3080 hw_watchpoint.flags = BP_MEM_ACCESS;
3081 break;
3082 }
3083 }
3084 }
3085 }
3086 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3087 ret = EXCP_DEBUG;
3088 }
3089 if (ret == 0) {
3090 cpu_synchronize_state(cs);
3091 assert(env->exception_injected == -1);
3092
3093 /* pass to guest */
3094 env->exception_injected = arch_info->exception;
3095 env->has_error_code = 0;
3096 }
3097
3098 return ret;
3099 }
3100
3101 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3102 {
3103 const uint8_t type_code[] = {
3104 [GDB_BREAKPOINT_HW] = 0x0,
3105 [GDB_WATCHPOINT_WRITE] = 0x1,
3106 [GDB_WATCHPOINT_ACCESS] = 0x3
3107 };
3108 const uint8_t len_code[] = {
3109 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3110 };
3111 int n;
3112
3113 if (kvm_sw_breakpoints_active(cpu)) {
3114 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3115 }
3116 if (nb_hw_breakpoint > 0) {
3117 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3118 dbg->arch.debugreg[7] = 0x0600;
3119 for (n = 0; n < nb_hw_breakpoint; n++) {
3120 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3121 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3122 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3123 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3124 }
3125 }
3126 }
3127
3128 static bool host_supports_vmx(void)
3129 {
3130 uint32_t ecx, unused;
3131
3132 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3133 return ecx & CPUID_EXT_VMX;
3134 }
3135
3136 #define VMX_INVALID_GUEST_STATE 0x80000021
3137
3138 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3139 {
3140 X86CPU *cpu = X86_CPU(cs);
3141 uint64_t code;
3142 int ret;
3143
3144 switch (run->exit_reason) {
3145 case KVM_EXIT_HLT:
3146 DPRINTF("handle_hlt\n");
3147 qemu_mutex_lock_iothread();
3148 ret = kvm_handle_halt(cpu);
3149 qemu_mutex_unlock_iothread();
3150 break;
3151 case KVM_EXIT_SET_TPR:
3152 ret = 0;
3153 break;
3154 case KVM_EXIT_TPR_ACCESS:
3155 qemu_mutex_lock_iothread();
3156 ret = kvm_handle_tpr_access(cpu);
3157 qemu_mutex_unlock_iothread();
3158 break;
3159 case KVM_EXIT_FAIL_ENTRY:
3160 code = run->fail_entry.hardware_entry_failure_reason;
3161 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3162 code);
3163 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3164 fprintf(stderr,
3165 "\nIf you're running a guest on an Intel machine without "
3166 "unrestricted mode\n"
3167 "support, the failure can be most likely due to the guest "
3168 "entering an invalid\n"
3169 "state for Intel VT. For example, the guest maybe running "
3170 "in big real mode\n"
3171 "which is not supported on less recent Intel processors."
3172 "\n\n");
3173 }
3174 ret = -1;
3175 break;
3176 case KVM_EXIT_EXCEPTION:
3177 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3178 run->ex.exception, run->ex.error_code);
3179 ret = -1;
3180 break;
3181 case KVM_EXIT_DEBUG:
3182 DPRINTF("kvm_exit_debug\n");
3183 qemu_mutex_lock_iothread();
3184 ret = kvm_handle_debug(cpu, &run->debug.arch);
3185 qemu_mutex_unlock_iothread();
3186 break;
3187 case KVM_EXIT_HYPERV:
3188 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3189 break;
3190 case KVM_EXIT_IOAPIC_EOI:
3191 ioapic_eoi_broadcast(run->eoi.vector);
3192 ret = 0;
3193 break;
3194 default:
3195 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3196 ret = -1;
3197 break;
3198 }
3199
3200 return ret;
3201 }
3202
3203 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3204 {
3205 X86CPU *cpu = X86_CPU(cs);
3206 CPUX86State *env = &cpu->env;
3207
3208 kvm_cpu_synchronize_state(cs);
3209 return !(env->cr[0] & CR0_PE_MASK) ||
3210 ((env->segs[R_CS].selector & 3) != 3);
3211 }
3212
3213 void kvm_arch_init_irq_routing(KVMState *s)
3214 {
3215 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3216 /* If kernel can't do irq routing, interrupt source
3217 * override 0->2 cannot be set up as required by HPET.
3218 * So we have to disable it.
3219 */
3220 no_hpet = 1;
3221 }
3222 /* We know at this point that we're using the in-kernel
3223 * irqchip, so we can use irqfds, and on x86 we know
3224 * we can use msi via irqfd and GSI routing.
3225 */
3226 kvm_msi_via_irqfd_allowed = true;
3227 kvm_gsi_routing_allowed = true;
3228
3229 if (kvm_irqchip_is_split()) {
3230 int i;
3231
3232 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3233 MSI routes for signaling interrupts to the local apics. */
3234 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3235 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3236 error_report("Could not enable split IRQ mode.");
3237 exit(1);
3238 }
3239 }
3240 }
3241 }
3242
3243 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3244 {
3245 int ret;
3246 if (machine_kernel_irqchip_split(ms)) {
3247 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3248 if (ret) {
3249 error_report("Could not enable split irqchip mode: %s",
3250 strerror(-ret));
3251 exit(1);
3252 } else {
3253 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3254 kvm_split_irqchip = true;
3255 return 1;
3256 }
3257 } else {
3258 return 0;
3259 }
3260 }
3261
3262 /* Classic KVM device assignment interface. Will remain x86 only. */
3263 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3264 uint32_t flags, uint32_t *dev_id)
3265 {
3266 struct kvm_assigned_pci_dev dev_data = {
3267 .segnr = dev_addr->domain,
3268 .busnr = dev_addr->bus,
3269 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3270 .flags = flags,
3271 };
3272 int ret;
3273
3274 dev_data.assigned_dev_id =
3275 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3276
3277 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3278 if (ret < 0) {
3279 return ret;
3280 }
3281
3282 *dev_id = dev_data.assigned_dev_id;
3283
3284 return 0;
3285 }
3286
3287 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3288 {
3289 struct kvm_assigned_pci_dev dev_data = {
3290 .assigned_dev_id = dev_id,
3291 };
3292
3293 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3294 }
3295
3296 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3297 uint32_t irq_type, uint32_t guest_irq)
3298 {
3299 struct kvm_assigned_irq assigned_irq = {
3300 .assigned_dev_id = dev_id,
3301 .guest_irq = guest_irq,
3302 .flags = irq_type,
3303 };
3304
3305 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3306 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3307 } else {
3308 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3309 }
3310 }
3311
3312 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3313 uint32_t guest_irq)
3314 {
3315 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3316 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3317
3318 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3319 }
3320
3321 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3322 {
3323 struct kvm_assigned_pci_dev dev_data = {
3324 .assigned_dev_id = dev_id,
3325 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3326 };
3327
3328 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3329 }
3330
3331 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3332 uint32_t type)
3333 {
3334 struct kvm_assigned_irq assigned_irq = {
3335 .assigned_dev_id = dev_id,
3336 .flags = type,
3337 };
3338
3339 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3340 }
3341
3342 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3343 {
3344 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3345 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3346 }
3347
3348 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3349 {
3350 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3351 KVM_DEV_IRQ_GUEST_MSI, virq);
3352 }
3353
3354 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3355 {
3356 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3357 KVM_DEV_IRQ_HOST_MSI);
3358 }
3359
3360 bool kvm_device_msix_supported(KVMState *s)
3361 {
3362 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3363 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3364 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3365 }
3366
3367 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3368 uint32_t nr_vectors)
3369 {
3370 struct kvm_assigned_msix_nr msix_nr = {
3371 .assigned_dev_id = dev_id,
3372 .entry_nr = nr_vectors,
3373 };
3374
3375 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3376 }
3377
3378 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3379 int virq)
3380 {
3381 struct kvm_assigned_msix_entry msix_entry = {
3382 .assigned_dev_id = dev_id,
3383 .gsi = virq,
3384 .entry = vector,
3385 };
3386
3387 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3388 }
3389
3390 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3391 {
3392 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3393 KVM_DEV_IRQ_GUEST_MSIX, 0);
3394 }
3395
3396 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3397 {
3398 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3399 KVM_DEV_IRQ_HOST_MSIX);
3400 }
3401
3402 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3403 uint64_t address, uint32_t data, PCIDevice *dev)
3404 {
3405 X86IOMMUState *iommu = x86_iommu_get_default();
3406
3407 if (iommu) {
3408 int ret;
3409 MSIMessage src, dst;
3410 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3411
3412 src.address = route->u.msi.address_hi;
3413 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3414 src.address |= route->u.msi.address_lo;
3415 src.data = route->u.msi.data;
3416
3417 ret = class->int_remap(iommu, &src, &dst, dev ? \
3418 pci_requester_id(dev) : \
3419 X86_IOMMU_SID_INVALID);
3420 if (ret) {
3421 trace_kvm_x86_fixup_msi_error(route->gsi);
3422 return 1;
3423 }
3424
3425 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3426 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3427 route->u.msi.data = dst.data;
3428 }
3429
3430 return 0;
3431 }
3432
3433 typedef struct MSIRouteEntry MSIRouteEntry;
3434
3435 struct MSIRouteEntry {
3436 PCIDevice *dev; /* Device pointer */
3437 int vector; /* MSI/MSIX vector index */
3438 int virq; /* Virtual IRQ index */
3439 QLIST_ENTRY(MSIRouteEntry) list;
3440 };
3441
3442 /* List of used GSI routes */
3443 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3444 QLIST_HEAD_INITIALIZER(msi_route_list);
3445
3446 static void kvm_update_msi_routes_all(void *private, bool global,
3447 uint32_t index, uint32_t mask)
3448 {
3449 int cnt = 0;
3450 MSIRouteEntry *entry;
3451 MSIMessage msg;
3452 /* TODO: explicit route update */
3453 QLIST_FOREACH(entry, &msi_route_list, list) {
3454 cnt++;
3455 msg = pci_get_msi_message(entry->dev, entry->vector);
3456 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3457 msg, entry->dev);
3458 }
3459 kvm_irqchip_commit_routes(kvm_state);
3460 trace_kvm_x86_update_msi_routes(cnt);
3461 }
3462
3463 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3464 int vector, PCIDevice *dev)
3465 {
3466 static bool notify_list_inited = false;
3467 MSIRouteEntry *entry;
3468
3469 if (!dev) {
3470 /* These are (possibly) IOAPIC routes only used for split
3471 * kernel irqchip mode, while what we are housekeeping are
3472 * PCI devices only. */
3473 return 0;
3474 }
3475
3476 entry = g_new0(MSIRouteEntry, 1);
3477 entry->dev = dev;
3478 entry->vector = vector;
3479 entry->virq = route->gsi;
3480 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3481
3482 trace_kvm_x86_add_msi_route(route->gsi);
3483
3484 if (!notify_list_inited) {
3485 /* For the first time we do add route, add ourselves into
3486 * IOMMU's IEC notify list if needed. */
3487 X86IOMMUState *iommu = x86_iommu_get_default();
3488 if (iommu) {
3489 x86_iommu_iec_register_notifier(iommu,
3490 kvm_update_msi_routes_all,
3491 NULL);
3492 }
3493 notify_list_inited = true;
3494 }
3495 return 0;
3496 }
3497
3498 int kvm_arch_release_virq_post(int virq)
3499 {
3500 MSIRouteEntry *entry, *next;
3501 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3502 if (entry->virq == virq) {
3503 trace_kvm_x86_remove_msi_route(virq);
3504 QLIST_REMOVE(entry, list);
3505 break;
3506 }
3507 }
3508 return 0;
3509 }
3510
3511 int kvm_arch_msi_data_to_gsi(uint32_t data)
3512 {
3513 abort();
3514 }
AR7 emulation for QEMU