4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/pci/pci_bus.h"
32 #include "hw/pci/pci_host.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
35 #include "migration/qemu-file-types.h"
36 #include "migration/vmstate.h"
37 #include "monitor/monitor.h"
39 #include "sysemu/numa.h"
40 #include "sysemu/sysemu.h"
41 #include "hw/loader.h"
42 #include "qemu/error-report.h"
43 #include "qemu/range.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "exec/address-spaces.h"
48 #include "hw/hotplug.h"
49 #include "hw/boards.h"
50 #include "qapi/error.h"
51 #include "qapi/qapi-commands-pci.h"
52 #include "qemu/cutils.h"
56 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
58 # define PCI_DPRINTF(format, ...) do { } while (0)
61 bool pci_available
= true;
63 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
64 static char *pcibus_get_dev_path(DeviceState
*dev
);
65 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
66 static void pcibus_reset(BusState
*qbus
);
68 static Property pci_props
[] = {
69 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
70 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
71 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
72 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
73 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
74 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
75 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
76 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
77 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
78 DEFINE_PROP_STRING("failover_pair_id", PCIDevice
,
80 DEFINE_PROP_END_OF_LIST()
83 static const VMStateDescription vmstate_pcibus
= {
86 .minimum_version_id
= 1,
87 .fields
= (VMStateField
[]) {
88 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
89 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
90 nirq
, 0, vmstate_info_int32
,
96 static void pci_init_bus_master(PCIDevice
*pci_dev
)
98 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
100 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
101 OBJECT(pci_dev
), "bus master",
102 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
103 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
104 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
105 &pci_dev
->bus_master_enable_region
);
108 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
110 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
113 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
114 if (bus
->devices
[i
]) {
115 pci_init_bus_master(bus
->devices
[i
]);
120 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
122 PCIBus
*bus
= PCI_BUS(qbus
);
124 bus
->machine_done
.notify
= pcibus_machine_done
;
125 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
127 vmstate_register(NULL
, VMSTATE_INSTANCE_ID_ANY
, &vmstate_pcibus
, bus
);
130 static void pcie_bus_realize(BusState
*qbus
, Error
**errp
)
132 PCIBus
*bus
= PCI_BUS(qbus
);
134 pci_bus_realize(qbus
, errp
);
137 * A PCI-E bus can support extended config space if it's the root
138 * bus, or if the bus/bridge above it does as well
140 if (pci_bus_is_root(bus
)) {
141 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
143 PCIBus
*parent_bus
= pci_get_bus(bus
->parent_dev
);
145 if (pci_bus_allows_extended_config_space(parent_bus
)) {
146 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
151 static void pci_bus_unrealize(BusState
*qbus
)
153 PCIBus
*bus
= PCI_BUS(qbus
);
155 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
157 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
160 static int pcibus_num(PCIBus
*bus
)
162 if (pci_bus_is_root(bus
)) {
163 return 0; /* pci host bridge */
165 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
168 static uint16_t pcibus_numa_node(PCIBus
*bus
)
170 return NUMA_NODE_UNASSIGNED
;
173 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
175 BusClass
*k
= BUS_CLASS(klass
);
176 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
178 k
->print_dev
= pcibus_dev_print
;
179 k
->get_dev_path
= pcibus_get_dev_path
;
180 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
181 k
->realize
= pci_bus_realize
;
182 k
->unrealize
= pci_bus_unrealize
;
183 k
->reset
= pcibus_reset
;
185 pbc
->bus_num
= pcibus_num
;
186 pbc
->numa_node
= pcibus_numa_node
;
189 static const TypeInfo pci_bus_info
= {
190 .name
= TYPE_PCI_BUS
,
192 .instance_size
= sizeof(PCIBus
),
193 .class_size
= sizeof(PCIBusClass
),
194 .class_init
= pci_bus_class_init
,
197 static const TypeInfo pcie_interface_info
= {
198 .name
= INTERFACE_PCIE_DEVICE
,
199 .parent
= TYPE_INTERFACE
,
202 static const TypeInfo conventional_pci_interface_info
= {
203 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
204 .parent
= TYPE_INTERFACE
,
207 static void pcie_bus_class_init(ObjectClass
*klass
, void *data
)
209 BusClass
*k
= BUS_CLASS(klass
);
211 k
->realize
= pcie_bus_realize
;
214 static const TypeInfo pcie_bus_info
= {
215 .name
= TYPE_PCIE_BUS
,
216 .parent
= TYPE_PCI_BUS
,
217 .class_init
= pcie_bus_class_init
,
220 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
221 static void pci_update_mappings(PCIDevice
*d
);
222 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
223 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
224 static void pci_del_option_rom(PCIDevice
*pdev
);
226 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
227 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
229 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
231 int pci_bar(PCIDevice
*d
, int reg
)
235 if (reg
!= PCI_ROM_SLOT
)
236 return PCI_BASE_ADDRESS_0
+ reg
* 4;
238 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
239 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
242 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
244 return (d
->irq_state
>> irq_num
) & 0x1;
247 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
249 d
->irq_state
&= ~(0x1 << irq_num
);
250 d
->irq_state
|= level
<< irq_num
;
253 static void pci_bus_change_irq_level(PCIBus
*bus
, int irq_num
, int change
)
255 assert(irq_num
>= 0);
256 assert(irq_num
< bus
->nirq
);
257 bus
->irq_count
[irq_num
] += change
;
258 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
261 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
265 bus
= pci_get_bus(pci_dev
);
266 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
269 pci_dev
= bus
->parent_dev
;
271 pci_bus_change_irq_level(bus
, irq_num
, change
);
274 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
276 assert(irq_num
>= 0);
277 assert(irq_num
< bus
->nirq
);
278 return !!bus
->irq_count
[irq_num
];
281 /* Update interrupt status bit in config space on interrupt
283 static void pci_update_irq_status(PCIDevice
*dev
)
285 if (dev
->irq_state
) {
286 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
288 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
292 void pci_device_deassert_intx(PCIDevice
*dev
)
295 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
296 pci_irq_handler(dev
, i
, 0);
300 static void pci_do_device_reset(PCIDevice
*dev
)
304 pci_device_deassert_intx(dev
);
305 assert(dev
->irq_state
== 0);
307 /* Clear all writable bits */
308 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
309 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
310 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
311 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
312 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
313 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
314 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
315 pci_byte_test_and_clear_mask(dev
->config
+ PCI_INTERRUPT_LINE
,
316 pci_get_word(dev
->wmask
+ PCI_INTERRUPT_LINE
) |
317 pci_get_word(dev
->w1cmask
+ PCI_INTERRUPT_LINE
));
318 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
319 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
320 PCIIORegion
*region
= &dev
->io_regions
[r
];
325 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
326 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
327 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
329 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
332 pci_update_mappings(dev
);
339 * This function is called on #RST and FLR.
340 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
342 void pci_device_reset(PCIDevice
*dev
)
344 qdev_reset_all(&dev
->qdev
);
345 pci_do_device_reset(dev
);
349 * Trigger pci bus reset under a given bus.
350 * Called via qbus_reset_all on RST# assert, after the devices
351 * have been reset qdev_reset_all-ed already.
353 static void pcibus_reset(BusState
*qbus
)
355 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
358 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
359 if (bus
->devices
[i
]) {
360 pci_do_device_reset(bus
->devices
[i
]);
364 for (i
= 0; i
< bus
->nirq
; i
++) {
365 assert(bus
->irq_count
[i
] == 0);
369 static void pci_host_bus_register(DeviceState
*host
)
371 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
373 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
376 static void pci_host_bus_unregister(DeviceState
*host
)
378 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
380 QLIST_REMOVE(host_bridge
, next
);
383 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
385 PCIBus
*bus
= pci_get_bus(d
);
387 while (!pci_bus_is_root(bus
)) {
391 bus
= pci_get_bus(d
);
397 const char *pci_root_bus_path(PCIDevice
*dev
)
399 PCIBus
*rootbus
= pci_device_root_bus(dev
);
400 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
401 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
403 assert(host_bridge
->bus
== rootbus
);
405 if (hc
->root_bus_path
) {
406 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
409 return rootbus
->qbus
.name
;
412 static void pci_root_bus_init(PCIBus
*bus
, DeviceState
*parent
,
413 MemoryRegion
*address_space_mem
,
414 MemoryRegion
*address_space_io
,
417 assert(PCI_FUNC(devfn_min
) == 0);
418 bus
->devfn_min
= devfn_min
;
419 bus
->slot_reserved_mask
= 0x0;
420 bus
->address_space_mem
= address_space_mem
;
421 bus
->address_space_io
= address_space_io
;
422 bus
->flags
|= PCI_BUS_IS_ROOT
;
425 QLIST_INIT(&bus
->child
);
427 pci_host_bus_register(parent
);
430 static void pci_bus_uninit(PCIBus
*bus
)
432 pci_host_bus_unregister(BUS(bus
)->parent
);
435 bool pci_bus_is_express(PCIBus
*bus
)
437 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
440 void pci_root_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
442 MemoryRegion
*address_space_mem
,
443 MemoryRegion
*address_space_io
,
444 uint8_t devfn_min
, const char *typename
)
446 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
447 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
451 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
452 MemoryRegion
*address_space_mem
,
453 MemoryRegion
*address_space_io
,
454 uint8_t devfn_min
, const char *typename
)
458 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
459 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
464 void pci_root_bus_cleanup(PCIBus
*bus
)
467 /* the caller of the unplug hotplug handler will delete this device */
468 qbus_unrealize(BUS(bus
));
471 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
472 void *irq_opaque
, int nirq
)
474 bus
->set_irq
= set_irq
;
475 bus
->map_irq
= map_irq
;
476 bus
->irq_opaque
= irq_opaque
;
478 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
481 void pci_bus_irqs_cleanup(PCIBus
*bus
)
485 bus
->irq_opaque
= NULL
;
487 g_free(bus
->irq_count
);
490 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
491 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
493 MemoryRegion
*address_space_mem
,
494 MemoryRegion
*address_space_io
,
495 uint8_t devfn_min
, int nirq
,
496 const char *typename
)
500 bus
= pci_root_bus_new(parent
, name
, address_space_mem
,
501 address_space_io
, devfn_min
, typename
);
502 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
506 void pci_unregister_root_bus(PCIBus
*bus
)
508 pci_bus_irqs_cleanup(bus
);
509 pci_root_bus_cleanup(bus
);
512 int pci_bus_num(PCIBus
*s
)
514 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
517 int pci_bus_numa_node(PCIBus
*bus
)
519 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
522 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
523 const VMStateField
*field
)
525 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
526 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
530 assert(size
== pci_config_size(s
));
531 config
= g_malloc(size
);
533 qemu_get_buffer(f
, config
, size
);
534 for (i
= 0; i
< size
; ++i
) {
535 if ((config
[i
] ^ s
->config
[i
]) &
536 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
537 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
538 "cmask: %x wmask: %x w1cmask:%x", __func__
,
539 i
, config
[i
], s
->config
[i
],
540 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
545 memcpy(s
->config
, config
, size
);
547 pci_update_mappings(s
);
549 PCIBridge
*b
= PCI_BRIDGE(s
);
550 pci_bridge_update_mappings(b
);
553 memory_region_set_enabled(&s
->bus_master_enable_region
,
554 pci_get_word(s
->config
+ PCI_COMMAND
)
555 & PCI_COMMAND_MASTER
);
561 /* just put buffer */
562 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
563 const VMStateField
*field
, JSONWriter
*vmdesc
)
565 const uint8_t **v
= pv
;
566 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
567 qemu_put_buffer(f
, *v
, size
);
572 static VMStateInfo vmstate_info_pci_config
= {
573 .name
= "pci config",
574 .get
= get_pci_config_device
,
575 .put
= put_pci_config_device
,
578 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
579 const VMStateField
*field
)
581 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
582 uint32_t irq_state
[PCI_NUM_PINS
];
584 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
585 irq_state
[i
] = qemu_get_be32(f
);
586 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
587 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
593 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
594 pci_set_irq_state(s
, i
, irq_state
[i
]);
600 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
601 const VMStateField
*field
, JSONWriter
*vmdesc
)
604 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
606 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
607 qemu_put_be32(f
, pci_irq_state(s
, i
));
613 static VMStateInfo vmstate_info_pci_irq_state
= {
614 .name
= "pci irq state",
615 .get
= get_pci_irq_state
,
616 .put
= put_pci_irq_state
,
619 static bool migrate_is_pcie(void *opaque
, int version_id
)
621 return pci_is_express((PCIDevice
*)opaque
);
624 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
626 return !pci_is_express((PCIDevice
*)opaque
);
629 const VMStateDescription vmstate_pci_device
= {
632 .minimum_version_id
= 1,
633 .fields
= (VMStateField
[]) {
634 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
635 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
637 0, vmstate_info_pci_config
,
638 PCI_CONFIG_SPACE_SIZE
),
639 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
641 0, vmstate_info_pci_config
,
642 PCIE_CONFIG_SPACE_SIZE
),
643 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
644 vmstate_info_pci_irq_state
,
645 PCI_NUM_PINS
* sizeof(int32_t)),
646 VMSTATE_END_OF_LIST()
651 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
653 /* Clear interrupt status bit: it is implicit
654 * in irq_state which we are saving.
655 * This makes us compatible with old devices
656 * which never set or clear this bit. */
657 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
658 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
659 /* Restore the interrupt status bit. */
660 pci_update_irq_status(s
);
663 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
666 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
667 /* Restore the interrupt status bit. */
668 pci_update_irq_status(s
);
672 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
674 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
675 pci_default_sub_vendor_id
);
676 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
677 pci_default_sub_device_id
);
681 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
682 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
684 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
685 unsigned int *slotp
, unsigned int *funcp
)
690 unsigned long dom
= 0, bus
= 0;
691 unsigned int slot
= 0;
692 unsigned int func
= 0;
695 val
= strtoul(p
, &e
, 16);
701 val
= strtoul(p
, &e
, 16);
708 val
= strtoul(p
, &e
, 16);
721 val
= strtoul(p
, &e
, 16);
728 /* if funcp == NULL func is 0 */
729 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
743 static void pci_init_cmask(PCIDevice
*dev
)
745 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
746 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
747 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
748 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
749 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
750 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
751 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
752 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
755 static void pci_init_wmask(PCIDevice
*dev
)
757 int config_size
= pci_config_size(dev
);
759 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
760 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
761 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
762 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
763 PCI_COMMAND_INTX_DISABLE
);
764 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
766 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
767 config_size
- PCI_CONFIG_HEADER_SIZE
);
770 static void pci_init_w1cmask(PCIDevice
*dev
)
773 * Note: It's okay to set w1cmask even for readonly bits as
774 * long as their value is hardwired to 0.
776 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
777 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
778 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
779 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
782 static void pci_init_mask_bridge(PCIDevice
*d
)
784 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
785 PCI_SEC_LETENCY_TIMER */
786 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
789 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
790 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
791 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
792 PCI_MEMORY_RANGE_MASK
& 0xffff);
793 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
794 PCI_MEMORY_RANGE_MASK
& 0xffff);
795 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
796 PCI_PREF_RANGE_MASK
& 0xffff);
797 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
798 PCI_PREF_RANGE_MASK
& 0xffff);
800 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
801 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
803 /* Supported memory and i/o types */
804 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
805 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
806 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
807 PCI_PREF_RANGE_TYPE_64
);
808 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
809 PCI_PREF_RANGE_TYPE_64
);
812 * TODO: Bridges default to 10-bit VGA decoding but we currently only
813 * implement 16-bit decoding (no alias support).
815 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
816 PCI_BRIDGE_CTL_PARITY
|
817 PCI_BRIDGE_CTL_SERR
|
820 PCI_BRIDGE_CTL_VGA_16BIT
|
821 PCI_BRIDGE_CTL_MASTER_ABORT
|
822 PCI_BRIDGE_CTL_BUS_RESET
|
823 PCI_BRIDGE_CTL_FAST_BACK
|
824 PCI_BRIDGE_CTL_DISCARD
|
825 PCI_BRIDGE_CTL_SEC_DISCARD
|
826 PCI_BRIDGE_CTL_DISCARD_SERR
);
827 /* Below does not do anything as we never set this bit, put here for
829 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
830 PCI_BRIDGE_CTL_DISCARD_STATUS
);
831 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
832 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
833 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
834 PCI_PREF_RANGE_TYPE_MASK
);
835 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
836 PCI_PREF_RANGE_TYPE_MASK
);
839 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
841 uint8_t slot
= PCI_SLOT(dev
->devfn
);
844 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
845 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
849 * multifunction bit is interpreted in two ways as follows.
850 * - all functions must set the bit to 1.
852 * - function 0 must set the bit, but the rest function (> 0)
853 * is allowed to leave the bit to 0.
854 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
856 * So OS (at least Linux) checks the bit of only function 0,
857 * and doesn't see the bit of function > 0.
859 * The below check allows both interpretation.
861 if (PCI_FUNC(dev
->devfn
)) {
862 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
863 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
864 /* function 0 should set multifunction bit */
865 error_setg(errp
, "PCI: single function device can't be populated "
866 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
872 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
875 /* function 0 indicates single function, so function > 0 must be NULL */
876 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
877 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
878 error_setg(errp
, "PCI: %x.0 indicates single function, "
879 "but %x.%x is already populated.",
886 static void pci_config_alloc(PCIDevice
*pci_dev
)
888 int config_size
= pci_config_size(pci_dev
);
890 pci_dev
->config
= g_malloc0(config_size
);
891 pci_dev
->cmask
= g_malloc0(config_size
);
892 pci_dev
->wmask
= g_malloc0(config_size
);
893 pci_dev
->w1cmask
= g_malloc0(config_size
);
894 pci_dev
->used
= g_malloc0(config_size
);
897 static void pci_config_free(PCIDevice
*pci_dev
)
899 g_free(pci_dev
->config
);
900 g_free(pci_dev
->cmask
);
901 g_free(pci_dev
->wmask
);
902 g_free(pci_dev
->w1cmask
);
903 g_free(pci_dev
->used
);
906 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
908 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
909 pci_config_free(pci_dev
);
911 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
912 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
913 &pci_dev
->bus_master_enable_region
);
915 address_space_destroy(&pci_dev
->bus_master_as
);
918 /* Extract PCIReqIDCache into BDF format */
919 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
924 switch (cache
->type
) {
926 result
= pci_get_bdf(cache
->dev
);
928 case PCI_REQ_ID_SECONDARY_BUS
:
929 bus_n
= pci_dev_bus_num(cache
->dev
);
930 result
= PCI_BUILD_BDF(bus_n
, 0);
933 error_report("Invalid PCI requester ID cache type: %d",
942 /* Parse bridges up to the root complex and return requester ID
943 * cache for specific device. For full PCIe topology, the cache
944 * result would be exactly the same as getting BDF of the device.
945 * However, several tricks are required when system mixed up with
946 * legacy PCI devices and PCIe-to-PCI bridges.
948 * Here we cache the proxy device (and type) not requester ID since
949 * bus number might change from time to time.
951 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
954 PCIReqIDCache cache
= {
956 .type
= PCI_REQ_ID_BDF
,
959 while (!pci_bus_is_root(pci_get_bus(dev
))) {
960 /* We are under PCI/PCIe bridges */
961 parent
= pci_get_bus(dev
)->parent_dev
;
962 if (pci_is_express(parent
)) {
963 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
964 /* When we pass through PCIe-to-PCI/PCIX bridges, we
965 * override the requester ID using secondary bus
966 * number of parent bridge with zeroed devfn
967 * (pcie-to-pci bridge spec chap 2.3). */
968 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
972 /* Legacy PCI, override requester ID with the bridge's
973 * BDF upstream. When the root complex connects to
974 * legacy PCI devices (including buses), it can only
975 * obtain requester ID info from directly attached
976 * devices. If devices are attached under bridges, only
977 * the requester ID of the bridge that is directly
978 * attached to the root complex can be recognized. */
979 cache
.type
= PCI_REQ_ID_BDF
;
988 uint16_t pci_requester_id(PCIDevice
*dev
)
990 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
993 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
995 return !(bus
->devices
[devfn
]);
998 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
1000 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
1003 /* -1 for devfn means auto assign */
1004 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
1005 const char *name
, int devfn
,
1008 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1009 PCIConfigReadFunc
*config_read
= pc
->config_read
;
1010 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
1011 Error
*local_err
= NULL
;
1012 DeviceState
*dev
= DEVICE(pci_dev
);
1013 PCIBus
*bus
= pci_get_bus(pci_dev
);
1015 /* Only pci bridges can be attached to extra PCI root buses */
1016 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !pc
->is_bridge
) {
1018 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1019 bus
->parent_dev
->name
);
1024 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
1025 devfn
+= PCI_FUNC_MAX
) {
1026 if (pci_bus_devfn_available(bus
, devfn
) &&
1027 !pci_bus_devfn_reserved(bus
, devfn
)) {
1031 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
1032 "or reserved", name
);
1035 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
1036 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1038 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1040 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1041 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1043 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1044 bus
->devices
[devfn
]->name
);
1046 } else if (dev
->hotplugged
&&
1047 pci_get_function_0(pci_dev
)) {
1048 error_setg(errp
, "PCI: slot %d function 0 already occupied by %s,"
1049 " new func %s cannot be exposed to guest.",
1050 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1051 pci_get_function_0(pci_dev
)->name
,
1057 pci_dev
->devfn
= devfn
;
1058 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1059 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1061 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1062 "bus master container", UINT64_MAX
);
1063 address_space_init(&pci_dev
->bus_master_as
,
1064 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1066 if (phase_check(PHASE_MACHINE_READY
)) {
1067 pci_init_bus_master(pci_dev
);
1069 pci_dev
->irq_state
= 0;
1070 pci_config_alloc(pci_dev
);
1072 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1073 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1074 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1075 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1077 if (!pc
->is_bridge
) {
1078 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1079 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1080 pc
->subsystem_vendor_id
);
1081 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1084 pci_set_default_subsystem_id(pci_dev
);
1087 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1088 assert(!pc
->subsystem_vendor_id
);
1089 assert(!pc
->subsystem_id
);
1091 pci_init_cmask(pci_dev
);
1092 pci_init_wmask(pci_dev
);
1093 pci_init_w1cmask(pci_dev
);
1094 if (pc
->is_bridge
) {
1095 pci_init_mask_bridge(pci_dev
);
1097 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1099 error_propagate(errp
, local_err
);
1100 do_pci_unregister_device(pci_dev
);
1105 config_read
= pci_default_read_config
;
1107 config_write
= pci_default_write_config
;
1108 pci_dev
->config_read
= config_read
;
1109 pci_dev
->config_write
= config_write
;
1110 bus
->devices
[devfn
] = pci_dev
;
1111 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1115 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1120 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1121 r
= &pci_dev
->io_regions
[i
];
1122 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1124 memory_region_del_subregion(r
->address_space
, r
->memory
);
1127 pci_unregister_vga(pci_dev
);
1130 static void pci_qdev_unrealize(DeviceState
*dev
)
1132 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1133 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1135 pci_unregister_io_regions(pci_dev
);
1136 pci_del_option_rom(pci_dev
);
1142 pci_device_deassert_intx(pci_dev
);
1143 do_pci_unregister_device(pci_dev
);
1146 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1147 uint8_t type
, MemoryRegion
*memory
)
1150 uint32_t addr
; /* offset in pci config space */
1152 pcibus_t size
= memory_region_size(memory
);
1155 assert(region_num
>= 0);
1156 assert(region_num
< PCI_NUM_REGIONS
);
1157 assert(is_power_of_2(size
));
1159 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
1161 pci_dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1162 assert(hdr_type
!= PCI_HEADER_TYPE_BRIDGE
|| region_num
< 2);
1164 r
= &pci_dev
->io_regions
[region_num
];
1165 r
->addr
= PCI_BAR_UNMAPPED
;
1169 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1170 ? pci_get_bus(pci_dev
)->address_space_io
1171 : pci_get_bus(pci_dev
)->address_space_mem
;
1173 wmask
= ~(size
- 1);
1174 if (region_num
== PCI_ROM_SLOT
) {
1175 /* ROM enable bit is writable */
1176 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1179 addr
= pci_bar(pci_dev
, region_num
);
1180 pci_set_long(pci_dev
->config
+ addr
, type
);
1182 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1183 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1184 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1185 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1187 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1188 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1192 static void pci_update_vga(PCIDevice
*pci_dev
)
1196 if (!pci_dev
->has_vga
) {
1200 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1202 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1203 cmd
& PCI_COMMAND_MEMORY
);
1204 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1205 cmd
& PCI_COMMAND_IO
);
1206 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1207 cmd
& PCI_COMMAND_IO
);
1210 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1211 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1213 PCIBus
*bus
= pci_get_bus(pci_dev
);
1215 assert(!pci_dev
->has_vga
);
1217 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1218 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1219 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1220 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1222 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1223 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1224 memory_region_add_subregion_overlap(bus
->address_space_io
,
1225 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1227 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1228 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1229 memory_region_add_subregion_overlap(bus
->address_space_io
,
1230 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1231 pci_dev
->has_vga
= true;
1233 pci_update_vga(pci_dev
);
1236 void pci_unregister_vga(PCIDevice
*pci_dev
)
1238 PCIBus
*bus
= pci_get_bus(pci_dev
);
1240 if (!pci_dev
->has_vga
) {
1244 memory_region_del_subregion(bus
->address_space_mem
,
1245 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1246 memory_region_del_subregion(bus
->address_space_io
,
1247 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1248 memory_region_del_subregion(bus
->address_space_io
,
1249 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1250 pci_dev
->has_vga
= false;
1253 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1255 return pci_dev
->io_regions
[region_num
].addr
;
1258 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1259 int reg
, uint8_t type
, pcibus_t size
)
1261 pcibus_t new_addr
, last_addr
;
1262 int bar
= pci_bar(d
, reg
);
1263 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1264 Object
*machine
= qdev_get_machine();
1265 ObjectClass
*oc
= object_get_class(machine
);
1266 MachineClass
*mc
= MACHINE_CLASS(oc
);
1267 bool allow_0_address
= mc
->pci_allow_0_address
;
1269 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1270 if (!(cmd
& PCI_COMMAND_IO
)) {
1271 return PCI_BAR_UNMAPPED
;
1273 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1274 last_addr
= new_addr
+ size
- 1;
1275 /* Check if 32 bit BAR wraps around explicitly.
1276 * TODO: make priorities correct and remove this work around.
1278 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1279 (!allow_0_address
&& new_addr
== 0)) {
1280 return PCI_BAR_UNMAPPED
;
1285 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1286 return PCI_BAR_UNMAPPED
;
1288 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1289 new_addr
= pci_get_quad(d
->config
+ bar
);
1291 new_addr
= pci_get_long(d
->config
+ bar
);
1293 /* the ROM slot has a specific enable bit */
1294 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1295 return PCI_BAR_UNMAPPED
;
1297 new_addr
&= ~(size
- 1);
1298 last_addr
= new_addr
+ size
- 1;
1299 /* NOTE: we do not support wrapping */
1300 /* XXX: as we cannot support really dynamic
1301 mappings, we handle specific values as invalid
1303 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1304 (!allow_0_address
&& new_addr
== 0)) {
1305 return PCI_BAR_UNMAPPED
;
1308 /* Now pcibus_t is 64bit.
1309 * Check if 32 bit BAR wraps around explicitly.
1310 * Without this, PC ide doesn't work well.
1311 * TODO: remove this work around.
1313 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1314 return PCI_BAR_UNMAPPED
;
1318 * OS is allowed to set BAR beyond its addressable
1319 * bits. For example, 32 bit OS can set 64bit bar
1320 * to >4G. Check it. TODO: we might need to support
1321 * it in the future for e.g. PAE.
1323 if (last_addr
>= HWADDR_MAX
) {
1324 return PCI_BAR_UNMAPPED
;
1330 static void pci_update_mappings(PCIDevice
*d
)
1336 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1337 r
= &d
->io_regions
[i
];
1339 /* this region isn't registered */
1343 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1345 /* This bar isn't changed */
1346 if (new_addr
== r
->addr
)
1349 /* now do the real mapping */
1350 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1351 trace_pci_update_mappings_del(d
, pci_dev_bus_num(d
),
1354 i
, r
->addr
, r
->size
);
1355 memory_region_del_subregion(r
->address_space
, r
->memory
);
1358 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1359 trace_pci_update_mappings_add(d
, pci_dev_bus_num(d
),
1362 i
, r
->addr
, r
->size
);
1363 memory_region_add_subregion_overlap(r
->address_space
,
1364 r
->addr
, r
->memory
, 1);
1371 static inline int pci_irq_disabled(PCIDevice
*d
)
1373 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1376 /* Called after interrupt disabled field update in config space,
1377 * assert/deassert interrupts if necessary.
1378 * Gets original interrupt disable bit value (before update). */
1379 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1381 int i
, disabled
= pci_irq_disabled(d
);
1382 if (disabled
== was_irq_disabled
)
1384 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1385 int state
= pci_irq_state(d
, i
);
1386 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1390 uint32_t pci_default_read_config(PCIDevice
*d
,
1391 uint32_t address
, int len
)
1395 assert(address
+ len
<= pci_config_size(d
));
1397 if (pci_is_express_downstream_port(d
) &&
1398 ranges_overlap(address
, len
, d
->exp
.exp_cap
+ PCI_EXP_LNKSTA
, 2)) {
1399 pcie_sync_bridge_lnk(d
);
1401 memcpy(&val
, d
->config
+ address
, len
);
1402 return le32_to_cpu(val
);
1405 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1407 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1408 uint32_t val
= val_in
;
1410 assert(addr
+ l
<= pci_config_size(d
));
1412 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1413 uint8_t wmask
= d
->wmask
[addr
+ i
];
1414 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1415 assert(!(wmask
& w1cmask
));
1416 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1417 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1419 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1420 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1421 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1422 range_covers_byte(addr
, l
, PCI_COMMAND
))
1423 pci_update_mappings(d
);
1425 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1426 pci_update_irq_disabled(d
, was_irq_disabled
);
1427 memory_region_set_enabled(&d
->bus_master_enable_region
,
1428 pci_get_word(d
->config
+ PCI_COMMAND
)
1429 & PCI_COMMAND_MASTER
);
1432 msi_write_config(d
, addr
, val_in
, l
);
1433 msix_write_config(d
, addr
, val_in
, l
);
1436 /***********************************************************/
1437 /* generic PCI irq support */
1439 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1440 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1442 PCIDevice
*pci_dev
= opaque
;
1445 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1449 pci_set_irq_state(pci_dev
, irq_num
, level
);
1450 pci_update_irq_status(pci_dev
);
1451 if (pci_irq_disabled(pci_dev
))
1453 pci_change_irq_level(pci_dev
, irq_num
, change
);
1456 static inline int pci_intx(PCIDevice
*pci_dev
)
1458 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1461 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1463 int intx
= pci_intx(pci_dev
);
1465 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1468 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1470 int intx
= pci_intx(pci_dev
);
1471 pci_irq_handler(pci_dev
, intx
, level
);
1474 /* Special hooks used by device assignment */
1475 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1477 assert(pci_bus_is_root(bus
));
1478 bus
->route_intx_to_irq
= route_intx_to_irq
;
1481 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1486 bus
= pci_get_bus(dev
);
1487 pin
= bus
->map_irq(dev
, pin
);
1488 dev
= bus
->parent_dev
;
1491 if (!bus
->route_intx_to_irq
) {
1492 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1493 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1494 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1497 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1500 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1502 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1505 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1511 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1512 dev
= bus
->devices
[i
];
1513 if (dev
&& dev
->intx_routing_notifier
) {
1514 dev
->intx_routing_notifier(dev
);
1518 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1519 pci_bus_fire_intx_routing_notifier(sec
);
1523 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1524 PCIINTxRoutingNotifier notifier
)
1526 dev
->intx_routing_notifier
= notifier
;
1530 * PCI-to-PCI bridge specification
1531 * 9.1: Interrupt routing. Table 9-1
1533 * the PCI Express Base Specification, Revision 2.1
1534 * 2.2.8.1: INTx interrutp signaling - Rules
1535 * the Implementation Note
1539 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1540 * 0-origin unlike PCI interrupt pin register.
1542 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1544 return pci_swizzle(PCI_SLOT(pci_dev
->devfn
), pin
);
1547 /***********************************************************/
1548 /* monitor info on PCI */
1553 const char *fw_name
;
1554 uint16_t fw_ign_bits
;
1557 static const pci_class_desc pci_class_descriptions
[] =
1559 { 0x0001, "VGA controller", "display"},
1560 { 0x0100, "SCSI controller", "scsi"},
1561 { 0x0101, "IDE controller", "ide"},
1562 { 0x0102, "Floppy controller", "fdc"},
1563 { 0x0103, "IPI controller", "ipi"},
1564 { 0x0104, "RAID controller", "raid"},
1565 { 0x0106, "SATA controller"},
1566 { 0x0107, "SAS controller"},
1567 { 0x0180, "Storage controller"},
1568 { 0x0200, "Ethernet controller", "ethernet"},
1569 { 0x0201, "Token Ring controller", "token-ring"},
1570 { 0x0202, "FDDI controller", "fddi"},
1571 { 0x0203, "ATM controller", "atm"},
1572 { 0x0280, "Network controller"},
1573 { 0x0300, "VGA controller", "display", 0x00ff},
1574 { 0x0301, "XGA controller"},
1575 { 0x0302, "3D controller"},
1576 { 0x0380, "Display controller"},
1577 { 0x0400, "Video controller", "video"},
1578 { 0x0401, "Audio controller", "sound"},
1580 { 0x0403, "Audio controller", "sound"},
1581 { 0x0480, "Multimedia controller"},
1582 { 0x0500, "RAM controller", "memory"},
1583 { 0x0501, "Flash controller", "flash"},
1584 { 0x0580, "Memory controller"},
1585 { 0x0600, "Host bridge", "host"},
1586 { 0x0601, "ISA bridge", "isa"},
1587 { 0x0602, "EISA bridge", "eisa"},
1588 { 0x0603, "MC bridge", "mca"},
1589 { 0x0604, "PCI bridge", "pci-bridge"},
1590 { 0x0605, "PCMCIA bridge", "pcmcia"},
1591 { 0x0606, "NUBUS bridge", "nubus"},
1592 { 0x0607, "CARDBUS bridge", "cardbus"},
1593 { 0x0608, "RACEWAY bridge"},
1594 { 0x0680, "Bridge"},
1595 { 0x0700, "Serial port", "serial"},
1596 { 0x0701, "Parallel port", "parallel"},
1597 { 0x0800, "Interrupt controller", "interrupt-controller"},
1598 { 0x0801, "DMA controller", "dma-controller"},
1599 { 0x0802, "Timer", "timer"},
1600 { 0x0803, "RTC", "rtc"},
1601 { 0x0900, "Keyboard", "keyboard"},
1602 { 0x0901, "Pen", "pen"},
1603 { 0x0902, "Mouse", "mouse"},
1604 { 0x0A00, "Dock station", "dock", 0x00ff},
1605 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1606 { 0x0c00, "Fireware contorller", "fireware"},
1607 { 0x0c01, "Access bus controller", "access-bus"},
1608 { 0x0c02, "SSA controller", "ssa"},
1609 { 0x0c03, "USB controller", "usb"},
1610 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1615 static void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1616 void (*fn
)(PCIBus
*b
,
1624 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1625 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1632 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1633 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1636 bus
= pci_find_bus_nr(bus
, bus_num
);
1639 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1643 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1644 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1651 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1652 d
= bus
->devices
[devfn
];
1659 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1660 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1663 bus
= pci_find_bus_nr(bus
, bus_num
);
1666 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1670 static const pci_class_desc
*get_class_desc(int class)
1672 const pci_class_desc
*desc
;
1674 desc
= pci_class_descriptions
;
1675 while (desc
->desc
&& class != desc
->class) {
1682 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1684 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1686 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1689 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1690 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1691 PciMemoryRegionList
*region
;
1697 region
= g_malloc0(sizeof(*region
));
1698 region
->value
= g_malloc0(sizeof(*region
->value
));
1700 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1701 region
->value
->type
= g_strdup("io");
1703 region
->value
->type
= g_strdup("memory");
1704 region
->value
->has_prefetch
= true;
1705 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1706 region
->value
->has_mem_type_64
= true;
1707 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1710 region
->value
->bar
= i
;
1711 region
->value
->address
= r
->addr
;
1712 region
->value
->size
= r
->size
;
1714 /* XXX: waiting for the qapi to support GSList */
1716 head
= cur_item
= region
;
1718 cur_item
->next
= region
;
1726 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1729 PciBridgeInfo
*info
;
1730 PciMemoryRange
*range
;
1732 info
= g_new0(PciBridgeInfo
, 1);
1734 info
->bus
= g_new0(PciBusInfo
, 1);
1735 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1736 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1737 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1739 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1740 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1741 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1743 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1744 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1745 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1747 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1748 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1749 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1751 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1752 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1754 info
->has_devices
= true;
1755 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1762 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1765 const pci_class_desc
*desc
;
1766 PciDeviceInfo
*info
;
1770 info
= g_new0(PciDeviceInfo
, 1);
1771 info
->bus
= bus_num
;
1772 info
->slot
= PCI_SLOT(dev
->devfn
);
1773 info
->function
= PCI_FUNC(dev
->devfn
);
1775 info
->class_info
= g_new0(PciDeviceClass
, 1);
1776 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1777 info
->class_info
->q_class
= class;
1778 desc
= get_class_desc(class);
1780 info
->class_info
->has_desc
= true;
1781 info
->class_info
->desc
= g_strdup(desc
->desc
);
1784 info
->id
= g_new0(PciDeviceId
, 1);
1785 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1786 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1787 info
->regions
= qmp_query_pci_regions(dev
);
1788 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1790 info
->irq_pin
= dev
->config
[PCI_INTERRUPT_PIN
];
1791 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1792 info
->has_irq
= true;
1793 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1796 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1797 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1798 info
->has_pci_bridge
= true;
1799 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1800 } else if (type
== PCI_HEADER_TYPE_NORMAL
) {
1801 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1802 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_SUBSYSTEM_ID
);
1803 info
->id
->subsystem_vendor
=
1804 pci_get_word(dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
);
1805 } else if (type
== PCI_HEADER_TYPE_CARDBUS
) {
1806 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1807 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_ID
);
1808 info
->id
->subsystem_vendor
=
1809 pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_VENDOR_ID
);
1815 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1817 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1821 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1822 dev
= bus
->devices
[devfn
];
1824 info
= g_malloc0(sizeof(*info
));
1825 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1827 /* XXX: waiting for the qapi to support GSList */
1829 head
= cur_item
= info
;
1831 cur_item
->next
= info
;
1840 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1842 PciInfo
*info
= NULL
;
1844 bus
= pci_find_bus_nr(bus
, bus_num
);
1846 info
= g_malloc0(sizeof(*info
));
1847 info
->bus
= bus_num
;
1848 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1854 PciInfoList
*qmp_query_pci(Error
**errp
)
1856 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1857 PCIHostState
*host_bridge
;
1859 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1860 info
= g_malloc0(sizeof(*info
));
1861 info
->value
= qmp_query_pci_bus(host_bridge
->bus
,
1862 pci_bus_num(host_bridge
->bus
));
1864 /* XXX: waiting for the qapi to support GSList */
1866 head
= cur_item
= info
;
1868 cur_item
->next
= info
;
1876 /* Initialize a PCI NIC. */
1877 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1878 const char *default_model
,
1879 const char *default_devaddr
)
1881 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1883 GPtrArray
*pci_nic_models
;
1892 if (nd
->model
&& !strcmp(nd
->model
, "virtio")) {
1894 nd
->model
= g_strdup("virtio-net-pci");
1897 list
= object_class_get_list_sorted(TYPE_PCI_DEVICE
, false);
1898 pci_nic_models
= g_ptr_array_new();
1900 DeviceClass
*dc
= OBJECT_CLASS_CHECK(DeviceClass
, list
->data
,
1903 if (test_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
) &&
1904 dc
->user_creatable
) {
1905 const char *name
= object_class_get_name(list
->data
);
1907 * A network device might also be something else than a NIC, see
1908 * e.g. the "rocker" device. Thus we have to look for the "netdev"
1909 * property, too. Unfortunately, some devices like virtio-net only
1910 * create this property during instance_init, so we have to create
1911 * a temporary instance here to be able to check it.
1913 Object
*obj
= object_new_with_class(OBJECT_CLASS(dc
));
1914 if (object_property_find(obj
, "netdev")) {
1915 g_ptr_array_add(pci_nic_models
, (gpointer
)name
);
1920 g_slist_free_1(list
);
1923 g_ptr_array_add(pci_nic_models
, NULL
);
1925 if (qemu_show_nic_models(nd
->model
, (const char **)pci_nic_models
->pdata
)) {
1929 i
= qemu_find_nic_model(nd
, (const char **)pci_nic_models
->pdata
,
1936 error_report("No primary PCI bus");
1940 assert(!rootbus
->parent_dev
);
1946 if (pci_parse_devaddr(devaddr
, &dom
, &busnr
, &slot
, NULL
) < 0) {
1947 error_report("Invalid PCI device address %s for device %s",
1948 devaddr
, nd
->model
);
1953 error_report("No support for non-zero PCI domains");
1957 devfn
= PCI_DEVFN(slot
, 0);
1960 bus
= pci_find_bus_nr(rootbus
, busnr
);
1962 error_report("Invalid PCI device address %s for device %s",
1963 devaddr
, nd
->model
);
1967 pci_dev
= pci_new(devfn
, nd
->model
);
1968 dev
= &pci_dev
->qdev
;
1969 qdev_set_nic_properties(dev
, nd
);
1970 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
1971 g_ptr_array_free(pci_nic_models
, true);
1975 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1977 switch (vga_interface_type
) {
1979 return pci_create_simple(bus
, -1, "cirrus-vga");
1981 return pci_create_simple(bus
, -1, "qxl-vga");
1983 return pci_create_simple(bus
, -1, "VGA");
1985 return pci_create_simple(bus
, -1, "vmware-svga");
1987 return pci_create_simple(bus
, -1, "virtio-vga");
1989 default: /* Other non-PCI types. Checking for unsupported types is already
1995 /* Whether a given bus number is in range of the secondary
1996 * bus of the given bridge device. */
1997 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1999 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
2000 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
2001 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
2002 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
2005 /* Whether a given bus number is in a range of a root bus */
2006 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
2010 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
2011 PCIDevice
*dev
= bus
->devices
[i
];
2013 if (dev
&& PCI_DEVICE_GET_CLASS(dev
)->is_bridge
) {
2014 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
2023 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
2031 if (pci_bus_num(bus
) == bus_num
) {
2035 /* Consider all bus numbers in range for the host pci bridge. */
2036 if (!pci_bus_is_root(bus
) &&
2037 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
2042 for (; bus
; bus
= sec
) {
2043 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2044 if (pci_bus_num(sec
) == bus_num
) {
2047 /* PXB buses assumed to be children of bus 0 */
2048 if (pci_bus_is_root(sec
)) {
2049 if (pci_root_bus_in_range(sec
, bus_num
)) {
2053 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
2063 void pci_for_each_bus_depth_first(PCIBus
*bus
,
2064 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
2065 void (*end
)(PCIBus
*bus
, void *state
),
2076 state
= begin(bus
, parent_state
);
2078 state
= parent_state
;
2081 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2082 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
2091 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
2093 bus
= pci_find_bus_nr(bus
, bus_num
);
2098 return bus
->devices
[devfn
];
2101 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2103 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2104 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2105 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2106 Error
*local_err
= NULL
;
2107 bool is_default_rom
;
2110 /* initialize cap_present for pci_is_express() and pci_config_size(),
2111 * Note that hybrid PCIs are not set automatically and need to manage
2112 * QEMU_PCI_CAP_EXPRESS manually */
2113 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2114 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2115 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2118 pci_dev
= do_pci_register_device(pci_dev
,
2119 object_get_typename(OBJECT(qdev
)),
2120 pci_dev
->devfn
, errp
);
2121 if (pci_dev
== NULL
)
2125 pc
->realize(pci_dev
, &local_err
);
2127 error_propagate(errp
, local_err
);
2128 do_pci_unregister_device(pci_dev
);
2133 if (pci_dev
->failover_pair_id
) {
2134 if (!pci_bus_is_express(pci_get_bus(pci_dev
))) {
2135 error_setg(errp
, "failover primary device must be on "
2137 pci_qdev_unrealize(DEVICE(pci_dev
));
2140 class_id
= pci_get_word(pci_dev
->config
+ PCI_CLASS_DEVICE
);
2141 if (class_id
!= PCI_CLASS_NETWORK_ETHERNET
) {
2142 error_setg(errp
, "failover primary device is not an "
2144 pci_qdev_unrealize(DEVICE(pci_dev
));
2147 if (!(pci_dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)
2148 && (PCI_FUNC(pci_dev
->devfn
) == 0)) {
2149 qdev
->allow_unplug_during_migration
= true;
2151 error_setg(errp
, "failover: primary device must be in its own "
2153 pci_qdev_unrealize(DEVICE(pci_dev
));
2156 qdev
->allow_unplug_during_migration
= true;
2160 is_default_rom
= false;
2161 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2162 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2163 is_default_rom
= true;
2166 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2168 error_propagate(errp
, local_err
);
2169 pci_qdev_unrealize(DEVICE(pci_dev
));
2174 PCIDevice
*pci_new_multifunction(int devfn
, bool multifunction
,
2179 dev
= qdev_new(name
);
2180 qdev_prop_set_int32(dev
, "addr", devfn
);
2181 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2182 return PCI_DEVICE(dev
);
2185 PCIDevice
*pci_new(int devfn
, const char *name
)
2187 return pci_new_multifunction(devfn
, false, name
);
2190 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
)
2192 return qdev_realize_and_unref(&dev
->qdev
, &bus
->qbus
, errp
);
2195 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2199 PCIDevice
*dev
= pci_new_multifunction(devfn
, multifunction
, name
);
2200 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2204 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2206 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
2209 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2211 int offset
= PCI_CONFIG_HEADER_SIZE
;
2213 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2216 else if (i
- offset
+ 1 == size
)
2222 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2227 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2230 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2231 prev
= next
+ PCI_CAP_LIST_NEXT
)
2232 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2240 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2242 uint8_t next
, prev
, found
= 0;
2244 if (!(pdev
->used
[offset
])) {
2248 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2250 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2251 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2252 if (next
<= offset
&& next
> found
) {
2259 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2260 This is needed for an option rom which is used for more than one device. */
2261 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
2265 uint16_t rom_vendor_id
;
2266 uint16_t rom_device_id
;
2268 uint16_t pcir_offset
;
2271 /* Words in rom data are little endian (like in PCI configuration),
2272 so they can be read / written with pci_get_word / pci_set_word. */
2274 /* Only a valid rom will be patched. */
2275 rom_magic
= pci_get_word(ptr
);
2276 if (rom_magic
!= 0xaa55) {
2277 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2280 pcir_offset
= pci_get_word(ptr
+ 0x18);
2281 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2282 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2286 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2287 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2288 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2289 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2291 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2292 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2296 if (vendor_id
!= rom_vendor_id
) {
2297 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2298 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2299 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2300 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2302 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2305 if (device_id
!= rom_device_id
) {
2306 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2307 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2308 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2309 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2311 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2315 /* Add an option rom for the device */
2316 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2323 const VMStateDescription
*vmsd
;
2327 if (strlen(pdev
->romfile
) == 0)
2330 if (!pdev
->rom_bar
) {
2332 * Load rom via fw_cfg instead of creating a rom bar,
2333 * for 0.11 compatibility.
2335 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2338 * Hot-plugged devices can't use the option ROM
2339 * if the rom bar is disabled.
2341 if (DEVICE(pdev
)->hotplugged
) {
2342 error_setg(errp
, "Hot-plugged device without ROM bar"
2343 " can't have an option ROM");
2347 if (class == 0x0300) {
2348 rom_add_vga(pdev
->romfile
);
2350 rom_add_option(pdev
->romfile
, -1);
2355 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2357 path
= g_strdup(pdev
->romfile
);
2360 size
= get_image_size(path
);
2362 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2365 } else if (size
== 0) {
2366 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2370 size
= pow2ceil(size
);
2372 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2375 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2377 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2379 pdev
->has_rom
= true;
2380 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, size
, &error_fatal
);
2381 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2382 if (load_image_size(path
, ptr
, size
) < 0) {
2383 error_setg(errp
, "failed to load romfile \"%s\"", pdev
->romfile
);
2389 if (is_default_rom
) {
2390 /* Only the default rom images will be patched (if needed). */
2391 pci_patch_ids(pdev
, ptr
, size
);
2394 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2397 static void pci_del_option_rom(PCIDevice
*pdev
)
2402 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2403 pdev
->has_rom
= false;
2407 * On success, pci_add_capability() returns a positive value
2408 * that the offset of the pci capability.
2409 * On failure, it sets an error and returns a negative error
2412 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2413 uint8_t offset
, uint8_t size
,
2417 int i
, overlapping_cap
;
2420 offset
= pci_find_space(pdev
, size
);
2421 /* out of PCI config space is programming error */
2424 /* Verify that capabilities don't overlap. Note: device assignment
2425 * depends on this check to verify that the device is not broken.
2426 * Should never trigger for emulated devices, but it's helpful
2427 * for debugging these. */
2428 for (i
= offset
; i
< offset
+ size
; i
++) {
2429 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2430 if (overlapping_cap
) {
2431 error_setg(errp
, "%s:%02x:%02x.%x "
2432 "Attempt to add PCI capability %x at offset "
2433 "%x overlaps existing capability %x at offset %x",
2434 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2435 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2436 cap_id
, offset
, overlapping_cap
, i
);
2442 config
= pdev
->config
+ offset
;
2443 config
[PCI_CAP_LIST_ID
] = cap_id
;
2444 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2445 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2446 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2447 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2448 /* Make capability read-only by default */
2449 memset(pdev
->wmask
+ offset
, 0, size
);
2450 /* Check capability by default */
2451 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2455 /* Unlink capability from the pci config space. */
2456 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2458 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2461 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2462 /* Make capability writable again */
2463 memset(pdev
->wmask
+ offset
, 0xff, size
);
2464 memset(pdev
->w1cmask
+ offset
, 0, size
);
2465 /* Clear cmask as device-specific registers can't be checked */
2466 memset(pdev
->cmask
+ offset
, 0, size
);
2467 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2469 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2470 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2473 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2475 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2478 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2480 PCIDevice
*d
= (PCIDevice
*)dev
;
2481 const pci_class_desc
*desc
;
2486 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2487 desc
= pci_class_descriptions
;
2488 while (desc
->desc
&& class != desc
->class)
2491 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2493 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2496 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2497 "pci id %04x:%04x (sub %04x:%04x)\n",
2498 indent
, "", ctxt
, pci_dev_bus_num(d
),
2499 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2500 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2501 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2502 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2503 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2504 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2505 r
= &d
->io_regions
[i
];
2508 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2509 " [0x%"FMT_PCIBUS
"]\n",
2511 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2512 r
->addr
, r
->addr
+ r
->size
- 1);
2516 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2518 PCIDevice
*d
= (PCIDevice
*)dev
;
2519 const char *name
= NULL
;
2520 const pci_class_desc
*desc
= pci_class_descriptions
;
2521 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2523 while (desc
->desc
&&
2524 (class & ~desc
->fw_ign_bits
) !=
2525 (desc
->class & ~desc
->fw_ign_bits
)) {
2530 name
= desc
->fw_name
;
2534 pstrcpy(buf
, len
, name
);
2536 snprintf(buf
, len
, "pci%04x,%04x",
2537 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2538 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2544 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2546 PCIDevice
*d
= (PCIDevice
*)dev
;
2547 char path
[50], name
[33];
2550 off
= snprintf(path
, sizeof(path
), "%s@%x",
2551 pci_dev_fw_name(dev
, name
, sizeof name
),
2552 PCI_SLOT(d
->devfn
));
2553 if (PCI_FUNC(d
->devfn
))
2554 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2555 return g_strdup(path
);
2558 static char *pcibus_get_dev_path(DeviceState
*dev
)
2560 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2563 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2564 * 00 is added here to make this format compatible with
2565 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2566 * Slot.Function list specifies the slot and function numbers for all
2567 * devices on the path from root to the specific device. */
2568 const char *root_bus_path
;
2570 char slot
[] = ":SS.F";
2571 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2576 root_bus_path
= pci_root_bus_path(d
);
2577 root_bus_len
= strlen(root_bus_path
);
2579 /* Calculate # of slots on path between device and root. */;
2581 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2585 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2587 /* Allocate memory, fill in the terminating null byte. */
2588 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2589 path
[path_len
] = '\0';
2591 memcpy(path
, root_bus_path
, root_bus_len
);
2593 /* Fill in slot numbers. We walk up from device to root, so need to print
2594 * them in the reverse order, last to first. */
2595 p
= path
+ path_len
;
2596 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2598 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2599 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2600 assert(s
== slot_len
);
2601 memcpy(p
, slot
, slot_len
);
2607 static int pci_qdev_find_recursive(PCIBus
*bus
,
2608 const char *id
, PCIDevice
**pdev
)
2610 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2615 /* roughly check if given qdev is pci device */
2616 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2617 *pdev
= PCI_DEVICE(qdev
);
2623 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2625 PCIHostState
*host_bridge
;
2628 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2629 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2634 if (tmp
!= -ENODEV
) {
2642 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2644 return pci_get_bus(dev
)->address_space_mem
;
2647 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2649 return pci_get_bus(dev
)->address_space_io
;
2652 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2654 DeviceClass
*k
= DEVICE_CLASS(klass
);
2656 k
->realize
= pci_qdev_realize
;
2657 k
->unrealize
= pci_qdev_unrealize
;
2658 k
->bus_type
= TYPE_PCI_BUS
;
2659 device_class_set_props(k
, pci_props
);
2662 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2664 if (!object_class_is_abstract(klass
)) {
2665 ObjectClass
*conventional
=
2666 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2668 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2669 assert(conventional
|| pcie
);
2673 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2675 PCIBus
*bus
= pci_get_bus(dev
);
2676 PCIBus
*iommu_bus
= bus
;
2677 uint8_t devfn
= dev
->devfn
;
2679 while (iommu_bus
&& !iommu_bus
->iommu_fn
&& iommu_bus
->parent_dev
) {
2680 PCIBus
*parent_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2683 * The requester ID of the provided device may be aliased, as seen from
2684 * the IOMMU, due to topology limitations. The IOMMU relies on a
2685 * requester ID to provide a unique AddressSpace for devices, but
2686 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2687 * to-PCI bridge creates and accepts transactions on behalf of down-
2688 * stream devices. When doing so, all downstream devices are masked
2689 * (aliased) behind a single requester ID. The requester ID used
2690 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2691 * bridges, with a PCIe capability indicating such, follow the
2692 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2693 * where the bridge uses the seconary bus as the bridge portion of the
2694 * requester ID and devfn of 00.0. For other bridges, typically those
2695 * found on the root complex such as the dmi-to-pci-bridge, we follow
2696 * the convention of typical bare-metal hardware, which uses the
2697 * requester ID of the bridge itself. There are device specific
2698 * exceptions to these rules, but these are the defaults that the
2699 * Linux kernel uses when determining DMA aliases itself and believed
2700 * to be true for the bare metal equivalents of the devices emulated
2703 if (!pci_bus_is_express(iommu_bus
)) {
2704 PCIDevice
*parent
= iommu_bus
->parent_dev
;
2706 if (pci_is_express(parent
) &&
2707 pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2708 devfn
= PCI_DEVFN(0, 0);
2711 devfn
= parent
->devfn
;
2716 iommu_bus
= parent_bus
;
2718 if (iommu_bus
&& iommu_bus
->iommu_fn
) {
2719 return iommu_bus
->iommu_fn(bus
, iommu_bus
->iommu_opaque
, devfn
);
2721 return &address_space_memory
;
2724 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2727 bus
->iommu_opaque
= opaque
;
2730 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2732 Range
*range
= opaque
;
2733 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2734 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2737 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2741 if (pc
->is_bridge
) {
2742 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2743 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2745 base
= MAX(base
, 0x1ULL
<< 32);
2747 if (limit
>= base
) {
2749 range_set_bounds(&pref_range
, base
, limit
);
2750 range_extend(range
, &pref_range
);
2753 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2754 PCIIORegion
*r
= &dev
->io_regions
[i
];
2759 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2760 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2764 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2765 upb
= lob
+ r
->size
- 1;
2766 if (lob
== PCI_BAR_UNMAPPED
) {
2770 lob
= MAX(lob
, 0x1ULL
<< 32);
2773 range_set_bounds(®ion_range
, lob
, upb
);
2774 range_extend(range
, ®ion_range
);
2779 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2781 range_make_empty(range
);
2782 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2785 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2787 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2789 /* Device associated with an upstream port.
2790 * As there are several types of these, it's easier to check the
2791 * parent device: upstream ports are always connected to
2792 * root or downstream ports.
2794 return parent_dev
&&
2795 pci_is_express(parent_dev
) &&
2796 parent_dev
->exp
.exp_cap
&&
2797 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2798 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2801 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2803 PCIBus
*bus
= pci_get_bus(pci_dev
);
2805 if(pcie_has_upstream_port(pci_dev
)) {
2806 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2807 return bus
->devices
[0];
2809 /* Other bus types might support multiple devices at slots 0-31 */
2810 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2814 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2817 if (msix_enabled(dev
)) {
2818 msg
= msix_get_message(dev
, vector
);
2819 } else if (msi_enabled(dev
)) {
2820 msg
= msi_get_message(dev
, vector
);
2822 /* Should never happen */
2823 error_report("%s: unknown interrupt type", __func__
);
2829 static const TypeInfo pci_device_type_info
= {
2830 .name
= TYPE_PCI_DEVICE
,
2831 .parent
= TYPE_DEVICE
,
2832 .instance_size
= sizeof(PCIDevice
),
2834 .class_size
= sizeof(PCIDeviceClass
),
2835 .class_init
= pci_device_class_init
,
2836 .class_base_init
= pci_device_class_base_init
,
2839 static void pci_register_types(void)
2841 type_register_static(&pci_bus_info
);
2842 type_register_static(&pcie_bus_info
);
2843 type_register_static(&conventional_pci_interface_info
);
2844 type_register_static(&pcie_interface_info
);
2845 type_register_static(&pci_device_type_info
);
2848 type_init(pci_register_types
)