hw/intc/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/thread.h"
  22 #include "hw/i386/apic_internal.h"
  23 #include "hw/i386/apic.h"
  24 #include "hw/i386/ioapic.h"
  25 #include "hw/pci/msi.h"
  26 #include "qemu/host-utils.h"
  27 #include "trace.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/i386/apic-msidef.h"
  30 #include "qapi/error.h"
  31
  32 #define MAX_APICS 255
  33 #define MAX_APIC_WORDS 8
  34
  35 #define SYNC_FROM_VAPIC                 0x1
  36 #define SYNC_TO_VAPIC                   0x2
  37 #define SYNC_ISR_IRR_TO_VAPIC           0x4
  38
  39 static APICCommonState *local_apics[MAX_APICS + 1];
  40
  41 #define TYPE_APIC "apic"
  42 #define APIC(obj) \
  43     OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC)
  44
  45 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
  46 static void apic_update_irq(APICCommonState *s);
  47 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
  48                                       uint8_t dest, uint8_t dest_mode);
  49
  50 /* Find first bit starting from msb */
  51 static int apic_fls_bit(uint32_t value)
  52 {
  53     return 31 - clz32(value);
  54 }
  55
  56 /* Find first bit starting from lsb */
  57 static int apic_ffs_bit(uint32_t value)
  58 {
  59     return ctz32(value);
  60 }
  61
  62 static inline void apic_reset_bit(uint32_t *tab, int index)
  63 {
  64     int i, mask;
  65     i = index >> 5;
  66     mask = 1 << (index & 0x1f);
  67     tab[i] &= ~mask;
  68 }
  69
  70 /* return -1 if no bit is set */
  71 static int get_highest_priority_int(uint32_t *tab)
  72 {
  73     int i;
  74     for (i = 7; i >= 0; i--) {
  75         if (tab[i] != 0) {
  76             return i * 32 + apic_fls_bit(tab[i]);
  77         }
  78     }
  79     return -1;
  80 }
  81
  82 static void apic_sync_vapic(APICCommonState *s, int sync_type)
  83 {
  84     VAPICState vapic_state;
  85     size_t length;
  86     off_t start;
  87     int vector;
  88
  89     if (!s->vapic_paddr) {
  90         return;
  91     }
  92     if (sync_type & SYNC_FROM_VAPIC) {
  93         cpu_physical_memory_read(s->vapic_paddr, &vapic_state,
  94                                  sizeof(vapic_state));
  95         s->tpr = vapic_state.tpr;
  96     }
  97     if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
  98         start = offsetof(VAPICState, isr);
  99         length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
 100
 101         if (sync_type & SYNC_TO_VAPIC) {
 102             assert(qemu_cpu_is_self(CPU(s->cpu)));
 103
 104             vapic_state.tpr = s->tpr;
 105             vapic_state.enabled = 1;
 106             start = 0;
 107             length = sizeof(VAPICState);
 108         }
 109
 110         vector = get_highest_priority_int(s->isr);
 111         if (vector < 0) {
 112             vector = 0;
 113         }
 114         vapic_state.isr = vector & 0xf0;
 115
 116         vapic_state.zero = 0;
 117
 118         vector = get_highest_priority_int(s->irr);
 119         if (vector < 0) {
 120             vector = 0;
 121         }
 122         vapic_state.irr = vector & 0xff;
 123
 124         address_space_write_rom(&address_space_memory,
 125                                 s->vapic_paddr + start,
 126                                 MEMTXATTRS_UNSPECIFIED,
 127                                 ((void *)&vapic_state) + start, length);
 128     }
 129 }
 130
 131 static void apic_vapic_base_update(APICCommonState *s)
 132 {
 133     apic_sync_vapic(s, SYNC_TO_VAPIC);
 134 }
 135
 136 static void apic_local_deliver(APICCommonState *s, int vector)
 137 {
 138     uint32_t lvt = s->lvt[vector];
 139     int trigger_mode;
 140
 141     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 142
 143     if (lvt & APIC_LVT_MASKED)
 144         return;
 145
 146     switch ((lvt >> 8) & 7) {
 147     case APIC_DM_SMI:
 148         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
 149         break;
 150
 151     case APIC_DM_NMI:
 152         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
 153         break;
 154
 155     case APIC_DM_EXTINT:
 156         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
 157         break;
 158
 159     case APIC_DM_FIXED:
 160         trigger_mode = APIC_TRIGGER_EDGE;
 161         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 162             (lvt & APIC_LVT_LEVEL_TRIGGER))
 163             trigger_mode = APIC_TRIGGER_LEVEL;
 164         apic_set_irq(s, lvt & 0xff, trigger_mode);
 165     }
 166 }
 167
 168 void apic_deliver_pic_intr(DeviceState *dev, int level)
 169 {
 170     APICCommonState *s = APIC(dev);
 171
 172     if (level) {
 173         apic_local_deliver(s, APIC_LVT_LINT0);
 174     } else {
 175         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 176
 177         switch ((lvt >> 8) & 7) {
 178         case APIC_DM_FIXED:
 179             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 180                 break;
 181             apic_reset_bit(s->irr, lvt & 0xff);
 182             /* fall through */
 183         case APIC_DM_EXTINT:
 184             apic_update_irq(s);
 185             break;
 186         }
 187     }
 188 }
 189
 190 static void apic_external_nmi(APICCommonState *s)
 191 {
 192     apic_local_deliver(s, APIC_LVT_LINT1);
 193 }
 194
 195 #define foreach_apic(apic, deliver_bitmask, code) \
 196 {\
 197     int __i, __j;\
 198     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 199         uint32_t __mask = deliver_bitmask[__i];\
 200         if (__mask) {\
 201             for(__j = 0; __j < 32; __j++) {\
 202                 if (__mask & (1U << __j)) {\
 203                     apic = local_apics[__i * 32 + __j];\
 204                     if (apic) {\
 205                         code;\
 206                     }\
 207                 }\
 208             }\
 209         }\
 210     }\
 211 }
 212
 213 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 214                              uint8_t delivery_mode, uint8_t vector_num,
 215                              uint8_t trigger_mode)
 216 {
 217     APICCommonState *apic_iter;
 218
 219     switch (delivery_mode) {
 220         case APIC_DM_LOWPRI:
 221             /* XXX: search for focus processor, arbitration */
 222             {
 223                 int i, d;
 224                 d = -1;
 225                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 226                     if (deliver_bitmask[i]) {
 227                         d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
 228                         break;
 229                     }
 230                 }
 231                 if (d >= 0) {
 232                     apic_iter = local_apics[d];
 233                     if (apic_iter) {
 234                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 235                     }
 236                 }
 237             }
 238             return;
 239
 240         case APIC_DM_FIXED:
 241             break;
 242
 243         case APIC_DM_SMI:
 244             foreach_apic(apic_iter, deliver_bitmask,
 245                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
 246             );
 247             return;
 248
 249         case APIC_DM_NMI:
 250             foreach_apic(apic_iter, deliver_bitmask,
 251                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
 252             );
 253             return;
 254
 255         case APIC_DM_INIT:
 256             /* normal INIT IPI sent to processors */
 257             foreach_apic(apic_iter, deliver_bitmask,
 258                          cpu_interrupt(CPU(apic_iter->cpu),
 259                                        CPU_INTERRUPT_INIT)
 260             );
 261             return;
 262
 263         case APIC_DM_EXTINT:
 264             /* handled in I/O APIC code */
 265             break;
 266
 267         default:
 268             return;
 269     }
 270
 271     foreach_apic(apic_iter, deliver_bitmask,
 272                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 273 }
 274
 275 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
 276                       uint8_t vector_num, uint8_t trigger_mode)
 277 {
 278     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 279
 280     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 281                            trigger_mode);
 282
 283     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 284     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 285 }
 286
 287 static void apic_set_base(APICCommonState *s, uint64_t val)
 288 {
 289     s->apicbase = (val & 0xfffff000) |
 290         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 291     /* if disabled, cannot be enabled again */
 292     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 293         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 294         cpu_clear_apic_feature(&s->cpu->env);
 295         s->spurious_vec &= ~APIC_SV_ENABLE;
 296     }
 297 }
 298
 299 static void apic_set_tpr(APICCommonState *s, uint8_t val)
 300 {
 301     /* Updates from cr8 are ignored while the VAPIC is active */
 302     if (!s->vapic_paddr) {
 303         s->tpr = val << 4;
 304         apic_update_irq(s);
 305     }
 306 }
 307
 308 int apic_get_highest_priority_irr(DeviceState *dev)
 309 {
 310     APICCommonState *s;
 311
 312     if (!dev) {
 313         /* no interrupts */
 314         return -1;
 315     }
 316     s = APIC_COMMON(dev);
 317     return get_highest_priority_int(s->irr);
 318 }
 319
 320 static uint8_t apic_get_tpr(APICCommonState *s)
 321 {
 322     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 323     return s->tpr >> 4;
 324 }
 325
 326 int apic_get_ppr(APICCommonState *s)
 327 {
 328     int tpr, isrv, ppr;
 329
 330     tpr = (s->tpr >> 4);
 331     isrv = get_highest_priority_int(s->isr);
 332     if (isrv < 0)
 333         isrv = 0;
 334     isrv >>= 4;
 335     if (tpr >= isrv)
 336         ppr = s->tpr;
 337     else
 338         ppr = isrv << 4;
 339     return ppr;
 340 }
 341
 342 static int apic_get_arb_pri(APICCommonState *s)
 343 {
 344     /* XXX: arbitration */
 345     return 0;
 346 }
 347
 348
 349 /*
 350  * <0 - low prio interrupt,
 351  * 0  - no interrupt,
 352  * >0 - interrupt number
 353  */
 354 static int apic_irq_pending(APICCommonState *s)
 355 {
 356     int irrv, ppr;
 357
 358     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 359         return 0;
 360     }
 361
 362     irrv = get_highest_priority_int(s->irr);
 363     if (irrv < 0) {
 364         return 0;
 365     }
 366     ppr = apic_get_ppr(s);
 367     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 368         return -1;
 369     }
 370
 371     return irrv;
 372 }
 373
 374 /* signal the CPU if an irq is pending */
 375 static void apic_update_irq(APICCommonState *s)
 376 {
 377     CPUState *cpu;
 378     DeviceState *dev = (DeviceState *)s;
 379
 380     cpu = CPU(s->cpu);
 381     if (!qemu_cpu_is_self(cpu)) {
 382         cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
 383     } else if (apic_irq_pending(s) > 0) {
 384         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
 385     } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
 386         cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
 387     }
 388 }
 389
 390 void apic_poll_irq(DeviceState *dev)
 391 {
 392     APICCommonState *s = APIC(dev);
 393
 394     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 395     apic_update_irq(s);
 396 }
 397
 398 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
 399 {
 400     apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
 401
 402     apic_set_bit(s->irr, vector_num);
 403     if (trigger_mode)
 404         apic_set_bit(s->tmr, vector_num);
 405     else
 406         apic_reset_bit(s->tmr, vector_num);
 407     if (s->vapic_paddr) {
 408         apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
 409         /*
 410          * The vcpu thread needs to see the new IRR before we pull its current
 411          * TPR value. That way, if we miss a lowering of the TRP, the guest
 412          * has the chance to notice the new IRR and poll for IRQs on its own.
 413          */
 414         smp_wmb();
 415         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 416     }
 417     apic_update_irq(s);
 418 }
 419
 420 static void apic_eoi(APICCommonState *s)
 421 {
 422     int isrv;
 423     isrv = get_highest_priority_int(s->isr);
 424     if (isrv < 0)
 425         return;
 426     apic_reset_bit(s->isr, isrv);
 427     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
 428         ioapic_eoi_broadcast(isrv);
 429     }
 430     apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
 431     apic_update_irq(s);
 432 }
 433
 434 static int apic_find_dest(uint8_t dest)
 435 {
 436     APICCommonState *apic = local_apics[dest];
 437     int i;
 438
 439     if (apic && apic->id == dest)
 440         return dest;  /* shortcut in case apic->id == local_apics[dest]->id */
 441
 442     for (i = 0; i < MAX_APICS; i++) {
 443         apic = local_apics[i];
 444         if (apic && apic->id == dest)
 445             return i;
 446         if (!apic)
 447             break;
 448     }
 449
 450     return -1;
 451 }
 452
 453 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 454                                       uint8_t dest, uint8_t dest_mode)
 455 {
 456     APICCommonState *apic_iter;
 457     int i;
 458
 459     if (dest_mode == 0) {
 460         if (dest == 0xff) {
 461             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 462         } else {
 463             int idx = apic_find_dest(dest);
 464             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 465             if (idx >= 0)
 466                 apic_set_bit(deliver_bitmask, idx);
 467         }
 468     } else {
 469         /* XXX: cluster mode */
 470         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 471         for(i = 0; i < MAX_APICS; i++) {
 472             apic_iter = local_apics[i];
 473             if (apic_iter) {
 474                 if (apic_iter->dest_mode == 0xf) {
 475                     if (dest & apic_iter->log_dest)
 476                         apic_set_bit(deliver_bitmask, i);
 477                 } else if (apic_iter->dest_mode == 0x0) {
 478                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 479                         (dest & apic_iter->log_dest & 0x0f)) {
 480                         apic_set_bit(deliver_bitmask, i);
 481                     }
 482                 }
 483             } else {
 484                 break;
 485             }
 486         }
 487     }
 488 }
 489
 490 static void apic_startup(APICCommonState *s, int vector_num)
 491 {
 492     s->sipi_vector = vector_num;
 493     cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 494 }
 495
 496 void apic_sipi(DeviceState *dev)
 497 {
 498     APICCommonState *s = APIC(dev);
 499
 500     cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 501
 502     if (!s->wait_for_sipi)
 503         return;
 504     cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
 505     s->wait_for_sipi = 0;
 506 }
 507
 508 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
 509                          uint8_t delivery_mode, uint8_t vector_num,
 510                          uint8_t trigger_mode)
 511 {
 512     APICCommonState *s = APIC(dev);
 513     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 514     int dest_shorthand = (s->icr[0] >> 18) & 3;
 515     APICCommonState *apic_iter;
 516
 517     switch (dest_shorthand) {
 518     case 0:
 519         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 520         break;
 521     case 1:
 522         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 523         apic_set_bit(deliver_bitmask, s->id);
 524         break;
 525     case 2:
 526         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 527         break;
 528     case 3:
 529         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 530         apic_reset_bit(deliver_bitmask, s->id);
 531         break;
 532     }
 533
 534     switch (delivery_mode) {
 535         case APIC_DM_INIT:
 536             {
 537                 int trig_mode = (s->icr[0] >> 15) & 1;
 538                 int level = (s->icr[0] >> 14) & 1;
 539                 if (level == 0 && trig_mode == 1) {
 540                     foreach_apic(apic_iter, deliver_bitmask,
 541                                  apic_iter->arb_id = apic_iter->id );
 542                     return;
 543                 }
 544             }
 545             break;
 546
 547         case APIC_DM_SIPI:
 548             foreach_apic(apic_iter, deliver_bitmask,
 549                          apic_startup(apic_iter, vector_num) );
 550             return;
 551     }
 552
 553     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 554 }
 555
 556 static bool apic_check_pic(APICCommonState *s)
 557 {
 558     DeviceState *dev = (DeviceState *)s;
 559
 560     if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
 561         return false;
 562     }
 563     apic_deliver_pic_intr(dev, 1);
 564     return true;
 565 }
 566
 567 int apic_get_interrupt(DeviceState *dev)
 568 {
 569     APICCommonState *s = APIC(dev);
 570     int intno;
 571
 572     /* if the APIC is installed or enabled, we let the 8259 handle the
 573        IRQs */
 574     if (!s)
 575         return -1;
 576     if (!(s->spurious_vec & APIC_SV_ENABLE))
 577         return -1;
 578
 579     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 580     intno = apic_irq_pending(s);
 581
 582     /* if there is an interrupt from the 8259, let the caller handle
 583      * that first since ExtINT interrupts ignore the priority.
 584      */
 585     if (intno == 0 || apic_check_pic(s)) {
 586         apic_sync_vapic(s, SYNC_TO_VAPIC);
 587         return -1;
 588     } else if (intno < 0) {
 589         apic_sync_vapic(s, SYNC_TO_VAPIC);
 590         return s->spurious_vec & 0xff;
 591     }
 592     apic_reset_bit(s->irr, intno);
 593     apic_set_bit(s->isr, intno);
 594     apic_sync_vapic(s, SYNC_TO_VAPIC);
 595
 596     apic_update_irq(s);
 597
 598     return intno;
 599 }
 600
 601 int apic_accept_pic_intr(DeviceState *dev)
 602 {
 603     APICCommonState *s = APIC(dev);
 604     uint32_t lvt0;
 605
 606     if (!s)
 607         return -1;
 608
 609     lvt0 = s->lvt[APIC_LVT_LINT0];
 610
 611     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 612         (lvt0 & APIC_LVT_MASKED) == 0)
 613         return 1;
 614
 615     return 0;
 616 }
 617
 618 static uint32_t apic_get_current_count(APICCommonState *s)
 619 {
 620     int64_t d;
 621     uint32_t val;
 622     d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
 623         s->count_shift;
 624     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 625         /* periodic */
 626         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 627     } else {
 628         if (d >= s->initial_count)
 629             val = 0;
 630         else
 631             val = s->initial_count - d;
 632     }
 633     return val;
 634 }
 635
 636 static void apic_timer_update(APICCommonState *s, int64_t current_time)
 637 {
 638     if (apic_next_timer(s, current_time)) {
 639         timer_mod(s->timer, s->next_time);
 640     } else {
 641         timer_del(s->timer);
 642     }
 643 }
 644
 645 static void apic_timer(void *opaque)
 646 {
 647     APICCommonState *s = opaque;
 648
 649     apic_local_deliver(s, APIC_LVT_TIMER);
 650     apic_timer_update(s, s->next_time);
 651 }
 652
 653 static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
 654 {
 655     DeviceState *dev;
 656     APICCommonState *s;
 657     uint32_t val;
 658     int index;
 659
 660     if (size < 4) {
 661         return 0;
 662     }
 663
 664     dev = cpu_get_current_apic();
 665     if (!dev) {
 666         return 0;
 667     }
 668     s = APIC(dev);
 669
 670     index = (addr >> 4) & 0xff;
 671     switch(index) {
 672     case 0x02: /* id */
 673         val = s->id << 24;
 674         break;
 675     case 0x03: /* version */
 676         val = s->version | ((APIC_LVT_NB - 1) << 16);
 677         break;
 678     case 0x08:
 679         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 680         if (apic_report_tpr_access) {
 681             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
 682         }
 683         val = s->tpr;
 684         break;
 685     case 0x09:
 686         val = apic_get_arb_pri(s);
 687         break;
 688     case 0x0a:
 689         /* ppr */
 690         val = apic_get_ppr(s);
 691         break;
 692     case 0x0b:
 693         val = 0;
 694         break;
 695     case 0x0d:
 696         val = s->log_dest << 24;
 697         break;
 698     case 0x0e:
 699         val = (s->dest_mode << 28) | 0xfffffff;
 700         break;
 701     case 0x0f:
 702         val = s->spurious_vec;
 703         break;
 704     case 0x10 ... 0x17:
 705         val = s->isr[index & 7];
 706         break;
 707     case 0x18 ... 0x1f:
 708         val = s->tmr[index & 7];
 709         break;
 710     case 0x20 ... 0x27:
 711         val = s->irr[index & 7];
 712         break;
 713     case 0x28:
 714         val = s->esr;
 715         break;
 716     case 0x30:
 717     case 0x31:
 718         val = s->icr[index & 1];
 719         break;
 720     case 0x32 ... 0x37:
 721         val = s->lvt[index - 0x32];
 722         break;
 723     case 0x38:
 724         val = s->initial_count;
 725         break;
 726     case 0x39:
 727         val = apic_get_current_count(s);
 728         break;
 729     case 0x3e:
 730         val = s->divide_conf;
 731         break;
 732     default:
 733         s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
 734         val = 0;
 735         break;
 736     }
 737     trace_apic_mem_readl(addr, val);
 738     return val;
 739 }
 740
 741 static void apic_send_msi(MSIMessage *msi)
 742 {
 743     uint64_t addr = msi->address;
 744     uint32_t data = msi->data;
 745     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 746     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 747     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 748     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 749     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 750     /* XXX: Ignore redirection hint. */
 751     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
 752 }
 753
 754 static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 755                            unsigned size)
 756 {
 757     DeviceState *dev;
 758     APICCommonState *s;
 759     int index = (addr >> 4) & 0xff;
 760
 761     if (size < 4) {
 762         return;
 763     }
 764
 765     if (addr > 0xfff || !index) {
 766         /* MSI and MMIO APIC are at the same memory location,
 767          * but actually not on the global bus: MSI is on PCI bus
 768          * APIC is connected directly to the CPU.
 769          * Mapping them on the global bus happens to work because
 770          * MSI registers are reserved in APIC MMIO and vice versa. */
 771         MSIMessage msi = { .address = addr, .data = val };
 772         apic_send_msi(&msi);
 773         return;
 774     }
 775
 776     dev = cpu_get_current_apic();
 777     if (!dev) {
 778         return;
 779     }
 780     s = APIC(dev);
 781
 782     trace_apic_mem_writel(addr, val);
 783
 784     switch(index) {
 785     case 0x02:
 786         s->id = (val >> 24);
 787         break;
 788     case 0x03:
 789         break;
 790     case 0x08:
 791         if (apic_report_tpr_access) {
 792             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
 793         }
 794         s->tpr = val;
 795         apic_sync_vapic(s, SYNC_TO_VAPIC);
 796         apic_update_irq(s);
 797         break;
 798     case 0x09:
 799     case 0x0a:
 800         break;
 801     case 0x0b: /* EOI */
 802         apic_eoi(s);
 803         break;
 804     case 0x0d:
 805         s->log_dest = val >> 24;
 806         break;
 807     case 0x0e:
 808         s->dest_mode = val >> 28;
 809         break;
 810     case 0x0f:
 811         s->spurious_vec = val & 0x1ff;
 812         apic_update_irq(s);
 813         break;
 814     case 0x10 ... 0x17:
 815     case 0x18 ... 0x1f:
 816     case 0x20 ... 0x27:
 817     case 0x28:
 818         break;
 819     case 0x30:
 820         s->icr[0] = val;
 821         apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 822                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 823                      (s->icr[0] >> 15) & 1);
 824         break;
 825     case 0x31:
 826         s->icr[1] = val;
 827         break;
 828     case 0x32 ... 0x37:
 829         {
 830             int n = index - 0x32;
 831             s->lvt[n] = val;
 832             if (n == APIC_LVT_TIMER) {
 833                 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 834             } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
 835                 apic_update_irq(s);
 836             }
 837         }
 838         break;
 839     case 0x38:
 840         s->initial_count = val;
 841         s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 842         apic_timer_update(s, s->initial_count_load_time);
 843         break;
 844     case 0x39:
 845         break;
 846     case 0x3e:
 847         {
 848             int v;
 849             s->divide_conf = val & 0xb;
 850             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 851             s->count_shift = (v + 1) & 7;
 852         }
 853         break;
 854     default:
 855         s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
 856         break;
 857     }
 858 }
 859
 860 static void apic_pre_save(APICCommonState *s)
 861 {
 862     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 863 }
 864
 865 static void apic_post_load(APICCommonState *s)
 866 {
 867     if (s->timer_expiry != -1) {
 868         timer_mod(s->timer, s->timer_expiry);
 869     } else {
 870         timer_del(s->timer);
 871     }
 872 }
 873
 874 static const MemoryRegionOps apic_io_ops = {
 875     .read = apic_mem_read,
 876     .write = apic_mem_write,
 877     .impl.min_access_size = 1,
 878     .impl.max_access_size = 4,
 879     .valid.min_access_size = 1,
 880     .valid.max_access_size = 4,
 881     .endianness = DEVICE_NATIVE_ENDIAN,
 882 };
 883
 884 static void apic_realize(DeviceState *dev, Error **errp)
 885 {
 886     APICCommonState *s = APIC(dev);
 887
 888     if (s->id >= MAX_APICS) {
 889         error_setg(errp, "%s initialization failed. APIC ID %d is invalid",
 890                    object_get_typename(OBJECT(dev)), s->id);
 891         return;
 892     }
 893
 894     memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
 895                           APIC_SPACE_SIZE);
 896
 897     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
 898     local_apics[s->id] = s;
 899
 900     msi_nonbroken = true;
 901 }
 902
 903 static void apic_unrealize(DeviceState *dev, Error **errp)
 904 {
 905     APICCommonState *s = APIC(dev);
 906
 907     timer_del(s->timer);
 908     timer_free(s->timer);
 909     local_apics[s->id] = NULL;
 910 }
 911
 912 static void apic_class_init(ObjectClass *klass, void *data)
 913 {
 914     APICCommonClass *k = APIC_COMMON_CLASS(klass);
 915
 916     k->realize = apic_realize;
 917     k->unrealize = apic_unrealize;
 918     k->set_base = apic_set_base;
 919     k->set_tpr = apic_set_tpr;
 920     k->get_tpr = apic_get_tpr;
 921     k->vapic_base_update = apic_vapic_base_update;
 922     k->external_nmi = apic_external_nmi;
 923     k->pre_save = apic_pre_save;
 924     k->post_load = apic_post_load;
 925     k->send_msi = apic_send_msi;
 926 }
 927
 928 static const TypeInfo apic_info = {
 929     .name          = TYPE_APIC,
 930     .instance_size = sizeof(APICCommonState),
 931     .parent        = TYPE_APIC_COMMON,
 932     .class_init    = apic_class_init,
 933 };
 934
 935 static void apic_register_types(void)
 936 {
 937     type_register_static(&apic_info);
 938 }
 939
 940 type_init(apic_register_types)