target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri)
 348 {
 349     bool secure = arm_is_secure_below_el3(env);
 350
 351     assert(!arm_el_is_aa64(env, 3));
 352     if (secure) {
 353         return CP_ACCESS_TRAP_UNCATEGORIZED;
 354     }
 355     return CP_ACCESS_OK;
 356 }
 357
 358 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 359                                                 const ARMCPRegInfo *ri)
 360 {
 361     if (!arm_el_is_aa64(env, 3)) {
 362         return access_el3_aa32ns(env, ri);
 363     }
 364     return CP_ACCESS_OK;
 365 }
 366
 367 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 368 {
 369     ARMCPU *cpu = arm_env_get_cpu(env);
 370
 371     raw_write(env, ri, value);
 372     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 373 }
 374
 375 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 376 {
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     if (raw_read(env, ri) != value) {
 380         /* Unlike real hardware the qemu TLB uses virtual addresses,
 381          * not modified virtual addresses, so this causes a TLB flush.
 382          */
 383         tlb_flush(CPU(cpu), 1);
 384         raw_write(env, ri, value);
 385     }
 386 }
 387
 388 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 389                              uint64_t value)
 390 {
 391     ARMCPU *cpu = arm_env_get_cpu(env);
 392
 393     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 394         && !extended_addresses_enabled(env)) {
 395         /* For VMSA (when not using the LPAE long descriptor page table
 396          * format) this register includes the ASID, so do a TLB flush.
 397          * For PMSA it is purely a process ID and no action is needed.
 398          */
 399         tlb_flush(CPU(cpu), 1);
 400     }
 401     raw_write(env, ri, value);
 402 }
 403
 404 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 405                           uint64_t value)
 406 {
 407     /* Invalidate all (TLBIALL) */
 408     ARMCPU *cpu = arm_env_get_cpu(env);
 409
 410     tlb_flush(CPU(cpu), 1);
 411 }
 412
 413 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 414                           uint64_t value)
 415 {
 416     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 417     ARMCPU *cpu = arm_env_get_cpu(env);
 418
 419     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 420 }
 421
 422 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 423                            uint64_t value)
 424 {
 425     /* Invalidate by ASID (TLBIASID) */
 426     ARMCPU *cpu = arm_env_get_cpu(env);
 427
 428     tlb_flush(CPU(cpu), value == 0);
 429 }
 430
 431 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 432                            uint64_t value)
 433 {
 434     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 435     ARMCPU *cpu = arm_env_get_cpu(env);
 436
 437     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 438 }
 439
 440 /* IS variants of TLB operations must affect all cores */
 441 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 442                              uint64_t value)
 443 {
 444     CPUState *other_cs;
 445
 446     CPU_FOREACH(other_cs) {
 447         tlb_flush(other_cs, 1);
 448     }
 449 }
 450
 451 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 452                              uint64_t value)
 453 {
 454     CPUState *other_cs;
 455
 456     CPU_FOREACH(other_cs) {
 457         tlb_flush(other_cs, value == 0);
 458     }
 459 }
 460
 461 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 462                              uint64_t value)
 463 {
 464     CPUState *other_cs;
 465
 466     CPU_FOREACH(other_cs) {
 467         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 468     }
 469 }
 470
 471 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 472                              uint64_t value)
 473 {
 474     CPUState *other_cs;
 475
 476     CPU_FOREACH(other_cs) {
 477         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 478     }
 479 }
 480
 481 static const ARMCPRegInfo cp_reginfo[] = {
 482     /* Define the secure and non-secure FCSE identifier CP registers
 483      * separately because there is no secure bank in V8 (no _EL3).  This allows
 484      * the secure register to be properly reset and migrated. There is also no
 485      * v8 EL1 version of the register so the non-secure instance stands alone.
 486      */
 487     { .name = "FCSEIDR(NS)",
 488       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 489       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 490       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 491       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 492     { .name = "FCSEIDR(S)",
 493       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 494       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 495       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 496       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 497     /* Define the secure and non-secure context identifier CP registers
 498      * separately because there is no secure bank in V8 (no _EL3).  This allows
 499      * the secure register to be properly reset and migrated.  In the
 500      * non-secure case, the 32-bit register will have reset and migration
 501      * disabled during registration as it is handled by the 64-bit instance.
 502      */
 503     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 504       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 505       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 506       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 507       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 508     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 509       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 510       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 511       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 512       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 513     REGINFO_SENTINEL
 514 };
 515
 516 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 517     /* NB: Some of these registers exist in v8 but with more precise
 518      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 519      */
 520     /* MMU Domain access control / MPU write buffer control */
 521     { .name = "DACR",
 522       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 523       .access = PL1_RW, .resetvalue = 0,
 524       .writefn = dacr_write, .raw_writefn = raw_write,
 525       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 526                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 527     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 528      * For v6 and v5, these mappings are overly broad.
 529      */
 530     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 531       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 532     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 533       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 534     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 535       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 536     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 537       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 538     /* Cache maintenance ops; some of this space may be overridden later. */
 539     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 540       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 541       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 542     REGINFO_SENTINEL
 543 };
 544
 545 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 546     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 547      * over-broad.
 548      */
 549     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 550       .access = PL1_W, .type = ARM_CP_WFI },
 551     REGINFO_SENTINEL
 552 };
 553
 554 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 555     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 556      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 557      */
 558     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 559       .access = PL1_W, .type = ARM_CP_WFI },
 560     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 561      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 562      * OMAPCP will override this space.
 563      */
 564     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 565       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 566       .resetvalue = 0 },
 567     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 568       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 569       .resetvalue = 0 },
 570     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 571     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 572       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 573       .resetvalue = 0 },
 574     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 575      * implementing it as RAZ means the "debug architecture version" bits
 576      * will read as a reserved value, which should cause Linux to not try
 577      * to use the debug hardware.
 578      */
 579     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 580       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 581     /* MMU TLB control. Note that the wildcarding means we cover not just
 582      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 583      */
 584     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 585       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 586       .type = ARM_CP_NO_RAW },
 587     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 588       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 589       .type = ARM_CP_NO_RAW },
 590     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 591       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 592       .type = ARM_CP_NO_RAW },
 593     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 594       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 595       .type = ARM_CP_NO_RAW },
 596     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 597       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 598     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 599       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 600     REGINFO_SENTINEL
 601 };
 602
 603 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 604                         uint64_t value)
 605 {
 606     uint32_t mask = 0;
 607
 608     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 609     if (!arm_feature(env, ARM_FEATURE_V8)) {
 610         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 611          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 612          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 613          */
 614         if (arm_feature(env, ARM_FEATURE_VFP)) {
 615             /* VFP coprocessor: cp10 & cp11 [23:20] */
 616             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 617
 618             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 619                 /* ASEDIS [31] bit is RAO/WI */
 620                 value |= (1 << 31);
 621             }
 622
 623             /* VFPv3 and upwards with NEON implement 32 double precision
 624              * registers (D0-D31).
 625              */
 626             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 627                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 628                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 629                 value |= (1 << 30);
 630             }
 631         }
 632         value &= mask;
 633     }
 634     env->cp15.cpacr_el1 = value;
 635 }
 636
 637 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 638 {
 639     if (arm_feature(env, ARM_FEATURE_V8)) {
 640         /* Check if CPACR accesses are to be trapped to EL2 */
 641         if (arm_current_el(env) == 1 &&
 642             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 643             return CP_ACCESS_TRAP_EL2;
 644         /* Check if CPACR accesses are to be trapped to EL3 */
 645         } else if (arm_current_el(env) < 3 &&
 646                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 647             return CP_ACCESS_TRAP_EL3;
 648         }
 649     }
 650
 651     return CP_ACCESS_OK;
 652 }
 653
 654 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 655 {
 656     /* Check if CPTR accesses are set to trap to EL3 */
 657     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 658         return CP_ACCESS_TRAP_EL3;
 659     }
 660
 661     return CP_ACCESS_OK;
 662 }
 663
 664 static const ARMCPRegInfo v6_cp_reginfo[] = {
 665     /* prefetch by MVA in v6, NOP in v7 */
 666     { .name = "MVA_prefetch",
 667       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 668       .access = PL1_W, .type = ARM_CP_NOP },
 669     /* We need to break the TB after ISB to execute self-modifying code
 670      * correctly and also to take any pending interrupts immediately.
 671      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 672      */
 673     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 674       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 675     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 676       .access = PL0_W, .type = ARM_CP_NOP },
 677     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 678       .access = PL0_W, .type = ARM_CP_NOP },
 679     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 680       .access = PL1_RW,
 681       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 682                              offsetof(CPUARMState, cp15.ifar_ns) },
 683       .resetvalue = 0, },
 684     /* Watchpoint Fault Address Register : should actually only be present
 685      * for 1136, 1176, 11MPCore.
 686      */
 687     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 688       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 689     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 690       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 691       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 692       .resetvalue = 0, .writefn = cpacr_write },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 697 {
 698     /* Performance monitor registers user accessibility is controlled
 699      * by PMUSERENR.
 700      */
 701     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 702         return CP_ACCESS_TRAP;
 703     }
 704     return CP_ACCESS_OK;
 705 }
 706
 707 #ifndef CONFIG_USER_ONLY
 708
 709 static inline bool arm_ccnt_enabled(CPUARMState *env)
 710 {
 711     /* This does not support checking PMCCFILTR_EL0 register */
 712
 713     if (!(env->cp15.c9_pmcr & PMCRE)) {
 714         return false;
 715     }
 716
 717     return true;
 718 }
 719
 720 void pmccntr_sync(CPUARMState *env)
 721 {
 722     uint64_t temp_ticks;
 723
 724     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 725                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 726
 727     if (env->cp15.c9_pmcr & PMCRD) {
 728         /* Increment once every 64 processor clock cycles */
 729         temp_ticks /= 64;
 730     }
 731
 732     if (arm_ccnt_enabled(env)) {
 733         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 734     }
 735 }
 736
 737 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 738                        uint64_t value)
 739 {
 740     pmccntr_sync(env);
 741
 742     if (value & PMCRC) {
 743         /* The counter has been reset */
 744         env->cp15.c15_ccnt = 0;
 745     }
 746
 747     /* only the DP, X, D and E bits are writable */
 748     env->cp15.c9_pmcr &= ~0x39;
 749     env->cp15.c9_pmcr |= (value & 0x39);
 750
 751     pmccntr_sync(env);
 752 }
 753
 754 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 755 {
 756     uint64_t total_ticks;
 757
 758     if (!arm_ccnt_enabled(env)) {
 759         /* Counter is disabled, do not change value */
 760         return env->cp15.c15_ccnt;
 761     }
 762
 763     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 764                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 765
 766     if (env->cp15.c9_pmcr & PMCRD) {
 767         /* Increment once every 64 processor clock cycles */
 768         total_ticks /= 64;
 769     }
 770     return total_ticks - env->cp15.c15_ccnt;
 771 }
 772
 773 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 774                         uint64_t value)
 775 {
 776     uint64_t total_ticks;
 777
 778     if (!arm_ccnt_enabled(env)) {
 779         /* Counter is disabled, set the absolute value */
 780         env->cp15.c15_ccnt = value;
 781         return;
 782     }
 783
 784     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 785                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 786
 787     if (env->cp15.c9_pmcr & PMCRD) {
 788         /* Increment once every 64 processor clock cycles */
 789         total_ticks /= 64;
 790     }
 791     env->cp15.c15_ccnt = total_ticks - value;
 792 }
 793
 794 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 795                             uint64_t value)
 796 {
 797     uint64_t cur_val = pmccntr_read(env, NULL);
 798
 799     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 800 }
 801
 802 #else /* CONFIG_USER_ONLY */
 803
 804 void pmccntr_sync(CPUARMState *env)
 805 {
 806 }
 807
 808 #endif
 809
 810 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 811                             uint64_t value)
 812 {
 813     pmccntr_sync(env);
 814     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 815     pmccntr_sync(env);
 816 }
 817
 818 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 819                             uint64_t value)
 820 {
 821     value &= (1 << 31);
 822     env->cp15.c9_pmcnten |= value;
 823 }
 824
 825 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 826                              uint64_t value)
 827 {
 828     value &= (1 << 31);
 829     env->cp15.c9_pmcnten &= ~value;
 830 }
 831
 832 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 833                          uint64_t value)
 834 {
 835     env->cp15.c9_pmovsr &= ~value;
 836 }
 837
 838 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 839                              uint64_t value)
 840 {
 841     env->cp15.c9_pmxevtyper = value & 0xff;
 842 }
 843
 844 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 845                             uint64_t value)
 846 {
 847     env->cp15.c9_pmuserenr = value & 1;
 848 }
 849
 850 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 851                              uint64_t value)
 852 {
 853     /* We have no event counters so only the C bit can be changed */
 854     value &= (1 << 31);
 855     env->cp15.c9_pminten |= value;
 856 }
 857
 858 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 859                              uint64_t value)
 860 {
 861     value &= (1 << 31);
 862     env->cp15.c9_pminten &= ~value;
 863 }
 864
 865 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 866                        uint64_t value)
 867 {
 868     /* Note that even though the AArch64 view of this register has bits
 869      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 870      * architectural requirements for bits which are RES0 only in some
 871      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 872      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 873      */
 874     raw_write(env, ri, value & ~0x1FULL);
 875 }
 876
 877 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 878 {
 879     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 880      * For bits that vary between AArch32/64, code needs to check the
 881      * current execution mode before directly using the feature bit.
 882      */
 883     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 884
 885     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 886         valid_mask &= ~SCR_HCE;
 887
 888         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 889          * supported if EL2 exists. The bit is UNK/SBZP when
 890          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 891          * when EL2 is unavailable.
 892          * On ARMv8, this bit is always available.
 893          */
 894         if (arm_feature(env, ARM_FEATURE_V7) &&
 895             !arm_feature(env, ARM_FEATURE_V8)) {
 896             valid_mask &= ~SCR_SMD;
 897         }
 898     }
 899
 900     /* Clear all-context RES0 bits.  */
 901     value &= valid_mask;
 902     raw_write(env, ri, value);
 903 }
 904
 905 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 906 {
 907     ARMCPU *cpu = arm_env_get_cpu(env);
 908
 909     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 910      * bank
 911      */
 912     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 913                                         ri->secure & ARM_CP_SECSTATE_S);
 914
 915     return cpu->ccsidr[index];
 916 }
 917
 918 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 919                          uint64_t value)
 920 {
 921     raw_write(env, ri, value & 0xf);
 922 }
 923
 924 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 925 {
 926     CPUState *cs = ENV_GET_CPU(env);
 927     uint64_t ret = 0;
 928
 929     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 930         ret |= CPSR_I;
 931     }
 932     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 933         ret |= CPSR_F;
 934     }
 935     /* External aborts are not possible in QEMU so A bit is always clear */
 936     return ret;
 937 }
 938
 939 static const ARMCPRegInfo v7_cp_reginfo[] = {
 940     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 941     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 942       .access = PL1_W, .type = ARM_CP_NOP },
 943     /* Performance monitors are implementation defined in v7,
 944      * but with an ARM recommended set of registers, which we
 945      * follow (although we don't actually implement any counters)
 946      *
 947      * Performance registers fall into three categories:
 948      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 949      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 950      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 951      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 952      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 953      */
 954     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 955       .access = PL0_RW, .type = ARM_CP_ALIAS,
 956       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 957       .writefn = pmcntenset_write,
 958       .accessfn = pmreg_access,
 959       .raw_writefn = raw_write },
 960     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 961       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 962       .access = PL0_RW, .accessfn = pmreg_access,
 963       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 964       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 965     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 966       .access = PL0_RW,
 967       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 968       .accessfn = pmreg_access,
 969       .writefn = pmcntenclr_write,
 970       .type = ARM_CP_ALIAS },
 971     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 972       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 973       .access = PL0_RW, .accessfn = pmreg_access,
 974       .type = ARM_CP_ALIAS,
 975       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 976       .writefn = pmcntenclr_write },
 977     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 978       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 979       .accessfn = pmreg_access,
 980       .writefn = pmovsr_write,
 981       .raw_writefn = raw_write },
 982     /* Unimplemented so WI. */
 983     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 984       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 985     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 986      * We choose to RAZ/WI.
 987      */
 988     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 989       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 990       .accessfn = pmreg_access },
 991 #ifndef CONFIG_USER_ONLY
 992     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 993       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 994       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 995       .accessfn = pmreg_access },
 996     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 997       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 998       .access = PL0_RW, .accessfn = pmreg_access,
 999       .type = ARM_CP_IO,
1000       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1001 #endif
1002     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1003       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1004       .writefn = pmccfiltr_write,
1005       .access = PL0_RW, .accessfn = pmreg_access,
1006       .type = ARM_CP_IO,
1007       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1008       .resetvalue = 0, },
1009     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1010       .access = PL0_RW,
1011       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1012       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1013       .raw_writefn = raw_write },
1014     /* Unimplemented, RAZ/WI. */
1015     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1016       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1017       .accessfn = pmreg_access },
1018     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1019       .access = PL0_R | PL1_RW,
1020       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1021       .resetvalue = 0,
1022       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1023     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1024       .access = PL1_RW,
1025       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1026       .resetvalue = 0,
1027       .writefn = pmintenset_write, .raw_writefn = raw_write },
1028     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1029       .access = PL1_RW, .type = ARM_CP_ALIAS,
1030       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1031       .writefn = pmintenclr_write, },
1032     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1033       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1034       .access = PL1_RW, .writefn = vbar_write,
1035       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1036                              offsetof(CPUARMState, cp15.vbar_ns) },
1037       .resetvalue = 0 },
1038     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1039       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1040       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1041     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1042       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1043       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1044       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1045                              offsetof(CPUARMState, cp15.csselr_ns) } },
1046     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1047      * just RAZ for all cores:
1048      */
1049     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1050       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1051       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1052     /* Auxiliary fault status registers: these also are IMPDEF, and we
1053      * choose to RAZ/WI for all cores.
1054      */
1055     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1056       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1057       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1058     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1059       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1060       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1061     /* MAIR can just read-as-written because we don't implement caches
1062      * and so don't need to care about memory attributes.
1063      */
1064     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1065       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1066       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1067       .resetvalue = 0 },
1068     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1069       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1070       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1071       .resetvalue = 0 },
1072     /* For non-long-descriptor page tables these are PRRR and NMRR;
1073      * regardless they still act as reads-as-written for QEMU.
1074      */
1075      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1076       * allows them to assign the correct fieldoffset based on the endianness
1077       * handled in the field definitions.
1078       */
1079     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1080       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1081       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1082                              offsetof(CPUARMState, cp15.mair0_ns) },
1083       .resetfn = arm_cp_reset_ignore },
1084     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1085       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1086       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1087                              offsetof(CPUARMState, cp15.mair1_ns) },
1088       .resetfn = arm_cp_reset_ignore },
1089     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1090       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1091       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1092     /* 32 bit ITLB invalidates */
1093     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1094       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1095     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1096       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1097     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1098       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1099     /* 32 bit DTLB invalidates */
1100     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1101       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1102     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1103       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1104     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1105       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1106     /* 32 bit TLB invalidates */
1107     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1108       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1109     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1110       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1111     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1112       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1113     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1114       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1115     REGINFO_SENTINEL
1116 };
1117
1118 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1119     /* 32 bit TLB invalidates, Inner Shareable */
1120     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1121       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1122     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1123       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1124     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1125       .type = ARM_CP_NO_RAW, .access = PL1_W,
1126       .writefn = tlbiasid_is_write },
1127     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1128       .type = ARM_CP_NO_RAW, .access = PL1_W,
1129       .writefn = tlbimvaa_is_write },
1130     REGINFO_SENTINEL
1131 };
1132
1133 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1134                         uint64_t value)
1135 {
1136     value &= 1;
1137     env->teecr = value;
1138 }
1139
1140 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1141 {
1142     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1143         return CP_ACCESS_TRAP;
1144     }
1145     return CP_ACCESS_OK;
1146 }
1147
1148 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1149     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1150       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1151       .resetvalue = 0,
1152       .writefn = teecr_write },
1153     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1154       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1155       .accessfn = teehbr_access, .resetvalue = 0 },
1156     REGINFO_SENTINEL
1157 };
1158
1159 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1160     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1161       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1162       .access = PL0_RW,
1163       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1164     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1165       .access = PL0_RW,
1166       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1167                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1168       .resetfn = arm_cp_reset_ignore },
1169     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1170       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1171       .access = PL0_R|PL1_W,
1172       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1173       .resetvalue = 0},
1174     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1175       .access = PL0_R|PL1_W,
1176       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1177                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1178       .resetfn = arm_cp_reset_ignore },
1179     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1180       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1181       .access = PL1_RW,
1182       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1183     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1184       .access = PL1_RW,
1185       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1186                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1187       .resetvalue = 0 },
1188     REGINFO_SENTINEL
1189 };
1190
1191 #ifndef CONFIG_USER_ONLY
1192
1193 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1194 {
1195     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1196     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1197         return CP_ACCESS_TRAP;
1198     }
1199     return CP_ACCESS_OK;
1200 }
1201
1202 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1203 {
1204     unsigned int cur_el = arm_current_el(env);
1205     bool secure = arm_is_secure(env);
1206
1207     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1208     if (cur_el == 0 &&
1209         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1210         return CP_ACCESS_TRAP;
1211     }
1212
1213     if (arm_feature(env, ARM_FEATURE_EL2) &&
1214         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1215         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1216         return CP_ACCESS_TRAP_EL2;
1217     }
1218     return CP_ACCESS_OK;
1219 }
1220
1221 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1222 {
1223     unsigned int cur_el = arm_current_el(env);
1224     bool secure = arm_is_secure(env);
1225
1226     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1227      * EL0[PV]TEN is zero.
1228      */
1229     if (cur_el == 0 &&
1230         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1231         return CP_ACCESS_TRAP;
1232     }
1233
1234     if (arm_feature(env, ARM_FEATURE_EL2) &&
1235         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1236         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1237         return CP_ACCESS_TRAP_EL2;
1238     }
1239     return CP_ACCESS_OK;
1240 }
1241
1242 static CPAccessResult gt_pct_access(CPUARMState *env,
1243                                          const ARMCPRegInfo *ri)
1244 {
1245     return gt_counter_access(env, GTIMER_PHYS);
1246 }
1247
1248 static CPAccessResult gt_vct_access(CPUARMState *env,
1249                                          const ARMCPRegInfo *ri)
1250 {
1251     return gt_counter_access(env, GTIMER_VIRT);
1252 }
1253
1254 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1255 {
1256     return gt_timer_access(env, GTIMER_PHYS);
1257 }
1258
1259 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1260 {
1261     return gt_timer_access(env, GTIMER_VIRT);
1262 }
1263
1264 static CPAccessResult gt_stimer_access(CPUARMState *env,
1265                                        const ARMCPRegInfo *ri)
1266 {
1267     /* The AArch64 register view of the secure physical timer is
1268      * always accessible from EL3, and configurably accessible from
1269      * Secure EL1.
1270      */
1271     switch (arm_current_el(env)) {
1272     case 1:
1273         if (!arm_is_secure(env)) {
1274             return CP_ACCESS_TRAP;
1275         }
1276         if (!(env->cp15.scr_el3 & SCR_ST)) {
1277             return CP_ACCESS_TRAP_EL3;
1278         }
1279         return CP_ACCESS_OK;
1280     case 0:
1281     case 2:
1282         return CP_ACCESS_TRAP;
1283     case 3:
1284         return CP_ACCESS_OK;
1285     default:
1286         g_assert_not_reached();
1287     }
1288 }
1289
1290 static uint64_t gt_get_countervalue(CPUARMState *env)
1291 {
1292     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1293 }
1294
1295 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1296 {
1297     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1298
1299     if (gt->ctl & 1) {
1300         /* Timer enabled: calculate and set current ISTATUS, irq, and
1301          * reset timer to when ISTATUS next has to change
1302          */
1303         uint64_t offset = timeridx == GTIMER_VIRT ?
1304                                       cpu->env.cp15.cntvoff_el2 : 0;
1305         uint64_t count = gt_get_countervalue(&cpu->env);
1306         /* Note that this must be unsigned 64 bit arithmetic: */
1307         int istatus = count - offset >= gt->cval;
1308         uint64_t nexttick;
1309
1310         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1311         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1312                      (istatus && !(gt->ctl & 2)));
1313         if (istatus) {
1314             /* Next transition is when count rolls back over to zero */
1315             nexttick = UINT64_MAX;
1316         } else {
1317             /* Next transition is when we hit cval */
1318             nexttick = gt->cval + offset;
1319         }
1320         /* Note that the desired next expiry time might be beyond the
1321          * signed-64-bit range of a QEMUTimer -- in this case we just
1322          * set the timer for as far in the future as possible. When the
1323          * timer expires we will reset the timer for any remaining period.
1324          */
1325         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1326             nexttick = INT64_MAX / GTIMER_SCALE;
1327         }
1328         timer_mod(cpu->gt_timer[timeridx], nexttick);
1329     } else {
1330         /* Timer disabled: ISTATUS and timer output always clear */
1331         gt->ctl &= ~4;
1332         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1333         timer_del(cpu->gt_timer[timeridx]);
1334     }
1335 }
1336
1337 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1338                            int timeridx)
1339 {
1340     ARMCPU *cpu = arm_env_get_cpu(env);
1341
1342     timer_del(cpu->gt_timer[timeridx]);
1343 }
1344
1345 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1346 {
1347     return gt_get_countervalue(env);
1348 }
1349
1350 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1351 {
1352     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1353 }
1354
1355 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1356                           int timeridx,
1357                           uint64_t value)
1358 {
1359     env->cp15.c14_timer[timeridx].cval = value;
1360     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1361 }
1362
1363 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1364                              int timeridx)
1365 {
1366     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1367
1368     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1369                       (gt_get_countervalue(env) - offset));
1370 }
1371
1372 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1373                           int timeridx,
1374                           uint64_t value)
1375 {
1376     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1377
1378     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1379                                          sextract64(value, 0, 32);
1380     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1381 }
1382
1383 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1384                          int timeridx,
1385                          uint64_t value)
1386 {
1387     ARMCPU *cpu = arm_env_get_cpu(env);
1388     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1389
1390     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1391     if ((oldval ^ value) & 1) {
1392         /* Enable toggled */
1393         gt_recalc_timer(cpu, timeridx);
1394     } else if ((oldval ^ value) & 2) {
1395         /* IMASK toggled: don't need to recalculate,
1396          * just set the interrupt line based on ISTATUS
1397          */
1398         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1399                      (oldval & 4) && !(value & 2));
1400     }
1401 }
1402
1403 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1404 {
1405     gt_timer_reset(env, ri, GTIMER_PHYS);
1406 }
1407
1408 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1409                                uint64_t value)
1410 {
1411     gt_cval_write(env, ri, GTIMER_PHYS, value);
1412 }
1413
1414 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1415 {
1416     return gt_tval_read(env, ri, GTIMER_PHYS);
1417 }
1418
1419 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1420                                uint64_t value)
1421 {
1422     gt_tval_write(env, ri, GTIMER_PHYS, value);
1423 }
1424
1425 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1426                               uint64_t value)
1427 {
1428     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1429 }
1430
1431 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1432 {
1433     gt_timer_reset(env, ri, GTIMER_VIRT);
1434 }
1435
1436 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1437                                uint64_t value)
1438 {
1439     gt_cval_write(env, ri, GTIMER_VIRT, value);
1440 }
1441
1442 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1443 {
1444     return gt_tval_read(env, ri, GTIMER_VIRT);
1445 }
1446
1447 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1448                                uint64_t value)
1449 {
1450     gt_tval_write(env, ri, GTIMER_VIRT, value);
1451 }
1452
1453 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1454                               uint64_t value)
1455 {
1456     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1457 }
1458
1459 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1460                               uint64_t value)
1461 {
1462     ARMCPU *cpu = arm_env_get_cpu(env);
1463
1464     raw_write(env, ri, value);
1465     gt_recalc_timer(cpu, GTIMER_VIRT);
1466 }
1467
1468 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1469 {
1470     gt_timer_reset(env, ri, GTIMER_HYP);
1471 }
1472
1473 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1474                               uint64_t value)
1475 {
1476     gt_cval_write(env, ri, GTIMER_HYP, value);
1477 }
1478
1479 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1480 {
1481     return gt_tval_read(env, ri, GTIMER_HYP);
1482 }
1483
1484 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1485                               uint64_t value)
1486 {
1487     gt_tval_write(env, ri, GTIMER_HYP, value);
1488 }
1489
1490 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1491                               uint64_t value)
1492 {
1493     gt_ctl_write(env, ri, GTIMER_HYP, value);
1494 }
1495
1496 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1497 {
1498     gt_timer_reset(env, ri, GTIMER_SEC);
1499 }
1500
1501 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1502                               uint64_t value)
1503 {
1504     gt_cval_write(env, ri, GTIMER_SEC, value);
1505 }
1506
1507 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1508 {
1509     return gt_tval_read(env, ri, GTIMER_SEC);
1510 }
1511
1512 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1513                               uint64_t value)
1514 {
1515     gt_tval_write(env, ri, GTIMER_SEC, value);
1516 }
1517
1518 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1519                               uint64_t value)
1520 {
1521     gt_ctl_write(env, ri, GTIMER_SEC, value);
1522 }
1523
1524 void arm_gt_ptimer_cb(void *opaque)
1525 {
1526     ARMCPU *cpu = opaque;
1527
1528     gt_recalc_timer(cpu, GTIMER_PHYS);
1529 }
1530
1531 void arm_gt_vtimer_cb(void *opaque)
1532 {
1533     ARMCPU *cpu = opaque;
1534
1535     gt_recalc_timer(cpu, GTIMER_VIRT);
1536 }
1537
1538 void arm_gt_htimer_cb(void *opaque)
1539 {
1540     ARMCPU *cpu = opaque;
1541
1542     gt_recalc_timer(cpu, GTIMER_HYP);
1543 }
1544
1545 void arm_gt_stimer_cb(void *opaque)
1546 {
1547     ARMCPU *cpu = opaque;
1548
1549     gt_recalc_timer(cpu, GTIMER_SEC);
1550 }
1551
1552 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1553     /* Note that CNTFRQ is purely reads-as-written for the benefit
1554      * of software; writing it doesn't actually change the timer frequency.
1555      * Our reset value matches the fixed frequency we implement the timer at.
1556      */
1557     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1558       .type = ARM_CP_ALIAS,
1559       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1560       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1561     },
1562     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1563       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1564       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1565       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1566       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1567     },
1568     /* overall control: mostly access permissions */
1569     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1570       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1571       .access = PL1_RW,
1572       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1573       .resetvalue = 0,
1574     },
1575     /* per-timer control */
1576     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1577       .secure = ARM_CP_SECSTATE_NS,
1578       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1579       .accessfn = gt_ptimer_access,
1580       .fieldoffset = offsetoflow32(CPUARMState,
1581                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1582       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1583     },
1584     { .name = "CNTP_CTL(S)",
1585       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1586       .secure = ARM_CP_SECSTATE_S,
1587       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1588       .accessfn = gt_ptimer_access,
1589       .fieldoffset = offsetoflow32(CPUARMState,
1590                                    cp15.c14_timer[GTIMER_SEC].ctl),
1591       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1592     },
1593     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1594       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1595       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1596       .accessfn = gt_ptimer_access,
1597       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1598       .resetvalue = 0,
1599       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1600     },
1601     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1602       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1603       .accessfn = gt_vtimer_access,
1604       .fieldoffset = offsetoflow32(CPUARMState,
1605                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1606       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1607     },
1608     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1609       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1610       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1611       .accessfn = gt_vtimer_access,
1612       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1613       .resetvalue = 0,
1614       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1615     },
1616     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1617     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1618       .secure = ARM_CP_SECSTATE_NS,
1619       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1620       .accessfn = gt_ptimer_access,
1621       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1622     },
1623     { .name = "CNTP_TVAL(S)",
1624       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1625       .secure = ARM_CP_SECSTATE_S,
1626       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1627       .accessfn = gt_ptimer_access,
1628       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1629     },
1630     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1631       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1632       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1633       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1634       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1635     },
1636     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1637       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1638       .accessfn = gt_vtimer_access,
1639       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1640     },
1641     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1642       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1643       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1644       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1645       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1646     },
1647     /* The counter itself */
1648     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1649       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1650       .accessfn = gt_pct_access,
1651       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1652     },
1653     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1654       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1655       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1656       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1657     },
1658     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1659       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1660       .accessfn = gt_vct_access,
1661       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1662     },
1663     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1664       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1665       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1666       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1667     },
1668     /* Comparison value, indicating when the timer goes off */
1669     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1670       .secure = ARM_CP_SECSTATE_NS,
1671       .access = PL1_RW | PL0_R,
1672       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1673       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1674       .accessfn = gt_ptimer_access,
1675       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1676     },
1677     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1678       .secure = ARM_CP_SECSTATE_S,
1679       .access = PL1_RW | PL0_R,
1680       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1681       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1682       .accessfn = gt_ptimer_access,
1683       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1684     },
1685     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1686       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1687       .access = PL1_RW | PL0_R,
1688       .type = ARM_CP_IO,
1689       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1690       .resetvalue = 0, .accessfn = gt_ptimer_access,
1691       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1692     },
1693     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1694       .access = PL1_RW | PL0_R,
1695       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1696       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1697       .accessfn = gt_vtimer_access,
1698       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1699     },
1700     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1701       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1702       .access = PL1_RW | PL0_R,
1703       .type = ARM_CP_IO,
1704       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1705       .resetvalue = 0, .accessfn = gt_vtimer_access,
1706       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1707     },
1708     /* Secure timer -- this is actually restricted to only EL3
1709      * and configurably Secure-EL1 via the accessfn.
1710      */
1711     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1712       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1713       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1714       .accessfn = gt_stimer_access,
1715       .readfn = gt_sec_tval_read,
1716       .writefn = gt_sec_tval_write,
1717       .resetfn = gt_sec_timer_reset,
1718     },
1719     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1720       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1721       .type = ARM_CP_IO, .access = PL1_RW,
1722       .accessfn = gt_stimer_access,
1723       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1724       .resetvalue = 0,
1725       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1726     },
1727     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1728       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1729       .type = ARM_CP_IO, .access = PL1_RW,
1730       .accessfn = gt_stimer_access,
1731       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1732       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1733     },
1734     REGINFO_SENTINEL
1735 };
1736
1737 #else
1738 /* In user-mode none of the generic timer registers are accessible,
1739  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1740  * so instead just don't register any of them.
1741  */
1742 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1743     REGINFO_SENTINEL
1744 };
1745
1746 #endif
1747
1748 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1749 {
1750     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1751         raw_write(env, ri, value);
1752     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1753         raw_write(env, ri, value & 0xfffff6ff);
1754     } else {
1755         raw_write(env, ri, value & 0xfffff1ff);
1756     }
1757 }
1758
1759 #ifndef CONFIG_USER_ONLY
1760 /* get_phys_addr() isn't present for user-mode-only targets */
1761
1762 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1763 {
1764     if (ri->opc2 & 4) {
1765         /* The ATS12NSO* operations must trap to EL3 if executed in
1766          * Secure EL1 (which can only happen if EL3 is AArch64).
1767          * They are simply UNDEF if executed from NS EL1.
1768          * They function normally from EL2 or EL3.
1769          */
1770         if (arm_current_el(env) == 1) {
1771             if (arm_is_secure_below_el3(env)) {
1772                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1773             }
1774             return CP_ACCESS_TRAP_UNCATEGORIZED;
1775         }
1776     }
1777     return CP_ACCESS_OK;
1778 }
1779
1780 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1781                              int access_type, ARMMMUIdx mmu_idx)
1782 {
1783     hwaddr phys_addr;
1784     target_ulong page_size;
1785     int prot;
1786     uint32_t fsr;
1787     bool ret;
1788     uint64_t par64;
1789     MemTxAttrs attrs = {};
1790     ARMMMUFaultInfo fi = {};
1791
1792     ret = get_phys_addr(env, value, access_type, mmu_idx,
1793                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1794     if (extended_addresses_enabled(env)) {
1795         /* fsr is a DFSR/IFSR value for the long descriptor
1796          * translation table format, but with WnR always clear.
1797          * Convert it to a 64-bit PAR.
1798          */
1799         par64 = (1 << 11); /* LPAE bit always set */
1800         if (!ret) {
1801             par64 |= phys_addr & ~0xfffULL;
1802             if (!attrs.secure) {
1803                 par64 |= (1 << 9); /* NS */
1804             }
1805             /* We don't set the ATTR or SH fields in the PAR. */
1806         } else {
1807             par64 |= 1; /* F */
1808             par64 |= (fsr & 0x3f) << 1; /* FS */
1809             /* Note that S2WLK and FSTAGE are always zero, because we don't
1810              * implement virtualization and therefore there can't be a stage 2
1811              * fault.
1812              */
1813         }
1814     } else {
1815         /* fsr is a DFSR/IFSR value for the short descriptor
1816          * translation table format (with WnR always clear).
1817          * Convert it to a 32-bit PAR.
1818          */
1819         if (!ret) {
1820             /* We do not set any attribute bits in the PAR */
1821             if (page_size == (1 << 24)
1822                 && arm_feature(env, ARM_FEATURE_V7)) {
1823                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1824             } else {
1825                 par64 = phys_addr & 0xfffff000;
1826             }
1827             if (!attrs.secure) {
1828                 par64 |= (1 << 9); /* NS */
1829             }
1830         } else {
1831             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1832                     ((fsr & 0xf) << 1) | 1;
1833         }
1834     }
1835     return par64;
1836 }
1837
1838 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1839 {
1840     int access_type = ri->opc2 & 1;
1841     uint64_t par64;
1842     ARMMMUIdx mmu_idx;
1843     int el = arm_current_el(env);
1844     bool secure = arm_is_secure_below_el3(env);
1845
1846     switch (ri->opc2 & 6) {
1847     case 0:
1848         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1849         switch (el) {
1850         case 3:
1851             mmu_idx = ARMMMUIdx_S1E3;
1852             break;
1853         case 2:
1854             mmu_idx = ARMMMUIdx_S1NSE1;
1855             break;
1856         case 1:
1857             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1858             break;
1859         default:
1860             g_assert_not_reached();
1861         }
1862         break;
1863     case 2:
1864         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1865         switch (el) {
1866         case 3:
1867             mmu_idx = ARMMMUIdx_S1SE0;
1868             break;
1869         case 2:
1870             mmu_idx = ARMMMUIdx_S1NSE0;
1871             break;
1872         case 1:
1873             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1874             break;
1875         default:
1876             g_assert_not_reached();
1877         }
1878         break;
1879     case 4:
1880         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1881         mmu_idx = ARMMMUIdx_S12NSE1;
1882         break;
1883     case 6:
1884         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1885         mmu_idx = ARMMMUIdx_S12NSE0;
1886         break;
1887     default:
1888         g_assert_not_reached();
1889     }
1890
1891     par64 = do_ats_write(env, value, access_type, mmu_idx);
1892
1893     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1894 }
1895
1896 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1897                         uint64_t value)
1898 {
1899     int access_type = ri->opc2 & 1;
1900     uint64_t par64;
1901
1902     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1903
1904     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1905 }
1906
1907 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
1908 {
1909     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1910         return CP_ACCESS_TRAP;
1911     }
1912     return CP_ACCESS_OK;
1913 }
1914
1915 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1916                         uint64_t value)
1917 {
1918     int access_type = ri->opc2 & 1;
1919     ARMMMUIdx mmu_idx;
1920     int secure = arm_is_secure_below_el3(env);
1921
1922     switch (ri->opc2 & 6) {
1923     case 0:
1924         switch (ri->opc1) {
1925         case 0: /* AT S1E1R, AT S1E1W */
1926             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1927             break;
1928         case 4: /* AT S1E2R, AT S1E2W */
1929             mmu_idx = ARMMMUIdx_S1E2;
1930             break;
1931         case 6: /* AT S1E3R, AT S1E3W */
1932             mmu_idx = ARMMMUIdx_S1E3;
1933             break;
1934         default:
1935             g_assert_not_reached();
1936         }
1937         break;
1938     case 2: /* AT S1E0R, AT S1E0W */
1939         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1940         break;
1941     case 4: /* AT S12E1R, AT S12E1W */
1942         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1943         break;
1944     case 6: /* AT S12E0R, AT S12E0W */
1945         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1946         break;
1947     default:
1948         g_assert_not_reached();
1949     }
1950
1951     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1952 }
1953 #endif
1954
1955 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1956     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1957       .access = PL1_RW, .resetvalue = 0,
1958       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1959                              offsetoflow32(CPUARMState, cp15.par_ns) },
1960       .writefn = par_write },
1961 #ifndef CONFIG_USER_ONLY
1962     /* This underdecoding is safe because the reginfo is NO_RAW. */
1963     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1964       .access = PL1_W, .accessfn = ats_access,
1965       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1966 #endif
1967     REGINFO_SENTINEL
1968 };
1969
1970 /* Return basic MPU access permission bits.  */
1971 static uint32_t simple_mpu_ap_bits(uint32_t val)
1972 {
1973     uint32_t ret;
1974     uint32_t mask;
1975     int i;
1976     ret = 0;
1977     mask = 3;
1978     for (i = 0; i < 16; i += 2) {
1979         ret |= (val >> i) & mask;
1980         mask <<= 2;
1981     }
1982     return ret;
1983 }
1984
1985 /* Pad basic MPU access permission bits to extended format.  */
1986 static uint32_t extended_mpu_ap_bits(uint32_t val)
1987 {
1988     uint32_t ret;
1989     uint32_t mask;
1990     int i;
1991     ret = 0;
1992     mask = 3;
1993     for (i = 0; i < 16; i += 2) {
1994         ret |= (val & mask) << i;
1995         mask <<= 2;
1996     }
1997     return ret;
1998 }
1999
2000 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2001                                  uint64_t value)
2002 {
2003     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2004 }
2005
2006 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2007 {
2008     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2009 }
2010
2011 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2012                                  uint64_t value)
2013 {
2014     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2015 }
2016
2017 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2018 {
2019     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2020 }
2021
2022 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2023 {
2024     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2025
2026     if (!u32p) {
2027         return 0;
2028     }
2029
2030     u32p += env->cp15.c6_rgnr;
2031     return *u32p;
2032 }
2033
2034 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2035                          uint64_t value)
2036 {
2037     ARMCPU *cpu = arm_env_get_cpu(env);
2038     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2039
2040     if (!u32p) {
2041         return;
2042     }
2043
2044     u32p += env->cp15.c6_rgnr;
2045     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2046     *u32p = value;
2047 }
2048
2049 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2050 {
2051     ARMCPU *cpu = arm_env_get_cpu(env);
2052     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2053
2054     if (!u32p) {
2055         return;
2056     }
2057
2058     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2059 }
2060
2061 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2062                               uint64_t value)
2063 {
2064     ARMCPU *cpu = arm_env_get_cpu(env);
2065     uint32_t nrgs = cpu->pmsav7_dregion;
2066
2067     if (value >= nrgs) {
2068         qemu_log_mask(LOG_GUEST_ERROR,
2069                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2070                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2071         return;
2072     }
2073
2074     raw_write(env, ri, value);
2075 }
2076
2077 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2078     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2079       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2080       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2081       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2082     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2083       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2084       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2085       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2086     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2087       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2088       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2089       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2090     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2091       .access = PL1_RW,
2092       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2093       .writefn = pmsav7_rgnr_write },
2094     REGINFO_SENTINEL
2095 };
2096
2097 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2098     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2099       .access = PL1_RW, .type = ARM_CP_ALIAS,
2100       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2101       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2102     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2103       .access = PL1_RW, .type = ARM_CP_ALIAS,
2104       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2105       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2106     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2107       .access = PL1_RW,
2108       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2109       .resetvalue = 0, },
2110     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2111       .access = PL1_RW,
2112       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2113       .resetvalue = 0, },
2114     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2115       .access = PL1_RW,
2116       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2117     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2118       .access = PL1_RW,
2119       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2120     /* Protection region base and size registers */
2121     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2122       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2123       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2124     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2125       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2126       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2127     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2128       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2129       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2130     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2131       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2132       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2133     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2134       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2135       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2136     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2137       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2138       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2139     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2140       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2141       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2142     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2143       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2144       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2145     REGINFO_SENTINEL
2146 };
2147
2148 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2149                                  uint64_t value)
2150 {
2151     TCR *tcr = raw_ptr(env, ri);
2152     int maskshift = extract32(value, 0, 3);
2153
2154     if (!arm_feature(env, ARM_FEATURE_V8)) {
2155         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2156             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2157              * using Long-desciptor translation table format */
2158             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2159         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2160             /* In an implementation that includes the Security Extensions
2161              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2162              * Short-descriptor translation table format.
2163              */
2164             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2165         } else {
2166             value &= TTBCR_N;
2167         }
2168     }
2169
2170     /* Update the masks corresponding to the TCR bank being written
2171      * Note that we always calculate mask and base_mask, but
2172      * they are only used for short-descriptor tables (ie if EAE is 0);
2173      * for long-descriptor tables the TCR fields are used differently
2174      * and the mask and base_mask values are meaningless.
2175      */
2176     tcr->raw_tcr = value;
2177     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2178     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2179 }
2180
2181 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2182                              uint64_t value)
2183 {
2184     ARMCPU *cpu = arm_env_get_cpu(env);
2185
2186     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2187         /* With LPAE the TTBCR could result in a change of ASID
2188          * via the TTBCR.A1 bit, so do a TLB flush.
2189          */
2190         tlb_flush(CPU(cpu), 1);
2191     }
2192     vmsa_ttbcr_raw_write(env, ri, value);
2193 }
2194
2195 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2196 {
2197     TCR *tcr = raw_ptr(env, ri);
2198
2199     /* Reset both the TCR as well as the masks corresponding to the bank of
2200      * the TCR being reset.
2201      */
2202     tcr->raw_tcr = 0;
2203     tcr->mask = 0;
2204     tcr->base_mask = 0xffffc000u;
2205 }
2206
2207 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2208                                uint64_t value)
2209 {
2210     ARMCPU *cpu = arm_env_get_cpu(env);
2211     TCR *tcr = raw_ptr(env, ri);
2212
2213     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2214     tlb_flush(CPU(cpu), 1);
2215     tcr->raw_tcr = value;
2216 }
2217
2218 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2219                             uint64_t value)
2220 {
2221     /* 64 bit accesses to the TTBRs can change the ASID and so we
2222      * must flush the TLB.
2223      */
2224     if (cpreg_field_is_64bit(ri)) {
2225         ARMCPU *cpu = arm_env_get_cpu(env);
2226
2227         tlb_flush(CPU(cpu), 1);
2228     }
2229     raw_write(env, ri, value);
2230 }
2231
2232 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2233                         uint64_t value)
2234 {
2235     ARMCPU *cpu = arm_env_get_cpu(env);
2236     CPUState *cs = CPU(cpu);
2237
2238     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2239     if (raw_read(env, ri) != value) {
2240         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2241                             ARMMMUIdx_S2NS, -1);
2242         raw_write(env, ri, value);
2243     }
2244 }
2245
2246 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2247     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2248       .access = PL1_RW, .type = ARM_CP_ALIAS,
2249       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2250                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2251     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2252       .access = PL1_RW, .resetvalue = 0,
2253       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2254                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2255     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2256       .access = PL1_RW, .resetvalue = 0,
2257       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2258                              offsetof(CPUARMState, cp15.dfar_ns) } },
2259     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2260       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2261       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2262       .resetvalue = 0, },
2263     REGINFO_SENTINEL
2264 };
2265
2266 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2267     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2268       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2269       .access = PL1_RW,
2270       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2271     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2272       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2273       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2274       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2275                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2276     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2277       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2278       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2279       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2280                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2281     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2282       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2283       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2284       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2285       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2286     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2287       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2288       .raw_writefn = vmsa_ttbcr_raw_write,
2289       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2290                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2291     REGINFO_SENTINEL
2292 };
2293
2294 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2295                                 uint64_t value)
2296 {
2297     env->cp15.c15_ticonfig = value & 0xe7;
2298     /* The OS_TYPE bit in this register changes the reported CPUID! */
2299     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2300         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2301 }
2302
2303 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2304                                 uint64_t value)
2305 {
2306     env->cp15.c15_threadid = value & 0xffff;
2307 }
2308
2309 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2310                            uint64_t value)
2311 {
2312     /* Wait-for-interrupt (deprecated) */
2313     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2314 }
2315
2316 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2317                                   uint64_t value)
2318 {
2319     /* On OMAP there are registers indicating the max/min index of dcache lines
2320      * containing a dirty line; cache flush operations have to reset these.
2321      */
2322     env->cp15.c15_i_max = 0x000;
2323     env->cp15.c15_i_min = 0xff0;
2324 }
2325
2326 static const ARMCPRegInfo omap_cp_reginfo[] = {
2327     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2328       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2329       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2330       .resetvalue = 0, },
2331     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2332       .access = PL1_RW, .type = ARM_CP_NOP },
2333     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2334       .access = PL1_RW,
2335       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2336       .writefn = omap_ticonfig_write },
2337     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2338       .access = PL1_RW,
2339       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2340     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2341       .access = PL1_RW, .resetvalue = 0xff0,
2342       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2343     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2344       .access = PL1_RW,
2345       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2346       .writefn = omap_threadid_write },
2347     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2348       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2349       .type = ARM_CP_NO_RAW,
2350       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2351     /* TODO: Peripheral port remap register:
2352      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2353      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2354      * when MMU is off.
2355      */
2356     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2357       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2358       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2359       .writefn = omap_cachemaint_write },
2360     { .name = "C9", .cp = 15, .crn = 9,
2361       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2362       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2363     REGINFO_SENTINEL
2364 };
2365
2366 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2367                               uint64_t value)
2368 {
2369     env->cp15.c15_cpar = value & 0x3fff;
2370 }
2371
2372 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2373     { .name = "XSCALE_CPAR",
2374       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2375       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2376       .writefn = xscale_cpar_write, },
2377     { .name = "XSCALE_AUXCR",
2378       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2379       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2380       .resetvalue = 0, },
2381     /* XScale specific cache-lockdown: since we have no cache we NOP these
2382      * and hope the guest does not really rely on cache behaviour.
2383      */
2384     { .name = "XSCALE_LOCK_ICACHE_LINE",
2385       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2386       .access = PL1_W, .type = ARM_CP_NOP },
2387     { .name = "XSCALE_UNLOCK_ICACHE",
2388       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2389       .access = PL1_W, .type = ARM_CP_NOP },
2390     { .name = "XSCALE_DCACHE_LOCK",
2391       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2392       .access = PL1_RW, .type = ARM_CP_NOP },
2393     { .name = "XSCALE_UNLOCK_DCACHE",
2394       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2395       .access = PL1_W, .type = ARM_CP_NOP },
2396     REGINFO_SENTINEL
2397 };
2398
2399 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2400     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2401      * implementation of this implementation-defined space.
2402      * Ideally this should eventually disappear in favour of actually
2403      * implementing the correct behaviour for all cores.
2404      */
2405     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2406       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2407       .access = PL1_RW,
2408       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2409       .resetvalue = 0 },
2410     REGINFO_SENTINEL
2411 };
2412
2413 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2414     /* Cache status: RAZ because we have no cache so it's always clean */
2415     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2416       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2417       .resetvalue = 0 },
2418     REGINFO_SENTINEL
2419 };
2420
2421 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2422     /* We never have a a block transfer operation in progress */
2423     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2424       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2425       .resetvalue = 0 },
2426     /* The cache ops themselves: these all NOP for QEMU */
2427     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2428       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2429     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2430       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2431     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2432       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2433     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2434       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2435     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2436       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2437     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2438       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2439     REGINFO_SENTINEL
2440 };
2441
2442 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2443     /* The cache test-and-clean instructions always return (1 << 30)
2444      * to indicate that there are no dirty cache lines.
2445      */
2446     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2447       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2448       .resetvalue = (1 << 30) },
2449     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2450       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2451       .resetvalue = (1 << 30) },
2452     REGINFO_SENTINEL
2453 };
2454
2455 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2456     /* Ignore ReadBuffer accesses */
2457     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2458       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2459       .access = PL1_RW, .resetvalue = 0,
2460       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2461     REGINFO_SENTINEL
2462 };
2463
2464 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2465 {
2466     ARMCPU *cpu = arm_env_get_cpu(env);
2467     unsigned int cur_el = arm_current_el(env);
2468     bool secure = arm_is_secure(env);
2469
2470     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2471         return env->cp15.vpidr_el2;
2472     }
2473     return raw_read(env, ri);
2474 }
2475
2476 static uint64_t mpidr_read_val(CPUARMState *env)
2477 {
2478     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2479     uint64_t mpidr = cpu->mp_affinity;
2480
2481     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2482         mpidr |= (1U << 31);
2483         /* Cores which are uniprocessor (non-coherent)
2484          * but still implement the MP extensions set
2485          * bit 30. (For instance, Cortex-R5).
2486          */
2487         if (cpu->mp_is_up) {
2488             mpidr |= (1u << 30);
2489         }
2490     }
2491     return mpidr;
2492 }
2493
2494 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2495 {
2496     unsigned int cur_el = arm_current_el(env);
2497     bool secure = arm_is_secure(env);
2498
2499     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2500         return env->cp15.vmpidr_el2;
2501     }
2502     return mpidr_read_val(env);
2503 }
2504
2505 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2506     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2507       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2508       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2509     REGINFO_SENTINEL
2510 };
2511
2512 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2513     /* NOP AMAIR0/1 */
2514     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2515       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2516       .access = PL1_RW, .type = ARM_CP_CONST,
2517       .resetvalue = 0 },
2518     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2519     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2520       .access = PL1_RW, .type = ARM_CP_CONST,
2521       .resetvalue = 0 },
2522     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2523       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2524       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2525                              offsetof(CPUARMState, cp15.par_ns)} },
2526     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2527       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2528       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2529                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2530       .writefn = vmsa_ttbr_write, },
2531     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2532       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2533       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2534                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2535       .writefn = vmsa_ttbr_write, },
2536     REGINFO_SENTINEL
2537 };
2538
2539 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2540 {
2541     return vfp_get_fpcr(env);
2542 }
2543
2544 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2545                             uint64_t value)
2546 {
2547     vfp_set_fpcr(env, value);
2548 }
2549
2550 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2551 {
2552     return vfp_get_fpsr(env);
2553 }
2554
2555 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2556                             uint64_t value)
2557 {
2558     vfp_set_fpsr(env, value);
2559 }
2560
2561 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2562 {
2563     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2564         return CP_ACCESS_TRAP;
2565     }
2566     return CP_ACCESS_OK;
2567 }
2568
2569 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2570                             uint64_t value)
2571 {
2572     env->daif = value & PSTATE_DAIF;
2573 }
2574
2575 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2576                                           const ARMCPRegInfo *ri)
2577 {
2578     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2579      * SCTLR_EL1.UCI is set.
2580      */
2581     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2582         return CP_ACCESS_TRAP;
2583     }
2584     return CP_ACCESS_OK;
2585 }
2586
2587 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2588  * Page D4-1736 (DDI0487A.b)
2589  */
2590
2591 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2592                                     uint64_t value)
2593 {
2594     ARMCPU *cpu = arm_env_get_cpu(env);
2595     CPUState *cs = CPU(cpu);
2596
2597     if (arm_is_secure_below_el3(env)) {
2598         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2599     } else {
2600         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2601     }
2602 }
2603
2604 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2605                                       uint64_t value)
2606 {
2607     bool sec = arm_is_secure_below_el3(env);
2608     CPUState *other_cs;
2609
2610     CPU_FOREACH(other_cs) {
2611         if (sec) {
2612             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2613         } else {
2614             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2615                                 ARMMMUIdx_S12NSE0, -1);
2616         }
2617     }
2618 }
2619
2620 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2621                                   uint64_t value)
2622 {
2623     /* Note that the 'ALL' scope must invalidate both stage 1 and
2624      * stage 2 translations, whereas most other scopes only invalidate
2625      * stage 1 translations.
2626      */
2627     ARMCPU *cpu = arm_env_get_cpu(env);
2628     CPUState *cs = CPU(cpu);
2629
2630     if (arm_is_secure_below_el3(env)) {
2631         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2632     } else {
2633         if (arm_feature(env, ARM_FEATURE_EL2)) {
2634             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2635                                 ARMMMUIdx_S2NS, -1);
2636         } else {
2637             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2638         }
2639     }
2640 }
2641
2642 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2643                                   uint64_t value)
2644 {
2645     ARMCPU *cpu = arm_env_get_cpu(env);
2646     CPUState *cs = CPU(cpu);
2647
2648     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2649 }
2650
2651 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2652                                   uint64_t value)
2653 {
2654     ARMCPU *cpu = arm_env_get_cpu(env);
2655     CPUState *cs = CPU(cpu);
2656
2657     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2658 }
2659
2660 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2661                                     uint64_t value)
2662 {
2663     /* Note that the 'ALL' scope must invalidate both stage 1 and
2664      * stage 2 translations, whereas most other scopes only invalidate
2665      * stage 1 translations.
2666      */
2667     bool sec = arm_is_secure_below_el3(env);
2668     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2669     CPUState *other_cs;
2670
2671     CPU_FOREACH(other_cs) {
2672         if (sec) {
2673             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2674         } else if (has_el2) {
2675             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2676                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2677         } else {
2678             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2679                                 ARMMMUIdx_S12NSE0, -1);
2680         }
2681     }
2682 }
2683
2684 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2685                                     uint64_t value)
2686 {
2687     CPUState *other_cs;
2688
2689     CPU_FOREACH(other_cs) {
2690         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2691     }
2692 }
2693
2694 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2695                                     uint64_t value)
2696 {
2697     CPUState *other_cs;
2698
2699     CPU_FOREACH(other_cs) {
2700         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2701     }
2702 }
2703
2704 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2705                                  uint64_t value)
2706 {
2707     /* Invalidate by VA, EL1&0 (AArch64 version).
2708      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2709      * since we don't support flush-for-specific-ASID-only or
2710      * flush-last-level-only.
2711      */
2712     ARMCPU *cpu = arm_env_get_cpu(env);
2713     CPUState *cs = CPU(cpu);
2714     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2715
2716     if (arm_is_secure_below_el3(env)) {
2717         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2718                                  ARMMMUIdx_S1SE0, -1);
2719     } else {
2720         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2721                                  ARMMMUIdx_S12NSE0, -1);
2722     }
2723 }
2724
2725 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2726                                  uint64_t value)
2727 {
2728     /* Invalidate by VA, EL2
2729      * Currently handles both VAE2 and VALE2, since we don't support
2730      * flush-last-level-only.
2731      */
2732     ARMCPU *cpu = arm_env_get_cpu(env);
2733     CPUState *cs = CPU(cpu);
2734     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2735
2736     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2737 }
2738
2739 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2740                                  uint64_t value)
2741 {
2742     /* Invalidate by VA, EL3
2743      * Currently handles both VAE3 and VALE3, since we don't support
2744      * flush-last-level-only.
2745      */
2746     ARMCPU *cpu = arm_env_get_cpu(env);
2747     CPUState *cs = CPU(cpu);
2748     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2749
2750     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2751 }
2752
2753 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2754                                    uint64_t value)
2755 {
2756     bool sec = arm_is_secure_below_el3(env);
2757     CPUState *other_cs;
2758     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2759
2760     CPU_FOREACH(other_cs) {
2761         if (sec) {
2762             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2763                                      ARMMMUIdx_S1SE0, -1);
2764         } else {
2765             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2766                                      ARMMMUIdx_S12NSE0, -1);
2767         }
2768     }
2769 }
2770
2771 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2772                                    uint64_t value)
2773 {
2774     CPUState *other_cs;
2775     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2776
2777     CPU_FOREACH(other_cs) {
2778         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2779     }
2780 }
2781
2782 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2783                                    uint64_t value)
2784 {
2785     CPUState *other_cs;
2786     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2787
2788     CPU_FOREACH(other_cs) {
2789         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2790     }
2791 }
2792
2793 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2794                                     uint64_t value)
2795 {
2796     /* Invalidate by IPA. This has to invalidate any structures that
2797      * contain only stage 2 translation information, but does not need
2798      * to apply to structures that contain combined stage 1 and stage 2
2799      * translation information.
2800      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2801      */
2802     ARMCPU *cpu = arm_env_get_cpu(env);
2803     CPUState *cs = CPU(cpu);
2804     uint64_t pageaddr;
2805
2806     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2807         return;
2808     }
2809
2810     pageaddr = sextract64(value << 12, 0, 48);
2811
2812     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2813 }
2814
2815 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2816                                       uint64_t value)
2817 {
2818     CPUState *other_cs;
2819     uint64_t pageaddr;
2820
2821     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2822         return;
2823     }
2824
2825     pageaddr = sextract64(value << 12, 0, 48);
2826
2827     CPU_FOREACH(other_cs) {
2828         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2829     }
2830 }
2831
2832 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2833 {
2834     /* We don't implement EL2, so the only control on DC ZVA is the
2835      * bit in the SCTLR which can prohibit access for EL0.
2836      */
2837     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2838         return CP_ACCESS_TRAP;
2839     }
2840     return CP_ACCESS_OK;
2841 }
2842
2843 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2844 {
2845     ARMCPU *cpu = arm_env_get_cpu(env);
2846     int dzp_bit = 1 << 4;
2847
2848     /* DZP indicates whether DC ZVA access is allowed */
2849     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2850         dzp_bit = 0;
2851     }
2852     return cpu->dcz_blocksize | dzp_bit;
2853 }
2854
2855 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2856 {
2857     if (!(env->pstate & PSTATE_SP)) {
2858         /* Access to SP_EL0 is undefined if it's being used as
2859          * the stack pointer.
2860          */
2861         return CP_ACCESS_TRAP_UNCATEGORIZED;
2862     }
2863     return CP_ACCESS_OK;
2864 }
2865
2866 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2867 {
2868     return env->pstate & PSTATE_SP;
2869 }
2870
2871 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2872 {
2873     update_spsel(env, val);
2874 }
2875
2876 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2877                         uint64_t value)
2878 {
2879     ARMCPU *cpu = arm_env_get_cpu(env);
2880
2881     if (raw_read(env, ri) == value) {
2882         /* Skip the TLB flush if nothing actually changed; Linux likes
2883          * to do a lot of pointless SCTLR writes.
2884          */
2885         return;
2886     }
2887
2888     raw_write(env, ri, value);
2889     /* ??? Lots of these bits are not implemented.  */
2890     /* This may enable/disable the MMU, so do a TLB flush.  */
2891     tlb_flush(CPU(cpu), 1);
2892 }
2893
2894 static const ARMCPRegInfo v8_cp_reginfo[] = {
2895     /* Minimal set of EL0-visible registers. This will need to be expanded
2896      * significantly for system emulation of AArch64 CPUs.
2897      */
2898     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2899       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2900       .access = PL0_RW, .type = ARM_CP_NZCV },
2901     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2902       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2903       .type = ARM_CP_NO_RAW,
2904       .access = PL0_RW, .accessfn = aa64_daif_access,
2905       .fieldoffset = offsetof(CPUARMState, daif),
2906       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2907     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2908       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2909       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2910     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2911       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2912       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2913     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2914       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2915       .access = PL0_R, .type = ARM_CP_NO_RAW,
2916       .readfn = aa64_dczid_read },
2917     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2918       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2919       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2920 #ifndef CONFIG_USER_ONLY
2921       /* Avoid overhead of an access check that always passes in user-mode */
2922       .accessfn = aa64_zva_access,
2923 #endif
2924     },
2925     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2926       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2927       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2928     /* Cache ops: all NOPs since we don't emulate caches */
2929     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2930       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2931       .access = PL1_W, .type = ARM_CP_NOP },
2932     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2933       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2934       .access = PL1_W, .type = ARM_CP_NOP },
2935     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2936       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2937       .access = PL0_W, .type = ARM_CP_NOP,
2938       .accessfn = aa64_cacheop_access },
2939     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2940       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2941       .access = PL1_W, .type = ARM_CP_NOP },
2942     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2943       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2944       .access = PL1_W, .type = ARM_CP_NOP },
2945     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2946       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2947       .access = PL0_W, .type = ARM_CP_NOP,
2948       .accessfn = aa64_cacheop_access },
2949     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2950       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2951       .access = PL1_W, .type = ARM_CP_NOP },
2952     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2953       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2954       .access = PL0_W, .type = ARM_CP_NOP,
2955       .accessfn = aa64_cacheop_access },
2956     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2957       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2958       .access = PL0_W, .type = ARM_CP_NOP,
2959       .accessfn = aa64_cacheop_access },
2960     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2961       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2962       .access = PL1_W, .type = ARM_CP_NOP },
2963     /* TLBI operations */
2964     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2965       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2966       .access = PL1_W, .type = ARM_CP_NO_RAW,
2967       .writefn = tlbi_aa64_vmalle1is_write },
2968     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2969       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2970       .access = PL1_W, .type = ARM_CP_NO_RAW,
2971       .writefn = tlbi_aa64_vae1is_write },
2972     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2973       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2974       .access = PL1_W, .type = ARM_CP_NO_RAW,
2975       .writefn = tlbi_aa64_vmalle1is_write },
2976     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2977       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2978       .access = PL1_W, .type = ARM_CP_NO_RAW,
2979       .writefn = tlbi_aa64_vae1is_write },
2980     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2981       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2982       .access = PL1_W, .type = ARM_CP_NO_RAW,
2983       .writefn = tlbi_aa64_vae1is_write },
2984     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2985       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2986       .access = PL1_W, .type = ARM_CP_NO_RAW,
2987       .writefn = tlbi_aa64_vae1is_write },
2988     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2989       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2990       .access = PL1_W, .type = ARM_CP_NO_RAW,
2991       .writefn = tlbi_aa64_vmalle1_write },
2992     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2993       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2994       .access = PL1_W, .type = ARM_CP_NO_RAW,
2995       .writefn = tlbi_aa64_vae1_write },
2996     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2997       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2998       .access = PL1_W, .type = ARM_CP_NO_RAW,
2999       .writefn = tlbi_aa64_vmalle1_write },
3000     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3001       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3002       .access = PL1_W, .type = ARM_CP_NO_RAW,
3003       .writefn = tlbi_aa64_vae1_write },
3004     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3005       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3006       .access = PL1_W, .type = ARM_CP_NO_RAW,
3007       .writefn = tlbi_aa64_vae1_write },
3008     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3009       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3010       .access = PL1_W, .type = ARM_CP_NO_RAW,
3011       .writefn = tlbi_aa64_vae1_write },
3012     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3013       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3014       .access = PL2_W, .type = ARM_CP_NO_RAW,
3015       .writefn = tlbi_aa64_ipas2e1is_write },
3016     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3017       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3018       .access = PL2_W, .type = ARM_CP_NO_RAW,
3019       .writefn = tlbi_aa64_ipas2e1is_write },
3020     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3021       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3022       .access = PL2_W, .type = ARM_CP_NO_RAW,
3023       .writefn = tlbi_aa64_alle1is_write },
3024     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3025       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3026       .access = PL2_W, .type = ARM_CP_NO_RAW,
3027       .writefn = tlbi_aa64_alle1is_write },
3028     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3029       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3030       .access = PL2_W, .type = ARM_CP_NO_RAW,
3031       .writefn = tlbi_aa64_ipas2e1_write },
3032     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3033       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3034       .access = PL2_W, .type = ARM_CP_NO_RAW,
3035       .writefn = tlbi_aa64_ipas2e1_write },
3036     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3037       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3038       .access = PL2_W, .type = ARM_CP_NO_RAW,
3039       .writefn = tlbi_aa64_alle1_write },
3040     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3041       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3042       .access = PL2_W, .type = ARM_CP_NO_RAW,
3043       .writefn = tlbi_aa64_alle1is_write },
3044 #ifndef CONFIG_USER_ONLY
3045     /* 64 bit address translation operations */
3046     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3047       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3048       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3049     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3050       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3051       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3052     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3053       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3054       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3055     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3056       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3057       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3058     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3059       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3060       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3061     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3062       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3063       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3064     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3065       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3066       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3067     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3068       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3069       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3070     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3071     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3072       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3073       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3074     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3075       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3076       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3077     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3078       .type = ARM_CP_ALIAS,
3079       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3080       .access = PL1_RW, .resetvalue = 0,
3081       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3082       .writefn = par_write },
3083 #endif
3084     /* TLB invalidate last level of translation table walk */
3085     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3086       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3087     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3088       .type = ARM_CP_NO_RAW, .access = PL1_W,
3089       .writefn = tlbimvaa_is_write },
3090     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3091       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3092     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3093       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3094     /* 32 bit cache operations */
3095     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3096       .type = ARM_CP_NOP, .access = PL1_W },
3097     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3098       .type = ARM_CP_NOP, .access = PL1_W },
3099     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3100       .type = ARM_CP_NOP, .access = PL1_W },
3101     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3102       .type = ARM_CP_NOP, .access = PL1_W },
3103     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3104       .type = ARM_CP_NOP, .access = PL1_W },
3105     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3106       .type = ARM_CP_NOP, .access = PL1_W },
3107     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3108       .type = ARM_CP_NOP, .access = PL1_W },
3109     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3110       .type = ARM_CP_NOP, .access = PL1_W },
3111     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3112       .type = ARM_CP_NOP, .access = PL1_W },
3113     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3114       .type = ARM_CP_NOP, .access = PL1_W },
3115     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3116       .type = ARM_CP_NOP, .access = PL1_W },
3117     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3118       .type = ARM_CP_NOP, .access = PL1_W },
3119     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3120       .type = ARM_CP_NOP, .access = PL1_W },
3121     /* MMU Domain access control / MPU write buffer control */
3122     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3123       .access = PL1_RW, .resetvalue = 0,
3124       .writefn = dacr_write, .raw_writefn = raw_write,
3125       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3126                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3127     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3128       .type = ARM_CP_ALIAS,
3129       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3130       .access = PL1_RW,
3131       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3132     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3133       .type = ARM_CP_ALIAS,
3134       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3135       .access = PL1_RW,
3136       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3137     /* We rely on the access checks not allowing the guest to write to the
3138      * state field when SPSel indicates that it's being used as the stack
3139      * pointer.
3140      */
3141     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3142       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3143       .access = PL1_RW, .accessfn = sp_el0_access,
3144       .type = ARM_CP_ALIAS,
3145       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3146     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3147       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3148       .access = PL2_RW, .type = ARM_CP_ALIAS,
3149       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3150     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3151       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3152       .type = ARM_CP_NO_RAW,
3153       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3154     REGINFO_SENTINEL
3155 };
3156
3157 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3158 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3159     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3160       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3161       .access = PL2_RW,
3162       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3163     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3164       .type = ARM_CP_NO_RAW,
3165       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3166       .access = PL2_RW,
3167       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3168     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3169       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3170       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3171     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3172       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3173       .access = PL2_RW, .type = ARM_CP_CONST,
3174       .resetvalue = 0 },
3175     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3176       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3177       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3178     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3179       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3180       .access = PL2_RW, .type = ARM_CP_CONST,
3181       .resetvalue = 0 },
3182     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3183       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3184       .access = PL2_RW, .type = ARM_CP_CONST,
3185       .resetvalue = 0 },
3186     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3187       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3188       .access = PL2_RW, .type = ARM_CP_CONST,
3189       .resetvalue = 0 },
3190     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3191       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3192       .access = PL2_RW, .type = ARM_CP_CONST,
3193       .resetvalue = 0 },
3194     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3195       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3196       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3197     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3198       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3199       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3200       .type = ARM_CP_CONST, .resetvalue = 0 },
3201     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3202       .cp = 15, .opc1 = 6, .crm = 2,
3203       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3204       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3205     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3207       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3208     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3209       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3210       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3211     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3212       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3213       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3214     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3215       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3216       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3217     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3218       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3219       .resetvalue = 0 },
3220     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3221       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3222       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3223     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3224       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3225       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3226     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3227       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3228       .resetvalue = 0 },
3229     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3230       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3231       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3232     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3233       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3234       .resetvalue = 0 },
3235     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3236       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3237       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3238     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3239       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3240       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3241     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3242       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3243       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3244     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3245       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3246       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3247       .type = ARM_CP_CONST, .resetvalue = 0 },
3248     REGINFO_SENTINEL
3249 };
3250
3251 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3252 {
3253     ARMCPU *cpu = arm_env_get_cpu(env);
3254     uint64_t valid_mask = HCR_MASK;
3255
3256     if (arm_feature(env, ARM_FEATURE_EL3)) {
3257         valid_mask &= ~HCR_HCD;
3258     } else {
3259         valid_mask &= ~HCR_TSC;
3260     }
3261
3262     /* Clear RES0 bits.  */
3263     value &= valid_mask;
3264
3265     /* These bits change the MMU setup:
3266      * HCR_VM enables stage 2 translation
3267      * HCR_PTW forbids certain page-table setups
3268      * HCR_DC Disables stage1 and enables stage2 translation
3269      */
3270     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3271         tlb_flush(CPU(cpu), 1);
3272     }
3273     raw_write(env, ri, value);
3274 }
3275
3276 static const ARMCPRegInfo el2_cp_reginfo[] = {
3277     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3278       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3279       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3280       .writefn = hcr_write },
3281     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3282       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3283       .access = PL2_RW, .resetvalue = 0,
3284       .writefn = dacr_write, .raw_writefn = raw_write,
3285       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3286     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3287       .type = ARM_CP_ALIAS,
3288       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3289       .access = PL2_RW,
3290       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3291     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3292       .type = ARM_CP_ALIAS,
3293       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3294       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3295     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3296       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3297       .access = PL2_RW, .resetvalue = 0,
3298       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3299     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3300       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3301       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3302     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3303       .type = ARM_CP_ALIAS,
3304       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3305       .access = PL2_RW,
3306       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3307     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3308       .type = ARM_CP_ALIAS,
3309       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3310       .access = PL2_RW,
3311       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3312     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3313       .type = ARM_CP_ALIAS,
3314       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3315       .access = PL2_RW,
3316       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3317     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3318       .type = ARM_CP_ALIAS,
3319       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3320       .access = PL2_RW,
3321       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3322     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3323       .type = ARM_CP_ALIAS,
3324       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3325       .access = PL2_RW,
3326       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3327     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3328       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3329       .access = PL2_RW, .writefn = vbar_write,
3330       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3331       .resetvalue = 0 },
3332     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3333       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3334       .access = PL3_RW, .type = ARM_CP_ALIAS,
3335       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3336     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3337       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3338       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3339       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3340     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3341       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3342       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3343       .resetvalue = 0 },
3344     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3345       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3346       .access = PL2_RW, .type = ARM_CP_ALIAS,
3347       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3348     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3349       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3350       .access = PL2_RW, .type = ARM_CP_CONST,
3351       .resetvalue = 0 },
3352     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3353     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3354       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3355       .access = PL2_RW, .type = ARM_CP_CONST,
3356       .resetvalue = 0 },
3357     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3358       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3359       .access = PL2_RW, .type = ARM_CP_CONST,
3360       .resetvalue = 0 },
3361     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3362       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3363       .access = PL2_RW, .type = ARM_CP_CONST,
3364       .resetvalue = 0 },
3365     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3366       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3367       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3368       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3369       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3370     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3371       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3372       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3373       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3374     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3375       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3376       .access = PL2_RW, .type = ARM_CP_ALIAS,
3377       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3378     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3379       .cp = 15, .opc1 = 6, .crm = 2,
3380       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3381       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3382       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3383       .writefn = vttbr_write },
3384     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3385       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3386       .access = PL2_RW, .writefn = vttbr_write,
3387       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3388     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3389       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3390       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3391       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3392     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3393       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3394       .access = PL2_RW, .resetvalue = 0,
3395       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3396     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3397       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3398       .access = PL2_RW, .resetvalue = 0,
3399       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3400     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3401       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3402       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3403     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3404       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3405       .type = ARM_CP_NO_RAW, .access = PL2_W,
3406       .writefn = tlbi_aa64_alle2_write },
3407     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3408       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3409       .type = ARM_CP_NO_RAW, .access = PL2_W,
3410       .writefn = tlbi_aa64_vae2_write },
3411     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3412       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3413       .access = PL2_W, .type = ARM_CP_NO_RAW,
3414       .writefn = tlbi_aa64_vae2_write },
3415     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3416       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3417       .access = PL2_W, .type = ARM_CP_NO_RAW,
3418       .writefn = tlbi_aa64_alle2is_write },
3419     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3420       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3421       .type = ARM_CP_NO_RAW, .access = PL2_W,
3422       .writefn = tlbi_aa64_vae2is_write },
3423     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3424       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3425       .access = PL2_W, .type = ARM_CP_NO_RAW,
3426       .writefn = tlbi_aa64_vae2is_write },
3427 #ifndef CONFIG_USER_ONLY
3428     /* Unlike the other EL2-related AT operations, these must
3429      * UNDEF from EL3 if EL2 is not implemented, which is why we
3430      * define them here rather than with the rest of the AT ops.
3431      */
3432     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3433       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3434       .access = PL2_W, .accessfn = at_s1e2_access,
3435       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3436     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3437       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3438       .access = PL2_W, .accessfn = at_s1e2_access,
3439       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3440     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3441      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3442      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3443      * to behave as if SCR.NS was 1.
3444      */
3445     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3446       .access = PL2_W,
3447       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3448     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3449       .access = PL2_W,
3450       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3451     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3452       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3453       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3454        * reset values as IMPDEF. We choose to reset to 3 to comply with
3455        * both ARMv7 and ARMv8.
3456        */
3457       .access = PL2_RW, .resetvalue = 3,
3458       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3459     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3460       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3461       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3462       .writefn = gt_cntvoff_write,
3463       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3464     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3465       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3466       .writefn = gt_cntvoff_write,
3467       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3468     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3469       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3470       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3471       .type = ARM_CP_IO, .access = PL2_RW,
3472       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3473     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3474       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3475       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3476       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3477     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3478       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3479       .type = ARM_CP_IO, .access = PL2_RW,
3480       .resetfn = gt_hyp_timer_reset,
3481       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3482     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3483       .type = ARM_CP_IO,
3484       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3485       .access = PL2_RW,
3486       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3487       .resetvalue = 0,
3488       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3489 #endif
3490     /* The only field of MDCR_EL2 that has a defined architectural reset value
3491      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3492      * don't impelment any PMU event counters, so using zero as a reset
3493      * value for MDCR_EL2 is okay
3494      */
3495     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3496       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3497       .access = PL2_RW, .resetvalue = 0,
3498       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3499     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3500       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3501       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3502       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3503     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3504       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3505       .access = PL2_RW,
3506       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3507     REGINFO_SENTINEL
3508 };
3509
3510 static const ARMCPRegInfo el3_cp_reginfo[] = {
3511     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3512       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3513       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3514       .resetvalue = 0, .writefn = scr_write },
3515     { .name = "SCR",  .type = ARM_CP_ALIAS,
3516       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3517       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3518       .writefn = scr_write },
3519     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3520       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3521       .access = PL3_RW, .resetvalue = 0,
3522       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3523     { .name = "SDER",
3524       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3525       .access = PL3_RW, .resetvalue = 0,
3526       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3527       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3528     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
3529       .access = PL3_W | PL1_R, .resetvalue = 0,
3530       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
3531     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3532       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
3533       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3534     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3535       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3536       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3537       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3538       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3539     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3540       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3541       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3542       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3543     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3544       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3545       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3546       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3547       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3548     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3549       .type = ARM_CP_ALIAS,
3550       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3551       .access = PL3_RW,
3552       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3553     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3554       .type = ARM_CP_ALIAS,
3555       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3556       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3557     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3558       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3559       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3560     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3561       .type = ARM_CP_ALIAS,
3562       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3563       .access = PL3_RW,
3564       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3565     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3566       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3567       .access = PL3_RW, .writefn = vbar_write,
3568       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3569       .resetvalue = 0 },
3570     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3571       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3572       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3573       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3574     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3575       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3576       .access = PL3_RW, .resetvalue = 0,
3577       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3578     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3579       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3580       .access = PL3_RW, .type = ARM_CP_CONST,
3581       .resetvalue = 0 },
3582     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3583       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3584       .access = PL3_RW, .type = ARM_CP_CONST,
3585       .resetvalue = 0 },
3586     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3587       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3588       .access = PL3_RW, .type = ARM_CP_CONST,
3589       .resetvalue = 0 },
3590     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3591       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3592       .access = PL3_W, .type = ARM_CP_NO_RAW,
3593       .writefn = tlbi_aa64_alle3is_write },
3594     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3595       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3596       .access = PL3_W, .type = ARM_CP_NO_RAW,
3597       .writefn = tlbi_aa64_vae3is_write },
3598     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3599       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3600       .access = PL3_W, .type = ARM_CP_NO_RAW,
3601       .writefn = tlbi_aa64_vae3is_write },
3602     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3603       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3604       .access = PL3_W, .type = ARM_CP_NO_RAW,
3605       .writefn = tlbi_aa64_alle3_write },
3606     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3607       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3608       .access = PL3_W, .type = ARM_CP_NO_RAW,
3609       .writefn = tlbi_aa64_vae3_write },
3610     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3611       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3612       .access = PL3_W, .type = ARM_CP_NO_RAW,
3613       .writefn = tlbi_aa64_vae3_write },
3614     REGINFO_SENTINEL
3615 };
3616
3617 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
3618 {
3619     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3620      * but the AArch32 CTR has its own reginfo struct)
3621      */
3622     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3623         return CP_ACCESS_TRAP;
3624     }
3625     return CP_ACCESS_OK;
3626 }
3627
3628 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3629                         uint64_t value)
3630 {
3631     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3632      * read via a bit in OSLSR_EL1.
3633      */
3634     int oslock;
3635
3636     if (ri->state == ARM_CP_STATE_AA32) {
3637         oslock = (value == 0xC5ACCE55);
3638     } else {
3639         oslock = value & 1;
3640     }
3641
3642     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3643 }
3644
3645 static const ARMCPRegInfo debug_cp_reginfo[] = {
3646     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3647      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3648      * unlike DBGDRAR it is never accessible from EL0.
3649      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3650      * accessor.
3651      */
3652     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3653       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3654     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3655       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3656       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3657     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3658       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3659     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3660     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3661       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3662       .access = PL1_RW,
3663       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3664       .resetvalue = 0 },
3665     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3666      * We don't implement the configurable EL0 access.
3667      */
3668     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3669       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3670       .type = ARM_CP_ALIAS,
3671       .access = PL1_R,
3672       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3673     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3674       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3675       .access = PL1_W, .type = ARM_CP_NO_RAW,
3676       .writefn = oslar_write },
3677     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3678       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3679       .access = PL1_R, .resetvalue = 10,
3680       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3681     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3682     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3683       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3684       .access = PL1_RW, .type = ARM_CP_NOP },
3685     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3686      * implement vector catch debug events yet.
3687      */
3688     { .name = "DBGVCR",
3689       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3690       .access = PL1_RW, .type = ARM_CP_NOP },
3691     REGINFO_SENTINEL
3692 };
3693
3694 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3695     /* 64 bit access versions of the (dummy) debug registers */
3696     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3697       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3698     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3699       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3700     REGINFO_SENTINEL
3701 };
3702
3703 void hw_watchpoint_update(ARMCPU *cpu, int n)
3704 {
3705     CPUARMState *env = &cpu->env;
3706     vaddr len = 0;
3707     vaddr wvr = env->cp15.dbgwvr[n];
3708     uint64_t wcr = env->cp15.dbgwcr[n];
3709     int mask;
3710     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3711
3712     if (env->cpu_watchpoint[n]) {
3713         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3714         env->cpu_watchpoint[n] = NULL;
3715     }
3716
3717     if (!extract64(wcr, 0, 1)) {
3718         /* E bit clear : watchpoint disabled */
3719         return;
3720     }
3721
3722     switch (extract64(wcr, 3, 2)) {
3723     case 0:
3724         /* LSC 00 is reserved and must behave as if the wp is disabled */
3725         return;
3726     case 1:
3727         flags |= BP_MEM_READ;
3728         break;
3729     case 2:
3730         flags |= BP_MEM_WRITE;
3731         break;
3732     case 3:
3733         flags |= BP_MEM_ACCESS;
3734         break;
3735     }
3736
3737     /* Attempts to use both MASK and BAS fields simultaneously are
3738      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3739      * thus generating a watchpoint for every byte in the masked region.
3740      */
3741     mask = extract64(wcr, 24, 4);
3742     if (mask == 1 || mask == 2) {
3743         /* Reserved values of MASK; we must act as if the mask value was
3744          * some non-reserved value, or as if the watchpoint were disabled.
3745          * We choose the latter.
3746          */
3747         return;
3748     } else if (mask) {
3749         /* Watchpoint covers an aligned area up to 2GB in size */
3750         len = 1ULL << mask;
3751         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3752          * whether the watchpoint fires when the unmasked bits match; we opt
3753          * to generate the exceptions.
3754          */
3755         wvr &= ~(len - 1);
3756     } else {
3757         /* Watchpoint covers bytes defined by the byte address select bits */
3758         int bas = extract64(wcr, 5, 8);
3759         int basstart;
3760
3761         if (bas == 0) {
3762             /* This must act as if the watchpoint is disabled */
3763             return;
3764         }
3765
3766         if (extract64(wvr, 2, 1)) {
3767             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3768              * ignored, and BAS[3:0] define which bytes to watch.
3769              */
3770             bas &= 0xf;
3771         }
3772         /* The BAS bits are supposed to be programmed to indicate a contiguous
3773          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3774          * we fire for each byte in the word/doubleword addressed by the WVR.
3775          * We choose to ignore any non-zero bits after the first range of 1s.
3776          */
3777         basstart = ctz32(bas);
3778         len = cto32(bas >> basstart);
3779         wvr += basstart;
3780     }
3781
3782     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3783                           &env->cpu_watchpoint[n]);
3784 }
3785
3786 void hw_watchpoint_update_all(ARMCPU *cpu)
3787 {
3788     int i;
3789     CPUARMState *env = &cpu->env;
3790
3791     /* Completely clear out existing QEMU watchpoints and our array, to
3792      * avoid possible stale entries following migration load.
3793      */
3794     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3795     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3796
3797     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3798         hw_watchpoint_update(cpu, i);
3799     }
3800 }
3801
3802 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3803                          uint64_t value)
3804 {
3805     ARMCPU *cpu = arm_env_get_cpu(env);
3806     int i = ri->crm;
3807
3808     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3809      * register reads and behaves as if values written are sign extended.
3810      * Bits [1:0] are RES0.
3811      */
3812     value = sextract64(value, 0, 49) & ~3ULL;
3813
3814     raw_write(env, ri, value);
3815     hw_watchpoint_update(cpu, i);
3816 }
3817
3818 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3819                          uint64_t value)
3820 {
3821     ARMCPU *cpu = arm_env_get_cpu(env);
3822     int i = ri->crm;
3823
3824     raw_write(env, ri, value);
3825     hw_watchpoint_update(cpu, i);
3826 }
3827
3828 void hw_breakpoint_update(ARMCPU *cpu, int n)
3829 {
3830     CPUARMState *env = &cpu->env;
3831     uint64_t bvr = env->cp15.dbgbvr[n];
3832     uint64_t bcr = env->cp15.dbgbcr[n];
3833     vaddr addr;
3834     int bt;
3835     int flags = BP_CPU;
3836
3837     if (env->cpu_breakpoint[n]) {
3838         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3839         env->cpu_breakpoint[n] = NULL;
3840     }
3841
3842     if (!extract64(bcr, 0, 1)) {
3843         /* E bit clear : watchpoint disabled */
3844         return;
3845     }
3846
3847     bt = extract64(bcr, 20, 4);
3848
3849     switch (bt) {
3850     case 4: /* unlinked address mismatch (reserved if AArch64) */
3851     case 5: /* linked address mismatch (reserved if AArch64) */
3852         qemu_log_mask(LOG_UNIMP,
3853                       "arm: address mismatch breakpoint types not implemented");
3854         return;
3855     case 0: /* unlinked address match */
3856     case 1: /* linked address match */
3857     {
3858         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3859          * we behave as if the register was sign extended. Bits [1:0] are
3860          * RES0. The BAS field is used to allow setting breakpoints on 16
3861          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3862          * a bp will fire if the addresses covered by the bp and the addresses
3863          * covered by the insn overlap but the insn doesn't start at the
3864          * start of the bp address range. We choose to require the insn and
3865          * the bp to have the same address. The constraints on writing to
3866          * BAS enforced in dbgbcr_write mean we have only four cases:
3867          *  0b0000  => no breakpoint
3868          *  0b0011  => breakpoint on addr
3869          *  0b1100  => breakpoint on addr + 2
3870          *  0b1111  => breakpoint on addr
3871          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3872          */
3873         int bas = extract64(bcr, 5, 4);
3874         addr = sextract64(bvr, 0, 49) & ~3ULL;
3875         if (bas == 0) {
3876             return;
3877         }
3878         if (bas == 0xc) {
3879             addr += 2;
3880         }
3881         break;
3882     }
3883     case 2: /* unlinked context ID match */
3884     case 8: /* unlinked VMID match (reserved if no EL2) */
3885     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3886         qemu_log_mask(LOG_UNIMP,
3887                       "arm: unlinked context breakpoint types not implemented");
3888         return;
3889     case 9: /* linked VMID match (reserved if no EL2) */
3890     case 11: /* linked context ID and VMID match (reserved if no EL2) */
3891     case 3: /* linked context ID match */
3892     default:
3893         /* We must generate no events for Linked context matches (unless
3894          * they are linked to by some other bp/wp, which is handled in
3895          * updates for the linking bp/wp). We choose to also generate no events
3896          * for reserved values.
3897          */
3898         return;
3899     }
3900
3901     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3902 }
3903
3904 void hw_breakpoint_update_all(ARMCPU *cpu)
3905 {
3906     int i;
3907     CPUARMState *env = &cpu->env;
3908
3909     /* Completely clear out existing QEMU breakpoints and our array, to
3910      * avoid possible stale entries following migration load.
3911      */
3912     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3913     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3914
3915     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3916         hw_breakpoint_update(cpu, i);
3917     }
3918 }
3919
3920 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3921                          uint64_t value)
3922 {
3923     ARMCPU *cpu = arm_env_get_cpu(env);
3924     int i = ri->crm;
3925
3926     raw_write(env, ri, value);
3927     hw_breakpoint_update(cpu, i);
3928 }
3929
3930 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3931                          uint64_t value)
3932 {
3933     ARMCPU *cpu = arm_env_get_cpu(env);
3934     int i = ri->crm;
3935
3936     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3937      * copy of BAS[0].
3938      */
3939     value = deposit64(value, 6, 1, extract64(value, 5, 1));
3940     value = deposit64(value, 8, 1, extract64(value, 7, 1));
3941
3942     raw_write(env, ri, value);
3943     hw_breakpoint_update(cpu, i);
3944 }
3945
3946 static void define_debug_regs(ARMCPU *cpu)
3947 {
3948     /* Define v7 and v8 architectural debug registers.
3949      * These are just dummy implementations for now.
3950      */
3951     int i;
3952     int wrps, brps, ctx_cmps;
3953     ARMCPRegInfo dbgdidr = {
3954         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3955         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3956     };
3957
3958     /* Note that all these register fields hold "number of Xs minus 1". */
3959     brps = extract32(cpu->dbgdidr, 24, 4);
3960     wrps = extract32(cpu->dbgdidr, 28, 4);
3961     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3962
3963     assert(ctx_cmps <= brps);
3964
3965     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3966      * of the debug registers such as number of breakpoints;
3967      * check that if they both exist then they agree.
3968      */
3969     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3970         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3971         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3972         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3973     }
3974
3975     define_one_arm_cp_reg(cpu, &dbgdidr);
3976     define_arm_cp_regs(cpu, debug_cp_reginfo);
3977
3978     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3979         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3980     }
3981
3982     for (i = 0; i < brps + 1; i++) {
3983         ARMCPRegInfo dbgregs[] = {
3984             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3985               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3986               .access = PL1_RW,
3987               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3988               .writefn = dbgbvr_write, .raw_writefn = raw_write
3989             },
3990             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3991               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3992               .access = PL1_RW,
3993               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3994               .writefn = dbgbcr_write, .raw_writefn = raw_write
3995             },
3996             REGINFO_SENTINEL
3997         };
3998         define_arm_cp_regs(cpu, dbgregs);
3999     }
4000
4001     for (i = 0; i < wrps + 1; i++) {
4002         ARMCPRegInfo dbgregs[] = {
4003             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4004               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4005               .access = PL1_RW,
4006               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4007               .writefn = dbgwvr_write, .raw_writefn = raw_write
4008             },
4009             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4010               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4011               .access = PL1_RW,
4012               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4013               .writefn = dbgwcr_write, .raw_writefn = raw_write
4014             },
4015             REGINFO_SENTINEL
4016         };
4017         define_arm_cp_regs(cpu, dbgregs);
4018     }
4019 }
4020
4021 void register_cp_regs_for_features(ARMCPU *cpu)
4022 {
4023     /* Register all the coprocessor registers based on feature bits */
4024     CPUARMState *env = &cpu->env;
4025     if (arm_feature(env, ARM_FEATURE_M)) {
4026         /* M profile has no coprocessor registers */
4027         return;
4028     }
4029
4030     define_arm_cp_regs(cpu, cp_reginfo);
4031     if (!arm_feature(env, ARM_FEATURE_V8)) {
4032         /* Must go early as it is full of wildcards that may be
4033          * overridden by later definitions.
4034          */
4035         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4036     }
4037
4038     if (arm_feature(env, ARM_FEATURE_V6)) {
4039         /* The ID registers all have impdef reset values */
4040         ARMCPRegInfo v6_idregs[] = {
4041             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4042               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4043               .access = PL1_R, .type = ARM_CP_CONST,
4044               .resetvalue = cpu->id_pfr0 },
4045             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4046               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4047               .access = PL1_R, .type = ARM_CP_CONST,
4048               .resetvalue = cpu->id_pfr1 },
4049             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4050               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4051               .access = PL1_R, .type = ARM_CP_CONST,
4052               .resetvalue = cpu->id_dfr0 },
4053             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4054               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4055               .access = PL1_R, .type = ARM_CP_CONST,
4056               .resetvalue = cpu->id_afr0 },
4057             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4058               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4059               .access = PL1_R, .type = ARM_CP_CONST,
4060               .resetvalue = cpu->id_mmfr0 },
4061             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4062               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4063               .access = PL1_R, .type = ARM_CP_CONST,
4064               .resetvalue = cpu->id_mmfr1 },
4065             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4066               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4067               .access = PL1_R, .type = ARM_CP_CONST,
4068               .resetvalue = cpu->id_mmfr2 },
4069             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4070               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4071               .access = PL1_R, .type = ARM_CP_CONST,
4072               .resetvalue = cpu->id_mmfr3 },
4073             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4074               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4075               .access = PL1_R, .type = ARM_CP_CONST,
4076               .resetvalue = cpu->id_isar0 },
4077             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4078               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4079               .access = PL1_R, .type = ARM_CP_CONST,
4080               .resetvalue = cpu->id_isar1 },
4081             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4082               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4083               .access = PL1_R, .type = ARM_CP_CONST,
4084               .resetvalue = cpu->id_isar2 },
4085             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4086               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4087               .access = PL1_R, .type = ARM_CP_CONST,
4088               .resetvalue = cpu->id_isar3 },
4089             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4090               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4091               .access = PL1_R, .type = ARM_CP_CONST,
4092               .resetvalue = cpu->id_isar4 },
4093             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4094               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4095               .access = PL1_R, .type = ARM_CP_CONST,
4096               .resetvalue = cpu->id_isar5 },
4097             /* 6..7 are as yet unallocated and must RAZ */
4098             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
4099               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
4100               .resetvalue = 0 },
4101             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
4102               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
4103               .resetvalue = 0 },
4104             REGINFO_SENTINEL
4105         };
4106         define_arm_cp_regs(cpu, v6_idregs);
4107         define_arm_cp_regs(cpu, v6_cp_reginfo);
4108     } else {
4109         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4110     }
4111     if (arm_feature(env, ARM_FEATURE_V6K)) {
4112         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4113     }
4114     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4115         !arm_feature(env, ARM_FEATURE_MPU)) {
4116         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4117     }
4118     if (arm_feature(env, ARM_FEATURE_V7)) {
4119         /* v7 performance monitor control register: same implementor
4120          * field as main ID register, and we implement only the cycle
4121          * count register.
4122          */
4123 #ifndef CONFIG_USER_ONLY
4124         ARMCPRegInfo pmcr = {
4125             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4126             .access = PL0_RW,
4127             .type = ARM_CP_IO | ARM_CP_ALIAS,
4128             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4129             .accessfn = pmreg_access, .writefn = pmcr_write,
4130             .raw_writefn = raw_write,
4131         };
4132         ARMCPRegInfo pmcr64 = {
4133             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4134             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4135             .access = PL0_RW, .accessfn = pmreg_access,
4136             .type = ARM_CP_IO,
4137             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4138             .resetvalue = cpu->midr & 0xff000000,
4139             .writefn = pmcr_write, .raw_writefn = raw_write,
4140         };
4141         define_one_arm_cp_reg(cpu, &pmcr);
4142         define_one_arm_cp_reg(cpu, &pmcr64);
4143 #endif
4144         ARMCPRegInfo clidr = {
4145             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4146             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4147             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4148         };
4149         define_one_arm_cp_reg(cpu, &clidr);
4150         define_arm_cp_regs(cpu, v7_cp_reginfo);
4151         define_debug_regs(cpu);
4152     } else {
4153         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4154     }
4155     if (arm_feature(env, ARM_FEATURE_V8)) {
4156         /* AArch64 ID registers, which all have impdef reset values */
4157         ARMCPRegInfo v8_idregs[] = {
4158             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4159               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4160               .access = PL1_R, .type = ARM_CP_CONST,
4161               .resetvalue = cpu->id_aa64pfr0 },
4162             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4163               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4164               .access = PL1_R, .type = ARM_CP_CONST,
4165               .resetvalue = cpu->id_aa64pfr1},
4166             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4167               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4168               .access = PL1_R, .type = ARM_CP_CONST,
4169               /* We mask out the PMUVer field, because we don't currently
4170                * implement the PMU. Not advertising it prevents the guest
4171                * from trying to use it and getting UNDEFs on registers we
4172                * don't implement.
4173                */
4174               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4175             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4176               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4177               .access = PL1_R, .type = ARM_CP_CONST,
4178               .resetvalue = cpu->id_aa64dfr1 },
4179             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4180               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4181               .access = PL1_R, .type = ARM_CP_CONST,
4182               .resetvalue = cpu->id_aa64afr0 },
4183             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4184               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4185               .access = PL1_R, .type = ARM_CP_CONST,
4186               .resetvalue = cpu->id_aa64afr1 },
4187             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4188               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4189               .access = PL1_R, .type = ARM_CP_CONST,
4190               .resetvalue = cpu->id_aa64isar0 },
4191             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4192               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4193               .access = PL1_R, .type = ARM_CP_CONST,
4194               .resetvalue = cpu->id_aa64isar1 },
4195             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4196               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4197               .access = PL1_R, .type = ARM_CP_CONST,
4198               .resetvalue = cpu->id_aa64mmfr0 },
4199             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4200               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4201               .access = PL1_R, .type = ARM_CP_CONST,
4202               .resetvalue = cpu->id_aa64mmfr1 },
4203             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4204               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4205               .access = PL1_R, .type = ARM_CP_CONST,
4206               .resetvalue = cpu->mvfr0 },
4207             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4208               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4209               .access = PL1_R, .type = ARM_CP_CONST,
4210               .resetvalue = cpu->mvfr1 },
4211             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4212               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4213               .access = PL1_R, .type = ARM_CP_CONST,
4214               .resetvalue = cpu->mvfr2 },
4215             REGINFO_SENTINEL
4216         };
4217         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4218         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4219             !arm_feature(env, ARM_FEATURE_EL2)) {
4220             ARMCPRegInfo rvbar = {
4221                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4222                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4223                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4224             };
4225             define_one_arm_cp_reg(cpu, &rvbar);
4226         }
4227         define_arm_cp_regs(cpu, v8_idregs);
4228         define_arm_cp_regs(cpu, v8_cp_reginfo);
4229     }
4230     if (arm_feature(env, ARM_FEATURE_EL2)) {
4231         uint64_t vmpidr_def = mpidr_read_val(env);
4232         ARMCPRegInfo vpidr_regs[] = {
4233             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4234               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4235               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4236               .resetvalue = cpu->midr,
4237               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4238             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4239               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4240               .access = PL2_RW, .resetvalue = cpu->midr,
4241               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4242             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4243               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4244               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4245               .resetvalue = vmpidr_def,
4246               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4247             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4248               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4249               .access = PL2_RW,
4250               .resetvalue = vmpidr_def,
4251               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4252             REGINFO_SENTINEL
4253         };
4254         define_arm_cp_regs(cpu, vpidr_regs);
4255         define_arm_cp_regs(cpu, el2_cp_reginfo);
4256         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4257         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4258             ARMCPRegInfo rvbar = {
4259                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4260                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4261                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4262             };
4263             define_one_arm_cp_reg(cpu, &rvbar);
4264         }
4265     } else {
4266         /* If EL2 is missing but higher ELs are enabled, we need to
4267          * register the no_el2 reginfos.
4268          */
4269         if (arm_feature(env, ARM_FEATURE_EL3)) {
4270             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4271              * of MIDR_EL1 and MPIDR_EL1.
4272              */
4273             ARMCPRegInfo vpidr_regs[] = {
4274                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4275                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4276                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4277                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4278                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4279                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4280                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4281                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4282                   .type = ARM_CP_NO_RAW,
4283                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4284                 REGINFO_SENTINEL
4285             };
4286             define_arm_cp_regs(cpu, vpidr_regs);
4287             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4288         }
4289     }
4290     if (arm_feature(env, ARM_FEATURE_EL3)) {
4291         define_arm_cp_regs(cpu, el3_cp_reginfo);
4292         ARMCPRegInfo rvbar = {
4293             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4294             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4295             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4296         };
4297         define_one_arm_cp_reg(cpu, &rvbar);
4298     }
4299     if (arm_feature(env, ARM_FEATURE_MPU)) {
4300         if (arm_feature(env, ARM_FEATURE_V6)) {
4301             /* PMSAv6 not implemented */
4302             assert(arm_feature(env, ARM_FEATURE_V7));
4303             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4304             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4305         } else {
4306             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4307         }
4308     } else {
4309         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4310         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4311     }
4312     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4313         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4314     }
4315     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4316         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4317     }
4318     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4319         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4320     }
4321     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4322         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4323     }
4324     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4325         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4326     }
4327     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4328         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4329     }
4330     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4331         define_arm_cp_regs(cpu, omap_cp_reginfo);
4332     }
4333     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4334         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4335     }
4336     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4337         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4338     }
4339     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4340         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4341     }
4342     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4343         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4344     }
4345     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4346      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4347      * be read-only (ie write causes UNDEF exception).
4348      */
4349     {
4350         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4351             /* Pre-v8 MIDR space.
4352              * Note that the MIDR isn't a simple constant register because
4353              * of the TI925 behaviour where writes to another register can
4354              * cause the MIDR value to change.
4355              *
4356              * Unimplemented registers in the c15 0 0 0 space default to
4357              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4358              * and friends override accordingly.
4359              */
4360             { .name = "MIDR",
4361               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4362               .access = PL1_R, .resetvalue = cpu->midr,
4363               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4364               .readfn = midr_read,
4365               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4366               .type = ARM_CP_OVERRIDE },
4367             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4368             { .name = "DUMMY",
4369               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4370               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4371             { .name = "DUMMY",
4372               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4373               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4374             { .name = "DUMMY",
4375               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4376               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4377             { .name = "DUMMY",
4378               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4379               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4380             { .name = "DUMMY",
4381               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4382               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4383             REGINFO_SENTINEL
4384         };
4385         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4386             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4387               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4388               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4389               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4390               .readfn = midr_read },
4391             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4392             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4393               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4394               .access = PL1_R, .resetvalue = cpu->midr },
4395             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4396               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4397               .access = PL1_R, .resetvalue = cpu->midr },
4398             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4399               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4400               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4401             REGINFO_SENTINEL
4402         };
4403         ARMCPRegInfo id_cp_reginfo[] = {
4404             /* These are common to v8 and pre-v8 */
4405             { .name = "CTR",
4406               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4407               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4408             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4409               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4410               .access = PL0_R, .accessfn = ctr_el0_access,
4411               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4412             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4413             { .name = "TCMTR",
4414               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4415               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4416             REGINFO_SENTINEL
4417         };
4418         /* TLBTR is specific to VMSA */
4419         ARMCPRegInfo id_tlbtr_reginfo = {
4420               .name = "TLBTR",
4421               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4422               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4423         };
4424         /* MPUIR is specific to PMSA V6+ */
4425         ARMCPRegInfo id_mpuir_reginfo = {
4426               .name = "MPUIR",
4427               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4428               .access = PL1_R, .type = ARM_CP_CONST,
4429               .resetvalue = cpu->pmsav7_dregion << 8
4430         };
4431         ARMCPRegInfo crn0_wi_reginfo = {
4432             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4433             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4434             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4435         };
4436         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4437             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4438             ARMCPRegInfo *r;
4439             /* Register the blanket "writes ignored" value first to cover the
4440              * whole space. Then update the specific ID registers to allow write
4441              * access, so that they ignore writes rather than causing them to
4442              * UNDEF.
4443              */
4444             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4445             for (r = id_pre_v8_midr_cp_reginfo;
4446                  r->type != ARM_CP_SENTINEL; r++) {
4447                 r->access = PL1_RW;
4448             }
4449             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4450                 r->access = PL1_RW;
4451             }
4452             id_tlbtr_reginfo.access = PL1_RW;
4453             id_tlbtr_reginfo.access = PL1_RW;
4454         }
4455         if (arm_feature(env, ARM_FEATURE_V8)) {
4456             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4457         } else {
4458             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4459         }
4460         define_arm_cp_regs(cpu, id_cp_reginfo);
4461         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4462             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4463         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4464             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4465         }
4466     }
4467
4468     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4469         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4470     }
4471
4472     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4473         ARMCPRegInfo auxcr_reginfo[] = {
4474             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4475               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4476               .access = PL1_RW, .type = ARM_CP_CONST,
4477               .resetvalue = cpu->reset_auxcr },
4478             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4479               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4480               .access = PL2_RW, .type = ARM_CP_CONST,
4481               .resetvalue = 0 },
4482             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4483               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4484               .access = PL3_RW, .type = ARM_CP_CONST,
4485               .resetvalue = 0 },
4486             REGINFO_SENTINEL
4487         };
4488         define_arm_cp_regs(cpu, auxcr_reginfo);
4489     }
4490
4491     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4492         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4493             /* 32 bit view is [31:18] 0...0 [43:32]. */
4494             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4495                 | extract64(cpu->reset_cbar, 32, 12);
4496             ARMCPRegInfo cbar_reginfo[] = {
4497                 { .name = "CBAR",
4498                   .type = ARM_CP_CONST,
4499                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4500                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4501                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4502                   .type = ARM_CP_CONST,
4503                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4504                   .access = PL1_R, .resetvalue = cbar32 },
4505                 REGINFO_SENTINEL
4506             };
4507             /* We don't implement a r/w 64 bit CBAR currently */
4508             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4509             define_arm_cp_regs(cpu, cbar_reginfo);
4510         } else {
4511             ARMCPRegInfo cbar = {
4512                 .name = "CBAR",
4513                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4514                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4515                 .fieldoffset = offsetof(CPUARMState,
4516                                         cp15.c15_config_base_address)
4517             };
4518             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4519                 cbar.access = PL1_R;
4520                 cbar.fieldoffset = 0;
4521                 cbar.type = ARM_CP_CONST;
4522             }
4523             define_one_arm_cp_reg(cpu, &cbar);
4524         }
4525     }
4526
4527     /* Generic registers whose values depend on the implementation */
4528     {
4529         ARMCPRegInfo sctlr = {
4530             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4531             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4532             .access = PL1_RW,
4533             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4534                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4535             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4536             .raw_writefn = raw_write,
4537         };
4538         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4539             /* Normally we would always end the TB on an SCTLR write, but Linux
4540              * arch/arm/mach-pxa/sleep.S expects two instructions following
4541              * an MMU enable to execute from cache.  Imitate this behaviour.
4542              */
4543             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4544         }
4545         define_one_arm_cp_reg(cpu, &sctlr);
4546     }
4547 }
4548
4549 ARMCPU *cpu_arm_init(const char *cpu_model)
4550 {
4551     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4552 }
4553
4554 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4555 {
4556     CPUState *cs = CPU(cpu);
4557     CPUARMState *env = &cpu->env;
4558
4559     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4560         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4561                                  aarch64_fpu_gdb_set_reg,
4562                                  34, "aarch64-fpu.xml", 0);
4563     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4564         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4565                                  51, "arm-neon.xml", 0);
4566     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4567         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4568                                  35, "arm-vfp3.xml", 0);
4569     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4570         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4571                                  19, "arm-vfp.xml", 0);
4572     }
4573 }
4574
4575 /* Sort alphabetically by type name, except for "any". */
4576 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4577 {
4578     ObjectClass *class_a = (ObjectClass *)a;
4579     ObjectClass *class_b = (ObjectClass *)b;
4580     const char *name_a, *name_b;
4581
4582     name_a = object_class_get_name(class_a);
4583     name_b = object_class_get_name(class_b);
4584     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4585         return 1;
4586     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4587         return -1;
4588     } else {
4589         return strcmp(name_a, name_b);
4590     }
4591 }
4592
4593 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4594 {
4595     ObjectClass *oc = data;
4596     CPUListState *s = user_data;
4597     const char *typename;
4598     char *name;
4599
4600     typename = object_class_get_name(oc);
4601     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4602     (*s->cpu_fprintf)(s->file, "  %s\n",
4603                       name);
4604     g_free(name);
4605 }
4606
4607 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4608 {
4609     CPUListState s = {
4610         .file = f,
4611         .cpu_fprintf = cpu_fprintf,
4612     };
4613     GSList *list;
4614
4615     list = object_class_get_list(TYPE_ARM_CPU, false);
4616     list = g_slist_sort(list, arm_cpu_list_compare);
4617     (*cpu_fprintf)(f, "Available CPUs:\n");
4618     g_slist_foreach(list, arm_cpu_list_entry, &s);
4619     g_slist_free(list);
4620 #ifdef CONFIG_KVM
4621     /* The 'host' CPU type is dynamically registered only if KVM is
4622      * enabled, so we have to special-case it here:
4623      */
4624     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
4625 #endif
4626 }
4627
4628 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4629 {
4630     ObjectClass *oc = data;
4631     CpuDefinitionInfoList **cpu_list = user_data;
4632     CpuDefinitionInfoList *entry;
4633     CpuDefinitionInfo *info;
4634     const char *typename;
4635
4636     typename = object_class_get_name(oc);
4637     info = g_malloc0(sizeof(*info));
4638     info->name = g_strndup(typename,
4639                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
4640
4641     entry = g_malloc0(sizeof(*entry));
4642     entry->value = info;
4643     entry->next = *cpu_list;
4644     *cpu_list = entry;
4645 }
4646
4647 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4648 {
4649     CpuDefinitionInfoList *cpu_list = NULL;
4650     GSList *list;
4651
4652     list = object_class_get_list(TYPE_ARM_CPU, false);
4653     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4654     g_slist_free(list);
4655
4656     return cpu_list;
4657 }
4658
4659 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4660                                    void *opaque, int state, int secstate,
4661                                    int crm, int opc1, int opc2)
4662 {
4663     /* Private utility function for define_one_arm_cp_reg_with_opaque():
4664      * add a single reginfo struct to the hash table.
4665      */
4666     uint32_t *key = g_new(uint32_t, 1);
4667     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4668     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4669     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4670
4671     /* Reset the secure state to the specific incoming state.  This is
4672      * necessary as the register may have been defined with both states.
4673      */
4674     r2->secure = secstate;
4675
4676     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4677         /* Register is banked (using both entries in array).
4678          * Overwriting fieldoffset as the array is only used to define
4679          * banked registers but later only fieldoffset is used.
4680          */
4681         r2->fieldoffset = r->bank_fieldoffsets[ns];
4682     }
4683
4684     if (state == ARM_CP_STATE_AA32) {
4685         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4686             /* If the register is banked then we don't need to migrate or
4687              * reset the 32-bit instance in certain cases:
4688              *
4689              * 1) If the register has both 32-bit and 64-bit instances then we
4690              *    can count on the 64-bit instance taking care of the
4691              *    non-secure bank.
4692              * 2) If ARMv8 is enabled then we can count on a 64-bit version
4693              *    taking care of the secure bank.  This requires that separate
4694              *    32 and 64-bit definitions are provided.
4695              */
4696             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4697                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4698                 r2->type |= ARM_CP_ALIAS;
4699             }
4700         } else if ((secstate != r->secure) && !ns) {
4701             /* The register is not banked so we only want to allow migration of
4702              * the non-secure instance.
4703              */
4704             r2->type |= ARM_CP_ALIAS;
4705         }
4706
4707         if (r->state == ARM_CP_STATE_BOTH) {
4708             /* We assume it is a cp15 register if the .cp field is left unset.
4709              */
4710             if (r2->cp == 0) {
4711                 r2->cp = 15;
4712             }
4713
4714 #ifdef HOST_WORDS_BIGENDIAN
4715             if (r2->fieldoffset) {
4716                 r2->fieldoffset += sizeof(uint32_t);
4717             }
4718 #endif
4719         }
4720     }
4721     if (state == ARM_CP_STATE_AA64) {
4722         /* To allow abbreviation of ARMCPRegInfo
4723          * definitions, we treat cp == 0 as equivalent to
4724          * the value for "standard guest-visible sysreg".
4725          * STATE_BOTH definitions are also always "standard
4726          * sysreg" in their AArch64 view (the .cp value may
4727          * be non-zero for the benefit of the AArch32 view).
4728          */
4729         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4730             r2->cp = CP_REG_ARM64_SYSREG_CP;
4731         }
4732         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4733                                   r2->opc0, opc1, opc2);
4734     } else {
4735         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4736     }
4737     if (opaque) {
4738         r2->opaque = opaque;
4739     }
4740     /* reginfo passed to helpers is correct for the actual access,
4741      * and is never ARM_CP_STATE_BOTH:
4742      */
4743     r2->state = state;
4744     /* Make sure reginfo passed to helpers for wildcarded regs
4745      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4746      */
4747     r2->crm = crm;
4748     r2->opc1 = opc1;
4749     r2->opc2 = opc2;
4750     /* By convention, for wildcarded registers only the first
4751      * entry is used for migration; the others are marked as
4752      * ALIAS so we don't try to transfer the register
4753      * multiple times. Special registers (ie NOP/WFI) are
4754      * never migratable and not even raw-accessible.
4755      */
4756     if ((r->type & ARM_CP_SPECIAL)) {
4757         r2->type |= ARM_CP_NO_RAW;
4758     }
4759     if (((r->crm == CP_ANY) && crm != 0) ||
4760         ((r->opc1 == CP_ANY) && opc1 != 0) ||
4761         ((r->opc2 == CP_ANY) && opc2 != 0)) {
4762         r2->type |= ARM_CP_ALIAS;
4763     }
4764
4765     /* Check that raw accesses are either forbidden or handled. Note that
4766      * we can't assert this earlier because the setup of fieldoffset for
4767      * banked registers has to be done first.
4768      */
4769     if (!(r2->type & ARM_CP_NO_RAW)) {
4770         assert(!raw_accessors_invalid(r2));
4771     }
4772
4773     /* Overriding of an existing definition must be explicitly
4774      * requested.
4775      */
4776     if (!(r->type & ARM_CP_OVERRIDE)) {
4777         ARMCPRegInfo *oldreg;
4778         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4779         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4780             fprintf(stderr, "Register redefined: cp=%d %d bit "
4781                     "crn=%d crm=%d opc1=%d opc2=%d, "
4782                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4783                     r2->crn, r2->crm, r2->opc1, r2->opc2,
4784                     oldreg->name, r2->name);
4785             g_assert_not_reached();
4786         }
4787     }
4788     g_hash_table_insert(cpu->cp_regs, key, r2);
4789 }
4790
4791
4792 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4793                                        const ARMCPRegInfo *r, void *opaque)
4794 {
4795     /* Define implementations of coprocessor registers.
4796      * We store these in a hashtable because typically
4797      * there are less than 150 registers in a space which
4798      * is 16*16*16*8*8 = 262144 in size.
4799      * Wildcarding is supported for the crm, opc1 and opc2 fields.
4800      * If a register is defined twice then the second definition is
4801      * used, so this can be used to define some generic registers and
4802      * then override them with implementation specific variations.
4803      * At least one of the original and the second definition should
4804      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4805      * against accidental use.
4806      *
4807      * The state field defines whether the register is to be
4808      * visible in the AArch32 or AArch64 execution state. If the
4809      * state is set to ARM_CP_STATE_BOTH then we synthesise a
4810      * reginfo structure for the AArch32 view, which sees the lower
4811      * 32 bits of the 64 bit register.
4812      *
4813      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4814      * be wildcarded. AArch64 registers are always considered to be 64
4815      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4816      * the register, if any.
4817      */
4818     int crm, opc1, opc2, state;
4819     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4820     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4821     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4822     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4823     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4824     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4825     /* 64 bit registers have only CRm and Opc1 fields */
4826     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4827     /* op0 only exists in the AArch64 encodings */
4828     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4829     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4830     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4831     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4832      * encodes a minimum access level for the register. We roll this
4833      * runtime check into our general permission check code, so check
4834      * here that the reginfo's specified permissions are strict enough
4835      * to encompass the generic architectural permission check.
4836      */
4837     if (r->state != ARM_CP_STATE_AA32) {
4838         int mask = 0;
4839         switch (r->opc1) {
4840         case 0: case 1: case 2:
4841             /* min_EL EL1 */
4842             mask = PL1_RW;
4843             break;
4844         case 3:
4845             /* min_EL EL0 */
4846             mask = PL0_RW;
4847             break;
4848         case 4:
4849             /* min_EL EL2 */
4850             mask = PL2_RW;
4851             break;
4852         case 5:
4853             /* unallocated encoding, so not possible */
4854             assert(false);
4855             break;
4856         case 6:
4857             /* min_EL EL3 */
4858             mask = PL3_RW;
4859             break;
4860         case 7:
4861             /* min_EL EL1, secure mode only (we don't check the latter) */
4862             mask = PL1_RW;
4863             break;
4864         default:
4865             /* broken reginfo with out-of-range opc1 */
4866             assert(false);
4867             break;
4868         }
4869         /* assert our permissions are not too lax (stricter is fine) */
4870         assert((r->access & ~mask) == 0);
4871     }
4872
4873     /* Check that the register definition has enough info to handle
4874      * reads and writes if they are permitted.
4875      */
4876     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4877         if (r->access & PL3_R) {
4878             assert((r->fieldoffset ||
4879                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4880                    r->readfn);
4881         }
4882         if (r->access & PL3_W) {
4883             assert((r->fieldoffset ||
4884                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4885                    r->writefn);
4886         }
4887     }
4888     /* Bad type field probably means missing sentinel at end of reg list */
4889     assert(cptype_valid(r->type));
4890     for (crm = crmmin; crm <= crmmax; crm++) {
4891         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
4892             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
4893                 for (state = ARM_CP_STATE_AA32;
4894                      state <= ARM_CP_STATE_AA64; state++) {
4895                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
4896                         continue;
4897                     }
4898                     if (state == ARM_CP_STATE_AA32) {
4899                         /* Under AArch32 CP registers can be common
4900                          * (same for secure and non-secure world) or banked.
4901                          */
4902                         switch (r->secure) {
4903                         case ARM_CP_SECSTATE_S:
4904                         case ARM_CP_SECSTATE_NS:
4905                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4906                                                    r->secure, crm, opc1, opc2);
4907                             break;
4908                         default:
4909                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4910                                                    ARM_CP_SECSTATE_S,
4911                                                    crm, opc1, opc2);
4912                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4913                                                    ARM_CP_SECSTATE_NS,
4914                                                    crm, opc1, opc2);
4915                             break;
4916                         }
4917                     } else {
4918                         /* AArch64 registers get mapped to non-secure instance
4919                          * of AArch32 */
4920                         add_cpreg_to_hashtable(cpu, r, opaque, state,
4921                                                ARM_CP_SECSTATE_NS,
4922                                                crm, opc1, opc2);
4923                     }
4924                 }
4925             }
4926         }
4927     }
4928 }
4929
4930 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
4931                                     const ARMCPRegInfo *regs, void *opaque)
4932 {
4933     /* Define a whole list of registers */
4934     const ARMCPRegInfo *r;
4935     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
4936         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
4937     }
4938 }
4939
4940 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4941 {
4942     return g_hash_table_lookup(cpregs, &encoded_cp);
4943 }
4944
4945 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
4946                          uint64_t value)
4947 {
4948     /* Helper coprocessor write function for write-ignore registers */
4949 }
4950
4951 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4952 {
4953     /* Helper coprocessor write function for read-as-zero registers */
4954     return 0;
4955 }
4956
4957 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
4958 {
4959     /* Helper coprocessor reset function for do-nothing-on-reset registers */
4960 }
4961
4962 static int bad_mode_switch(CPUARMState *env, int mode)
4963 {
4964     /* Return true if it is not valid for us to switch to
4965      * this CPU mode (ie all the UNPREDICTABLE cases in
4966      * the ARM ARM CPSRWriteByInstr pseudocode).
4967      */
4968     switch (mode) {
4969     case ARM_CPU_MODE_USR:
4970     case ARM_CPU_MODE_SYS:
4971     case ARM_CPU_MODE_SVC:
4972     case ARM_CPU_MODE_ABT:
4973     case ARM_CPU_MODE_UND:
4974     case ARM_CPU_MODE_IRQ:
4975     case ARM_CPU_MODE_FIQ:
4976         return 0;
4977     case ARM_CPU_MODE_MON:
4978         return !arm_is_secure(env);
4979     default:
4980         return 1;
4981     }
4982 }
4983
4984 uint32_t cpsr_read(CPUARMState *env)
4985 {
4986     int ZF;
4987     ZF = (env->ZF == 0);
4988     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
4989         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
4990         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
4991         | ((env->condexec_bits & 0xfc) << 8)
4992         | (env->GE << 16) | (env->daif & CPSR_AIF);
4993 }
4994
4995 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
4996 {
4997     uint32_t changed_daif;
4998
4999     if (mask & CPSR_NZCV) {
5000         env->ZF = (~val) & CPSR_Z;
5001         env->NF = val;
5002         env->CF = (val >> 29) & 1;
5003         env->VF = (val << 3) & 0x80000000;
5004     }
5005     if (mask & CPSR_Q)
5006         env->QF = ((val & CPSR_Q) != 0);
5007     if (mask & CPSR_T)
5008         env->thumb = ((val & CPSR_T) != 0);
5009     if (mask & CPSR_IT_0_1) {
5010         env->condexec_bits &= ~3;
5011         env->condexec_bits |= (val >> 25) & 3;
5012     }
5013     if (mask & CPSR_IT_2_7) {
5014         env->condexec_bits &= 3;
5015         env->condexec_bits |= (val >> 8) & 0xfc;
5016     }
5017     if (mask & CPSR_GE) {
5018         env->GE = (val >> 16) & 0xf;
5019     }
5020
5021     /* In a V7 implementation that includes the security extensions but does
5022      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5023      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5024      * bits respectively.
5025      *
5026      * In a V8 implementation, it is permitted for privileged software to
5027      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5028      */
5029     if (!arm_feature(env, ARM_FEATURE_V8) &&
5030         arm_feature(env, ARM_FEATURE_EL3) &&
5031         !arm_feature(env, ARM_FEATURE_EL2) &&
5032         !arm_is_secure(env)) {
5033
5034         changed_daif = (env->daif ^ val) & mask;
5035
5036         if (changed_daif & CPSR_A) {
5037             /* Check to see if we are allowed to change the masking of async
5038              * abort exceptions from a non-secure state.
5039              */
5040             if (!(env->cp15.scr_el3 & SCR_AW)) {
5041                 qemu_log_mask(LOG_GUEST_ERROR,
5042                               "Ignoring attempt to switch CPSR_A flag from "
5043                               "non-secure world with SCR.AW bit clear\n");
5044                 mask &= ~CPSR_A;
5045             }
5046         }
5047
5048         if (changed_daif & CPSR_F) {
5049             /* Check to see if we are allowed to change the masking of FIQ
5050              * exceptions from a non-secure state.
5051              */
5052             if (!(env->cp15.scr_el3 & SCR_FW)) {
5053                 qemu_log_mask(LOG_GUEST_ERROR,
5054                               "Ignoring attempt to switch CPSR_F flag from "
5055                               "non-secure world with SCR.FW bit clear\n");
5056                 mask &= ~CPSR_F;
5057             }
5058
5059             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5060              * If this bit is set software is not allowed to mask
5061              * FIQs, but is allowed to set CPSR_F to 0.
5062              */
5063             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5064                 (val & CPSR_F)) {
5065                 qemu_log_mask(LOG_GUEST_ERROR,
5066                               "Ignoring attempt to enable CPSR_F flag "
5067                               "(non-maskable FIQ [NMFI] support enabled)\n");
5068                 mask &= ~CPSR_F;
5069             }
5070         }
5071     }
5072
5073     env->daif &= ~(CPSR_AIF & mask);
5074     env->daif |= val & CPSR_AIF & mask;
5075
5076     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
5077         if (bad_mode_switch(env, val & CPSR_M)) {
5078             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
5079              * We choose to ignore the attempt and leave the CPSR M field
5080              * untouched.
5081              */
5082             mask &= ~CPSR_M;
5083         } else {
5084             switch_mode(env, val & CPSR_M);
5085         }
5086     }
5087     mask &= ~CACHED_CPSR_BITS;
5088     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5089 }
5090
5091 /* Sign/zero extend */
5092 uint32_t HELPER(sxtb16)(uint32_t x)
5093 {
5094     uint32_t res;
5095     res = (uint16_t)(int8_t)x;
5096     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5097     return res;
5098 }
5099
5100 uint32_t HELPER(uxtb16)(uint32_t x)
5101 {
5102     uint32_t res;
5103     res = (uint16_t)(uint8_t)x;
5104     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5105     return res;
5106 }
5107
5108 uint32_t HELPER(clz)(uint32_t x)
5109 {
5110     return clz32(x);
5111 }
5112
5113 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5114 {
5115     if (den == 0)
5116       return 0;
5117     if (num == INT_MIN && den == -1)
5118       return INT_MIN;
5119     return num / den;
5120 }
5121
5122 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5123 {
5124     if (den == 0)
5125       return 0;
5126     return num / den;
5127 }
5128
5129 uint32_t HELPER(rbit)(uint32_t x)
5130 {
5131     return revbit32(x);
5132 }
5133
5134 #if defined(CONFIG_USER_ONLY)
5135
5136 /* These should probably raise undefined insn exceptions.  */
5137 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5138 {
5139     ARMCPU *cpu = arm_env_get_cpu(env);
5140
5141     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5142 }
5143
5144 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5145 {
5146     ARMCPU *cpu = arm_env_get_cpu(env);
5147
5148     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5149     return 0;
5150 }
5151
5152 void switch_mode(CPUARMState *env, int mode)
5153 {
5154     ARMCPU *cpu = arm_env_get_cpu(env);
5155
5156     if (mode != ARM_CPU_MODE_USR) {
5157         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5158     }
5159 }
5160
5161 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5162 {
5163     ARMCPU *cpu = arm_env_get_cpu(env);
5164
5165     cpu_abort(CPU(cpu), "banked r13 write\n");
5166 }
5167
5168 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5169 {
5170     ARMCPU *cpu = arm_env_get_cpu(env);
5171
5172     cpu_abort(CPU(cpu), "banked r13 read\n");
5173     return 0;
5174 }
5175
5176 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5177                                  uint32_t cur_el, bool secure)
5178 {
5179     return 1;
5180 }
5181
5182 void aarch64_sync_64_to_32(CPUARMState *env)
5183 {
5184     g_assert_not_reached();
5185 }
5186
5187 #else
5188
5189 /* Map CPU modes onto saved register banks.  */
5190 int bank_number(int mode)
5191 {
5192     switch (mode) {
5193     case ARM_CPU_MODE_USR:
5194     case ARM_CPU_MODE_SYS:
5195         return BANK_USRSYS;
5196     case ARM_CPU_MODE_SVC:
5197         return BANK_SVC;
5198     case ARM_CPU_MODE_ABT:
5199         return BANK_ABT;
5200     case ARM_CPU_MODE_UND:
5201         return BANK_UND;
5202     case ARM_CPU_MODE_IRQ:
5203         return BANK_IRQ;
5204     case ARM_CPU_MODE_FIQ:
5205         return BANK_FIQ;
5206     case ARM_CPU_MODE_HYP:
5207         return BANK_HYP;
5208     case ARM_CPU_MODE_MON:
5209         return BANK_MON;
5210     }
5211     g_assert_not_reached();
5212 }
5213
5214 void switch_mode(CPUARMState *env, int mode)
5215 {
5216     int old_mode;
5217     int i;
5218
5219     old_mode = env->uncached_cpsr & CPSR_M;
5220     if (mode == old_mode)
5221         return;
5222
5223     if (old_mode == ARM_CPU_MODE_FIQ) {
5224         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5225         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5226     } else if (mode == ARM_CPU_MODE_FIQ) {
5227         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5228         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5229     }
5230
5231     i = bank_number(old_mode);
5232     env->banked_r13[i] = env->regs[13];
5233     env->banked_r14[i] = env->regs[14];
5234     env->banked_spsr[i] = env->spsr;
5235
5236     i = bank_number(mode);
5237     env->regs[13] = env->banked_r13[i];
5238     env->regs[14] = env->banked_r14[i];
5239     env->spsr = env->banked_spsr[i];
5240 }
5241
5242 /* Physical Interrupt Target EL Lookup Table
5243  *
5244  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5245  *
5246  * The below multi-dimensional table is used for looking up the target
5247  * exception level given numerous condition criteria.  Specifically, the
5248  * target EL is based on SCR and HCR routing controls as well as the
5249  * currently executing EL and secure state.
5250  *
5251  *    Dimensions:
5252  *    target_el_table[2][2][2][2][2][4]
5253  *                    |  |  |  |  |  +--- Current EL
5254  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5255  *                    |  |  |  +--------- HCR mask override
5256  *                    |  |  +------------ SCR exec state control
5257  *                    |  +--------------- SCR mask override
5258  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5259  *
5260  *    The table values are as such:
5261  *    0-3 = EL0-EL3
5262  *     -1 = Cannot occur
5263  *
5264  * The ARM ARM target EL table includes entries indicating that an "exception
5265  * is not taken".  The two cases where this is applicable are:
5266  *    1) An exception is taken from EL3 but the SCR does not have the exception
5267  *    routed to EL3.
5268  *    2) An exception is taken from EL2 but the HCR does not have the exception
5269  *    routed to EL2.
5270  * In these two cases, the below table contain a target of EL1.  This value is
5271  * returned as it is expected that the consumer of the table data will check
5272  * for "target EL >= current EL" to ensure the exception is not taken.
5273  *
5274  *            SCR     HCR
5275  *         64  EA     AMO                 From
5276  *        BIT IRQ     IMO      Non-secure         Secure
5277  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5278  */
5279 static const int8_t target_el_table[2][2][2][2][2][4] = {
5280     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5281        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5282       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5283        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5284      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5285        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5286       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5287        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5288     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5289        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5290       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5291        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5292      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5293        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5294       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5295        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5296 };
5297
5298 /*
5299  * Determine the target EL for physical exceptions
5300  */
5301 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5302                                  uint32_t cur_el, bool secure)
5303 {
5304     CPUARMState *env = cs->env_ptr;
5305     int rw;
5306     int scr;
5307     int hcr;
5308     int target_el;
5309     /* Is the highest EL AArch64? */
5310     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5311
5312     if (arm_feature(env, ARM_FEATURE_EL3)) {
5313         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5314     } else {
5315         /* Either EL2 is the highest EL (and so the EL2 register width
5316          * is given by is64); or there is no EL2 or EL3, in which case
5317          * the value of 'rw' does not affect the table lookup anyway.
5318          */
5319         rw = is64;
5320     }
5321
5322     switch (excp_idx) {
5323     case EXCP_IRQ:
5324         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5325         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5326         break;
5327     case EXCP_FIQ:
5328         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5329         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5330         break;
5331     default:
5332         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5333         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5334         break;
5335     };
5336
5337     /* If HCR.TGE is set then HCR is treated as being 1 */
5338     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5339
5340     /* Perform a table-lookup for the target EL given the current state */
5341     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5342
5343     assert(target_el > 0);
5344
5345     return target_el;
5346 }
5347
5348 static void v7m_push(CPUARMState *env, uint32_t val)
5349 {
5350     CPUState *cs = CPU(arm_env_get_cpu(env));
5351
5352     env->regs[13] -= 4;
5353     stl_phys(cs->as, env->regs[13], val);
5354 }
5355
5356 static uint32_t v7m_pop(CPUARMState *env)
5357 {
5358     CPUState *cs = CPU(arm_env_get_cpu(env));
5359     uint32_t val;
5360
5361     val = ldl_phys(cs->as, env->regs[13]);
5362     env->regs[13] += 4;
5363     return val;
5364 }
5365
5366 /* Switch to V7M main or process stack pointer.  */
5367 static void switch_v7m_sp(CPUARMState *env, int process)
5368 {
5369     uint32_t tmp;
5370     if (env->v7m.current_sp != process) {
5371         tmp = env->v7m.other_sp;
5372         env->v7m.other_sp = env->regs[13];
5373         env->regs[13] = tmp;
5374         env->v7m.current_sp = process;
5375     }
5376 }
5377
5378 static void do_v7m_exception_exit(CPUARMState *env)
5379 {
5380     uint32_t type;
5381     uint32_t xpsr;
5382
5383     type = env->regs[15];
5384     if (env->v7m.exception != 0)
5385         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5386
5387     /* Switch to the target stack.  */
5388     switch_v7m_sp(env, (type & 4) != 0);
5389     /* Pop registers.  */
5390     env->regs[0] = v7m_pop(env);
5391     env->regs[1] = v7m_pop(env);
5392     env->regs[2] = v7m_pop(env);
5393     env->regs[3] = v7m_pop(env);
5394     env->regs[12] = v7m_pop(env);
5395     env->regs[14] = v7m_pop(env);
5396     env->regs[15] = v7m_pop(env);
5397     if (env->regs[15] & 1) {
5398         qemu_log_mask(LOG_GUEST_ERROR,
5399                       "M profile return from interrupt with misaligned "
5400                       "PC is UNPREDICTABLE\n");
5401         /* Actual hardware seems to ignore the lsbit, and there are several
5402          * RTOSes out there which incorrectly assume the r15 in the stack
5403          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5404          */
5405         env->regs[15] &= ~1U;
5406     }
5407     xpsr = v7m_pop(env);
5408     xpsr_write(env, xpsr, 0xfffffdff);
5409     /* Undo stack alignment.  */
5410     if (xpsr & 0x200)
5411         env->regs[13] |= 4;
5412     /* ??? The exception return type specifies Thread/Handler mode.  However
5413        this is also implied by the xPSR value. Not sure what to do
5414        if there is a mismatch.  */
5415     /* ??? Likewise for mismatches between the CONTROL register and the stack
5416        pointer.  */
5417 }
5418
5419 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5420 {
5421     ARMCPU *cpu = ARM_CPU(cs);
5422     CPUARMState *env = &cpu->env;
5423     uint32_t xpsr = xpsr_read(env);
5424     uint32_t lr;
5425     uint32_t addr;
5426
5427     arm_log_exception(cs->exception_index);
5428
5429     lr = 0xfffffff1;
5430     if (env->v7m.current_sp)
5431         lr |= 4;
5432     if (env->v7m.exception == 0)
5433         lr |= 8;
5434
5435     /* For exceptions we just mark as pending on the NVIC, and let that
5436        handle it.  */
5437     /* TODO: Need to escalate if the current priority is higher than the
5438        one we're raising.  */
5439     switch (cs->exception_index) {
5440     case EXCP_UDEF:
5441         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5442         return;
5443     case EXCP_SWI:
5444         /* The PC already points to the next instruction.  */
5445         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5446         return;
5447     case EXCP_PREFETCH_ABORT:
5448     case EXCP_DATA_ABORT:
5449         /* TODO: if we implemented the MPU registers, this is where we
5450          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5451          */
5452         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5453         return;
5454     case EXCP_BKPT:
5455         if (semihosting_enabled()) {
5456             int nr;
5457             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5458             if (nr == 0xab) {
5459                 env->regs[15] += 2;
5460                 qemu_log_mask(CPU_LOG_INT,
5461                               "...handling as semihosting call 0x%x\n",
5462                               env->regs[0]);
5463                 env->regs[0] = do_arm_semihosting(env);
5464                 return;
5465             }
5466         }
5467         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5468         return;
5469     case EXCP_IRQ:
5470         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5471         break;
5472     case EXCP_EXCEPTION_EXIT:
5473         do_v7m_exception_exit(env);
5474         return;
5475     default:
5476         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5477         return; /* Never happens.  Keep compiler happy.  */
5478     }
5479
5480     /* Align stack pointer.  */
5481     /* ??? Should only do this if Configuration Control Register
5482        STACKALIGN bit is set.  */
5483     if (env->regs[13] & 4) {
5484         env->regs[13] -= 4;
5485         xpsr |= 0x200;
5486     }
5487     /* Switch to the handler mode.  */
5488     v7m_push(env, xpsr);
5489     v7m_push(env, env->regs[15]);
5490     v7m_push(env, env->regs[14]);
5491     v7m_push(env, env->regs[12]);
5492     v7m_push(env, env->regs[3]);
5493     v7m_push(env, env->regs[2]);
5494     v7m_push(env, env->regs[1]);
5495     v7m_push(env, env->regs[0]);
5496     switch_v7m_sp(env, 0);
5497     /* Clear IT bits */
5498     env->condexec_bits = 0;
5499     env->regs[14] = lr;
5500     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5501     env->regs[15] = addr & 0xfffffffe;
5502     env->thumb = addr & 1;
5503 }
5504
5505 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5506  * register set.  This is necessary when switching between AArch32 and AArch64
5507  * execution state.
5508  */
5509 void aarch64_sync_32_to_64(CPUARMState *env)
5510 {
5511     int i;
5512     uint32_t mode = env->uncached_cpsr & CPSR_M;
5513
5514     /* We can blanket copy R[0:7] to X[0:7] */
5515     for (i = 0; i < 8; i++) {
5516         env->xregs[i] = env->regs[i];
5517     }
5518
5519     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5520      * Otherwise, they come from the banked user regs.
5521      */
5522     if (mode == ARM_CPU_MODE_FIQ) {
5523         for (i = 8; i < 13; i++) {
5524             env->xregs[i] = env->usr_regs[i - 8];
5525         }
5526     } else {
5527         for (i = 8; i < 13; i++) {
5528             env->xregs[i] = env->regs[i];
5529         }
5530     }
5531
5532     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5533      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5534      * from the mode banked register.
5535      */
5536     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5537         env->xregs[13] = env->regs[13];
5538         env->xregs[14] = env->regs[14];
5539     } else {
5540         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5541         /* HYP is an exception in that it is copied from r14 */
5542         if (mode == ARM_CPU_MODE_HYP) {
5543             env->xregs[14] = env->regs[14];
5544         } else {
5545             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5546         }
5547     }
5548
5549     if (mode == ARM_CPU_MODE_HYP) {
5550         env->xregs[15] = env->regs[13];
5551     } else {
5552         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5553     }
5554
5555     if (mode == ARM_CPU_MODE_IRQ) {
5556         env->xregs[16] = env->regs[14];
5557         env->xregs[17] = env->regs[13];
5558     } else {
5559         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5560         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5561     }
5562
5563     if (mode == ARM_CPU_MODE_SVC) {
5564         env->xregs[18] = env->regs[14];
5565         env->xregs[19] = env->regs[13];
5566     } else {
5567         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5568         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5569     }
5570
5571     if (mode == ARM_CPU_MODE_ABT) {
5572         env->xregs[20] = env->regs[14];
5573         env->xregs[21] = env->regs[13];
5574     } else {
5575         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5576         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5577     }
5578
5579     if (mode == ARM_CPU_MODE_UND) {
5580         env->xregs[22] = env->regs[14];
5581         env->xregs[23] = env->regs[13];
5582     } else {
5583         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5584         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5585     }
5586
5587     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5588      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5589      * FIQ bank for r8-r14.
5590      */
5591     if (mode == ARM_CPU_MODE_FIQ) {
5592         for (i = 24; i < 31; i++) {
5593             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5594         }
5595     } else {
5596         for (i = 24; i < 29; i++) {
5597             env->xregs[i] = env->fiq_regs[i - 24];
5598         }
5599         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5600         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5601     }
5602
5603     env->pc = env->regs[15];
5604 }
5605
5606 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5607  * register set.  This is necessary when switching between AArch32 and AArch64
5608  * execution state.
5609  */
5610 void aarch64_sync_64_to_32(CPUARMState *env)
5611 {
5612     int i;
5613     uint32_t mode = env->uncached_cpsr & CPSR_M;
5614
5615     /* We can blanket copy X[0:7] to R[0:7] */
5616     for (i = 0; i < 8; i++) {
5617         env->regs[i] = env->xregs[i];
5618     }
5619
5620     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5621      * Otherwise, we copy x8-x12 into the banked user regs.
5622      */
5623     if (mode == ARM_CPU_MODE_FIQ) {
5624         for (i = 8; i < 13; i++) {
5625             env->usr_regs[i - 8] = env->xregs[i];
5626         }
5627     } else {
5628         for (i = 8; i < 13; i++) {
5629             env->regs[i] = env->xregs[i];
5630         }
5631     }
5632
5633     /* Registers r13 & r14 depend on the current mode.
5634      * If we are in a given mode, we copy the corresponding x registers to r13
5635      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
5636      * for the mode.
5637      */
5638     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5639         env->regs[13] = env->xregs[13];
5640         env->regs[14] = env->xregs[14];
5641     } else {
5642         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5643
5644         /* HYP is an exception in that it does not have its own banked r14 but
5645          * shares the USR r14
5646          */
5647         if (mode == ARM_CPU_MODE_HYP) {
5648             env->regs[14] = env->xregs[14];
5649         } else {
5650             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5651         }
5652     }
5653
5654     if (mode == ARM_CPU_MODE_HYP) {
5655         env->regs[13] = env->xregs[15];
5656     } else {
5657         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5658     }
5659
5660     if (mode == ARM_CPU_MODE_IRQ) {
5661         env->regs[14] = env->xregs[16];
5662         env->regs[13] = env->xregs[17];
5663     } else {
5664         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5665         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5666     }
5667
5668     if (mode == ARM_CPU_MODE_SVC) {
5669         env->regs[14] = env->xregs[18];
5670         env->regs[13] = env->xregs[19];
5671     } else {
5672         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5673         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5674     }
5675
5676     if (mode == ARM_CPU_MODE_ABT) {
5677         env->regs[14] = env->xregs[20];
5678         env->regs[13] = env->xregs[21];
5679     } else {
5680         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5681         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5682     }
5683
5684     if (mode == ARM_CPU_MODE_UND) {
5685         env->regs[14] = env->xregs[22];
5686         env->regs[13] = env->xregs[23];
5687     } else {
5688         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5689         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5690     }
5691
5692     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5693      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
5694      * FIQ bank for r8-r14.
5695      */
5696     if (mode == ARM_CPU_MODE_FIQ) {
5697         for (i = 24; i < 31; i++) {
5698             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
5699         }
5700     } else {
5701         for (i = 24; i < 29; i++) {
5702             env->fiq_regs[i - 24] = env->xregs[i];
5703         }
5704         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5705         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5706     }
5707
5708     env->regs[15] = env->pc;
5709 }
5710
5711 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
5712 {
5713     ARMCPU *cpu = ARM_CPU(cs);
5714     CPUARMState *env = &cpu->env;
5715     uint32_t addr;
5716     uint32_t mask;
5717     int new_mode;
5718     uint32_t offset;
5719     uint32_t moe;
5720
5721     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5722     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5723     case EC_BREAKPOINT:
5724     case EC_BREAKPOINT_SAME_EL:
5725         moe = 1;
5726         break;
5727     case EC_WATCHPOINT:
5728     case EC_WATCHPOINT_SAME_EL:
5729         moe = 10;
5730         break;
5731     case EC_AA32_BKPT:
5732         moe = 3;
5733         break;
5734     case EC_VECTORCATCH:
5735         moe = 5;
5736         break;
5737     default:
5738         moe = 0;
5739         break;
5740     }
5741
5742     if (moe) {
5743         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5744     }
5745
5746     /* TODO: Vectored interrupt controller.  */
5747     switch (cs->exception_index) {
5748     case EXCP_UDEF:
5749         new_mode = ARM_CPU_MODE_UND;
5750         addr = 0x04;
5751         mask = CPSR_I;
5752         if (env->thumb)
5753             offset = 2;
5754         else
5755             offset = 4;
5756         break;
5757     case EXCP_SWI:
5758         new_mode = ARM_CPU_MODE_SVC;
5759         addr = 0x08;
5760         mask = CPSR_I;
5761         /* The PC already points to the next instruction.  */
5762         offset = 0;
5763         break;
5764     case EXCP_BKPT:
5765         env->exception.fsr = 2;
5766         /* Fall through to prefetch abort.  */
5767     case EXCP_PREFETCH_ABORT:
5768         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5769         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5770         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5771                       env->exception.fsr, (uint32_t)env->exception.vaddress);
5772         new_mode = ARM_CPU_MODE_ABT;
5773         addr = 0x0c;
5774         mask = CPSR_A | CPSR_I;
5775         offset = 4;
5776         break;
5777     case EXCP_DATA_ABORT:
5778         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5779         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5780         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5781                       env->exception.fsr,
5782                       (uint32_t)env->exception.vaddress);
5783         new_mode = ARM_CPU_MODE_ABT;
5784         addr = 0x10;
5785         mask = CPSR_A | CPSR_I;
5786         offset = 8;
5787         break;
5788     case EXCP_IRQ:
5789         new_mode = ARM_CPU_MODE_IRQ;
5790         addr = 0x18;
5791         /* Disable IRQ and imprecise data aborts.  */
5792         mask = CPSR_A | CPSR_I;
5793         offset = 4;
5794         if (env->cp15.scr_el3 & SCR_IRQ) {
5795             /* IRQ routed to monitor mode */
5796             new_mode = ARM_CPU_MODE_MON;
5797             mask |= CPSR_F;
5798         }
5799         break;
5800     case EXCP_FIQ:
5801         new_mode = ARM_CPU_MODE_FIQ;
5802         addr = 0x1c;
5803         /* Disable FIQ, IRQ and imprecise data aborts.  */
5804         mask = CPSR_A | CPSR_I | CPSR_F;
5805         if (env->cp15.scr_el3 & SCR_FIQ) {
5806             /* FIQ routed to monitor mode */
5807             new_mode = ARM_CPU_MODE_MON;
5808         }
5809         offset = 4;
5810         break;
5811     case EXCP_SMC:
5812         new_mode = ARM_CPU_MODE_MON;
5813         addr = 0x08;
5814         mask = CPSR_A | CPSR_I | CPSR_F;
5815         offset = 0;
5816         break;
5817     default:
5818         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5819         return; /* Never happens.  Keep compiler happy.  */
5820     }
5821
5822     if (new_mode == ARM_CPU_MODE_MON) {
5823         addr += env->cp15.mvbar;
5824     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5825         /* High vectors. When enabled, base address cannot be remapped. */
5826         addr += 0xffff0000;
5827     } else {
5828         /* ARM v7 architectures provide a vector base address register to remap
5829          * the interrupt vector table.
5830          * This register is only followed in non-monitor mode, and is banked.
5831          * Note: only bits 31:5 are valid.
5832          */
5833         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5834     }
5835
5836     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5837         env->cp15.scr_el3 &= ~SCR_NS;
5838     }
5839
5840     switch_mode (env, new_mode);
5841     /* For exceptions taken to AArch32 we must clear the SS bit in both
5842      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5843      */
5844     env->uncached_cpsr &= ~PSTATE_SS;
5845     env->spsr = cpsr_read(env);
5846     /* Clear IT bits.  */
5847     env->condexec_bits = 0;
5848     /* Switch to the new mode, and to the correct instruction set.  */
5849     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5850     env->daif |= mask;
5851     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5852      * and we should just guard the thumb mode on V4 */
5853     if (arm_feature(env, ARM_FEATURE_V4T)) {
5854         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5855     }
5856     env->regs[14] = env->regs[15] + offset;
5857     env->regs[15] = addr;
5858 }
5859
5860 /* Handle exception entry to a target EL which is using AArch64 */
5861 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
5862 {
5863     ARMCPU *cpu = ARM_CPU(cs);
5864     CPUARMState *env = &cpu->env;
5865     unsigned int new_el = env->exception.target_el;
5866     target_ulong addr = env->cp15.vbar_el[new_el];
5867     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
5868
5869     if (arm_current_el(env) < new_el) {
5870         /* Entry vector offset depends on whether the implemented EL
5871          * immediately lower than the target level is using AArch32 or AArch64
5872          */
5873         bool is_aa64;
5874
5875         switch (new_el) {
5876         case 3:
5877             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
5878             break;
5879         case 2:
5880             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
5881             break;
5882         case 1:
5883             is_aa64 = is_a64(env);
5884             break;
5885         default:
5886             g_assert_not_reached();
5887         }
5888
5889         if (is_aa64) {
5890             addr += 0x400;
5891         } else {
5892             addr += 0x600;
5893         }
5894     } else if (pstate_read(env) & PSTATE_SP) {
5895         addr += 0x200;
5896     }
5897
5898     switch (cs->exception_index) {
5899     case EXCP_PREFETCH_ABORT:
5900     case EXCP_DATA_ABORT:
5901         env->cp15.far_el[new_el] = env->exception.vaddress;
5902         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
5903                       env->cp15.far_el[new_el]);
5904         /* fall through */
5905     case EXCP_BKPT:
5906     case EXCP_UDEF:
5907     case EXCP_SWI:
5908     case EXCP_HVC:
5909     case EXCP_HYP_TRAP:
5910     case EXCP_SMC:
5911         env->cp15.esr_el[new_el] = env->exception.syndrome;
5912         break;
5913     case EXCP_IRQ:
5914     case EXCP_VIRQ:
5915         addr += 0x80;
5916         break;
5917     case EXCP_FIQ:
5918     case EXCP_VFIQ:
5919         addr += 0x100;
5920         break;
5921     case EXCP_SEMIHOST:
5922         qemu_log_mask(CPU_LOG_INT,
5923                       "...handling as semihosting call 0x%" PRIx64 "\n",
5924                       env->xregs[0]);
5925         env->xregs[0] = do_arm_semihosting(env);
5926         return;
5927     default:
5928         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5929     }
5930
5931     if (is_a64(env)) {
5932         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
5933         aarch64_save_sp(env, arm_current_el(env));
5934         env->elr_el[new_el] = env->pc;
5935     } else {
5936         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
5937         if (!env->thumb) {
5938             env->cp15.esr_el[new_el] |= 1 << 25;
5939         }
5940         env->elr_el[new_el] = env->regs[15];
5941
5942         aarch64_sync_32_to_64(env);
5943
5944         env->condexec_bits = 0;
5945     }
5946     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
5947                   env->elr_el[new_el]);
5948
5949     pstate_write(env, PSTATE_DAIF | new_mode);
5950     env->aarch64 = 1;
5951     aarch64_restore_sp(env, new_el);
5952
5953     env->pc = addr;
5954
5955     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
5956                   new_el, env->pc, pstate_read(env));
5957 }
5958
5959 static inline bool check_for_semihosting(CPUState *cs)
5960 {
5961     /* Check whether this exception is a semihosting call; if so
5962      * then handle it and return true; otherwise return false.
5963      */
5964     ARMCPU *cpu = ARM_CPU(cs);
5965     CPUARMState *env = &cpu->env;
5966
5967     if (is_a64(env)) {
5968         if (cs->exception_index == EXCP_SEMIHOST) {
5969             /* This is always the 64-bit semihosting exception.
5970              * The "is this usermode" and "is semihosting enabled"
5971              * checks have been done at translate time.
5972              */
5973             qemu_log_mask(CPU_LOG_INT,
5974                           "...handling as semihosting call 0x%" PRIx64 "\n",
5975                           env->xregs[0]);
5976             env->xregs[0] = do_arm_semihosting(env);
5977             return true;
5978         }
5979         return false;
5980     } else {
5981         uint32_t imm;
5982
5983         /* Only intercept calls from privileged modes, to provide some
5984          * semblance of security.
5985          */
5986         if (!semihosting_enabled() ||
5987             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
5988             return false;
5989         }
5990
5991         switch (cs->exception_index) {
5992         case EXCP_SWI:
5993             /* Check for semihosting interrupt.  */
5994             if (env->thumb) {
5995                 imm = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
5996                     & 0xff;
5997                 if (imm == 0xab) {
5998                     break;
5999                 }
6000             } else {
6001                 imm = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
6002                     & 0xffffff;
6003                 if (imm == 0x123456) {
6004                     break;
6005                 }
6006             }
6007             return false;
6008         case EXCP_BKPT:
6009             /* See if this is a semihosting syscall.  */
6010             if (env->thumb) {
6011                 imm = arm_lduw_code(env, env->regs[15], env->bswap_code)
6012                     & 0xff;
6013                 if (imm == 0xab) {
6014                     env->regs[15] += 2;
6015                     break;
6016                 }
6017             }
6018             return false;
6019         default:
6020             return false;
6021         }
6022
6023         qemu_log_mask(CPU_LOG_INT,
6024                       "...handling as semihosting call 0x%x\n",
6025                       env->regs[0]);
6026         env->regs[0] = do_arm_semihosting(env);
6027         return true;
6028     }
6029 }
6030
6031 /* Handle a CPU exception for A and R profile CPUs.
6032  * Do any appropriate logging, handle PSCI calls, and then hand off
6033  * to the AArch64-entry or AArch32-entry function depending on the
6034  * target exception level's register width.
6035  */
6036 void arm_cpu_do_interrupt(CPUState *cs)
6037 {
6038     ARMCPU *cpu = ARM_CPU(cs);
6039     CPUARMState *env = &cpu->env;
6040     unsigned int new_el = env->exception.target_el;
6041
6042     assert(!IS_M(env));
6043
6044     arm_log_exception(cs->exception_index);
6045     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6046                   new_el);
6047     if (qemu_loglevel_mask(CPU_LOG_INT)
6048         && !excp_is_internal(cs->exception_index)) {
6049         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6050                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6051                       env->exception.syndrome);
6052     }
6053
6054     if (arm_is_psci_call(cpu, cs->exception_index)) {
6055         arm_handle_psci_call(cpu);
6056         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6057         return;
6058     }
6059
6060     /* Semihosting semantics depend on the register width of the
6061      * code that caused the exception, not the target exception level,
6062      * so must be handled here.
6063      */
6064     if (check_for_semihosting(cs)) {
6065         return;
6066     }
6067
6068     assert(!excp_is_internal(cs->exception_index));
6069     if (arm_el_is_aa64(env, new_el)) {
6070         arm_cpu_do_interrupt_aarch64(cs);
6071     } else {
6072         arm_cpu_do_interrupt_aarch32(cs);
6073     }
6074
6075     if (!kvm_enabled()) {
6076         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6077     }
6078 }
6079
6080 /* Return the exception level which controls this address translation regime */
6081 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6082 {
6083     switch (mmu_idx) {
6084     case ARMMMUIdx_S2NS:
6085     case ARMMMUIdx_S1E2:
6086         return 2;
6087     case ARMMMUIdx_S1E3:
6088         return 3;
6089     case ARMMMUIdx_S1SE0:
6090         return arm_el_is_aa64(env, 3) ? 1 : 3;
6091     case ARMMMUIdx_S1SE1:
6092     case ARMMMUIdx_S1NSE0:
6093     case ARMMMUIdx_S1NSE1:
6094         return 1;
6095     default:
6096         g_assert_not_reached();
6097     }
6098 }
6099
6100 /* Return true if this address translation regime is secure */
6101 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6102 {
6103     switch (mmu_idx) {
6104     case ARMMMUIdx_S12NSE0:
6105     case ARMMMUIdx_S12NSE1:
6106     case ARMMMUIdx_S1NSE0:
6107     case ARMMMUIdx_S1NSE1:
6108     case ARMMMUIdx_S1E2:
6109     case ARMMMUIdx_S2NS:
6110         return false;
6111     case ARMMMUIdx_S1E3:
6112     case ARMMMUIdx_S1SE0:
6113     case ARMMMUIdx_S1SE1:
6114         return true;
6115     default:
6116         g_assert_not_reached();
6117     }
6118 }
6119
6120 /* Return the SCTLR value which controls this address translation regime */
6121 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6122 {
6123     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6124 }
6125
6126 /* Return true if the specified stage of address translation is disabled */
6127 static inline bool regime_translation_disabled(CPUARMState *env,
6128                                                ARMMMUIdx mmu_idx)
6129 {
6130     if (mmu_idx == ARMMMUIdx_S2NS) {
6131         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6132     }
6133     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6134 }
6135
6136 /* Return the TCR controlling this translation regime */
6137 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6138 {
6139     if (mmu_idx == ARMMMUIdx_S2NS) {
6140         return &env->cp15.vtcr_el2;
6141     }
6142     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6143 }
6144
6145 /* Return the TTBR associated with this translation regime */
6146 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6147                                    int ttbrn)
6148 {
6149     if (mmu_idx == ARMMMUIdx_S2NS) {
6150         return env->cp15.vttbr_el2;
6151     }
6152     if (ttbrn == 0) {
6153         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6154     } else {
6155         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6156     }
6157 }
6158
6159 /* Return true if the translation regime is using LPAE format page tables */
6160 static inline bool regime_using_lpae_format(CPUARMState *env,
6161                                             ARMMMUIdx mmu_idx)
6162 {
6163     int el = regime_el(env, mmu_idx);
6164     if (el == 2 || arm_el_is_aa64(env, el)) {
6165         return true;
6166     }
6167     if (arm_feature(env, ARM_FEATURE_LPAE)
6168         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6169         return true;
6170     }
6171     return false;
6172 }
6173
6174 /* Returns true if the stage 1 translation regime is using LPAE format page
6175  * tables. Used when raising alignment exceptions, whose FSR changes depending
6176  * on whether the long or short descriptor format is in use. */
6177 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6178 {
6179     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6180         mmu_idx += ARMMMUIdx_S1NSE0;
6181     }
6182
6183     return regime_using_lpae_format(env, mmu_idx);
6184 }
6185
6186 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6187 {
6188     switch (mmu_idx) {
6189     case ARMMMUIdx_S1SE0:
6190     case ARMMMUIdx_S1NSE0:
6191         return true;
6192     default:
6193         return false;
6194     case ARMMMUIdx_S12NSE0:
6195     case ARMMMUIdx_S12NSE1:
6196         g_assert_not_reached();
6197     }
6198 }
6199
6200 /* Translate section/page access permissions to page
6201  * R/W protection flags
6202  *
6203  * @env:         CPUARMState
6204  * @mmu_idx:     MMU index indicating required translation regime
6205  * @ap:          The 3-bit access permissions (AP[2:0])
6206  * @domain_prot: The 2-bit domain access permissions
6207  */
6208 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6209                                 int ap, int domain_prot)
6210 {
6211     bool is_user = regime_is_user(env, mmu_idx);
6212
6213     if (domain_prot == 3) {
6214         return PAGE_READ | PAGE_WRITE;
6215     }
6216
6217     switch (ap) {
6218     case 0:
6219         if (arm_feature(env, ARM_FEATURE_V7)) {
6220             return 0;
6221         }
6222         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6223         case SCTLR_S:
6224             return is_user ? 0 : PAGE_READ;
6225         case SCTLR_R:
6226             return PAGE_READ;
6227         default:
6228             return 0;
6229         }
6230     case 1:
6231         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6232     case 2:
6233         if (is_user) {
6234             return PAGE_READ;
6235         } else {
6236             return PAGE_READ | PAGE_WRITE;
6237         }
6238     case 3:
6239         return PAGE_READ | PAGE_WRITE;
6240     case 4: /* Reserved.  */
6241         return 0;
6242     case 5:
6243         return is_user ? 0 : PAGE_READ;
6244     case 6:
6245         return PAGE_READ;
6246     case 7:
6247         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6248             return 0;
6249         }
6250         return PAGE_READ;
6251     default:
6252         g_assert_not_reached();
6253     }
6254 }
6255
6256 /* Translate section/page access permissions to page
6257  * R/W protection flags.
6258  *
6259  * @ap:      The 2-bit simple AP (AP[2:1])
6260  * @is_user: TRUE if accessing from PL0
6261  */
6262 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6263 {
6264     switch (ap) {
6265     case 0:
6266         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6267     case 1:
6268         return PAGE_READ | PAGE_WRITE;
6269     case 2:
6270         return is_user ? 0 : PAGE_READ;
6271     case 3:
6272         return PAGE_READ;
6273     default:
6274         g_assert_not_reached();
6275     }
6276 }
6277
6278 static inline int
6279 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6280 {
6281     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6282 }
6283
6284 /* Translate S2 section/page access permissions to protection flags
6285  *
6286  * @env:     CPUARMState
6287  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6288  * @xn:      XN (execute-never) bit
6289  */
6290 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6291 {
6292     int prot = 0;
6293
6294     if (s2ap & 1) {
6295         prot |= PAGE_READ;
6296     }
6297     if (s2ap & 2) {
6298         prot |= PAGE_WRITE;
6299     }
6300     if (!xn) {
6301         prot |= PAGE_EXEC;
6302     }
6303     return prot;
6304 }
6305
6306 /* Translate section/page access permissions to protection flags
6307  *
6308  * @env:     CPUARMState
6309  * @mmu_idx: MMU index indicating required translation regime
6310  * @is_aa64: TRUE if AArch64
6311  * @ap:      The 2-bit simple AP (AP[2:1])
6312  * @ns:      NS (non-secure) bit
6313  * @xn:      XN (execute-never) bit
6314  * @pxn:     PXN (privileged execute-never) bit
6315  */
6316 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6317                       int ap, int ns, int xn, int pxn)
6318 {
6319     bool is_user = regime_is_user(env, mmu_idx);
6320     int prot_rw, user_rw;
6321     bool have_wxn;
6322     int wxn = 0;
6323
6324     assert(mmu_idx != ARMMMUIdx_S2NS);
6325
6326     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6327     if (is_user) {
6328         prot_rw = user_rw;
6329     } else {
6330         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6331     }
6332
6333     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6334         return prot_rw;
6335     }
6336
6337     /* TODO have_wxn should be replaced with
6338      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6339      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6340      * compatible processors have EL2, which is required for [U]WXN.
6341      */
6342     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6343
6344     if (have_wxn) {
6345         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6346     }
6347
6348     if (is_aa64) {
6349         switch (regime_el(env, mmu_idx)) {
6350         case 1:
6351             if (!is_user) {
6352                 xn = pxn || (user_rw & PAGE_WRITE);
6353             }
6354             break;
6355         case 2:
6356         case 3:
6357             break;
6358         }
6359     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6360         switch (regime_el(env, mmu_idx)) {
6361         case 1:
6362         case 3:
6363             if (is_user) {
6364                 xn = xn || !(user_rw & PAGE_READ);
6365             } else {
6366                 int uwxn = 0;
6367                 if (have_wxn) {
6368                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6369                 }
6370                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6371                      (uwxn && (user_rw & PAGE_WRITE));
6372             }
6373             break;
6374         case 2:
6375             break;
6376         }
6377     } else {
6378         xn = wxn = 0;
6379     }
6380
6381     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6382         return prot_rw;
6383     }
6384     return prot_rw | PAGE_EXEC;
6385 }
6386
6387 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6388                                      uint32_t *table, uint32_t address)
6389 {
6390     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6391     TCR *tcr = regime_tcr(env, mmu_idx);
6392
6393     if (address & tcr->mask) {
6394         if (tcr->raw_tcr & TTBCR_PD1) {
6395             /* Translation table walk disabled for TTBR1 */
6396             return false;
6397         }
6398         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6399     } else {
6400         if (tcr->raw_tcr & TTBCR_PD0) {
6401             /* Translation table walk disabled for TTBR0 */
6402             return false;
6403         }
6404         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6405     }
6406     *table |= (address >> 18) & 0x3ffc;
6407     return true;
6408 }
6409
6410 /* Translate a S1 pagetable walk through S2 if needed.  */
6411 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6412                                hwaddr addr, MemTxAttrs txattrs,
6413                                uint32_t *fsr,
6414                                ARMMMUFaultInfo *fi)
6415 {
6416     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6417         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6418         target_ulong s2size;
6419         hwaddr s2pa;
6420         int s2prot;
6421         int ret;
6422
6423         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6424                                  &txattrs, &s2prot, &s2size, fsr, fi);
6425         if (ret) {
6426             fi->s2addr = addr;
6427             fi->stage2 = true;
6428             fi->s1ptw = true;
6429             return ~0;
6430         }
6431         addr = s2pa;
6432     }
6433     return addr;
6434 }
6435
6436 /* All loads done in the course of a page table walk go through here.
6437  * TODO: rather than ignoring errors from physical memory reads (which
6438  * are external aborts in ARM terminology) we should propagate this
6439  * error out so that we can turn it into a Data Abort if this walk
6440  * was being done for a CPU load/store or an address translation instruction
6441  * (but not if it was for a debug access).
6442  */
6443 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6444                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6445                             ARMMMUFaultInfo *fi)
6446 {
6447     ARMCPU *cpu = ARM_CPU(cs);
6448     CPUARMState *env = &cpu->env;
6449     MemTxAttrs attrs = {};
6450     AddressSpace *as;
6451
6452     attrs.secure = is_secure;
6453     as = arm_addressspace(cs, attrs);
6454     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6455     if (fi->s1ptw) {
6456         return 0;
6457     }
6458     return address_space_ldl(as, addr, attrs, NULL);
6459 }
6460
6461 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6462                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6463                             ARMMMUFaultInfo *fi)
6464 {
6465     ARMCPU *cpu = ARM_CPU(cs);
6466     CPUARMState *env = &cpu->env;
6467     MemTxAttrs attrs = {};
6468     AddressSpace *as;
6469
6470     attrs.secure = is_secure;
6471     as = arm_addressspace(cs, attrs);
6472     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6473     if (fi->s1ptw) {
6474         return 0;
6475     }
6476     return address_space_ldq(as, addr, attrs, NULL);
6477 }
6478
6479 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6480                              int access_type, ARMMMUIdx mmu_idx,
6481                              hwaddr *phys_ptr, int *prot,
6482                              target_ulong *page_size, uint32_t *fsr,
6483                              ARMMMUFaultInfo *fi)
6484 {
6485     CPUState *cs = CPU(arm_env_get_cpu(env));
6486     int code;
6487     uint32_t table;
6488     uint32_t desc;
6489     int type;
6490     int ap;
6491     int domain = 0;
6492     int domain_prot;
6493     hwaddr phys_addr;
6494     uint32_t dacr;
6495
6496     /* Pagetable walk.  */
6497     /* Lookup l1 descriptor.  */
6498     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6499         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6500         code = 5;
6501         goto do_fault;
6502     }
6503     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6504                        mmu_idx, fsr, fi);
6505     type = (desc & 3);
6506     domain = (desc >> 5) & 0x0f;
6507     if (regime_el(env, mmu_idx) == 1) {
6508         dacr = env->cp15.dacr_ns;
6509     } else {
6510         dacr = env->cp15.dacr_s;
6511     }
6512     domain_prot = (dacr >> (domain * 2)) & 3;
6513     if (type == 0) {
6514         /* Section translation fault.  */
6515         code = 5;
6516         goto do_fault;
6517     }
6518     if (domain_prot == 0 || domain_prot == 2) {
6519         if (type == 2)
6520             code = 9; /* Section domain fault.  */
6521         else
6522             code = 11; /* Page domain fault.  */
6523         goto do_fault;
6524     }
6525     if (type == 2) {
6526         /* 1Mb section.  */
6527         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6528         ap = (desc >> 10) & 3;
6529         code = 13;
6530         *page_size = 1024 * 1024;
6531     } else {
6532         /* Lookup l2 entry.  */
6533         if (type == 1) {
6534             /* Coarse pagetable.  */
6535             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6536         } else {
6537             /* Fine pagetable.  */
6538             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6539         }
6540         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6541                            mmu_idx, fsr, fi);
6542         switch (desc & 3) {
6543         case 0: /* Page translation fault.  */
6544             code = 7;
6545             goto do_fault;
6546         case 1: /* 64k page.  */
6547             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6548             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6549             *page_size = 0x10000;
6550             break;
6551         case 2: /* 4k page.  */
6552             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6553             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6554             *page_size = 0x1000;
6555             break;
6556         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6557             if (type == 1) {
6558                 /* ARMv6/XScale extended small page format */
6559                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6560                     || arm_feature(env, ARM_FEATURE_V6)) {
6561                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6562                     *page_size = 0x1000;
6563                 } else {
6564                     /* UNPREDICTABLE in ARMv5; we choose to take a
6565                      * page translation fault.
6566                      */
6567                     code = 7;
6568                     goto do_fault;
6569                 }
6570             } else {
6571                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6572                 *page_size = 0x400;
6573             }
6574             ap = (desc >> 4) & 3;
6575             break;
6576         default:
6577             /* Never happens, but compiler isn't smart enough to tell.  */
6578             abort();
6579         }
6580         code = 15;
6581     }
6582     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6583     *prot |= *prot ? PAGE_EXEC : 0;
6584     if (!(*prot & (1 << access_type))) {
6585         /* Access permission fault.  */
6586         goto do_fault;
6587     }
6588     *phys_ptr = phys_addr;
6589     return false;
6590 do_fault:
6591     *fsr = code | (domain << 4);
6592     return true;
6593 }
6594
6595 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6596                              int access_type, ARMMMUIdx mmu_idx,
6597                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6598                              target_ulong *page_size, uint32_t *fsr,
6599                              ARMMMUFaultInfo *fi)
6600 {
6601     CPUState *cs = CPU(arm_env_get_cpu(env));
6602     int code;
6603     uint32_t table;
6604     uint32_t desc;
6605     uint32_t xn;
6606     uint32_t pxn = 0;
6607     int type;
6608     int ap;
6609     int domain = 0;
6610     int domain_prot;
6611     hwaddr phys_addr;
6612     uint32_t dacr;
6613     bool ns;
6614
6615     /* Pagetable walk.  */
6616     /* Lookup l1 descriptor.  */
6617     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6618         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6619         code = 5;
6620         goto do_fault;
6621     }
6622     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6623                        mmu_idx, fsr, fi);
6624     type = (desc & 3);
6625     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6626         /* Section translation fault, or attempt to use the encoding
6627          * which is Reserved on implementations without PXN.
6628          */
6629         code = 5;
6630         goto do_fault;
6631     }
6632     if ((type == 1) || !(desc & (1 << 18))) {
6633         /* Page or Section.  */
6634         domain = (desc >> 5) & 0x0f;
6635     }
6636     if (regime_el(env, mmu_idx) == 1) {
6637         dacr = env->cp15.dacr_ns;
6638     } else {
6639         dacr = env->cp15.dacr_s;
6640     }
6641     domain_prot = (dacr >> (domain * 2)) & 3;
6642     if (domain_prot == 0 || domain_prot == 2) {
6643         if (type != 1) {
6644             code = 9; /* Section domain fault.  */
6645         } else {
6646             code = 11; /* Page domain fault.  */
6647         }
6648         goto do_fault;
6649     }
6650     if (type != 1) {
6651         if (desc & (1 << 18)) {
6652             /* Supersection.  */
6653             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6654             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6655             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6656             *page_size = 0x1000000;
6657         } else {
6658             /* Section.  */
6659             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6660             *page_size = 0x100000;
6661         }
6662         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6663         xn = desc & (1 << 4);
6664         pxn = desc & 1;
6665         code = 13;
6666         ns = extract32(desc, 19, 1);
6667     } else {
6668         if (arm_feature(env, ARM_FEATURE_PXN)) {
6669             pxn = (desc >> 2) & 1;
6670         }
6671         ns = extract32(desc, 3, 1);
6672         /* Lookup l2 entry.  */
6673         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6674         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6675                            mmu_idx, fsr, fi);
6676         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6677         switch (desc & 3) {
6678         case 0: /* Page translation fault.  */
6679             code = 7;
6680             goto do_fault;
6681         case 1: /* 64k page.  */
6682             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6683             xn = desc & (1 << 15);
6684             *page_size = 0x10000;
6685             break;
6686         case 2: case 3: /* 4k page.  */
6687             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6688             xn = desc & 1;
6689             *page_size = 0x1000;
6690             break;
6691         default:
6692             /* Never happens, but compiler isn't smart enough to tell.  */
6693             abort();
6694         }
6695         code = 15;
6696     }
6697     if (domain_prot == 3) {
6698         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6699     } else {
6700         if (pxn && !regime_is_user(env, mmu_idx)) {
6701             xn = 1;
6702         }
6703         if (xn && access_type == 2)
6704             goto do_fault;
6705
6706         if (arm_feature(env, ARM_FEATURE_V6K) &&
6707                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6708             /* The simplified model uses AP[0] as an access control bit.  */
6709             if ((ap & 1) == 0) {
6710                 /* Access flag fault.  */
6711                 code = (code == 15) ? 6 : 3;
6712                 goto do_fault;
6713             }
6714             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6715         } else {
6716             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6717         }
6718         if (*prot && !xn) {
6719             *prot |= PAGE_EXEC;
6720         }
6721         if (!(*prot & (1 << access_type))) {
6722             /* Access permission fault.  */
6723             goto do_fault;
6724         }
6725     }
6726     if (ns) {
6727         /* The NS bit will (as required by the architecture) have no effect if
6728          * the CPU doesn't support TZ or this is a non-secure translation
6729          * regime, because the attribute will already be non-secure.
6730          */
6731         attrs->secure = false;
6732     }
6733     *phys_ptr = phys_addr;
6734     return false;
6735 do_fault:
6736     *fsr = code | (domain << 4);
6737     return true;
6738 }
6739
6740 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6741  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6742  */
6743 typedef enum {
6744     translation_fault = 1,
6745     access_fault = 2,
6746     permission_fault = 3,
6747 } MMUFaultType;
6748
6749 /*
6750  * check_s2_startlevel
6751  * @cpu:        ARMCPU
6752  * @is_aa64:    True if the translation regime is in AArch64 state
6753  * @startlevel: Suggested starting level
6754  * @inputsize:  Bitsize of IPAs
6755  * @stride:     Page-table stride (See the ARM ARM)
6756  *
6757  * Returns true if the suggested starting level is OK and false otherwise.
6758  */
6759 static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level,
6760                                 int inputsize, int stride)
6761 {
6762     /* Negative levels are never allowed.  */
6763     if (level < 0) {
6764         return false;
6765     }
6766
6767     if (is_aa64) {
6768         unsigned int pamax = arm_pamax(cpu);
6769
6770         switch (stride) {
6771         case 13: /* 64KB Pages.  */
6772             if (level == 0 || (level == 1 && pamax <= 42)) {
6773                 return false;
6774             }
6775             break;
6776         case 11: /* 16KB Pages.  */
6777             if (level == 0 || (level == 1 && pamax <= 40)) {
6778                 return false;
6779             }
6780             break;
6781         case 9: /* 4KB Pages.  */
6782             if (level == 0 && pamax <= 42) {
6783                 return false;
6784             }
6785             break;
6786         default:
6787             g_assert_not_reached();
6788         }
6789     } else {
6790         const int grainsize = stride + 3;
6791         int startsizecheck;
6792
6793         /* AArch32 only supports 4KB pages. Assert on that.  */
6794         assert(stride == 9);
6795
6796         if (level == 0) {
6797             return false;
6798         }
6799
6800         startsizecheck = inputsize - ((3 - level) * stride + grainsize);
6801         if (startsizecheck < 1 || startsizecheck > stride + 4) {
6802             return false;
6803         }
6804     }
6805     return true;
6806 }
6807
6808 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6809                                int access_type, ARMMMUIdx mmu_idx,
6810                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6811                                target_ulong *page_size_ptr, uint32_t *fsr,
6812                                ARMMMUFaultInfo *fi)
6813 {
6814     ARMCPU *cpu = arm_env_get_cpu(env);
6815     CPUState *cs = CPU(cpu);
6816     /* Read an LPAE long-descriptor translation table. */
6817     MMUFaultType fault_type = translation_fault;
6818     uint32_t level = 1;
6819     uint32_t epd = 0;
6820     int32_t t0sz, t1sz;
6821     uint32_t tg;
6822     uint64_t ttbr;
6823     int ttbr_select;
6824     hwaddr descaddr, descmask;
6825     uint32_t tableattrs;
6826     target_ulong page_size;
6827     uint32_t attrs;
6828     int32_t stride = 9;
6829     int32_t va_size = 32;
6830     int inputsize;
6831     int32_t tbi = 0;
6832     TCR *tcr = regime_tcr(env, mmu_idx);
6833     int ap, ns, xn, pxn;
6834     uint32_t el = regime_el(env, mmu_idx);
6835     bool ttbr1_valid = true;
6836     uint64_t descaddrmask;
6837
6838     /* TODO:
6839      * This code does not handle the different format TCR for VTCR_EL2.
6840      * This code also does not support shareability levels.
6841      * Attribute and permission bit handling should also be checked when adding
6842      * support for those page table walks.
6843      */
6844     if (arm_el_is_aa64(env, el)) {
6845         va_size = 64;
6846         if (el > 1) {
6847             if (mmu_idx != ARMMMUIdx_S2NS) {
6848                 tbi = extract64(tcr->raw_tcr, 20, 1);
6849             }
6850         } else {
6851             if (extract64(address, 55, 1)) {
6852                 tbi = extract64(tcr->raw_tcr, 38, 1);
6853             } else {
6854                 tbi = extract64(tcr->raw_tcr, 37, 1);
6855             }
6856         }
6857         tbi *= 8;
6858
6859         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6860          * invalid.
6861          */
6862         if (el > 1) {
6863             ttbr1_valid = false;
6864         }
6865     } else {
6866         /* There is no TTBR1 for EL2 */
6867         if (el == 2) {
6868             ttbr1_valid = false;
6869         }
6870     }
6871
6872     /* Determine whether this address is in the region controlled by
6873      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6874      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6875      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6876      */
6877     if (va_size == 64) {
6878         /* AArch64 translation.  */
6879         t0sz = extract32(tcr->raw_tcr, 0, 6);
6880         t0sz = MIN(t0sz, 39);
6881         t0sz = MAX(t0sz, 16);
6882     } else if (mmu_idx != ARMMMUIdx_S2NS) {
6883         /* AArch32 stage 1 translation.  */
6884         t0sz = extract32(tcr->raw_tcr, 0, 3);
6885     } else {
6886         /* AArch32 stage 2 translation.  */
6887         bool sext = extract32(tcr->raw_tcr, 4, 1);
6888         bool sign = extract32(tcr->raw_tcr, 3, 1);
6889         t0sz = sextract32(tcr->raw_tcr, 0, 4);
6890
6891         /* If the sign-extend bit is not the same as t0sz[3], the result
6892          * is unpredictable. Flag this as a guest error.  */
6893         if (sign != sext) {
6894             qemu_log_mask(LOG_GUEST_ERROR,
6895                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
6896         }
6897     }
6898     t1sz = extract32(tcr->raw_tcr, 16, 6);
6899     if (va_size == 64) {
6900         t1sz = MIN(t1sz, 39);
6901         t1sz = MAX(t1sz, 16);
6902     }
6903     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
6904         /* there is a ttbr0 region and we are in it (high bits all zero) */
6905         ttbr_select = 0;
6906     } else if (ttbr1_valid && t1sz &&
6907                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
6908         /* there is a ttbr1 region and we are in it (high bits all one) */
6909         ttbr_select = 1;
6910     } else if (!t0sz) {
6911         /* ttbr0 region is "everything not in the ttbr1 region" */
6912         ttbr_select = 0;
6913     } else if (!t1sz && ttbr1_valid) {
6914         /* ttbr1 region is "everything not in the ttbr0 region" */
6915         ttbr_select = 1;
6916     } else {
6917         /* in the gap between the two regions, this is a Translation fault */
6918         fault_type = translation_fault;
6919         goto do_fault;
6920     }
6921
6922     /* Note that QEMU ignores shareability and cacheability attributes,
6923      * so we don't need to do anything with the SH, ORGN, IRGN fields
6924      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
6925      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6926      * implement any ASID-like capability so we can ignore it (instead
6927      * we will always flush the TLB any time the ASID is changed).
6928      */
6929     if (ttbr_select == 0) {
6930         ttbr = regime_ttbr(env, mmu_idx, 0);
6931         if (el < 2) {
6932             epd = extract32(tcr->raw_tcr, 7, 1);
6933         }
6934         inputsize = va_size - t0sz;
6935
6936         tg = extract32(tcr->raw_tcr, 14, 2);
6937         if (tg == 1) { /* 64KB pages */
6938             stride = 13;
6939         }
6940         if (tg == 2) { /* 16KB pages */
6941             stride = 11;
6942         }
6943     } else {
6944         /* We should only be here if TTBR1 is valid */
6945         assert(ttbr1_valid);
6946
6947         ttbr = regime_ttbr(env, mmu_idx, 1);
6948         epd = extract32(tcr->raw_tcr, 23, 1);
6949         inputsize = va_size - t1sz;
6950
6951         tg = extract32(tcr->raw_tcr, 30, 2);
6952         if (tg == 3)  { /* 64KB pages */
6953             stride = 13;
6954         }
6955         if (tg == 1) { /* 16KB pages */
6956             stride = 11;
6957         }
6958     }
6959
6960     /* Here we should have set up all the parameters for the translation:
6961      * va_size, inputsize, ttbr, epd, stride, tbi
6962      */
6963
6964     if (epd) {
6965         /* Translation table walk disabled => Translation fault on TLB miss
6966          * Note: This is always 0 on 64-bit EL2 and EL3.
6967          */
6968         goto do_fault;
6969     }
6970
6971     if (mmu_idx != ARMMMUIdx_S2NS) {
6972         /* The starting level depends on the virtual address size (which can
6973          * be up to 48 bits) and the translation granule size. It indicates
6974          * the number of strides (stride bits at a time) needed to
6975          * consume the bits of the input address. In the pseudocode this is:
6976          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
6977          * where their 'inputsize' is our 'inputsize', 'grainsize' is
6978          * our 'stride + 3' and 'stride' is our 'stride'.
6979          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6980          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
6981          * = 4 - (inputsize - 4) / stride;
6982          */
6983         level = 4 - (inputsize - 4) / stride;
6984     } else {
6985         /* For stage 2 translations the starting level is specified by the
6986          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
6987          */
6988         int startlevel = extract32(tcr->raw_tcr, 6, 2);
6989         bool ok;
6990
6991         if (va_size == 32 || stride == 9) {
6992             /* AArch32 or 4KB pages */
6993             level = 2 - startlevel;
6994         } else {
6995             /* 16KB or 64KB pages */
6996             level = 3 - startlevel;
6997         }
6998
6999         /* Check that the starting level is valid. */
7000         ok = check_s2_startlevel(cpu, va_size == 64, level,
7001                                  inputsize, stride);
7002         if (!ok) {
7003             /* AArch64 reports these as level 0 faults.
7004              * AArch32 reports these as level 1 faults.
7005              */
7006             level = va_size == 64 ? 0 : 1;
7007             fault_type = translation_fault;
7008             goto do_fault;
7009         }
7010     }
7011
7012     /* Clear the vaddr bits which aren't part of the within-region address,
7013      * so that we don't have to special case things when calculating the
7014      * first descriptor address.
7015      */
7016     if (va_size != inputsize) {
7017         address &= (1ULL << inputsize) - 1;
7018     }
7019
7020     descmask = (1ULL << (stride + 3)) - 1;
7021
7022     /* Now we can extract the actual base address from the TTBR */
7023     descaddr = extract64(ttbr, 0, 48);
7024     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
7025
7026     /* The address field in the descriptor goes up to bit 39 for ARMv7
7027      * but up to bit 47 for ARMv8.
7028      */
7029     if (arm_feature(env, ARM_FEATURE_V8)) {
7030         descaddrmask = 0xfffffffff000ULL;
7031     } else {
7032         descaddrmask = 0xfffffff000ULL;
7033     }
7034
7035     /* Secure accesses start with the page table in secure memory and
7036      * can be downgraded to non-secure at any step. Non-secure accesses
7037      * remain non-secure. We implement this by just ORing in the NSTable/NS
7038      * bits at each step.
7039      */
7040     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7041     for (;;) {
7042         uint64_t descriptor;
7043         bool nstable;
7044
7045         descaddr |= (address >> (stride * (4 - level))) & descmask;
7046         descaddr &= ~7ULL;
7047         nstable = extract32(tableattrs, 4, 1);
7048         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7049         if (fi->s1ptw) {
7050             goto do_fault;
7051         }
7052
7053         if (!(descriptor & 1) ||
7054             (!(descriptor & 2) && (level == 3))) {
7055             /* Invalid, or the Reserved level 3 encoding */
7056             goto do_fault;
7057         }
7058         descaddr = descriptor & descaddrmask;
7059
7060         if ((descriptor & 2) && (level < 3)) {
7061             /* Table entry. The top five bits are attributes which  may
7062              * propagate down through lower levels of the table (and
7063              * which are all arranged so that 0 means "no effect", so
7064              * we can gather them up by ORing in the bits at each level).
7065              */
7066             tableattrs |= extract64(descriptor, 59, 5);
7067             level++;
7068             continue;
7069         }
7070         /* Block entry at level 1 or 2, or page entry at level 3.
7071          * These are basically the same thing, although the number
7072          * of bits we pull in from the vaddr varies.
7073          */
7074         page_size = (1ULL << ((stride * (4 - level)) + 3));
7075         descaddr |= (address & (page_size - 1));
7076         /* Extract attributes from the descriptor */
7077         attrs = extract64(descriptor, 2, 10)
7078             | (extract64(descriptor, 52, 12) << 10);
7079
7080         if (mmu_idx == ARMMMUIdx_S2NS) {
7081             /* Stage 2 table descriptors do not include any attribute fields */
7082             break;
7083         }
7084         /* Merge in attributes from table descriptors */
7085         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7086         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7087         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7088          * means "force PL1 access only", which means forcing AP[1] to 0.
7089          */
7090         if (extract32(tableattrs, 2, 1)) {
7091             attrs &= ~(1 << 4);
7092         }
7093         attrs |= nstable << 3; /* NS */
7094         break;
7095     }
7096     /* Here descaddr is the final physical address, and attributes
7097      * are all in attrs.
7098      */
7099     fault_type = access_fault;
7100     if ((attrs & (1 << 8)) == 0) {
7101         /* Access flag */
7102         goto do_fault;
7103     }
7104
7105     ap = extract32(attrs, 4, 2);
7106     xn = extract32(attrs, 12, 1);
7107
7108     if (mmu_idx == ARMMMUIdx_S2NS) {
7109         ns = true;
7110         *prot = get_S2prot(env, ap, xn);
7111     } else {
7112         ns = extract32(attrs, 3, 1);
7113         pxn = extract32(attrs, 11, 1);
7114         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7115     }
7116
7117     fault_type = permission_fault;
7118     if (!(*prot & (1 << access_type))) {
7119         goto do_fault;
7120     }
7121
7122     if (ns) {
7123         /* The NS bit will (as required by the architecture) have no effect if
7124          * the CPU doesn't support TZ or this is a non-secure translation
7125          * regime, because the attribute will already be non-secure.
7126          */
7127         txattrs->secure = false;
7128     }
7129     *phys_ptr = descaddr;
7130     *page_size_ptr = page_size;
7131     return false;
7132
7133 do_fault:
7134     /* Long-descriptor format IFSR/DFSR value */
7135     *fsr = (1 << 9) | (fault_type << 2) | level;
7136     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7137     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7138     return true;
7139 }
7140
7141 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7142                                                 ARMMMUIdx mmu_idx,
7143                                                 int32_t address, int *prot)
7144 {
7145     *prot = PAGE_READ | PAGE_WRITE;
7146     switch (address) {
7147     case 0xF0000000 ... 0xFFFFFFFF:
7148         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7149             *prot |= PAGE_EXEC;
7150         }
7151         break;
7152     case 0x00000000 ... 0x7FFFFFFF:
7153         *prot |= PAGE_EXEC;
7154         break;
7155     }
7156
7157 }
7158
7159 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7160                                  int access_type, ARMMMUIdx mmu_idx,
7161                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7162 {
7163     ARMCPU *cpu = arm_env_get_cpu(env);
7164     int n;
7165     bool is_user = regime_is_user(env, mmu_idx);
7166
7167     *phys_ptr = address;
7168     *prot = 0;
7169
7170     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7171         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7172     } else { /* MPU enabled */
7173         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7174             /* region search */
7175             uint32_t base = env->pmsav7.drbar[n];
7176             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7177             uint32_t rmask;
7178             bool srdis = false;
7179
7180             if (!(env->pmsav7.drsr[n] & 0x1)) {
7181                 continue;
7182             }
7183
7184             if (!rsize) {
7185                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7186                 continue;
7187             }
7188             rsize++;
7189             rmask = (1ull << rsize) - 1;
7190
7191             if (base & rmask) {
7192                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7193                               "to DRSR region size, mask = %" PRIx32,
7194                               base, rmask);
7195                 continue;
7196             }
7197
7198             if (address < base || address > base + rmask) {
7199                 continue;
7200             }
7201
7202             /* Region matched */
7203
7204             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7205                 int i, snd;
7206                 uint32_t srdis_mask;
7207
7208                 rsize -= 3; /* sub region size (power of 2) */
7209                 snd = ((address - base) >> rsize) & 0x7;
7210                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7211
7212                 srdis_mask = srdis ? 0x3 : 0x0;
7213                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7214                     /* This will check in groups of 2, 4 and then 8, whether
7215                      * the subregion bits are consistent. rsize is incremented
7216                      * back up to give the region size, considering consistent
7217                      * adjacent subregions as one region. Stop testing if rsize
7218                      * is already big enough for an entire QEMU page.
7219                      */
7220                     int snd_rounded = snd & ~(i - 1);
7221                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7222                                                      snd_rounded + 8, i);
7223                     if (srdis_mask ^ srdis_multi) {
7224                         break;
7225                     }
7226                     srdis_mask = (srdis_mask << i) | srdis_mask;
7227                     rsize++;
7228                 }
7229             }
7230             if (rsize < TARGET_PAGE_BITS) {
7231                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7232                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7233                               rsize, TARGET_PAGE_BITS);
7234                 continue;
7235             }
7236             if (srdis) {
7237                 continue;
7238             }
7239             break;
7240         }
7241
7242         if (n == -1) { /* no hits */
7243             if (cpu->pmsav7_dregion &&
7244                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7245                 /* background fault */
7246                 *fsr = 0;
7247                 return true;
7248             }
7249             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7250         } else { /* a MPU hit! */
7251             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7252
7253             if (is_user) { /* User mode AP bit decoding */
7254                 switch (ap) {
7255                 case 0:
7256                 case 1:
7257                 case 5:
7258                     break; /* no access */
7259                 case 3:
7260                     *prot |= PAGE_WRITE;
7261                     /* fall through */
7262                 case 2:
7263                 case 6:
7264                     *prot |= PAGE_READ | PAGE_EXEC;
7265                     break;
7266                 default:
7267                     qemu_log_mask(LOG_GUEST_ERROR,
7268                                   "Bad value for AP bits in DRACR %"
7269                                   PRIx32 "\n", ap);
7270                 }
7271             } else { /* Priv. mode AP bits decoding */
7272                 switch (ap) {
7273                 case 0:
7274                     break; /* no access */
7275                 case 1:
7276                 case 2:
7277                 case 3:
7278                     *prot |= PAGE_WRITE;
7279                     /* fall through */
7280                 case 5:
7281                 case 6:
7282                     *prot |= PAGE_READ | PAGE_EXEC;
7283                     break;
7284                 default:
7285                     qemu_log_mask(LOG_GUEST_ERROR,
7286                                   "Bad value for AP bits in DRACR %"
7287                                   PRIx32 "\n", ap);
7288                 }
7289             }
7290
7291             /* execute never */
7292             if (env->pmsav7.dracr[n] & (1 << 12)) {
7293                 *prot &= ~PAGE_EXEC;
7294             }
7295         }
7296     }
7297
7298     *fsr = 0x00d; /* Permission fault */
7299     return !(*prot & (1 << access_type));
7300 }
7301
7302 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7303                                  int access_type, ARMMMUIdx mmu_idx,
7304                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7305 {
7306     int n;
7307     uint32_t mask;
7308     uint32_t base;
7309     bool is_user = regime_is_user(env, mmu_idx);
7310
7311     *phys_ptr = address;
7312     for (n = 7; n >= 0; n--) {
7313         base = env->cp15.c6_region[n];
7314         if ((base & 1) == 0) {
7315             continue;
7316         }
7317         mask = 1 << ((base >> 1) & 0x1f);
7318         /* Keep this shift separate from the above to avoid an
7319            (undefined) << 32.  */
7320         mask = (mask << 1) - 1;
7321         if (((base ^ address) & ~mask) == 0) {
7322             break;
7323         }
7324     }
7325     if (n < 0) {
7326         *fsr = 2;
7327         return true;
7328     }
7329
7330     if (access_type == 2) {
7331         mask = env->cp15.pmsav5_insn_ap;
7332     } else {
7333         mask = env->cp15.pmsav5_data_ap;
7334     }
7335     mask = (mask >> (n * 4)) & 0xf;
7336     switch (mask) {
7337     case 0:
7338         *fsr = 1;
7339         return true;
7340     case 1:
7341         if (is_user) {
7342             *fsr = 1;
7343             return true;
7344         }
7345         *prot = PAGE_READ | PAGE_WRITE;
7346         break;
7347     case 2:
7348         *prot = PAGE_READ;
7349         if (!is_user) {
7350             *prot |= PAGE_WRITE;
7351         }
7352         break;
7353     case 3:
7354         *prot = PAGE_READ | PAGE_WRITE;
7355         break;
7356     case 5:
7357         if (is_user) {
7358             *fsr = 1;
7359             return true;
7360         }
7361         *prot = PAGE_READ;
7362         break;
7363     case 6:
7364         *prot = PAGE_READ;
7365         break;
7366     default:
7367         /* Bad permission.  */
7368         *fsr = 1;
7369         return true;
7370     }
7371     *prot |= PAGE_EXEC;
7372     return false;
7373 }
7374
7375 /* get_phys_addr - get the physical address for this virtual address
7376  *
7377  * Find the physical address corresponding to the given virtual address,
7378  * by doing a translation table walk on MMU based systems or using the
7379  * MPU state on MPU based systems.
7380  *
7381  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7382  * prot and page_size may not be filled in, and the populated fsr value provides
7383  * information on why the translation aborted, in the format of a
7384  * DFSR/IFSR fault register, with the following caveats:
7385  *  * we honour the short vs long DFSR format differences.
7386  *  * the WnR bit is never set (the caller must do this).
7387  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7388  *    value.
7389  *
7390  * @env: CPUARMState
7391  * @address: virtual address to get physical address for
7392  * @access_type: 0 for read, 1 for write, 2 for execute
7393  * @mmu_idx: MMU index indicating required translation regime
7394  * @phys_ptr: set to the physical address corresponding to the virtual address
7395  * @attrs: set to the memory transaction attributes to use
7396  * @prot: set to the permissions for the page containing phys_ptr
7397  * @page_size: set to the size of the page containing phys_ptr
7398  * @fsr: set to the DFSR/IFSR value on failure
7399  */
7400 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7401                           int access_type, ARMMMUIdx mmu_idx,
7402                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7403                           target_ulong *page_size, uint32_t *fsr,
7404                           ARMMMUFaultInfo *fi)
7405 {
7406     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7407         /* Call ourselves recursively to do the stage 1 and then stage 2
7408          * translations.
7409          */
7410         if (arm_feature(env, ARM_FEATURE_EL2)) {
7411             hwaddr ipa;
7412             int s2_prot;
7413             int ret;
7414
7415             ret = get_phys_addr(env, address, access_type,
7416                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7417                                 prot, page_size, fsr, fi);
7418
7419             /* If S1 fails or S2 is disabled, return early.  */
7420             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7421                 *phys_ptr = ipa;
7422                 return ret;
7423             }
7424
7425             /* S1 is done. Now do S2 translation.  */
7426             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7427                                      phys_ptr, attrs, &s2_prot,
7428                                      page_size, fsr, fi);
7429             fi->s2addr = ipa;
7430             /* Combine the S1 and S2 perms.  */
7431             *prot &= s2_prot;
7432             return ret;
7433         } else {
7434             /*
7435              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7436              */
7437             mmu_idx += ARMMMUIdx_S1NSE0;
7438         }
7439     }
7440
7441     /* The page table entries may downgrade secure to non-secure, but
7442      * cannot upgrade an non-secure translation regime's attributes
7443      * to secure.
7444      */
7445     attrs->secure = regime_is_secure(env, mmu_idx);
7446     attrs->user = regime_is_user(env, mmu_idx);
7447
7448     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7449      * In v7 and earlier it affects all stage 1 translations.
7450      */
7451     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7452         && !arm_feature(env, ARM_FEATURE_V8)) {
7453         if (regime_el(env, mmu_idx) == 3) {
7454             address += env->cp15.fcseidr_s;
7455         } else {
7456             address += env->cp15.fcseidr_ns;
7457         }
7458     }
7459
7460     /* pmsav7 has special handling for when MPU is disabled so call it before
7461      * the common MMU/MPU disabled check below.
7462      */
7463     if (arm_feature(env, ARM_FEATURE_MPU) &&
7464         arm_feature(env, ARM_FEATURE_V7)) {
7465         *page_size = TARGET_PAGE_SIZE;
7466         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7467                                     phys_ptr, prot, fsr);
7468     }
7469
7470     if (regime_translation_disabled(env, mmu_idx)) {
7471         /* MMU/MPU disabled.  */
7472         *phys_ptr = address;
7473         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7474         *page_size = TARGET_PAGE_SIZE;
7475         return 0;
7476     }
7477
7478     if (arm_feature(env, ARM_FEATURE_MPU)) {
7479         /* Pre-v7 MPU */
7480         *page_size = TARGET_PAGE_SIZE;
7481         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7482                                     phys_ptr, prot, fsr);
7483     }
7484
7485     if (regime_using_lpae_format(env, mmu_idx)) {
7486         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7487                                   attrs, prot, page_size, fsr, fi);
7488     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7489         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7490                                 attrs, prot, page_size, fsr, fi);
7491     } else {
7492         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7493                                 prot, page_size, fsr, fi);
7494     }
7495 }
7496
7497 /* Walk the page table and (if the mapping exists) add the page
7498  * to the TLB. Return false on success, or true on failure. Populate
7499  * fsr with ARM DFSR/IFSR fault register format value on failure.
7500  */
7501 bool arm_tlb_fill(CPUState *cs, vaddr address,
7502                   int access_type, int mmu_idx, uint32_t *fsr,
7503                   ARMMMUFaultInfo *fi)
7504 {
7505     ARMCPU *cpu = ARM_CPU(cs);
7506     CPUARMState *env = &cpu->env;
7507     hwaddr phys_addr;
7508     target_ulong page_size;
7509     int prot;
7510     int ret;
7511     MemTxAttrs attrs = {};
7512
7513     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7514                         &attrs, &prot, &page_size, fsr, fi);
7515     if (!ret) {
7516         /* Map a single [sub]page.  */
7517         phys_addr &= TARGET_PAGE_MASK;
7518         address &= TARGET_PAGE_MASK;
7519         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7520                                 prot, mmu_idx, page_size);
7521         return 0;
7522     }
7523
7524     return ret;
7525 }
7526
7527 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7528                                          MemTxAttrs *attrs)
7529 {
7530     ARMCPU *cpu = ARM_CPU(cs);
7531     CPUARMState *env = &cpu->env;
7532     hwaddr phys_addr;
7533     target_ulong page_size;
7534     int prot;
7535     bool ret;
7536     uint32_t fsr;
7537     ARMMMUFaultInfo fi = {};
7538
7539     *attrs = (MemTxAttrs) {};
7540
7541     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7542                         attrs, &prot, &page_size, &fsr, &fi);
7543
7544     if (ret) {
7545         return -1;
7546     }
7547     return phys_addr;
7548 }
7549
7550 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
7551 {
7552     if ((env->uncached_cpsr & CPSR_M) == mode) {
7553         env->regs[13] = val;
7554     } else {
7555         env->banked_r13[bank_number(mode)] = val;
7556     }
7557 }
7558
7559 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
7560 {
7561     if ((env->uncached_cpsr & CPSR_M) == mode) {
7562         return env->regs[13];
7563     } else {
7564         return env->banked_r13[bank_number(mode)];
7565     }
7566 }
7567
7568 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7569 {
7570     ARMCPU *cpu = arm_env_get_cpu(env);
7571
7572     switch (reg) {
7573     case 0: /* APSR */
7574         return xpsr_read(env) & 0xf8000000;
7575     case 1: /* IAPSR */
7576         return xpsr_read(env) & 0xf80001ff;
7577     case 2: /* EAPSR */
7578         return xpsr_read(env) & 0xff00fc00;
7579     case 3: /* xPSR */
7580         return xpsr_read(env) & 0xff00fdff;
7581     case 5: /* IPSR */
7582         return xpsr_read(env) & 0x000001ff;
7583     case 6: /* EPSR */
7584         return xpsr_read(env) & 0x0700fc00;
7585     case 7: /* IEPSR */
7586         return xpsr_read(env) & 0x0700edff;
7587     case 8: /* MSP */
7588         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7589     case 9: /* PSP */
7590         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7591     case 16: /* PRIMASK */
7592         return (env->daif & PSTATE_I) != 0;
7593     case 17: /* BASEPRI */
7594     case 18: /* BASEPRI_MAX */
7595         return env->v7m.basepri;
7596     case 19: /* FAULTMASK */
7597         return (env->daif & PSTATE_F) != 0;
7598     case 20: /* CONTROL */
7599         return env->v7m.control;
7600     default:
7601         /* ??? For debugging only.  */
7602         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
7603         return 0;
7604     }
7605 }
7606
7607 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
7608 {
7609     ARMCPU *cpu = arm_env_get_cpu(env);
7610
7611     switch (reg) {
7612     case 0: /* APSR */
7613         xpsr_write(env, val, 0xf8000000);
7614         break;
7615     case 1: /* IAPSR */
7616         xpsr_write(env, val, 0xf8000000);
7617         break;
7618     case 2: /* EAPSR */
7619         xpsr_write(env, val, 0xfe00fc00);
7620         break;
7621     case 3: /* xPSR */
7622         xpsr_write(env, val, 0xfe00fc00);
7623         break;
7624     case 5: /* IPSR */
7625         /* IPSR bits are readonly.  */
7626         break;
7627     case 6: /* EPSR */
7628         xpsr_write(env, val, 0x0600fc00);
7629         break;
7630     case 7: /* IEPSR */
7631         xpsr_write(env, val, 0x0600fc00);
7632         break;
7633     case 8: /* MSP */
7634         if (env->v7m.current_sp)
7635             env->v7m.other_sp = val;
7636         else
7637             env->regs[13] = val;
7638         break;
7639     case 9: /* PSP */
7640         if (env->v7m.current_sp)
7641             env->regs[13] = val;
7642         else
7643             env->v7m.other_sp = val;
7644         break;
7645     case 16: /* PRIMASK */
7646         if (val & 1) {
7647             env->daif |= PSTATE_I;
7648         } else {
7649             env->daif &= ~PSTATE_I;
7650         }
7651         break;
7652     case 17: /* BASEPRI */
7653         env->v7m.basepri = val & 0xff;
7654         break;
7655     case 18: /* BASEPRI_MAX */
7656         val &= 0xff;
7657         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
7658             env->v7m.basepri = val;
7659         break;
7660     case 19: /* FAULTMASK */
7661         if (val & 1) {
7662             env->daif |= PSTATE_F;
7663         } else {
7664             env->daif &= ~PSTATE_F;
7665         }
7666         break;
7667     case 20: /* CONTROL */
7668         env->v7m.control = val & 3;
7669         switch_v7m_sp(env, (val & 2) != 0);
7670         break;
7671     default:
7672         /* ??? For debugging only.  */
7673         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7674         return;
7675     }
7676 }
7677
7678 #endif
7679
7680 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7681 {
7682     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7683      * Note that we do not implement the (architecturally mandated)
7684      * alignment fault for attempts to use this on Device memory
7685      * (which matches the usual QEMU behaviour of not implementing either
7686      * alignment faults or any memory attribute handling).
7687      */
7688
7689     ARMCPU *cpu = arm_env_get_cpu(env);
7690     uint64_t blocklen = 4 << cpu->dcz_blocksize;
7691     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7692
7693 #ifndef CONFIG_USER_ONLY
7694     {
7695         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7696          * the block size so we might have to do more than one TLB lookup.
7697          * We know that in fact for any v8 CPU the page size is at least 4K
7698          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7699          * 1K as an artefact of legacy v5 subpage support being present in the
7700          * same QEMU executable.
7701          */
7702         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7703         void *hostaddr[maxidx];
7704         int try, i;
7705         unsigned mmu_idx = cpu_mmu_index(env, false);
7706         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7707
7708         for (try = 0; try < 2; try++) {
7709
7710             for (i = 0; i < maxidx; i++) {
7711                 hostaddr[i] = tlb_vaddr_to_host(env,
7712                                                 vaddr + TARGET_PAGE_SIZE * i,
7713                                                 1, mmu_idx);
7714                 if (!hostaddr[i]) {
7715                     break;
7716                 }
7717             }
7718             if (i == maxidx) {
7719                 /* If it's all in the TLB it's fair game for just writing to;
7720                  * we know we don't need to update dirty status, etc.
7721                  */
7722                 for (i = 0; i < maxidx - 1; i++) {
7723                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7724                 }
7725                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7726                 return;
7727             }
7728             /* OK, try a store and see if we can populate the tlb. This
7729              * might cause an exception if the memory isn't writable,
7730              * in which case we will longjmp out of here. We must for
7731              * this purpose use the actual register value passed to us
7732              * so that we get the fault address right.
7733              */
7734             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7735             /* Now we can populate the other TLB entries, if any */
7736             for (i = 0; i < maxidx; i++) {
7737                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7738                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7739                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7740                 }
7741             }
7742         }
7743
7744         /* Slow path (probably attempt to do this to an I/O device or
7745          * similar, or clearing of a block of code we have translations
7746          * cached for). Just do a series of byte writes as the architecture
7747          * demands. It's not worth trying to use a cpu_physical_memory_map(),
7748          * memset(), unmap() sequence here because:
7749          *  + we'd need to account for the blocksize being larger than a page
7750          *  + the direct-RAM access case is almost always going to be dealt
7751          *    with in the fastpath code above, so there's no speed benefit
7752          *  + we would have to deal with the map returning NULL because the
7753          *    bounce buffer was in use
7754          */
7755         for (i = 0; i < blocklen; i++) {
7756             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7757         }
7758     }
7759 #else
7760     memset(g2h(vaddr), 0, blocklen);
7761 #endif
7762 }
7763
7764 /* Note that signed overflow is undefined in C.  The following routines are
7765    careful to use unsigned types where modulo arithmetic is required.
7766    Failure to do so _will_ break on newer gcc.  */
7767
7768 /* Signed saturating arithmetic.  */
7769
7770 /* Perform 16-bit signed saturating addition.  */
7771 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7772 {
7773     uint16_t res;
7774
7775     res = a + b;
7776     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7777         if (a & 0x8000)
7778             res = 0x8000;
7779         else
7780             res = 0x7fff;
7781     }
7782     return res;
7783 }
7784
7785 /* Perform 8-bit signed saturating addition.  */
7786 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7787 {
7788     uint8_t res;
7789
7790     res = a + b;
7791     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7792         if (a & 0x80)
7793             res = 0x80;
7794         else
7795             res = 0x7f;
7796     }
7797     return res;
7798 }
7799
7800 /* Perform 16-bit signed saturating subtraction.  */
7801 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7802 {
7803     uint16_t res;
7804
7805     res = a - b;
7806     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7807         if (a & 0x8000)
7808             res = 0x8000;
7809         else
7810             res = 0x7fff;
7811     }
7812     return res;
7813 }
7814
7815 /* Perform 8-bit signed saturating subtraction.  */
7816 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7817 {
7818     uint8_t res;
7819
7820     res = a - b;
7821     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7822         if (a & 0x80)
7823             res = 0x80;
7824         else
7825             res = 0x7f;
7826     }
7827     return res;
7828 }
7829
7830 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7831 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7832 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
7833 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
7834 #define PFX q
7835
7836 #include "op_addsub.h"
7837
7838 /* Unsigned saturating arithmetic.  */
7839 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7840 {
7841     uint16_t res;
7842     res = a + b;
7843     if (res < a)
7844         res = 0xffff;
7845     return res;
7846 }
7847
7848 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7849 {
7850     if (a > b)
7851         return a - b;
7852     else
7853         return 0;
7854 }
7855
7856 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7857 {
7858     uint8_t res;
7859     res = a + b;
7860     if (res < a)
7861         res = 0xff;
7862     return res;
7863 }
7864
7865 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7866 {
7867     if (a > b)
7868         return a - b;
7869     else
7870         return 0;
7871 }
7872
7873 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7874 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7875 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
7876 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
7877 #define PFX uq
7878
7879 #include "op_addsub.h"
7880
7881 /* Signed modulo arithmetic.  */
7882 #define SARITH16(a, b, n, op) do { \
7883     int32_t sum; \
7884     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7885     RESULT(sum, n, 16); \
7886     if (sum >= 0) \
7887         ge |= 3 << (n * 2); \
7888     } while(0)
7889
7890 #define SARITH8(a, b, n, op) do { \
7891     int32_t sum; \
7892     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7893     RESULT(sum, n, 8); \
7894     if (sum >= 0) \
7895         ge |= 1 << n; \
7896     } while(0)
7897
7898
7899 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7900 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7901 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
7902 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
7903 #define PFX s
7904 #define ARITH_GE
7905
7906 #include "op_addsub.h"
7907
7908 /* Unsigned modulo arithmetic.  */
7909 #define ADD16(a, b, n) do { \
7910     uint32_t sum; \
7911     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7912     RESULT(sum, n, 16); \
7913     if ((sum >> 16) == 1) \
7914         ge |= 3 << (n * 2); \
7915     } while(0)
7916
7917 #define ADD8(a, b, n) do { \
7918     uint32_t sum; \
7919     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7920     RESULT(sum, n, 8); \
7921     if ((sum >> 8) == 1) \
7922         ge |= 1 << n; \
7923     } while(0)
7924
7925 #define SUB16(a, b, n) do { \
7926     uint32_t sum; \
7927     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7928     RESULT(sum, n, 16); \
7929     if ((sum >> 16) == 0) \
7930         ge |= 3 << (n * 2); \
7931     } while(0)
7932
7933 #define SUB8(a, b, n) do { \
7934     uint32_t sum; \
7935     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7936     RESULT(sum, n, 8); \
7937     if ((sum >> 8) == 0) \
7938         ge |= 1 << n; \
7939     } while(0)
7940
7941 #define PFX u
7942 #define ARITH_GE
7943
7944 #include "op_addsub.h"
7945
7946 /* Halved signed arithmetic.  */
7947 #define ADD16(a, b, n) \
7948   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7949 #define SUB16(a, b, n) \
7950   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7951 #define ADD8(a, b, n) \
7952   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7953 #define SUB8(a, b, n) \
7954   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7955 #define PFX sh
7956
7957 #include "op_addsub.h"
7958
7959 /* Halved unsigned arithmetic.  */
7960 #define ADD16(a, b, n) \
7961   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7962 #define SUB16(a, b, n) \
7963   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7964 #define ADD8(a, b, n) \
7965   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7966 #define SUB8(a, b, n) \
7967   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7968 #define PFX uh
7969
7970 #include "op_addsub.h"
7971
7972 static inline uint8_t do_usad(uint8_t a, uint8_t b)
7973 {
7974     if (a > b)
7975         return a - b;
7976     else
7977         return b - a;
7978 }
7979
7980 /* Unsigned sum of absolute byte differences.  */
7981 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
7982 {
7983     uint32_t sum;
7984     sum = do_usad(a, b);
7985     sum += do_usad(a >> 8, b >> 8);
7986     sum += do_usad(a >> 16, b >>16);
7987     sum += do_usad(a >> 24, b >> 24);
7988     return sum;
7989 }
7990
7991 /* For ARMv6 SEL instruction.  */
7992 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
7993 {
7994     uint32_t mask;
7995
7996     mask = 0;
7997     if (flags & 1)
7998         mask |= 0xff;
7999     if (flags & 2)
8000         mask |= 0xff00;
8001     if (flags & 4)
8002         mask |= 0xff0000;
8003     if (flags & 8)
8004         mask |= 0xff000000;
8005     return (a & mask) | (b & ~mask);
8006 }
8007
8008 /* VFP support.  We follow the convention used for VFP instructions:
8009    Single precision routines have a "s" suffix, double precision a
8010    "d" suffix.  */
8011
8012 /* Convert host exception flags to vfp form.  */
8013 static inline int vfp_exceptbits_from_host(int host_bits)
8014 {
8015     int target_bits = 0;
8016
8017     if (host_bits & float_flag_invalid)
8018         target_bits |= 1;
8019     if (host_bits & float_flag_divbyzero)
8020         target_bits |= 2;
8021     if (host_bits & float_flag_overflow)
8022         target_bits |= 4;
8023     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8024         target_bits |= 8;
8025     if (host_bits & float_flag_inexact)
8026         target_bits |= 0x10;
8027     if (host_bits & float_flag_input_denormal)
8028         target_bits |= 0x80;
8029     return target_bits;
8030 }
8031
8032 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8033 {
8034     int i;
8035     uint32_t fpscr;
8036
8037     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8038             | (env->vfp.vec_len << 16)
8039             | (env->vfp.vec_stride << 20);
8040     i = get_float_exception_flags(&env->vfp.fp_status);
8041     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8042     fpscr |= vfp_exceptbits_from_host(i);
8043     return fpscr;
8044 }
8045
8046 uint32_t vfp_get_fpscr(CPUARMState *env)
8047 {
8048     return HELPER(vfp_get_fpscr)(env);
8049 }
8050
8051 /* Convert vfp exception flags to target form.  */
8052 static inline int vfp_exceptbits_to_host(int target_bits)
8053 {
8054     int host_bits = 0;
8055
8056     if (target_bits & 1)
8057         host_bits |= float_flag_invalid;
8058     if (target_bits & 2)
8059         host_bits |= float_flag_divbyzero;
8060     if (target_bits & 4)
8061         host_bits |= float_flag_overflow;
8062     if (target_bits & 8)
8063         host_bits |= float_flag_underflow;
8064     if (target_bits & 0x10)
8065         host_bits |= float_flag_inexact;
8066     if (target_bits & 0x80)
8067         host_bits |= float_flag_input_denormal;
8068     return host_bits;
8069 }
8070
8071 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8072 {
8073     int i;
8074     uint32_t changed;
8075
8076     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8077     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8078     env->vfp.vec_len = (val >> 16) & 7;
8079     env->vfp.vec_stride = (val >> 20) & 3;
8080
8081     changed ^= val;
8082     if (changed & (3 << 22)) {
8083         i = (val >> 22) & 3;
8084         switch (i) {
8085         case FPROUNDING_TIEEVEN:
8086             i = float_round_nearest_even;
8087             break;
8088         case FPROUNDING_POSINF:
8089             i = float_round_up;
8090             break;
8091         case FPROUNDING_NEGINF:
8092             i = float_round_down;
8093             break;
8094         case FPROUNDING_ZERO:
8095             i = float_round_to_zero;
8096             break;
8097         }
8098         set_float_rounding_mode(i, &env->vfp.fp_status);
8099     }
8100     if (changed & (1 << 24)) {
8101         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8102         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8103     }
8104     if (changed & (1 << 25))
8105         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8106
8107     i = vfp_exceptbits_to_host(val);
8108     set_float_exception_flags(i, &env->vfp.fp_status);
8109     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8110 }
8111
8112 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8113 {
8114     HELPER(vfp_set_fpscr)(env, val);
8115 }
8116
8117 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8118
8119 #define VFP_BINOP(name) \
8120 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8121 { \
8122     float_status *fpst = fpstp; \
8123     return float32_ ## name(a, b, fpst); \
8124 } \
8125 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8126 { \
8127     float_status *fpst = fpstp; \
8128     return float64_ ## name(a, b, fpst); \
8129 }
8130 VFP_BINOP(add)
8131 VFP_BINOP(sub)
8132 VFP_BINOP(mul)
8133 VFP_BINOP(div)
8134 VFP_BINOP(min)
8135 VFP_BINOP(max)
8136 VFP_BINOP(minnum)
8137 VFP_BINOP(maxnum)
8138 #undef VFP_BINOP
8139
8140 float32 VFP_HELPER(neg, s)(float32 a)
8141 {
8142     return float32_chs(a);
8143 }
8144
8145 float64 VFP_HELPER(neg, d)(float64 a)
8146 {
8147     return float64_chs(a);
8148 }
8149
8150 float32 VFP_HELPER(abs, s)(float32 a)
8151 {
8152     return float32_abs(a);
8153 }
8154
8155 float64 VFP_HELPER(abs, d)(float64 a)
8156 {
8157     return float64_abs(a);
8158 }
8159
8160 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8161 {
8162     return float32_sqrt(a, &env->vfp.fp_status);
8163 }
8164
8165 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8166 {
8167     return float64_sqrt(a, &env->vfp.fp_status);
8168 }
8169
8170 /* XXX: check quiet/signaling case */
8171 #define DO_VFP_cmp(p, type) \
8172 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8173 { \
8174     uint32_t flags; \
8175     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8176     case 0: flags = 0x6; break; \
8177     case -1: flags = 0x8; break; \
8178     case 1: flags = 0x2; break; \
8179     default: case 2: flags = 0x3; break; \
8180     } \
8181     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8182         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8183 } \
8184 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8185 { \
8186     uint32_t flags; \
8187     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8188     case 0: flags = 0x6; break; \
8189     case -1: flags = 0x8; break; \
8190     case 1: flags = 0x2; break; \
8191     default: case 2: flags = 0x3; break; \
8192     } \
8193     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8194         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8195 }
8196 DO_VFP_cmp(s, float32)
8197 DO_VFP_cmp(d, float64)
8198 #undef DO_VFP_cmp
8199
8200 /* Integer to float and float to integer conversions */
8201
8202 #define CONV_ITOF(name, fsz, sign) \
8203     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8204 { \
8205     float_status *fpst = fpstp; \
8206     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8207 }
8208
8209 #define CONV_FTOI(name, fsz, sign, round) \
8210 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8211 { \
8212     float_status *fpst = fpstp; \
8213     if (float##fsz##_is_any_nan(x)) { \
8214         float_raise(float_flag_invalid, fpst); \
8215         return 0; \
8216     } \
8217     return float##fsz##_to_##sign##int32##round(x, fpst); \
8218 }
8219
8220 #define FLOAT_CONVS(name, p, fsz, sign) \
8221 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8222 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8223 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8224
8225 FLOAT_CONVS(si, s, 32, )
8226 FLOAT_CONVS(si, d, 64, )
8227 FLOAT_CONVS(ui, s, 32, u)
8228 FLOAT_CONVS(ui, d, 64, u)
8229
8230 #undef CONV_ITOF
8231 #undef CONV_FTOI
8232 #undef FLOAT_CONVS
8233
8234 /* floating point conversion */
8235 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8236 {
8237     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8238     /* ARM requires that S<->D conversion of any kind of NaN generates
8239      * a quiet NaN by forcing the most significant frac bit to 1.
8240      */
8241     return float64_maybe_silence_nan(r);
8242 }
8243
8244 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8245 {
8246     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8247     /* ARM requires that S<->D conversion of any kind of NaN generates
8248      * a quiet NaN by forcing the most significant frac bit to 1.
8249      */
8250     return float32_maybe_silence_nan(r);
8251 }
8252
8253 /* VFP3 fixed point conversion.  */
8254 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8255 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8256                                      void *fpstp) \
8257 { \
8258     float_status *fpst = fpstp; \
8259     float##fsz tmp; \
8260     tmp = itype##_to_##float##fsz(x, fpst); \
8261     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8262 }
8263
8264 /* Notice that we want only input-denormal exception flags from the
8265  * scalbn operation: the other possible flags (overflow+inexact if
8266  * we overflow to infinity, output-denormal) aren't correct for the
8267  * complete scale-and-convert operation.
8268  */
8269 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8270 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8271                                              uint32_t shift, \
8272                                              void *fpstp) \
8273 { \
8274     float_status *fpst = fpstp; \
8275     int old_exc_flags = get_float_exception_flags(fpst); \
8276     float##fsz tmp; \
8277     if (float##fsz##_is_any_nan(x)) { \
8278         float_raise(float_flag_invalid, fpst); \
8279         return 0; \
8280     } \
8281     tmp = float##fsz##_scalbn(x, shift, fpst); \
8282     old_exc_flags |= get_float_exception_flags(fpst) \
8283         & float_flag_input_denormal; \
8284     set_float_exception_flags(old_exc_flags, fpst); \
8285     return float##fsz##_to_##itype##round(tmp, fpst); \
8286 }
8287
8288 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8289 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8290 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8291 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8292
8293 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8294 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8295 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8296
8297 VFP_CONV_FIX(sh, d, 64, 64, int16)
8298 VFP_CONV_FIX(sl, d, 64, 64, int32)
8299 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8300 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8301 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8302 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8303 VFP_CONV_FIX(sh, s, 32, 32, int16)
8304 VFP_CONV_FIX(sl, s, 32, 32, int32)
8305 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8306 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8307 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8308 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8309 #undef VFP_CONV_FIX
8310 #undef VFP_CONV_FIX_FLOAT
8311 #undef VFP_CONV_FLOAT_FIX_ROUND
8312
8313 /* Set the current fp rounding mode and return the old one.
8314  * The argument is a softfloat float_round_ value.
8315  */
8316 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8317 {
8318     float_status *fp_status = &env->vfp.fp_status;
8319
8320     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8321     set_float_rounding_mode(rmode, fp_status);
8322
8323     return prev_rmode;
8324 }
8325
8326 /* Set the current fp rounding mode in the standard fp status and return
8327  * the old one. This is for NEON instructions that need to change the
8328  * rounding mode but wish to use the standard FPSCR values for everything
8329  * else. Always set the rounding mode back to the correct value after
8330  * modifying it.
8331  * The argument is a softfloat float_round_ value.
8332  */
8333 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8334 {
8335     float_status *fp_status = &env->vfp.standard_fp_status;
8336
8337     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8338     set_float_rounding_mode(rmode, fp_status);
8339
8340     return prev_rmode;
8341 }
8342
8343 /* Half precision conversions.  */
8344 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8345 {
8346     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8347     float32 r = float16_to_float32(make_float16(a), ieee, s);
8348     if (ieee) {
8349         return float32_maybe_silence_nan(r);
8350     }
8351     return r;
8352 }
8353
8354 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8355 {
8356     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8357     float16 r = float32_to_float16(a, ieee, s);
8358     if (ieee) {
8359         r = float16_maybe_silence_nan(r);
8360     }
8361     return float16_val(r);
8362 }
8363
8364 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8365 {
8366     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8367 }
8368
8369 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8370 {
8371     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8372 }
8373
8374 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8375 {
8376     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8377 }
8378
8379 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8380 {
8381     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8382 }
8383
8384 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8385 {
8386     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8387     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8388     if (ieee) {
8389         return float64_maybe_silence_nan(r);
8390     }
8391     return r;
8392 }
8393
8394 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8395 {
8396     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8397     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8398     if (ieee) {
8399         r = float16_maybe_silence_nan(r);
8400     }
8401     return float16_val(r);
8402 }
8403
8404 #define float32_two make_float32(0x40000000)
8405 #define float32_three make_float32(0x40400000)
8406 #define float32_one_point_five make_float32(0x3fc00000)
8407
8408 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8409 {
8410     float_status *s = &env->vfp.standard_fp_status;
8411     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8412         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8413         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8414             float_raise(float_flag_input_denormal, s);
8415         }
8416         return float32_two;
8417     }
8418     return float32_sub(float32_two, float32_mul(a, b, s), s);
8419 }
8420
8421 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8422 {
8423     float_status *s = &env->vfp.standard_fp_status;
8424     float32 product;
8425     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8426         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8427         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8428             float_raise(float_flag_input_denormal, s);
8429         }
8430         return float32_one_point_five;
8431     }
8432     product = float32_mul(a, b, s);
8433     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8434 }
8435
8436 /* NEON helpers.  */
8437
8438 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8439  * int->float conversions at run-time.  */
8440 #define float64_256 make_float64(0x4070000000000000LL)
8441 #define float64_512 make_float64(0x4080000000000000LL)
8442 #define float32_maxnorm make_float32(0x7f7fffff)
8443 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8444
8445 /* Reciprocal functions
8446  *
8447  * The algorithm that must be used to calculate the estimate
8448  * is specified by the ARM ARM, see FPRecipEstimate()
8449  */
8450
8451 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8452 {
8453     /* These calculations mustn't set any fp exception flags,
8454      * so we use a local copy of the fp_status.
8455      */
8456     float_status dummy_status = *real_fp_status;
8457     float_status *s = &dummy_status;
8458     /* q = (int)(a * 512.0) */
8459     float64 q = float64_mul(float64_512, a, s);
8460     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8461
8462     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8463     q = int64_to_float64(q_int, s);
8464     q = float64_add(q, float64_half, s);
8465     q = float64_div(q, float64_512, s);
8466     q = float64_div(float64_one, q, s);
8467
8468     /* s = (int)(256.0 * r + 0.5) */
8469     q = float64_mul(q, float64_256, s);
8470     q = float64_add(q, float64_half, s);
8471     q_int = float64_to_int64_round_to_zero(q, s);
8472
8473     /* return (double)s / 256.0 */
8474     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8475 }
8476
8477 /* Common wrapper to call recip_estimate */
8478 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8479 {
8480     uint64_t val64 = float64_val(num);
8481     uint64_t frac = extract64(val64, 0, 52);
8482     int64_t exp = extract64(val64, 52, 11);
8483     uint64_t sbit;
8484     float64 scaled, estimate;
8485
8486     /* Generate the scaled number for the estimate function */
8487     if (exp == 0) {
8488         if (extract64(frac, 51, 1) == 0) {
8489             exp = -1;
8490             frac = extract64(frac, 0, 50) << 2;
8491         } else {
8492             frac = extract64(frac, 0, 51) << 1;
8493         }
8494     }
8495
8496     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8497     scaled = make_float64((0x3feULL << 52)
8498                           | extract64(frac, 44, 8) << 44);
8499
8500     estimate = recip_estimate(scaled, fpst);
8501
8502     /* Build new result */
8503     val64 = float64_val(estimate);
8504     sbit = 0x8000000000000000ULL & val64;
8505     exp = off - exp;
8506     frac = extract64(val64, 0, 52);
8507
8508     if (exp == 0) {
8509         frac = 1ULL << 51 | extract64(frac, 1, 51);
8510     } else if (exp == -1) {
8511         frac = 1ULL << 50 | extract64(frac, 2, 50);
8512         exp = 0;
8513     }
8514
8515     return make_float64(sbit | (exp << 52) | frac);
8516 }
8517
8518 static bool round_to_inf(float_status *fpst, bool sign_bit)
8519 {
8520     switch (fpst->float_rounding_mode) {
8521     case float_round_nearest_even: /* Round to Nearest */
8522         return true;
8523     case float_round_up: /* Round to +Inf */
8524         return !sign_bit;
8525     case float_round_down: /* Round to -Inf */
8526         return sign_bit;
8527     case float_round_to_zero: /* Round to Zero */
8528         return false;
8529     }
8530
8531     g_assert_not_reached();
8532 }
8533
8534 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8535 {
8536     float_status *fpst = fpstp;
8537     float32 f32 = float32_squash_input_denormal(input, fpst);
8538     uint32_t f32_val = float32_val(f32);
8539     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8540     int32_t f32_exp = extract32(f32_val, 23, 8);
8541     uint32_t f32_frac = extract32(f32_val, 0, 23);
8542     float64 f64, r64;
8543     uint64_t r64_val;
8544     int64_t r64_exp;
8545     uint64_t r64_frac;
8546
8547     if (float32_is_any_nan(f32)) {
8548         float32 nan = f32;
8549         if (float32_is_signaling_nan(f32)) {
8550             float_raise(float_flag_invalid, fpst);
8551             nan = float32_maybe_silence_nan(f32);
8552         }
8553         if (fpst->default_nan_mode) {
8554             nan =  float32_default_nan;
8555         }
8556         return nan;
8557     } else if (float32_is_infinity(f32)) {
8558         return float32_set_sign(float32_zero, float32_is_neg(f32));
8559     } else if (float32_is_zero(f32)) {
8560         float_raise(float_flag_divbyzero, fpst);
8561         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8562     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8563         /* Abs(value) < 2.0^-128 */
8564         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8565         if (round_to_inf(fpst, f32_sbit)) {
8566             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8567         } else {
8568             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8569         }
8570     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8571         float_raise(float_flag_underflow, fpst);
8572         return float32_set_sign(float32_zero, float32_is_neg(f32));
8573     }
8574
8575
8576     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8577     r64 = call_recip_estimate(f64, 253, fpst);
8578     r64_val = float64_val(r64);
8579     r64_exp = extract64(r64_val, 52, 11);
8580     r64_frac = extract64(r64_val, 0, 52);
8581
8582     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8583     return make_float32(f32_sbit |
8584                         (r64_exp & 0xff) << 23 |
8585                         extract64(r64_frac, 29, 24));
8586 }
8587
8588 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8589 {
8590     float_status *fpst = fpstp;
8591     float64 f64 = float64_squash_input_denormal(input, fpst);
8592     uint64_t f64_val = float64_val(f64);
8593     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
8594     int64_t f64_exp = extract64(f64_val, 52, 11);
8595     float64 r64;
8596     uint64_t r64_val;
8597     int64_t r64_exp;
8598     uint64_t r64_frac;
8599
8600     /* Deal with any special cases */
8601     if (float64_is_any_nan(f64)) {
8602         float64 nan = f64;
8603         if (float64_is_signaling_nan(f64)) {
8604             float_raise(float_flag_invalid, fpst);
8605             nan = float64_maybe_silence_nan(f64);
8606         }
8607         if (fpst->default_nan_mode) {
8608             nan =  float64_default_nan;
8609         }
8610         return nan;
8611     } else if (float64_is_infinity(f64)) {
8612         return float64_set_sign(float64_zero, float64_is_neg(f64));
8613     } else if (float64_is_zero(f64)) {
8614         float_raise(float_flag_divbyzero, fpst);
8615         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8616     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
8617         /* Abs(value) < 2.0^-1024 */
8618         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8619         if (round_to_inf(fpst, f64_sbit)) {
8620             return float64_set_sign(float64_infinity, float64_is_neg(f64));
8621         } else {
8622             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
8623         }
8624     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
8625         float_raise(float_flag_underflow, fpst);
8626         return float64_set_sign(float64_zero, float64_is_neg(f64));
8627     }
8628
8629     r64 = call_recip_estimate(f64, 2045, fpst);
8630     r64_val = float64_val(r64);
8631     r64_exp = extract64(r64_val, 52, 11);
8632     r64_frac = extract64(r64_val, 0, 52);
8633
8634     /* result = sign : result_exp<10:0> : fraction<51:0> */
8635     return make_float64(f64_sbit |
8636                         ((r64_exp & 0x7ff) << 52) |
8637                         r64_frac);
8638 }
8639
8640 /* The algorithm that must be used to calculate the estimate
8641  * is specified by the ARM ARM.
8642  */
8643 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
8644 {
8645     /* These calculations mustn't set any fp exception flags,
8646      * so we use a local copy of the fp_status.
8647      */
8648     float_status dummy_status = *real_fp_status;
8649     float_status *s = &dummy_status;
8650     float64 q;
8651     int64_t q_int;
8652
8653     if (float64_lt(a, float64_half, s)) {
8654         /* range 0.25 <= a < 0.5 */
8655
8656         /* a in units of 1/512 rounded down */
8657         /* q0 = (int)(a * 512.0);  */
8658         q = float64_mul(float64_512, a, s);
8659         q_int = float64_to_int64_round_to_zero(q, s);
8660
8661         /* reciprocal root r */
8662         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
8663         q = int64_to_float64(q_int, s);
8664         q = float64_add(q, float64_half, s);
8665         q = float64_div(q, float64_512, s);
8666         q = float64_sqrt(q, s);
8667         q = float64_div(float64_one, q, s);
8668     } else {
8669         /* range 0.5 <= a < 1.0 */
8670
8671         /* a in units of 1/256 rounded down */
8672         /* q1 = (int)(a * 256.0); */
8673         q = float64_mul(float64_256, a, s);
8674         int64_t q_int = float64_to_int64_round_to_zero(q, s);
8675
8676         /* reciprocal root r */
8677         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8678         q = int64_to_float64(q_int, s);
8679         q = float64_add(q, float64_half, s);
8680         q = float64_div(q, float64_256, s);
8681         q = float64_sqrt(q, s);
8682         q = float64_div(float64_one, q, s);
8683     }
8684     /* r in units of 1/256 rounded to nearest */
8685     /* s = (int)(256.0 * r + 0.5); */
8686
8687     q = float64_mul(q, float64_256,s );
8688     q = float64_add(q, float64_half, s);
8689     q_int = float64_to_int64_round_to_zero(q, s);
8690
8691     /* return (double)s / 256.0;*/
8692     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8693 }
8694
8695 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8696 {
8697     float_status *s = fpstp;
8698     float32 f32 = float32_squash_input_denormal(input, s);
8699     uint32_t val = float32_val(f32);
8700     uint32_t f32_sbit = 0x80000000 & val;
8701     int32_t f32_exp = extract32(val, 23, 8);
8702     uint32_t f32_frac = extract32(val, 0, 23);
8703     uint64_t f64_frac;
8704     uint64_t val64;
8705     int result_exp;
8706     float64 f64;
8707
8708     if (float32_is_any_nan(f32)) {
8709         float32 nan = f32;
8710         if (float32_is_signaling_nan(f32)) {
8711             float_raise(float_flag_invalid, s);
8712             nan = float32_maybe_silence_nan(f32);
8713         }
8714         if (s->default_nan_mode) {
8715             nan =  float32_default_nan;
8716         }
8717         return nan;
8718     } else if (float32_is_zero(f32)) {
8719         float_raise(float_flag_divbyzero, s);
8720         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8721     } else if (float32_is_neg(f32)) {
8722         float_raise(float_flag_invalid, s);
8723         return float32_default_nan;
8724     } else if (float32_is_infinity(f32)) {
8725         return float32_zero;
8726     }
8727
8728     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8729      * preserving the parity of the exponent.  */
8730
8731     f64_frac = ((uint64_t) f32_frac) << 29;
8732     if (f32_exp == 0) {
8733         while (extract64(f64_frac, 51, 1) == 0) {
8734             f64_frac = f64_frac << 1;
8735             f32_exp = f32_exp-1;
8736         }
8737         f64_frac = extract64(f64_frac, 0, 51) << 1;
8738     }
8739
8740     if (extract64(f32_exp, 0, 1) == 0) {
8741         f64 = make_float64(((uint64_t) f32_sbit) << 32
8742                            | (0x3feULL << 52)
8743                            | f64_frac);
8744     } else {
8745         f64 = make_float64(((uint64_t) f32_sbit) << 32
8746                            | (0x3fdULL << 52)
8747                            | f64_frac);
8748     }
8749
8750     result_exp = (380 - f32_exp) / 2;
8751
8752     f64 = recip_sqrt_estimate(f64, s);
8753
8754     val64 = float64_val(f64);
8755
8756     val = ((result_exp & 0xff) << 23)
8757         | ((val64 >> 29)  & 0x7fffff);
8758     return make_float32(val);
8759 }
8760
8761 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8762 {
8763     float_status *s = fpstp;
8764     float64 f64 = float64_squash_input_denormal(input, s);
8765     uint64_t val = float64_val(f64);
8766     uint64_t f64_sbit = 0x8000000000000000ULL & val;
8767     int64_t f64_exp = extract64(val, 52, 11);
8768     uint64_t f64_frac = extract64(val, 0, 52);
8769     int64_t result_exp;
8770     uint64_t result_frac;
8771
8772     if (float64_is_any_nan(f64)) {
8773         float64 nan = f64;
8774         if (float64_is_signaling_nan(f64)) {
8775             float_raise(float_flag_invalid, s);
8776             nan = float64_maybe_silence_nan(f64);
8777         }
8778         if (s->default_nan_mode) {
8779             nan =  float64_default_nan;
8780         }
8781         return nan;
8782     } else if (float64_is_zero(f64)) {
8783         float_raise(float_flag_divbyzero, s);
8784         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8785     } else if (float64_is_neg(f64)) {
8786         float_raise(float_flag_invalid, s);
8787         return float64_default_nan;
8788     } else if (float64_is_infinity(f64)) {
8789         return float64_zero;
8790     }
8791
8792     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8793      * preserving the parity of the exponent.  */
8794
8795     if (f64_exp == 0) {
8796         while (extract64(f64_frac, 51, 1) == 0) {
8797             f64_frac = f64_frac << 1;
8798             f64_exp = f64_exp - 1;
8799         }
8800         f64_frac = extract64(f64_frac, 0, 51) << 1;
8801     }
8802
8803     if (extract64(f64_exp, 0, 1) == 0) {
8804         f64 = make_float64(f64_sbit
8805                            | (0x3feULL << 52)
8806                            | f64_frac);
8807     } else {
8808         f64 = make_float64(f64_sbit
8809                            | (0x3fdULL << 52)
8810                            | f64_frac);
8811     }
8812
8813     result_exp = (3068 - f64_exp) / 2;
8814
8815     f64 = recip_sqrt_estimate(f64, s);
8816
8817     result_frac = extract64(float64_val(f64), 0, 52);
8818
8819     return make_float64(f64_sbit |
8820                         ((result_exp & 0x7ff) << 52) |
8821                         result_frac);
8822 }
8823
8824 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8825 {
8826     float_status *s = fpstp;
8827     float64 f64;
8828
8829     if ((a & 0x80000000) == 0) {
8830         return 0xffffffff;
8831     }
8832
8833     f64 = make_float64((0x3feULL << 52)
8834                        | ((int64_t)(a & 0x7fffffff) << 21));
8835
8836     f64 = recip_estimate(f64, s);
8837
8838     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8839 }
8840
8841 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8842 {
8843     float_status *fpst = fpstp;
8844     float64 f64;
8845
8846     if ((a & 0xc0000000) == 0) {
8847         return 0xffffffff;
8848     }
8849
8850     if (a & 0x80000000) {
8851         f64 = make_float64((0x3feULL << 52)
8852                            | ((uint64_t)(a & 0x7fffffff) << 21));
8853     } else { /* bits 31-30 == '01' */
8854         f64 = make_float64((0x3fdULL << 52)
8855                            | ((uint64_t)(a & 0x3fffffff) << 22));
8856     }
8857
8858     f64 = recip_sqrt_estimate(f64, fpst);
8859
8860     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8861 }
8862
8863 /* VFPv4 fused multiply-accumulate */
8864 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8865 {
8866     float_status *fpst = fpstp;
8867     return float32_muladd(a, b, c, 0, fpst);
8868 }
8869
8870 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
8871 {
8872     float_status *fpst = fpstp;
8873     return float64_muladd(a, b, c, 0, fpst);
8874 }
8875
8876 /* ARMv8 round to integral */
8877 float32 HELPER(rints_exact)(float32 x, void *fp_status)
8878 {
8879     return float32_round_to_int(x, fp_status);
8880 }
8881
8882 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
8883 {
8884     return float64_round_to_int(x, fp_status);
8885 }
8886
8887 float32 HELPER(rints)(float32 x, void *fp_status)
8888 {
8889     int old_flags = get_float_exception_flags(fp_status), new_flags;
8890     float32 ret;
8891
8892     ret = float32_round_to_int(x, fp_status);
8893
8894     /* Suppress any inexact exceptions the conversion produced */
8895     if (!(old_flags & float_flag_inexact)) {
8896         new_flags = get_float_exception_flags(fp_status);
8897         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8898     }
8899
8900     return ret;
8901 }
8902
8903 float64 HELPER(rintd)(float64 x, void *fp_status)
8904 {
8905     int old_flags = get_float_exception_flags(fp_status), new_flags;
8906     float64 ret;
8907
8908     ret = float64_round_to_int(x, fp_status);
8909
8910     new_flags = get_float_exception_flags(fp_status);
8911
8912     /* Suppress any inexact exceptions the conversion produced */
8913     if (!(old_flags & float_flag_inexact)) {
8914         new_flags = get_float_exception_flags(fp_status);
8915         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8916     }
8917
8918     return ret;
8919 }
8920
8921 /* Convert ARM rounding mode to softfloat */
8922 int arm_rmode_to_sf(int rmode)
8923 {
8924     switch (rmode) {
8925     case FPROUNDING_TIEAWAY:
8926         rmode = float_round_ties_away;
8927         break;
8928     case FPROUNDING_ODD:
8929         /* FIXME: add support for TIEAWAY and ODD */
8930         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
8931                       rmode);
8932     case FPROUNDING_TIEEVEN:
8933     default:
8934         rmode = float_round_nearest_even;
8935         break;
8936     case FPROUNDING_POSINF:
8937         rmode = float_round_up;
8938         break;
8939     case FPROUNDING_NEGINF:
8940         rmode = float_round_down;
8941         break;
8942     case FPROUNDING_ZERO:
8943         rmode = float_round_to_zero;
8944         break;
8945     }
8946     return rmode;
8947 }
8948
8949 /* CRC helpers.
8950  * The upper bytes of val (above the number specified by 'bytes') must have
8951  * been zeroed out by the caller.
8952  */
8953 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
8954 {
8955     uint8_t buf[4];
8956
8957     stl_le_p(buf, val);
8958
8959     /* zlib crc32 converts the accumulator and output to one's complement.  */
8960     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
8961 }
8962
8963 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
8964 {
8965     uint8_t buf[4];
8966
8967     stl_le_p(buf, val);
8968
8969     /* Linux crc32c converts the output to one's complement.  */
8970     return crc32c(acc, buf, bytes) ^ 0xffffffff;
8971 }