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arm: Enforce should-be-1 bits in MRS decoding
[qemu/ar7.git] / tcg / sparc / tcg-target.inc.c
blobd1f4c0deadbe5183390a7e4cdcd135e635574e7c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-null.h"
26
27 #ifdef CONFIG_DEBUG_TCG
28 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
29 "%g0",
30 "%g1",
31 "%g2",
32 "%g3",
33 "%g4",
34 "%g5",
35 "%g6",
36 "%g7",
37 "%o0",
38 "%o1",
39 "%o2",
40 "%o3",
41 "%o4",
42 "%o5",
43 "%o6",
44 "%o7",
45 "%l0",
46 "%l1",
47 "%l2",
48 "%l3",
49 "%l4",
50 "%l5",
51 "%l6",
52 "%l7",
53 "%i0",
54 "%i1",
55 "%i2",
56 "%i3",
57 "%i4",
58 "%i5",
59 "%i6",
60 "%i7",
61 };
62 #endif
63
64 #ifdef __arch64__
65 # define SPARC64 1
66 #else
67 # define SPARC64 0
68 #endif
69
70 /* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
71 registers. These are saved manually by the kernel in full 64-bit
72 slots. The %i and %l registers are saved by the register window
73 mechanism, which only allocates space for 32 bits. Given that this
74 window spill/fill can happen on any signal, we must consider the
75 high bits of the %i and %l registers garbage at all times. */
76 #if SPARC64
77 # define ALL_64 0xffffffffu
78 #else
79 # define ALL_64 0xffffu
80 #endif
81
82 /* Define some temporary registers. T2 is used for constant generation. */
83 #define TCG_REG_T1 TCG_REG_G1
84 #define TCG_REG_T2 TCG_REG_O7
85
86 #ifndef CONFIG_SOFTMMU
87 # define TCG_GUEST_BASE_REG TCG_REG_I5
88 #endif
89
90 static const int tcg_target_reg_alloc_order[] = {
91 TCG_REG_L0,
92 TCG_REG_L1,
93 TCG_REG_L2,
94 TCG_REG_L3,
95 TCG_REG_L4,
96 TCG_REG_L5,
97 TCG_REG_L6,
98 TCG_REG_L7,
99
100 TCG_REG_I0,
101 TCG_REG_I1,
102 TCG_REG_I2,
103 TCG_REG_I3,
104 TCG_REG_I4,
105 TCG_REG_I5,
106
107 TCG_REG_G2,
108 TCG_REG_G3,
109 TCG_REG_G4,
110 TCG_REG_G5,
111
112 TCG_REG_O0,
113 TCG_REG_O1,
114 TCG_REG_O2,
115 TCG_REG_O3,
116 TCG_REG_O4,
117 TCG_REG_O5,
118 };
119
120 static const int tcg_target_call_iarg_regs[6] = {
121 TCG_REG_O0,
122 TCG_REG_O1,
123 TCG_REG_O2,
124 TCG_REG_O3,
125 TCG_REG_O4,
126 TCG_REG_O5,
127 };
128
129 static const int tcg_target_call_oarg_regs[] = {
130 TCG_REG_O0,
131 TCG_REG_O1,
132 TCG_REG_O2,
133 TCG_REG_O3,
134 };
135
136 #define INSN_OP(x) ((x) << 30)
137 #define INSN_OP2(x) ((x) << 22)
138 #define INSN_OP3(x) ((x) << 19)
139 #define INSN_OPF(x) ((x) << 5)
140 #define INSN_RD(x) ((x) << 25)
141 #define INSN_RS1(x) ((x) << 14)
142 #define INSN_RS2(x) (x)
143 #define INSN_ASI(x) ((x) << 5)
144
145 #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
146 #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
147 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
148 #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
149 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
150 #define INSN_COND(x) ((x) << 25)
151
152 #define COND_N 0x0
153 #define COND_E 0x1
154 #define COND_LE 0x2
155 #define COND_L 0x3
156 #define COND_LEU 0x4
157 #define COND_CS 0x5
158 #define COND_NEG 0x6
159 #define COND_VS 0x7
160 #define COND_A 0x8
161 #define COND_NE 0x9
162 #define COND_G 0xa
163 #define COND_GE 0xb
164 #define COND_GU 0xc
165 #define COND_CC 0xd
166 #define COND_POS 0xe
167 #define COND_VC 0xf
168 #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
169
170 #define RCOND_Z 1
171 #define RCOND_LEZ 2
172 #define RCOND_LZ 3
173 #define RCOND_NZ 5
174 #define RCOND_GZ 6
175 #define RCOND_GEZ 7
176
177 #define MOVCC_ICC (1 << 18)
178 #define MOVCC_XCC (1 << 18 | 1 << 12)
179
180 #define BPCC_ICC 0
181 #define BPCC_XCC (2 << 20)
182 #define BPCC_PT (1 << 19)
183 #define BPCC_PN 0
184 #define BPCC_A (1 << 29)
185
186 #define BPR_PT BPCC_PT
187
188 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
189 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
190 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
191 #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
192 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
193 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
194 #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
195 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
196 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
197 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
198 #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08))
199 #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c))
200 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
201 #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
202 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
203 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
204 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
205 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
206 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
207 #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
208 #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
209
210 #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
211 #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
212
213 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
214 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
215 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
216
217 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
218 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
219 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
220
221 #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
222 #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
223 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
224 #define RETURN (INSN_OP(2) | INSN_OP3(0x39))
225 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
226 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
227 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
228 #define CALL INSN_OP(1)
229 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
230 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
231 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
232 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
233 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
234 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
235 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
236 #define STB (INSN_OP(3) | INSN_OP3(0x05))
237 #define STH (INSN_OP(3) | INSN_OP3(0x06))
238 #define STW (INSN_OP(3) | INSN_OP3(0x04))
239 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
240 #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
241 #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
242 #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
243 #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
244 #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
245 #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
246 #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
247 #define STBA (INSN_OP(3) | INSN_OP3(0x15))
248 #define STHA (INSN_OP(3) | INSN_OP3(0x16))
249 #define STWA (INSN_OP(3) | INSN_OP3(0x14))
250 #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
251
252 #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
253
254 #ifndef ASI_PRIMARY_LITTLE
255 #define ASI_PRIMARY_LITTLE 0x88
256 #endif
257
258 #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
259 #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
260 #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
261 #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
262 #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
263
264 #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
265 #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
266 #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
267
268 #ifndef use_vis3_instructions
269 bool use_vis3_instructions;
270 #endif
271
272 static inline int check_fit_i64(int64_t val, unsigned int bits)
273 {
274 return val == sextract64(val, 0, bits);
275 }
276
277 static inline int check_fit_i32(int32_t val, unsigned int bits)
278 {
279 return val == sextract32(val, 0, bits);
280 }
281
282 #define check_fit_tl check_fit_i64
283 #if SPARC64
284 # define check_fit_ptr check_fit_i64
285 #else
286 # define check_fit_ptr check_fit_i32
287 #endif
288
289 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
290 intptr_t value, intptr_t addend)
291 {
292 uint32_t insn;
293
294 tcg_debug_assert(addend == 0);
295 value = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr);
296
297 switch (type) {
298 case R_SPARC_WDISP16:
299 if (!check_fit_ptr(value >> 2, 16)) {
300 tcg_abort();
301 }
302 insn = *code_ptr;
303 insn &= ~INSN_OFF16(-1);
304 insn |= INSN_OFF16(value);
305 *code_ptr = insn;
306 break;
307 case R_SPARC_WDISP19:
308 if (!check_fit_ptr(value >> 2, 19)) {
309 tcg_abort();
310 }
311 insn = *code_ptr;
312 insn &= ~INSN_OFF19(-1);
313 insn |= INSN_OFF19(value);
314 *code_ptr = insn;
315 break;
316 default:
317 tcg_abort();
318 }
319 }
320
321 /* parse target specific constraints */
322 static const char *target_parse_constraint(TCGArgConstraint *ct,
323 const char *ct_str, TCGType type)
324 {
325 switch (*ct_str++) {
326 case 'r':
327 ct->ct |= TCG_CT_REG;
328 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
329 break;
330 case 'R':
331 ct->ct |= TCG_CT_REG;
332 tcg_regset_set32(ct->u.regs, 0, ALL_64);
333 break;
334 case 'A': /* qemu_ld/st address constraint */
335 ct->ct |= TCG_CT_REG;
336 tcg_regset_set32(ct->u.regs, 0,
337 TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff);
338 reserve_helpers:
339 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
340 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
341 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
342 break;
343 case 's': /* qemu_st data 32-bit constraint */
344 ct->ct |= TCG_CT_REG;
345 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
346 goto reserve_helpers;
347 case 'S': /* qemu_st data 64-bit constraint */
348 ct->ct |= TCG_CT_REG;
349 tcg_regset_set32(ct->u.regs, 0, ALL_64);
350 goto reserve_helpers;
351 case 'I':
352 ct->ct |= TCG_CT_CONST_S11;
353 break;
354 case 'J':
355 ct->ct |= TCG_CT_CONST_S13;
356 break;
357 case 'Z':
358 ct->ct |= TCG_CT_CONST_ZERO;
359 break;
360 default:
361 return NULL;
362 }
363 return ct_str;
364 }
365
366 /* test if a constant matches the constraint */
367 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
368 const TCGArgConstraint *arg_ct)
369 {
370 int ct = arg_ct->ct;
371
372 if (ct & TCG_CT_CONST) {
373 return 1;
374 }
375
376 if (type == TCG_TYPE_I32) {
377 val = (int32_t)val;
378 }
379
380 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
381 return 1;
382 } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
383 return 1;
384 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
385 return 1;
386 } else {
387 return 0;
388 }
389 }
390
391 static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1,
392 TCGReg rs2, int op)
393 {
394 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2));
395 }
396
397 static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
398 int32_t offset, int op)
399 {
400 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset));
401 }
402
403 static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
404 int32_t val2, int val2const, int op)
405 {
406 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
407 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
408 }
409
410 static inline void tcg_out_mov(TCGContext *s, TCGType type,
411 TCGReg ret, TCGReg arg)
412 {
413 if (ret != arg) {
414 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
415 }
416 }
417
418 static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
419 {
420 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
421 }
422
423 static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)
424 {
425 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
426 }
427
428 static void tcg_out_movi(TCGContext *s, TCGType type,
429 TCGReg ret, tcg_target_long arg)
430 {
431 tcg_target_long hi, lo = (int32_t)arg;
432
433 /* Make sure we test 32-bit constants for imm13 properly. */
434 if (type == TCG_TYPE_I32) {
435 arg = lo;
436 }
437
438 /* A 13-bit constant sign-extended to 64-bits. */
439 if (check_fit_tl(arg, 13)) {
440 tcg_out_movi_imm13(s, ret, arg);
441 return;
442 }
443
444 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
445 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
446 tcg_out_sethi(s, ret, arg);
447 if (arg & 0x3ff) {
448 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
449 }
450 return;
451 }
452
453 /* A 32-bit constant sign-extended to 64-bits. */
454 if (arg == lo) {
455 tcg_out_sethi(s, ret, ~arg);
456 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
457 return;
458 }
459
460 /* A 64-bit constant decomposed into 2 32-bit pieces. */
461 if (check_fit_i32(lo, 13)) {
462 hi = (arg - lo) >> 32;
463 tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
464 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
465 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD);
466 } else {
467 hi = arg >> 32;
468 tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
469 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo);
470 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
471 tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR);
472 }
473 }
474
475 static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
476 TCGReg a2, int op)
477 {
478 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
479 }
480
481 static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
482 intptr_t offset, int op)
483 {
484 if (check_fit_ptr(offset, 13)) {
485 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
486 INSN_IMM13(offset));
487 } else {
488 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
489 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
490 }
491 }
492
493 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
494 TCGReg arg1, intptr_t arg2)
495 {
496 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
497 }
498
499 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
500 TCGReg arg1, intptr_t arg2)
501 {
502 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
503 }
504
505 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
506 TCGReg base, intptr_t ofs)
507 {
508 if (val == 0) {
509 tcg_out_st(s, type, TCG_REG_G0, base, ofs);
510 return true;
511 }
512 return false;
513 }
514
515 static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg)
516 {
517 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);
518 tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);
519 }
520
521 static inline void tcg_out_sety(TCGContext *s, TCGReg rs)
522 {
523 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
524 }
525
526 static inline void tcg_out_rdy(TCGContext *s, TCGReg rd)
527 {
528 tcg_out32(s, RDY | INSN_RD(rd));
529 }
530
531 static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
532 int32_t val2, int val2const, int uns)
533 {
534 /* Load Y with the sign/zero extension of RS1 to 64-bits. */
535 if (uns) {
536 tcg_out_sety(s, TCG_REG_G0);
537 } else {
538 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
539 tcg_out_sety(s, TCG_REG_T1);
540 }
541
542 tcg_out_arithc(s, rd, rs1, val2, val2const,
543 uns ? ARITH_UDIV : ARITH_SDIV);
544 }
545
546 static inline void tcg_out_nop(TCGContext *s)
547 {
548 tcg_out_sethi(s, TCG_REG_G0, 0);
549 }
550
551 static const uint8_t tcg_cond_to_bcond[] = {
552 [TCG_COND_EQ] = COND_E,
553 [TCG_COND_NE] = COND_NE,
554 [TCG_COND_LT] = COND_L,
555 [TCG_COND_GE] = COND_GE,
556 [TCG_COND_LE] = COND_LE,
557 [TCG_COND_GT] = COND_G,
558 [TCG_COND_LTU] = COND_CS,
559 [TCG_COND_GEU] = COND_CC,
560 [TCG_COND_LEU] = COND_LEU,
561 [TCG_COND_GTU] = COND_GU,
562 };
563
564 static const uint8_t tcg_cond_to_rcond[] = {
565 [TCG_COND_EQ] = RCOND_Z,
566 [TCG_COND_NE] = RCOND_NZ,
567 [TCG_COND_LT] = RCOND_LZ,
568 [TCG_COND_GT] = RCOND_GZ,
569 [TCG_COND_LE] = RCOND_LEZ,
570 [TCG_COND_GE] = RCOND_GEZ
571 };
572
573 static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
574 {
575 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
576 }
577
578 static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
579 {
580 int off19;
581
582 if (l->has_value) {
583 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr));
584 } else {
585 /* Make sure to preserve destinations during retranslation. */
586 off19 = *s->code_ptr & INSN_OFF19(-1);
587 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0);
588 }
589 tcg_out_bpcc0(s, scond, flags, off19);
590 }
591
592 static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const)
593 {
594 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
595 }
596
597 static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
598 int32_t arg2, int const_arg2, TCGLabel *l)
599 {
600 tcg_out_cmp(s, arg1, arg2, const_arg2);
601 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l);
602 tcg_out_nop(s);
603 }
604
605 static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret,
606 int32_t v1, int v1const)
607 {
608 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
609 | INSN_RS1(tcg_cond_to_bcond[cond])
610 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
611 }
612
613 static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
614 TCGReg c1, int32_t c2, int c2const,
615 int32_t v1, int v1const)
616 {
617 tcg_out_cmp(s, c1, c2, c2const);
618 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
619 }
620
621 static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1,
622 int32_t arg2, int const_arg2, TCGLabel *l)
623 {
624 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
625 if (arg2 == 0 && !is_unsigned_cond(cond)) {
626 int off16;
627
628 if (l->has_value) {
629 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr));
630 } else {
631 /* Make sure to preserve destinations during retranslation. */
632 off16 = *s->code_ptr & INSN_OFF16(-1);
633 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0);
634 }
635 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
636 | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
637 } else {
638 tcg_out_cmp(s, arg1, arg2, const_arg2);
639 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l);
640 }
641 tcg_out_nop(s);
642 }
643
644 static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1,
645 int32_t v1, int v1const)
646 {
647 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
648 | (tcg_cond_to_rcond[cond] << 10)
649 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
650 }
651
652 static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
653 TCGReg c1, int32_t c2, int c2const,
654 int32_t v1, int v1const)
655 {
656 /* For 64-bit signed comparisons vs zero, we can avoid the compare.
657 Note that the immediate range is one bit smaller, so we must check
658 for that as well. */
659 if (c2 == 0 && !is_unsigned_cond(cond)
660 && (!v1const || check_fit_i32(v1, 10))) {
661 tcg_out_movr(s, cond, ret, c1, v1, v1const);
662 } else {
663 tcg_out_cmp(s, c1, c2, c2const);
664 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
665 }
666 }
667
668 static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
669 TCGReg c1, int32_t c2, int c2const)
670 {
671 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */
672 switch (cond) {
673 case TCG_COND_LTU:
674 case TCG_COND_GEU:
675 /* The result of the comparison is in the carry bit. */
676 break;
677
678 case TCG_COND_EQ:
679 case TCG_COND_NE:
680 /* For equality, we can transform to inequality vs zero. */
681 if (c2 != 0) {
682 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR);
683 c2 = TCG_REG_T1;
684 } else {
685 c2 = c1;
686 }
687 c1 = TCG_REG_G0, c2const = 0;
688 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
689 break;
690
691 case TCG_COND_GTU:
692 case TCG_COND_LEU:
693 /* If we don't need to load a constant into a register, we can
694 swap the operands on GTU/LEU. There's no benefit to loading
695 the constant into a temporary register. */
696 if (!c2const || c2 == 0) {
697 TCGReg t = c1;
698 c1 = c2;
699 c2 = t;
700 c2const = 0;
701 cond = tcg_swap_cond(cond);
702 break;
703 }
704 /* FALLTHRU */
705
706 default:
707 tcg_out_cmp(s, c1, c2, c2const);
708 tcg_out_movi_imm13(s, ret, 0);
709 tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
710 return;
711 }
712
713 tcg_out_cmp(s, c1, c2, c2const);
714 if (cond == TCG_COND_LTU) {
715 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
716 } else {
717 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
718 }
719 }
720
721 static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
722 TCGReg c1, int32_t c2, int c2const)
723 {
724 if (use_vis3_instructions) {
725 switch (cond) {
726 case TCG_COND_NE:
727 if (c2 != 0) {
728 break;
729 }
730 c2 = c1, c2const = 0, c1 = TCG_REG_G0;
731 /* FALLTHRU */
732 case TCG_COND_LTU:
733 tcg_out_cmp(s, c1, c2, c2const);
734 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC);
735 return;
736 default:
737 break;
738 }
739 }
740
741 /* For 64-bit signed comparisons vs zero, we can avoid the compare
742 if the input does not overlap the output. */
743 if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
744 tcg_out_movi_imm13(s, ret, 0);
745 tcg_out_movr(s, cond, ret, c1, 1, 1);
746 } else {
747 tcg_out_cmp(s, c1, c2, c2const);
748 tcg_out_movi_imm13(s, ret, 0);
749 tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
750 }
751 }
752
753 static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh,
754 TCGReg al, TCGReg ah, int32_t bl, int blconst,
755 int32_t bh, int bhconst, int opl, int oph)
756 {
757 TCGReg tmp = TCG_REG_T1;
758
759 /* Note that the low parts are fully consumed before tmp is set. */
760 if (rl != ah && (bhconst || rl != bh)) {
761 tmp = rl;
762 }
763
764 tcg_out_arithc(s, tmp, al, bl, blconst, opl);
765 tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
766 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
767 }
768
769 static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
770 TCGReg al, TCGReg ah, int32_t bl, int blconst,
771 int32_t bh, int bhconst, bool is_sub)
772 {
773 TCGReg tmp = TCG_REG_T1;
774
775 /* Note that the low parts are fully consumed before tmp is set. */
776 if (rl != ah && (bhconst || rl != bh)) {
777 tmp = rl;
778 }
779
780 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC);
781
782 if (use_vis3_instructions && !is_sub) {
783 /* Note that ADDXC doesn't accept immediates. */
784 if (bhconst && bh != 0) {
785 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh);
786 bh = TCG_REG_T2;
787 }
788 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
789 } else if (bh == TCG_REG_G0) {
790 /* If we have a zero, we can perform the operation in two insns,
791 with the arithmetic first, and a conditional move into place. */
792 if (rh == ah) {
793 tcg_out_arithi(s, TCG_REG_T2, ah, 1,
794 is_sub ? ARITH_SUB : ARITH_ADD);
795 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
796 } else {
797 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
798 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
799 }
800 } else {
801 /* Otherwise adjust BH as if there is carry into T2 ... */
802 if (bhconst) {
803 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1));
804 } else {
805 tcg_out_arithi(s, TCG_REG_T2, bh, 1,
806 is_sub ? ARITH_SUB : ARITH_ADD);
807 }
808 /* ... smoosh T2 back to original BH if carry is clear ... */
809 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
810 /* ... and finally perform the arithmetic with the new operand. */
811 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
812 }
813
814 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
815 }
816
817 static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest)
818 {
819 ptrdiff_t disp = tcg_pcrel_diff(s, dest);
820
821 if (disp == (int32_t)disp) {
822 tcg_out32(s, CALL | (uint32_t)disp >> 2);
823 } else {
824 uintptr_t desti = (uintptr_t)dest;
825 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff);
826 tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL);
827 }
828 }
829
830 static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
831 {
832 tcg_out_call_nodelay(s, dest);
833 tcg_out_nop(s);
834 }
835
836 static void tcg_out_mb(TCGContext *s, TCGArg a0)
837 {
838 /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
839 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
840 }
841
842 #ifdef CONFIG_SOFTMMU
843 static tcg_insn_unit *qemu_ld_trampoline[16];
844 static tcg_insn_unit *qemu_st_trampoline[16];
845
846 static void build_trampolines(TCGContext *s)
847 {
848 static void * const qemu_ld_helpers[16] = {
849 [MO_UB] = helper_ret_ldub_mmu,
850 [MO_SB] = helper_ret_ldsb_mmu,
851 [MO_LEUW] = helper_le_lduw_mmu,
852 [MO_LESW] = helper_le_ldsw_mmu,
853 [MO_LEUL] = helper_le_ldul_mmu,
854 [MO_LEQ] = helper_le_ldq_mmu,
855 [MO_BEUW] = helper_be_lduw_mmu,
856 [MO_BESW] = helper_be_ldsw_mmu,
857 [MO_BEUL] = helper_be_ldul_mmu,
858 [MO_BEQ] = helper_be_ldq_mmu,
859 };
860 static void * const qemu_st_helpers[16] = {
861 [MO_UB] = helper_ret_stb_mmu,
862 [MO_LEUW] = helper_le_stw_mmu,
863 [MO_LEUL] = helper_le_stl_mmu,
864 [MO_LEQ] = helper_le_stq_mmu,
865 [MO_BEUW] = helper_be_stw_mmu,
866 [MO_BEUL] = helper_be_stl_mmu,
867 [MO_BEQ] = helper_be_stq_mmu,
868 };
869
870 int i;
871 TCGReg ra;
872
873 for (i = 0; i < 16; ++i) {
874 if (qemu_ld_helpers[i] == NULL) {
875 continue;
876 }
877
878 /* May as well align the trampoline. */
879 while ((uintptr_t)s->code_ptr & 15) {
880 tcg_out_nop(s);
881 }
882 qemu_ld_trampoline[i] = s->code_ptr;
883
884 if (SPARC64 || TARGET_LONG_BITS == 32) {
885 ra = TCG_REG_O3;
886 } else {
887 /* Install the high part of the address. */
888 tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
889 ra = TCG_REG_O4;
890 }
891
892 /* Set the retaddr operand. */
893 tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
894 /* Set the env operand. */
895 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
896 /* Tail call. */
897 tcg_out_call_nodelay(s, qemu_ld_helpers[i]);
898 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
899 }
900
901 for (i = 0; i < 16; ++i) {
902 if (qemu_st_helpers[i] == NULL) {
903 continue;
904 }
905
906 /* May as well align the trampoline. */
907 while ((uintptr_t)s->code_ptr & 15) {
908 tcg_out_nop(s);
909 }
910 qemu_st_trampoline[i] = s->code_ptr;
911
912 if (SPARC64) {
913 ra = TCG_REG_O4;
914 } else {
915 ra = TCG_REG_O1;
916 if (TARGET_LONG_BITS == 64) {
917 /* Install the high part of the address. */
918 tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
919 ra += 2;
920 } else {
921 ra += 1;
922 }
923 if ((i & MO_SIZE) == MO_64) {
924 /* Install the high part of the data. */
925 tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
926 ra += 2;
927 } else {
928 ra += 1;
929 }
930 /* Skip the oi argument. */
931 ra += 1;
932 }
933
934 /* Set the retaddr operand. */
935 if (ra >= TCG_REG_O6) {
936 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK,
937 TCG_TARGET_CALL_STACK_OFFSET);
938 ra = TCG_REG_G1;
939 }
940 tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
941 /* Set the env operand. */
942 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
943 /* Tail call. */
944 tcg_out_call_nodelay(s, qemu_st_helpers[i]);
945 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
946 }
947 }
948 #endif
949
950 /* Generate global QEMU prologue and epilogue code */
951 static void tcg_target_qemu_prologue(TCGContext *s)
952 {
953 int tmp_buf_size, frame_size;
954
955 /* The TCG temp buffer is at the top of the frame, immediately
956 below the frame pointer. */
957 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long);
958 tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size,
959 tmp_buf_size);
960
961 /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is
962 otherwise the minimal frame usable by callees. */
963 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS;
964 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size;
965 frame_size += TCG_TARGET_STACK_ALIGN - 1;
966 frame_size &= -TCG_TARGET_STACK_ALIGN;
967 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
968 INSN_IMM13(-frame_size));
969
970 #ifndef CONFIG_SOFTMMU
971 if (guest_base != 0) {
972 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
973 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
974 }
975 #endif
976
977 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);
978 /* delay slot */
979 tcg_out_nop(s);
980
981 /* No epilogue required. We issue ret + restore directly in the TB. */
982
983 #ifdef CONFIG_SOFTMMU
984 build_trampolines(s);
985 #endif
986 }
987
988 #if defined(CONFIG_SOFTMMU)
989 /* Perform the TLB load and compare.
990
991 Inputs:
992 ADDRLO and ADDRHI contain the possible two parts of the address.
993
994 MEM_INDEX and S_BITS are the memory context and log2 size of the load.
995
996 WHICH is the offset into the CPUTLBEntry structure of the slot to read.
997 This should be offsetof addr_read or addr_write.
998
999 The result of the TLB comparison is in %[ix]cc. The sanitized address
1000 is in the returned register, maybe %o0. The TLB addend is in %o1. */
1001
1002 static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
1003 TCGMemOp opc, int which)
1004 {
1005 const TCGReg r0 = TCG_REG_O0;
1006 const TCGReg r1 = TCG_REG_O1;
1007 const TCGReg r2 = TCG_REG_O2;
1008 unsigned s_bits = opc & MO_SIZE;
1009 unsigned a_bits = get_alignment_bits(opc);
1010 int tlb_ofs;
1011
1012 /* Shift the page number down. */
1013 tcg_out_arithi(s, r1, addr, TARGET_PAGE_BITS, SHIFT_SRL);
1014
1015 /* Mask out the page offset, except for the required alignment.
1016 We don't support unaligned accesses. */
1017 if (a_bits < s_bits) {
1018 a_bits = s_bits;
1019 }
1020 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_T1,
1021 TARGET_PAGE_MASK | ((1 << a_bits) - 1));
1022
1023 /* Mask the tlb index. */
1024 tcg_out_arithi(s, r1, r1, CPU_TLB_SIZE - 1, ARITH_AND);
1025
1026 /* Mask page, part 2. */
1027 tcg_out_arith(s, r0, addr, TCG_REG_T1, ARITH_AND);
1028
1029 /* Shift the tlb index into place. */
1030 tcg_out_arithi(s, r1, r1, CPU_TLB_ENTRY_BITS, SHIFT_SLL);
1031
1032 /* Relative to the current ENV. */
1033 tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD);
1034
1035 /* Find a base address that can load both tlb comparator and addend. */
1036 tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]);
1037 if (!check_fit_ptr(tlb_ofs + sizeof(CPUTLBEntry), 13)) {
1038 if (tlb_ofs & ~0x3ff) {
1039 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, tlb_ofs & ~0x3ff);
1040 tcg_out_arith(s, r1, r1, TCG_REG_T1, ARITH_ADD);
1041 }
1042 tlb_ofs &= 0x3ff;
1043 }
1044
1045 /* Load the tlb comparator and the addend. */
1046 tcg_out_ld(s, TCG_TYPE_TL, r2, r1, tlb_ofs + which);
1047 tcg_out_ld(s, TCG_TYPE_PTR, r1, r1, tlb_ofs+offsetof(CPUTLBEntry, addend));
1048
1049 /* subcc arg0, arg2, %g0 */
1050 tcg_out_cmp(s, r0, r2, 0);
1051
1052 /* If the guest address must be zero-extended, do so now. */
1053 if (SPARC64 && TARGET_LONG_BITS == 32) {
1054 tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
1055 return r0;
1056 }
1057 return addr;
1058 }
1059 #endif /* CONFIG_SOFTMMU */
1060
1061 static const int qemu_ld_opc[16] = {
1062 [MO_UB] = LDUB,
1063 [MO_SB] = LDSB,
1064
1065 [MO_BEUW] = LDUH,
1066 [MO_BESW] = LDSH,
1067 [MO_BEUL] = LDUW,
1068 [MO_BESL] = LDSW,
1069 [MO_BEQ] = LDX,
1070
1071 [MO_LEUW] = LDUH_LE,
1072 [MO_LESW] = LDSH_LE,
1073 [MO_LEUL] = LDUW_LE,
1074 [MO_LESL] = LDSW_LE,
1075 [MO_LEQ] = LDX_LE,
1076 };
1077
1078 static const int qemu_st_opc[16] = {
1079 [MO_UB] = STB,
1080
1081 [MO_BEUW] = STH,
1082 [MO_BEUL] = STW,
1083 [MO_BEQ] = STX,
1084
1085 [MO_LEUW] = STH_LE,
1086 [MO_LEUL] = STW_LE,
1087 [MO_LEQ] = STX_LE,
1088 };
1089
1090 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
1091 TCGMemOpIdx oi, bool is_64)
1092 {
1093 TCGMemOp memop = get_memop(oi);
1094 #ifdef CONFIG_SOFTMMU
1095 unsigned memi = get_mmuidx(oi);
1096 TCGReg addrz, param;
1097 tcg_insn_unit *func;
1098 tcg_insn_unit *label_ptr;
1099
1100 addrz = tcg_out_tlb_load(s, addr, memi, memop,
1101 offsetof(CPUTLBEntry, addr_read));
1102
1103 /* The fast path is exactly one insn. Thus we can perform the
1104 entire TLB Hit in the (annulled) delay slot of the branch
1105 over the TLB Miss case. */
1106
1107 /* beq,a,pt %[xi]cc, label0 */
1108 label_ptr = s->code_ptr;
1109 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1110 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1111 /* delay slot */
1112 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1113 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1114
1115 /* TLB Miss. */
1116
1117 param = TCG_REG_O1;
1118 if (!SPARC64 && TARGET_LONG_BITS == 64) {
1119 /* Skip the high-part; we'll perform the extract in the trampoline. */
1120 param++;
1121 }
1122 tcg_out_mov(s, TCG_TYPE_REG, param++, addr);
1123
1124 /* We use the helpers to extend SB and SW data, leaving the case
1125 of SL needing explicit extending below. */
1126 if ((memop & MO_SSIZE) == MO_SL) {
1127 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1128 } else {
1129 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];
1130 }
1131 tcg_debug_assert(func != NULL);
1132 tcg_out_call_nodelay(s, func);
1133 /* delay slot */
1134 tcg_out_movi(s, TCG_TYPE_I32, param, oi);
1135
1136 /* Recall that all of the helpers return 64-bit results.
1137 Which complicates things for sparcv8plus. */
1138 if (SPARC64) {
1139 /* We let the helper sign-extend SB and SW, but leave SL for here. */
1140 if (is_64 && (memop & MO_SSIZE) == MO_SL) {
1141 tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
1142 } else {
1143 tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
1144 }
1145 } else {
1146 if ((memop & MO_SIZE) == MO_64) {
1147 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);
1148 tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);
1149 tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);
1150 } else if (is_64) {
1151 /* Re-extend from 32-bit rather than reassembling when we
1152 know the high register must be an extension. */
1153 tcg_out_arithi(s, data, TCG_REG_O1, 0,
1154 memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL);
1155 } else {
1156 tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1);
1157 }
1158 }
1159
1160 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1161 #else
1162 if (SPARC64 && TARGET_LONG_BITS == 32) {
1163 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1164 addr = TCG_REG_T1;
1165 }
1166 tcg_out_ldst_rr(s, data, addr,
1167 (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
1168 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1169 #endif /* CONFIG_SOFTMMU */
1170 }
1171
1172 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
1173 TCGMemOpIdx oi)
1174 {
1175 TCGMemOp memop = get_memop(oi);
1176 #ifdef CONFIG_SOFTMMU
1177 unsigned memi = get_mmuidx(oi);
1178 TCGReg addrz, param;
1179 tcg_insn_unit *func;
1180 tcg_insn_unit *label_ptr;
1181
1182 addrz = tcg_out_tlb_load(s, addr, memi, memop,
1183 offsetof(CPUTLBEntry, addr_write));
1184
1185 /* The fast path is exactly one insn. Thus we can perform the entire
1186 TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
1187 /* beq,a,pt %[xi]cc, label0 */
1188 label_ptr = s->code_ptr;
1189 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1190 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1191 /* delay slot */
1192 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1193 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1194
1195 /* TLB Miss. */
1196
1197 param = TCG_REG_O1;
1198 if (!SPARC64 && TARGET_LONG_BITS == 64) {
1199 /* Skip the high-part; we'll perform the extract in the trampoline. */
1200 param++;
1201 }
1202 tcg_out_mov(s, TCG_TYPE_REG, param++, addr);
1203 if (!SPARC64 && (memop & MO_SIZE) == MO_64) {
1204 /* Skip the high-part; we'll perform the extract in the trampoline. */
1205 param++;
1206 }
1207 tcg_out_mov(s, TCG_TYPE_REG, param++, data);
1208
1209 func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1210 tcg_debug_assert(func != NULL);
1211 tcg_out_call_nodelay(s, func);
1212 /* delay slot */
1213 tcg_out_movi(s, TCG_TYPE_I32, param, oi);
1214
1215 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1216 #else
1217 if (SPARC64 && TARGET_LONG_BITS == 32) {
1218 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1219 addr = TCG_REG_T1;
1220 }
1221 tcg_out_ldst_rr(s, data, addr,
1222 (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
1223 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1224 #endif /* CONFIG_SOFTMMU */
1225 }
1226
1227 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1228 const TCGArg args[TCG_MAX_OP_ARGS],
1229 const int const_args[TCG_MAX_OP_ARGS])
1230 {
1231 TCGArg a0, a1, a2;
1232 int c, c2;
1233
1234 /* Hoist the loads of the most common arguments. */
1235 a0 = args[0];
1236 a1 = args[1];
1237 a2 = args[2];
1238 c2 = const_args[2];
1239
1240 switch (opc) {
1241 case INDEX_op_exit_tb:
1242 if (check_fit_ptr(a0, 13)) {
1243 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1244 tcg_out_movi_imm13(s, TCG_REG_O0, a0);
1245 } else {
1246 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);
1247 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1248 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);
1249 }
1250 break;
1251 case INDEX_op_goto_tb:
1252 if (s->tb_jmp_insn_offset) {
1253 /* direct jump method */
1254 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1255 /* Make sure to preserve links during retranslation. */
1256 tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1)));
1257 } else {
1258 /* indirect jump method */
1259 tcg_out_ld_ptr(s, TCG_REG_T1,
1260 (uintptr_t)(s->tb_jmp_target_addr + a0));
1261 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL);
1262 }
1263 tcg_out_nop(s);
1264 s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);
1265 break;
1266 case INDEX_op_br:
1267 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));
1268 tcg_out_nop(s);
1269 break;
1270
1271 #define OP_32_64(x) \
1272 glue(glue(case INDEX_op_, x), _i32): \
1273 glue(glue(case INDEX_op_, x), _i64)
1274
1275 OP_32_64(ld8u):
1276 tcg_out_ldst(s, a0, a1, a2, LDUB);
1277 break;
1278 OP_32_64(ld8s):
1279 tcg_out_ldst(s, a0, a1, a2, LDSB);
1280 break;
1281 OP_32_64(ld16u):
1282 tcg_out_ldst(s, a0, a1, a2, LDUH);
1283 break;
1284 OP_32_64(ld16s):
1285 tcg_out_ldst(s, a0, a1, a2, LDSH);
1286 break;
1287 case INDEX_op_ld_i32:
1288 case INDEX_op_ld32u_i64:
1289 tcg_out_ldst(s, a0, a1, a2, LDUW);
1290 break;
1291 OP_32_64(st8):
1292 tcg_out_ldst(s, a0, a1, a2, STB);
1293 break;
1294 OP_32_64(st16):
1295 tcg_out_ldst(s, a0, a1, a2, STH);
1296 break;
1297 case INDEX_op_st_i32:
1298 case INDEX_op_st32_i64:
1299 tcg_out_ldst(s, a0, a1, a2, STW);
1300 break;
1301 OP_32_64(add):
1302 c = ARITH_ADD;
1303 goto gen_arith;
1304 OP_32_64(sub):
1305 c = ARITH_SUB;
1306 goto gen_arith;
1307 OP_32_64(and):
1308 c = ARITH_AND;
1309 goto gen_arith;
1310 OP_32_64(andc):
1311 c = ARITH_ANDN;
1312 goto gen_arith;
1313 OP_32_64(or):
1314 c = ARITH_OR;
1315 goto gen_arith;
1316 OP_32_64(orc):
1317 c = ARITH_ORN;
1318 goto gen_arith;
1319 OP_32_64(xor):
1320 c = ARITH_XOR;
1321 goto gen_arith;
1322 case INDEX_op_shl_i32:
1323 c = SHIFT_SLL;
1324 do_shift32:
1325 /* Limit immediate shift count lest we create an illegal insn. */
1326 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c);
1327 break;
1328 case INDEX_op_shr_i32:
1329 c = SHIFT_SRL;
1330 goto do_shift32;
1331 case INDEX_op_sar_i32:
1332 c = SHIFT_SRA;
1333 goto do_shift32;
1334 case INDEX_op_mul_i32:
1335 c = ARITH_UMUL;
1336 goto gen_arith;
1337
1338 OP_32_64(neg):
1339 c = ARITH_SUB;
1340 goto gen_arith1;
1341 OP_32_64(not):
1342 c = ARITH_ORN;
1343 goto gen_arith1;
1344
1345 case INDEX_op_div_i32:
1346 tcg_out_div32(s, a0, a1, a2, c2, 0);
1347 break;
1348 case INDEX_op_divu_i32:
1349 tcg_out_div32(s, a0, a1, a2, c2, 1);
1350 break;
1351
1352 case INDEX_op_brcond_i32:
1353 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1354 break;
1355 case INDEX_op_setcond_i32:
1356 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
1357 break;
1358 case INDEX_op_movcond_i32:
1359 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1360 break;
1361
1362 case INDEX_op_add2_i32:
1363 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1364 args[4], const_args[4], args[5], const_args[5],
1365 ARITH_ADDCC, ARITH_ADDC);
1366 break;
1367 case INDEX_op_sub2_i32:
1368 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1369 args[4], const_args[4], args[5], const_args[5],
1370 ARITH_SUBCC, ARITH_SUBC);
1371 break;
1372 case INDEX_op_mulu2_i32:
1373 c = ARITH_UMUL;
1374 goto do_mul2;
1375 case INDEX_op_muls2_i32:
1376 c = ARITH_SMUL;
1377 do_mul2:
1378 /* The 32-bit multiply insns produce a full 64-bit result. If the
1379 destination register can hold it, we can avoid the slower RDY. */
1380 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
1381 if (SPARC64 || a0 <= TCG_REG_O7) {
1382 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
1383 } else {
1384 tcg_out_rdy(s, a1);
1385 }
1386 break;
1387
1388 case INDEX_op_qemu_ld_i32:
1389 tcg_out_qemu_ld(s, a0, a1, a2, false);
1390 break;
1391 case INDEX_op_qemu_ld_i64:
1392 tcg_out_qemu_ld(s, a0, a1, a2, true);
1393 break;
1394 case INDEX_op_qemu_st_i32:
1395 case INDEX_op_qemu_st_i64:
1396 tcg_out_qemu_st(s, a0, a1, a2);
1397 break;
1398
1399 case INDEX_op_ld32s_i64:
1400 tcg_out_ldst(s, a0, a1, a2, LDSW);
1401 break;
1402 case INDEX_op_ld_i64:
1403 tcg_out_ldst(s, a0, a1, a2, LDX);
1404 break;
1405 case INDEX_op_st_i64:
1406 tcg_out_ldst(s, a0, a1, a2, STX);
1407 break;
1408 case INDEX_op_shl_i64:
1409 c = SHIFT_SLLX;
1410 do_shift64:
1411 /* Limit immediate shift count lest we create an illegal insn. */
1412 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c);
1413 break;
1414 case INDEX_op_shr_i64:
1415 c = SHIFT_SRLX;
1416 goto do_shift64;
1417 case INDEX_op_sar_i64:
1418 c = SHIFT_SRAX;
1419 goto do_shift64;
1420 case INDEX_op_mul_i64:
1421 c = ARITH_MULX;
1422 goto gen_arith;
1423 case INDEX_op_div_i64:
1424 c = ARITH_SDIVX;
1425 goto gen_arith;
1426 case INDEX_op_divu_i64:
1427 c = ARITH_UDIVX;
1428 goto gen_arith;
1429 case INDEX_op_ext_i32_i64:
1430 case INDEX_op_ext32s_i64:
1431 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA);
1432 break;
1433 case INDEX_op_extu_i32_i64:
1434 case INDEX_op_ext32u_i64:
1435 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
1436 break;
1437 case INDEX_op_extrl_i64_i32:
1438 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1439 break;
1440 case INDEX_op_extrh_i64_i32:
1441 tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
1442 break;
1443
1444 case INDEX_op_brcond_i64:
1445 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1446 break;
1447 case INDEX_op_setcond_i64:
1448 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
1449 break;
1450 case INDEX_op_movcond_i64:
1451 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1452 break;
1453 case INDEX_op_add2_i64:
1454 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1455 const_args[4], args[5], const_args[5], false);
1456 break;
1457 case INDEX_op_sub2_i64:
1458 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1459 const_args[4], args[5], const_args[5], true);
1460 break;
1461 case INDEX_op_muluh_i64:
1462 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
1463 break;
1464
1465 gen_arith:
1466 tcg_out_arithc(s, a0, a1, a2, c2, c);
1467 break;
1468
1469 gen_arith1:
1470 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
1471 break;
1472
1473 case INDEX_op_mb:
1474 tcg_out_mb(s, a0);
1475 break;
1476
1477 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1478 case INDEX_op_mov_i64:
1479 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
1480 case INDEX_op_movi_i64:
1481 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1482 default:
1483 tcg_abort();
1484 }
1485 }
1486
1487 static const TCGTargetOpDef sparc_op_defs[] = {
1488 { INDEX_op_exit_tb, { } },
1489 { INDEX_op_goto_tb, { } },
1490 { INDEX_op_br, { } },
1491
1492 { INDEX_op_ld8u_i32, { "r", "r" } },
1493 { INDEX_op_ld8s_i32, { "r", "r" } },
1494 { INDEX_op_ld16u_i32, { "r", "r" } },
1495 { INDEX_op_ld16s_i32, { "r", "r" } },
1496 { INDEX_op_ld_i32, { "r", "r" } },
1497 { INDEX_op_st8_i32, { "rZ", "r" } },
1498 { INDEX_op_st16_i32, { "rZ", "r" } },
1499 { INDEX_op_st_i32, { "rZ", "r" } },
1500
1501 { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
1502 { INDEX_op_mul_i32, { "r", "rZ", "rJ" } },
1503 { INDEX_op_div_i32, { "r", "rZ", "rJ" } },
1504 { INDEX_op_divu_i32, { "r", "rZ", "rJ" } },
1505 { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
1506 { INDEX_op_and_i32, { "r", "rZ", "rJ" } },
1507 { INDEX_op_andc_i32, { "r", "rZ", "rJ" } },
1508 { INDEX_op_or_i32, { "r", "rZ", "rJ" } },
1509 { INDEX_op_orc_i32, { "r", "rZ", "rJ" } },
1510 { INDEX_op_xor_i32, { "r", "rZ", "rJ" } },
1511
1512 { INDEX_op_shl_i32, { "r", "rZ", "rJ" } },
1513 { INDEX_op_shr_i32, { "r", "rZ", "rJ" } },
1514 { INDEX_op_sar_i32, { "r", "rZ", "rJ" } },
1515
1516 { INDEX_op_neg_i32, { "r", "rJ" } },
1517 { INDEX_op_not_i32, { "r", "rJ" } },
1518
1519 { INDEX_op_brcond_i32, { "rZ", "rJ" } },
1520 { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
1521 { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
1522
1523 { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1524 { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1525 { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
1526 { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } },
1527
1528 { INDEX_op_ld8u_i64, { "R", "r" } },
1529 { INDEX_op_ld8s_i64, { "R", "r" } },
1530 { INDEX_op_ld16u_i64, { "R", "r" } },
1531 { INDEX_op_ld16s_i64, { "R", "r" } },
1532 { INDEX_op_ld32u_i64, { "R", "r" } },
1533 { INDEX_op_ld32s_i64, { "R", "r" } },
1534 { INDEX_op_ld_i64, { "R", "r" } },
1535 { INDEX_op_st8_i64, { "RZ", "r" } },
1536 { INDEX_op_st16_i64, { "RZ", "r" } },
1537 { INDEX_op_st32_i64, { "RZ", "r" } },
1538 { INDEX_op_st_i64, { "RZ", "r" } },
1539
1540 { INDEX_op_add_i64, { "R", "RZ", "RJ" } },
1541 { INDEX_op_mul_i64, { "R", "RZ", "RJ" } },
1542 { INDEX_op_div_i64, { "R", "RZ", "RJ" } },
1543 { INDEX_op_divu_i64, { "R", "RZ", "RJ" } },
1544 { INDEX_op_sub_i64, { "R", "RZ", "RJ" } },
1545 { INDEX_op_and_i64, { "R", "RZ", "RJ" } },
1546 { INDEX_op_andc_i64, { "R", "RZ", "RJ" } },
1547 { INDEX_op_or_i64, { "R", "RZ", "RJ" } },
1548 { INDEX_op_orc_i64, { "R", "RZ", "RJ" } },
1549 { INDEX_op_xor_i64, { "R", "RZ", "RJ" } },
1550
1551 { INDEX_op_shl_i64, { "R", "RZ", "RJ" } },
1552 { INDEX_op_shr_i64, { "R", "RZ", "RJ" } },
1553 { INDEX_op_sar_i64, { "R", "RZ", "RJ" } },
1554
1555 { INDEX_op_neg_i64, { "R", "RJ" } },
1556 { INDEX_op_not_i64, { "R", "RJ" } },
1557
1558 { INDEX_op_ext32s_i64, { "R", "R" } },
1559 { INDEX_op_ext32u_i64, { "R", "R" } },
1560 { INDEX_op_ext_i32_i64, { "R", "r" } },
1561 { INDEX_op_extu_i32_i64, { "R", "r" } },
1562 { INDEX_op_extrl_i64_i32, { "r", "R" } },
1563 { INDEX_op_extrh_i64_i32, { "r", "R" } },
1564
1565 { INDEX_op_brcond_i64, { "RZ", "RJ" } },
1566 { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } },
1567 { INDEX_op_movcond_i64, { "R", "RZ", "RJ", "RI", "0" } },
1568
1569 { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
1570 { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
1571 { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } },
1572
1573 { INDEX_op_qemu_ld_i32, { "r", "A" } },
1574 { INDEX_op_qemu_ld_i64, { "R", "A" } },
1575 { INDEX_op_qemu_st_i32, { "sZ", "A" } },
1576 { INDEX_op_qemu_st_i64, { "SZ", "A" } },
1577
1578 { INDEX_op_mb, { } },
1579 { -1 },
1580 };
1581
1582 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
1583 {
1584 int i, n = ARRAY_SIZE(sparc_op_defs);
1585
1586 for (i = 0; i < n; ++i) {
1587 if (sparc_op_defs[i].op == op) {
1588 return &sparc_op_defs[i];
1589 }
1590 }
1591 return NULL;
1592 }
1593
1594 static void tcg_target_init(TCGContext *s)
1595 {
1596 /* Only probe for the platform and capabilities if we havn't already
1597 determined maximum values at compile time. */
1598 #ifndef use_vis3_instructions
1599 {
1600 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
1601 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
1602 }
1603 #endif
1604
1605 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1606 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64);
1607
1608 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1609 (1 << TCG_REG_G1) |
1610 (1 << TCG_REG_G2) |
1611 (1 << TCG_REG_G3) |
1612 (1 << TCG_REG_G4) |
1613 (1 << TCG_REG_G5) |
1614 (1 << TCG_REG_G6) |
1615 (1 << TCG_REG_G7) |
1616 (1 << TCG_REG_O0) |
1617 (1 << TCG_REG_O1) |
1618 (1 << TCG_REG_O2) |
1619 (1 << TCG_REG_O3) |
1620 (1 << TCG_REG_O4) |
1621 (1 << TCG_REG_O5) |
1622 (1 << TCG_REG_O7));
1623
1624 tcg_regset_clear(s->reserved_regs);
1625 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
1626 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
1627 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
1628 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */
1629 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */
1630 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
1631 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
1632 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
1633 }
1634
1635 #if SPARC64
1636 # define ELF_HOST_MACHINE EM_SPARCV9
1637 #else
1638 # define ELF_HOST_MACHINE EM_SPARC32PLUS
1639 # define ELF_HOST_FLAGS EF_SPARC_32PLUS
1640 #endif
1641
1642 typedef struct {
1643 DebugFrameHeader h;
1644 uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
1645 uint8_t fde_win_save;
1646 uint8_t fde_ret_save[3];
1647 } DebugFrame;
1648
1649 static const DebugFrame debug_frame = {
1650 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
1651 .h.cie.id = -1,
1652 .h.cie.version = 1,
1653 .h.cie.code_align = 1,
1654 .h.cie.data_align = -sizeof(void *) & 0x7f,
1655 .h.cie.return_column = 15, /* o7 */
1656
1657 /* Total FDE size does not include the "len" member. */
1658 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1659
1660 .fde_def_cfa = {
1661 #if SPARC64
1662 12, 30, /* DW_CFA_def_cfa i6, 2047 */
1663 (2047 & 0x7f) | 0x80, (2047 >> 7)
1664 #else
1665 13, 30 /* DW_CFA_def_cfa_register i6 */
1666 #endif
1667 },
1668 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */
1669 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
1670 };
1671
1672 void tcg_register_jit(void *buf, size_t buf_size)
1673 {
1674 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1675 }
1676
1677 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
1678 {
1679 uint32_t *ptr = (uint32_t *)jmp_addr;
1680 uintptr_t disp = addr - jmp_addr;
1681
1682 /* We can reach the entire address space for 32-bit. For 64-bit
1683 the code_gen_buffer can't be larger than 2GB. */
1684 tcg_debug_assert(disp == (int32_t)disp);
1685
1686 atomic_set(ptr, deposit32(CALL, 0, 30, disp >> 2));
1687 flush_icache_range(jmp_addr, jmp_addr + 4);
1688 }
AR7 emulation for QEMU