2 * QEMU PowerPC PowerNV (POWER9) PHB4 model
4 * Copyright (c) 2018-2020, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
9 #include "qemu/osdep.h"
11 #include "qapi/visitor.h"
12 #include "qapi/error.h"
13 #include "qemu-common.h"
14 #include "monitor/monitor.h"
15 #include "target/ppc/cpu.h"
16 #include "hw/pci-host/pnv_phb4_regs.h"
17 #include "hw/pci-host/pnv_phb4.h"
18 #include "hw/pci/pcie_host.h"
19 #include "hw/pci/pcie_port.h"
20 #include "hw/ppc/pnv.h"
21 #include "hw/ppc/pnv_xscom.h"
23 #include "hw/qdev-properties.h"
24 #include "qom/object.h"
26 #define phb_error(phb, fmt, ...) \
27 qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \
28 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
31 * QEMU version of the GETFIELD/SETFIELD macros
33 * These are common with the PnvXive model.
35 static inline uint64_t GETFIELD(uint64_t mask
, uint64_t word
)
37 return (word
& mask
) >> ctz64(mask
);
40 static inline uint64_t SETFIELD(uint64_t mask
, uint64_t word
,
43 return (word
& ~mask
) | ((value
<< ctz64(mask
)) & mask
);
46 static PCIDevice
*pnv_phb4_find_cfg_dev(PnvPHB4
*phb
)
48 PCIHostState
*pci
= PCI_HOST_BRIDGE(phb
);
49 uint64_t addr
= phb
->regs
[PHB_CONFIG_ADDRESS
>> 3];
55 bus
= (addr
>> 52) & 0xff;
56 devfn
= (addr
>> 44) & 0xff;
58 /* We don't access the root complex this way */
59 if (bus
== 0 && devfn
== 0) {
62 return pci_find_device(pci
->bus
, bus
, devfn
);
66 * The CONFIG_DATA register expects little endian accesses, but as the
67 * region is big endian, we have to swap the value.
69 static void pnv_phb4_config_write(PnvPHB4
*phb
, unsigned off
,
70 unsigned size
, uint64_t val
)
72 uint32_t cfg_addr
, limit
;
75 pdev
= pnv_phb4_find_cfg_dev(phb
);
79 cfg_addr
= (phb
->regs
[PHB_CONFIG_ADDRESS
>> 3] >> 32) & 0xffc;
81 limit
= pci_config_size(pdev
);
82 if (limit
<= cfg_addr
) {
84 * conventional pci device can be behind pcie-to-pci bridge.
85 * 256 <= addr < 4K has no effects.
99 g_assert_not_reached();
101 pci_host_config_write_common(pdev
, cfg_addr
, limit
, val
, size
);
104 static uint64_t pnv_phb4_config_read(PnvPHB4
*phb
, unsigned off
,
107 uint32_t cfg_addr
, limit
;
111 pdev
= pnv_phb4_find_cfg_dev(phb
);
115 cfg_addr
= (phb
->regs
[PHB_CONFIG_ADDRESS
>> 3] >> 32) & 0xffc;
117 limit
= pci_config_size(pdev
);
118 if (limit
<= cfg_addr
) {
120 * conventional pci device can be behind pcie-to-pci bridge.
121 * 256 <= addr < 4K has no effects.
125 val
= pci_host_config_read_common(pdev
, cfg_addr
, limit
, size
);
134 g_assert_not_reached();
139 * Root complex register accesses are memory mapped.
141 static void pnv_phb4_rc_config_write(PnvPHB4
*phb
, unsigned off
,
142 unsigned size
, uint64_t val
)
144 PCIHostState
*pci
= PCI_HOST_BRIDGE(phb
);
148 phb_error(phb
, "rc_config_write invalid size %d\n", size
);
152 pdev
= pci_find_device(pci
->bus
, 0, 0);
155 pci_host_config_write_common(pdev
, off
, PHB_RC_CONFIG_SIZE
,
159 static uint64_t pnv_phb4_rc_config_read(PnvPHB4
*phb
, unsigned off
,
162 PCIHostState
*pci
= PCI_HOST_BRIDGE(phb
);
167 phb_error(phb
, "rc_config_read invalid size %d\n", size
);
171 pdev
= pci_find_device(pci
->bus
, 0, 0);
174 val
= pci_host_config_read_common(pdev
, off
, PHB_RC_CONFIG_SIZE
, 4);
178 static void pnv_phb4_check_mbt(PnvPHB4
*phb
, uint32_t index
)
180 uint64_t base
, start
, size
, mbe0
, mbe1
;
181 MemoryRegion
*parent
;
185 if (memory_region_is_mapped(&phb
->mr_mmio
[index
])) {
186 /* Should we destroy it in RCU friendly way... ? */
187 memory_region_del_subregion(phb
->mr_mmio
[index
].container
,
188 &phb
->mr_mmio
[index
]);
191 /* Get table entry */
192 mbe0
= phb
->ioda_MBT
[(index
<< 1)];
193 mbe1
= phb
->ioda_MBT
[(index
<< 1) + 1];
195 if (!(mbe0
& IODA3_MBT0_ENABLE
)) {
199 /* Grab geometry from registers */
200 base
= GETFIELD(IODA3_MBT0_BASE_ADDR
, mbe0
) << 12;
201 size
= GETFIELD(IODA3_MBT1_MASK
, mbe1
) << 12;
202 size
|= 0xff00000000000000ull
;
205 /* Calculate PCI side start address based on M32/M64 window type */
206 if (mbe0
& IODA3_MBT0_TYPE_M32
) {
207 start
= phb
->regs
[PHB_M32_START_ADDR
>> 3];
208 if ((start
+ size
) > 0x100000000ull
) {
209 phb_error(phb
, "M32 set beyond 4GB boundary !");
210 size
= 0x100000000 - start
;
213 start
= base
| (phb
->regs
[PHB_M64_UPPER_BITS
>> 3]);
216 /* TODO: Figure out how to implemet/decode AOMASK */
218 /* Check if it matches an enabled MMIO region in the PEC stack */
219 if (memory_region_is_mapped(&phb
->stack
->mmbar0
) &&
220 base
>= phb
->stack
->mmio0_base
&&
221 (base
+ size
) <= (phb
->stack
->mmio0_base
+ phb
->stack
->mmio0_size
)) {
222 parent
= &phb
->stack
->mmbar0
;
223 base
-= phb
->stack
->mmio0_base
;
224 } else if (memory_region_is_mapped(&phb
->stack
->mmbar1
) &&
225 base
>= phb
->stack
->mmio1_base
&&
226 (base
+ size
) <= (phb
->stack
->mmio1_base
+ phb
->stack
->mmio1_size
)) {
227 parent
= &phb
->stack
->mmbar1
;
228 base
-= phb
->stack
->mmio1_base
;
230 phb_error(phb
, "PHB MBAR %d out of parent bounds", index
);
234 /* Create alias (better name ?) */
235 snprintf(name
, sizeof(name
), "phb4-mbar%d", index
);
236 memory_region_init_alias(&phb
->mr_mmio
[index
], OBJECT(phb
), name
,
237 &phb
->pci_mmio
, start
, size
);
238 memory_region_add_subregion(parent
, base
, &phb
->mr_mmio
[index
]);
241 static void pnv_phb4_check_all_mbt(PnvPHB4
*phb
)
244 uint32_t num_windows
= phb
->big_phb
? PNV_PHB4_MAX_MMIO_WINDOWS
:
245 PNV_PHB4_MIN_MMIO_WINDOWS
;
247 for (i
= 0; i
< num_windows
; i
++) {
248 pnv_phb4_check_mbt(phb
, i
);
252 static uint64_t *pnv_phb4_ioda_access(PnvPHB4
*phb
,
253 unsigned *out_table
, unsigned *out_idx
)
255 uint64_t adreg
= phb
->regs
[PHB_IODA_ADDR
>> 3];
256 unsigned int index
= GETFIELD(PHB_IODA_AD_TADR
, adreg
);
257 unsigned int table
= GETFIELD(PHB_IODA_AD_TSEL
, adreg
);
259 uint64_t *tptr
= NULL
;
263 tptr
= phb
->ioda_LIST
;
267 tptr
= phb
->ioda_MIST
;
268 mask
= phb
->big_phb
? PNV_PHB4_MAX_MIST
: (PNV_PHB4_MAX_MIST
>> 1);
272 mask
= phb
->big_phb
? 127 : 63;
275 mask
= phb
->big_phb
? 15 : 7;
277 case IODA3_TBL_PESTA
:
278 case IODA3_TBL_PESTB
:
279 mask
= phb
->big_phb
? PNV_PHB4_MAX_PEs
: (PNV_PHB4_MAX_PEs
>> 1);
283 tptr
= phb
->ioda_TVT
;
284 mask
= phb
->big_phb
? PNV_PHB4_MAX_TVEs
: (PNV_PHB4_MAX_TVEs
>> 1);
289 mask
= phb
->big_phb
? 1023 : 511;
292 tptr
= phb
->ioda_MBT
;
293 mask
= phb
->big_phb
? PNV_PHB4_MAX_MBEs
: (PNV_PHB4_MAX_MBEs
>> 1);
297 tptr
= phb
->ioda_MDT
;
298 mask
= phb
->big_phb
? PNV_PHB4_MAX_PEs
: (PNV_PHB4_MAX_PEs
>> 1);
302 tptr
= phb
->ioda_PEEV
;
303 mask
= phb
->big_phb
? PNV_PHB4_MAX_PEEVs
: (PNV_PHB4_MAX_PEEVs
>> 1);
307 phb_error(phb
, "invalid IODA table %d", table
);
320 if (adreg
& PHB_IODA_AD_AUTOINC
) {
321 index
= (index
+ 1) & mask
;
322 adreg
= SETFIELD(PHB_IODA_AD_TADR
, adreg
, index
);
325 phb
->regs
[PHB_IODA_ADDR
>> 3] = adreg
;
329 static uint64_t pnv_phb4_ioda_read(PnvPHB4
*phb
)
334 tptr
= pnv_phb4_ioda_access(phb
, &table
, &idx
);
336 /* Special PESTA case */
337 if (table
== IODA3_TBL_PESTA
) {
338 return ((uint64_t)(phb
->ioda_PEST_AB
[idx
] & 1)) << 63;
339 } else if (table
== IODA3_TBL_PESTB
) {
340 return ((uint64_t)(phb
->ioda_PEST_AB
[idx
] & 2)) << 62;
342 /* Return 0 on unsupported tables, not ff's */
348 static void pnv_phb4_ioda_write(PnvPHB4
*phb
, uint64_t val
)
353 tptr
= pnv_phb4_ioda_access(phb
, &table
, &idx
);
355 /* Special PESTA case */
356 if (table
== IODA3_TBL_PESTA
) {
357 phb
->ioda_PEST_AB
[idx
] &= ~1;
358 phb
->ioda_PEST_AB
[idx
] |= (val
>> 63) & 1;
359 } else if (table
== IODA3_TBL_PESTB
) {
360 phb
->ioda_PEST_AB
[idx
] &= ~2;
361 phb
->ioda_PEST_AB
[idx
] |= (val
>> 62) & 2;
366 /* Handle side effects */
370 case IODA3_TBL_MIST
: {
371 /* Special mask for MIST partial write */
372 uint64_t adreg
= phb
->regs
[PHB_IODA_ADDR
>> 3];
373 uint32_t mmask
= GETFIELD(PHB_IODA_AD_MIST_PWV
, adreg
);
379 v
&= 0x0000ffffffffffffull
;
380 v
|= 0xcfff000000000000ull
& val
;
383 v
&= 0xffff0000ffffffffull
;
384 v
|= 0x0000cfff00000000ull
& val
;
387 v
&= 0xffffffff0000ffffull
;
388 v
|= 0x00000000cfff0000ull
& val
;
391 v
&= 0xffffffffffff0000ull
;
392 v
|= 0x000000000000cfffull
& val
;
400 /* Copy accross the valid bit to the other half */
401 phb
->ioda_MBT
[idx
^ 1] &= 0x7fffffffffffffffull
;
402 phb
->ioda_MBT
[idx
^ 1] |= 0x8000000000000000ull
& val
;
404 /* Update mappings */
405 pnv_phb4_check_mbt(phb
, idx
>> 1);
412 static void pnv_phb4_rtc_invalidate(PnvPHB4
*phb
, uint64_t val
)
416 /* Always invalidate all for now ... */
417 QLIST_FOREACH(ds
, &phb
->dma_spaces
, list
) {
418 ds
->pe_num
= PHB_INVALID_PE
;
422 static void pnv_phb4_update_msi_regions(PnvPhb4DMASpace
*ds
)
424 uint64_t cfg
= ds
->phb
->regs
[PHB_PHB4_CONFIG
>> 3];
426 if (cfg
& PHB_PHB4C_32BIT_MSI_EN
) {
427 if (!memory_region_is_mapped(MEMORY_REGION(&ds
->msi32_mr
))) {
428 memory_region_add_subregion(MEMORY_REGION(&ds
->dma_mr
),
429 0xffff0000, &ds
->msi32_mr
);
432 if (memory_region_is_mapped(MEMORY_REGION(&ds
->msi32_mr
))) {
433 memory_region_del_subregion(MEMORY_REGION(&ds
->dma_mr
),
438 if (cfg
& PHB_PHB4C_64BIT_MSI_EN
) {
439 if (!memory_region_is_mapped(MEMORY_REGION(&ds
->msi64_mr
))) {
440 memory_region_add_subregion(MEMORY_REGION(&ds
->dma_mr
),
441 (1ull << 60), &ds
->msi64_mr
);
444 if (memory_region_is_mapped(MEMORY_REGION(&ds
->msi64_mr
))) {
445 memory_region_del_subregion(MEMORY_REGION(&ds
->dma_mr
),
451 static void pnv_phb4_update_all_msi_regions(PnvPHB4
*phb
)
455 QLIST_FOREACH(ds
, &phb
->dma_spaces
, list
) {
456 pnv_phb4_update_msi_regions(ds
);
460 static void pnv_phb4_update_xsrc(PnvPHB4
*phb
)
462 int shift
, flags
, i
, lsi_base
;
463 XiveSource
*xsrc
= &phb
->xsrc
;
465 /* The XIVE source characteristics can be set at run time */
466 if (phb
->regs
[PHB_CTRLR
>> 3] & PHB_CTRLR_IRQ_PGSZ_64K
) {
467 shift
= XIVE_ESB_64K
;
471 if (phb
->regs
[PHB_CTRLR
>> 3] & PHB_CTRLR_IRQ_STORE_EOI
) {
472 flags
= XIVE_SRC_STORE_EOI
;
477 phb
->xsrc
.esb_shift
= shift
;
478 phb
->xsrc
.esb_flags
= flags
;
480 lsi_base
= GETFIELD(PHB_LSI_SRC_ID
, phb
->regs
[PHB_LSI_SOURCE_ID
>> 3]);
483 /* TODO: handle reset values of PHB_LSI_SRC_ID */
488 /* TODO: need a xive_source_irq_reset_lsi() */
489 bitmap_zero(xsrc
->lsi_map
, xsrc
->nr_irqs
);
491 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
492 bool msi
= (i
< lsi_base
|| i
>= (lsi_base
+ 8));
494 xive_source_irq_set_lsi(xsrc
, i
);
499 static void pnv_phb4_reg_write(void *opaque
, hwaddr off
, uint64_t val
,
502 PnvPHB4
*phb
= PNV_PHB4(opaque
);
505 /* Special case outbound configuration data */
506 if ((off
& 0xfffc) == PHB_CONFIG_DATA
) {
507 pnv_phb4_config_write(phb
, off
& 0x3, size
, val
);
511 /* Special case RC configuration space */
512 if ((off
& 0xf800) == PHB_RC_CONFIG_BASE
) {
513 pnv_phb4_rc_config_write(phb
, off
& 0x7ff, size
, val
);
517 /* Other registers are 64-bit only */
518 if (size
!= 8 || off
& 0x7) {
519 phb_error(phb
, "Invalid register access, offset: 0x%"PRIx64
" size: %d",
526 case PHB_LSI_SOURCE_ID
:
527 val
&= PHB_LSI_SRC_ID
;
529 case PHB_M64_UPPER_BITS
:
530 val
&= 0xff00000000000000ull
;
534 /* Clear top 3 bits which HW does to indicate successful queuing */
535 val
&= ~(PHB_TCE_KILL_ALL
| PHB_TCE_KILL_PE
| PHB_TCE_KILL_ONE
);
539 * This is enough logic to make SW happy but we aren't
540 * actually quiescing the DMAs
542 if (val
& PHB_Q_DMA_R_AUTORESET
) {
545 val
&= PHB_Q_DMA_R_QUIESCE_DMA
;
549 case PHB_LEM_FIR_AND_MASK
:
550 phb
->regs
[PHB_LEM_FIR_ACCUM
>> 3] &= val
;
552 case PHB_LEM_FIR_OR_MASK
:
553 phb
->regs
[PHB_LEM_FIR_ACCUM
>> 3] |= val
;
555 case PHB_LEM_ERROR_AND_MASK
:
556 phb
->regs
[PHB_LEM_ERROR_MASK
>> 3] &= val
;
558 case PHB_LEM_ERROR_OR_MASK
:
559 phb
->regs
[PHB_LEM_ERROR_MASK
>> 3] |= val
;
564 /* TODO: More regs ..., maybe create a table with masks... */
566 /* Read only registers */
567 case PHB_CPU_LOADSTORE_STATUS
:
568 case PHB_ETU_ERR_SUMMARY
:
569 case PHB_PHB4_GEN_CAP
:
570 case PHB_PHB4_TCE_CAP
:
571 case PHB_PHB4_IRQ_CAP
:
572 case PHB_PHB4_EEH_CAP
:
576 /* Record whether it changed */
577 changed
= phb
->regs
[off
>> 3] != val
;
579 /* Store in register cache first */
580 phb
->regs
[off
>> 3] = val
;
582 /* Handle side effects */
584 case PHB_PHB4_CONFIG
:
586 pnv_phb4_update_all_msi_regions(phb
);
589 case PHB_M32_START_ADDR
:
590 case PHB_M64_UPPER_BITS
:
592 pnv_phb4_check_all_mbt(phb
);
596 /* IODA table accesses */
598 pnv_phb4_ioda_write(phb
, val
);
601 /* RTC invalidation */
602 case PHB_RTC_INVALIDATE
:
603 pnv_phb4_rtc_invalidate(phb
, val
);
606 /* PHB Control (Affects XIVE source) */
608 case PHB_LSI_SOURCE_ID
:
609 pnv_phb4_update_xsrc(phb
);
612 /* Silent simple writes */
614 case PHB_CONFIG_ADDRESS
:
617 case PHB_TCE_SPEC_CTL
:
621 case PHB_LEM_FIR_ACCUM
:
622 case PHB_LEM_ERROR_MASK
:
623 case PHB_LEM_ACTION0
:
624 case PHB_LEM_ACTION1
:
625 case PHB_TCE_TAG_ENABLE
:
626 case PHB_INT_NOTIFY_ADDR
:
627 case PHB_INT_NOTIFY_INDEX
:
631 /* Noise on anything else */
633 qemu_log_mask(LOG_UNIMP
, "phb4: reg_write 0x%"PRIx64
"=%"PRIx64
"\n",
638 static uint64_t pnv_phb4_reg_read(void *opaque
, hwaddr off
, unsigned size
)
640 PnvPHB4
*phb
= PNV_PHB4(opaque
);
643 if ((off
& 0xfffc) == PHB_CONFIG_DATA
) {
644 return pnv_phb4_config_read(phb
, off
& 0x3, size
);
647 /* Special case RC configuration space */
648 if ((off
& 0xf800) == PHB_RC_CONFIG_BASE
) {
649 return pnv_phb4_rc_config_read(phb
, off
& 0x7ff, size
);
652 /* Other registers are 64-bit only */
653 if (size
!= 8 || off
& 0x7) {
654 phb_error(phb
, "Invalid register access, offset: 0x%"PRIx64
" size: %d",
659 /* Default read from cache */
660 val
= phb
->regs
[off
>> 3];
667 case PHB_PHB4_GEN_CAP
:
668 return 0xe4b8000000000000ull
;
669 case PHB_PHB4_TCE_CAP
:
670 return phb
->big_phb
? 0x4008440000000400ull
: 0x2008440000000200ull
;
671 case PHB_PHB4_IRQ_CAP
:
672 return phb
->big_phb
? 0x0800000000001000ull
: 0x0800000000000800ull
;
673 case PHB_PHB4_EEH_CAP
:
674 return phb
->big_phb
? 0x2000000000000000ull
: 0x1000000000000000ull
;
676 /* IODA table accesses */
678 return pnv_phb4_ioda_read(phb
);
680 /* Link training always appears trained */
681 case PHB_PCIE_DLP_TRAIN_CTL
:
682 /* TODO: Do something sensible with speed ? */
683 return PHB_PCIE_DLP_INBAND_PRESENCE
| PHB_PCIE_DLP_TL_LINKACT
;
685 /* DMA read sync: make it look like it's complete */
687 return PHB_DMARD_SYNC_COMPLETE
;
689 /* Silent simple reads */
690 case PHB_LSI_SOURCE_ID
:
691 case PHB_CPU_LOADSTORE_STATUS
:
693 case PHB_PHB4_CONFIG
:
694 case PHB_M32_START_ADDR
:
695 case PHB_CONFIG_ADDRESS
:
697 case PHB_RTC_INVALIDATE
:
699 case PHB_TCE_SPEC_CTL
:
703 case PHB_M64_UPPER_BITS
:
705 case PHB_LEM_FIR_ACCUM
:
706 case PHB_LEM_ERROR_MASK
:
707 case PHB_LEM_ACTION0
:
708 case PHB_LEM_ACTION1
:
709 case PHB_TCE_TAG_ENABLE
:
710 case PHB_INT_NOTIFY_ADDR
:
711 case PHB_INT_NOTIFY_INDEX
:
713 case PHB_ETU_ERR_SUMMARY
:
716 /* Noise on anything else */
718 qemu_log_mask(LOG_UNIMP
, "phb4: reg_read 0x%"PRIx64
"=%"PRIx64
"\n",
724 static const MemoryRegionOps pnv_phb4_reg_ops
= {
725 .read
= pnv_phb4_reg_read
,
726 .write
= pnv_phb4_reg_write
,
727 .valid
.min_access_size
= 1,
728 .valid
.max_access_size
= 8,
729 .impl
.min_access_size
= 1,
730 .impl
.max_access_size
= 8,
731 .endianness
= DEVICE_BIG_ENDIAN
,
734 static uint64_t pnv_phb4_xscom_read(void *opaque
, hwaddr addr
, unsigned size
)
736 PnvPHB4
*phb
= PNV_PHB4(opaque
);
737 uint32_t reg
= addr
>> 3;
742 case PHB_SCOM_HV_IND_ADDR
:
743 return phb
->scom_hv_ind_addr_reg
;
745 case PHB_SCOM_HV_IND_DATA
:
746 if (!(phb
->scom_hv_ind_addr_reg
& PHB_SCOM_HV_IND_ADDR_VALID
)) {
747 phb_error(phb
, "Invalid indirect address");
750 size
= (phb
->scom_hv_ind_addr_reg
& PHB_SCOM_HV_IND_ADDR_4B
) ? 4 : 8;
751 offset
= GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR
, phb
->scom_hv_ind_addr_reg
);
752 val
= pnv_phb4_reg_read(phb
, offset
, size
);
753 if (phb
->scom_hv_ind_addr_reg
& PHB_SCOM_HV_IND_ADDR_AUTOINC
) {
756 phb
->scom_hv_ind_addr_reg
= SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR
,
757 phb
->scom_hv_ind_addr_reg
,
761 case PHB_SCOM_ETU_LEM_FIR
:
762 case PHB_SCOM_ETU_LEM_FIR_AND
:
763 case PHB_SCOM_ETU_LEM_FIR_OR
:
764 case PHB_SCOM_ETU_LEM_FIR_MSK
:
765 case PHB_SCOM_ETU_LEM_ERR_MSK_AND
:
766 case PHB_SCOM_ETU_LEM_ERR_MSK_OR
:
767 case PHB_SCOM_ETU_LEM_ACT0
:
768 case PHB_SCOM_ETU_LEM_ACT1
:
769 case PHB_SCOM_ETU_LEM_WOF
:
770 offset
= ((reg
- PHB_SCOM_ETU_LEM_FIR
) << 3) + PHB_LEM_FIR_ACCUM
;
771 return pnv_phb4_reg_read(phb
, offset
, size
);
772 case PHB_SCOM_ETU_PMON_CONFIG
:
773 case PHB_SCOM_ETU_PMON_CTR0
:
774 case PHB_SCOM_ETU_PMON_CTR1
:
775 case PHB_SCOM_ETU_PMON_CTR2
:
776 case PHB_SCOM_ETU_PMON_CTR3
:
777 offset
= ((reg
- PHB_SCOM_ETU_PMON_CONFIG
) << 3) + PHB_PERFMON_CONFIG
;
778 return pnv_phb4_reg_read(phb
, offset
, size
);
781 qemu_log_mask(LOG_UNIMP
, "phb4: xscom_read 0x%"HWADDR_PRIx
"\n", addr
);
786 static void pnv_phb4_xscom_write(void *opaque
, hwaddr addr
,
787 uint64_t val
, unsigned size
)
789 PnvPHB4
*phb
= PNV_PHB4(opaque
);
790 uint32_t reg
= addr
>> 3;
794 case PHB_SCOM_HV_IND_ADDR
:
795 phb
->scom_hv_ind_addr_reg
= val
& 0xe000000000001fff;
797 case PHB_SCOM_HV_IND_DATA
:
798 if (!(phb
->scom_hv_ind_addr_reg
& PHB_SCOM_HV_IND_ADDR_VALID
)) {
799 phb_error(phb
, "Invalid indirect address");
802 size
= (phb
->scom_hv_ind_addr_reg
& PHB_SCOM_HV_IND_ADDR_4B
) ? 4 : 8;
803 offset
= GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR
, phb
->scom_hv_ind_addr_reg
);
804 pnv_phb4_reg_write(phb
, offset
, val
, size
);
805 if (phb
->scom_hv_ind_addr_reg
& PHB_SCOM_HV_IND_ADDR_AUTOINC
) {
808 phb
->scom_hv_ind_addr_reg
= SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR
,
809 phb
->scom_hv_ind_addr_reg
,
813 case PHB_SCOM_ETU_LEM_FIR
:
814 case PHB_SCOM_ETU_LEM_FIR_AND
:
815 case PHB_SCOM_ETU_LEM_FIR_OR
:
816 case PHB_SCOM_ETU_LEM_FIR_MSK
:
817 case PHB_SCOM_ETU_LEM_ERR_MSK_AND
:
818 case PHB_SCOM_ETU_LEM_ERR_MSK_OR
:
819 case PHB_SCOM_ETU_LEM_ACT0
:
820 case PHB_SCOM_ETU_LEM_ACT1
:
821 case PHB_SCOM_ETU_LEM_WOF
:
822 offset
= ((reg
- PHB_SCOM_ETU_LEM_FIR
) << 3) + PHB_LEM_FIR_ACCUM
;
823 pnv_phb4_reg_write(phb
, offset
, val
, size
);
825 case PHB_SCOM_ETU_PMON_CONFIG
:
826 case PHB_SCOM_ETU_PMON_CTR0
:
827 case PHB_SCOM_ETU_PMON_CTR1
:
828 case PHB_SCOM_ETU_PMON_CTR2
:
829 case PHB_SCOM_ETU_PMON_CTR3
:
830 offset
= ((reg
- PHB_SCOM_ETU_PMON_CONFIG
) << 3) + PHB_PERFMON_CONFIG
;
831 pnv_phb4_reg_write(phb
, offset
, val
, size
);
834 qemu_log_mask(LOG_UNIMP
, "phb4: xscom_write 0x%"HWADDR_PRIx
835 "=%"PRIx64
"\n", addr
, val
);
839 const MemoryRegionOps pnv_phb4_xscom_ops
= {
840 .read
= pnv_phb4_xscom_read
,
841 .write
= pnv_phb4_xscom_write
,
842 .valid
.min_access_size
= 8,
843 .valid
.max_access_size
= 8,
844 .impl
.min_access_size
= 8,
845 .impl
.max_access_size
= 8,
846 .endianness
= DEVICE_BIG_ENDIAN
,
849 static int pnv_phb4_map_irq(PCIDevice
*pci_dev
, int irq_num
)
851 /* Check that out properly ... */
855 static void pnv_phb4_set_irq(void *opaque
, int irq_num
, int level
)
857 PnvPHB4
*phb
= PNV_PHB4(opaque
);
862 phb_error(phb
, "IRQ %x is not an LSI", irq_num
);
864 lsi_base
= GETFIELD(PHB_LSI_SRC_ID
, phb
->regs
[PHB_LSI_SOURCE_ID
>> 3]);
866 qemu_set_irq(phb
->qirqs
[lsi_base
+ irq_num
], level
);
869 static bool pnv_phb4_resolve_pe(PnvPhb4DMASpace
*ds
)
876 /* Already resolved ? */
877 if (ds
->pe_num
!= PHB_INVALID_PE
) {
881 /* We need to lookup the RTT */
882 rtt
= ds
->phb
->regs
[PHB_RTT_BAR
>> 3];
883 if (!(rtt
& PHB_RTT_BAR_ENABLE
)) {
884 phb_error(ds
->phb
, "DMA with RTT BAR disabled !");
885 /* Set error bits ? fence ? ... */
890 bus_num
= pci_bus_num(ds
->bus
);
891 addr
= rtt
& PHB_RTT_BASE_ADDRESS_MASK
;
892 addr
+= 2 * ((bus_num
<< 8) | ds
->devfn
);
893 if (dma_memory_read(&address_space_memory
, addr
, &rte
, sizeof(rte
))) {
894 phb_error(ds
->phb
, "Failed to read RTT entry at 0x%"PRIx64
, addr
);
895 /* Set error bits ? fence ? ... */
898 rte
= be16_to_cpu(rte
);
900 /* Fail upon reading of invalid PE# */
901 num_PEs
= ds
->phb
->big_phb
? PNV_PHB4_MAX_PEs
: (PNV_PHB4_MAX_PEs
>> 1);
902 if (rte
>= num_PEs
) {
903 phb_error(ds
->phb
, "RTE for RID 0x%x invalid (%04x", ds
->devfn
, rte
);
910 static void pnv_phb4_translate_tve(PnvPhb4DMASpace
*ds
, hwaddr addr
,
911 bool is_write
, uint64_t tve
,
914 uint64_t tta
= GETFIELD(IODA3_TVT_TABLE_ADDR
, tve
);
915 int32_t lev
= GETFIELD(IODA3_TVT_NUM_LEVELS
, tve
);
916 uint32_t tts
= GETFIELD(IODA3_TVT_TCE_TABLE_SIZE
, tve
);
917 uint32_t tps
= GETFIELD(IODA3_TVT_IO_PSIZE
, tve
);
921 phb_error(ds
->phb
, "Invalid #levels in TVE %d", lev
);
927 phb_error(ds
->phb
, "Access to invalid TVE");
931 /* IO Page Size of 0 means untranslated, else use TCEs */
933 /* TODO: Handle boundaries */
935 /* Use 4k pages like q35 ... for now */
936 tlb
->iova
= addr
& 0xfffffffffffff000ull
;
937 tlb
->translated_addr
= addr
& 0x0003fffffffff000ull
;
938 tlb
->addr_mask
= 0xfffull
;
939 tlb
->perm
= IOMMU_RW
;
941 uint32_t tce_shift
, tbl_shift
, sh
;
942 uint64_t base
, taddr
, tce
, tce_mask
;
944 /* Address bits per bottom level TCE entry */
945 tce_shift
= tps
+ 11;
947 /* Address bits per table level */
950 /* Top level table base address */
953 /* Total shift to first level */
954 sh
= tbl_shift
* lev
+ tce_shift
;
956 /* TODO: Limit to support IO page sizes */
958 /* TODO: Multi-level untested */
959 while ((lev
--) >= 0) {
960 /* Grab the TCE address */
961 taddr
= base
| (((addr
>> sh
) & ((1ul << tbl_shift
) - 1)) << 3);
962 if (dma_memory_read(&address_space_memory
, taddr
, &tce
,
964 phb_error(ds
->phb
, "Failed to read TCE at 0x%"PRIx64
, taddr
);
967 tce
= be64_to_cpu(tce
);
969 /* Check permission for indirect TCE */
970 if ((lev
>= 0) && !(tce
& 3)) {
971 phb_error(ds
->phb
, "Invalid indirect TCE at 0x%"PRIx64
, taddr
);
972 phb_error(ds
->phb
, " xlate %"PRIx64
":%c TVE=%"PRIx64
, addr
,
973 is_write
? 'W' : 'R', tve
);
974 phb_error(ds
->phb
, " tta=%"PRIx64
" lev=%d tts=%d tps=%d",
979 base
= tce
& ~0xfffull
;
982 /* We exit the loop with TCE being the final TCE */
983 tce_mask
= ~((1ull << tce_shift
) - 1);
984 tlb
->iova
= addr
& tce_mask
;
985 tlb
->translated_addr
= tce
& tce_mask
;
986 tlb
->addr_mask
= ~tce_mask
;
988 if ((is_write
& !(tce
& 2)) || ((!is_write
) && !(tce
& 1))) {
989 phb_error(ds
->phb
, "TCE access fault at 0x%"PRIx64
, taddr
);
990 phb_error(ds
->phb
, " xlate %"PRIx64
":%c TVE=%"PRIx64
, addr
,
991 is_write
? 'W' : 'R', tve
);
992 phb_error(ds
->phb
, " tta=%"PRIx64
" lev=%d tts=%d tps=%d",
998 static IOMMUTLBEntry
pnv_phb4_translate_iommu(IOMMUMemoryRegion
*iommu
,
1000 IOMMUAccessFlags flag
,
1003 PnvPhb4DMASpace
*ds
= container_of(iommu
, PnvPhb4DMASpace
, dma_mr
);
1006 IOMMUTLBEntry ret
= {
1007 .target_as
= &address_space_memory
,
1009 .translated_addr
= 0,
1010 .addr_mask
= ~(hwaddr
)0,
1015 if (!pnv_phb4_resolve_pe(ds
)) {
1016 phb_error(ds
->phb
, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
1017 ds
->bus
, pci_bus_num(ds
->bus
), ds
->devfn
);
1021 /* Check top bits */
1022 switch (addr
>> 60) {
1024 /* DMA or 32-bit MSI ? */
1025 cfg
= ds
->phb
->regs
[PHB_PHB4_CONFIG
>> 3];
1026 if ((cfg
& PHB_PHB4C_32BIT_MSI_EN
) &&
1027 ((addr
& 0xffffffffffff0000ull
) == 0xffff0000ull
)) {
1028 phb_error(ds
->phb
, "xlate on 32-bit MSI region");
1031 /* Choose TVE XXX Use PHB4 Control Register */
1032 tve_sel
= (addr
>> 59) & 1;
1033 tve
= ds
->phb
->ioda_TVT
[ds
->pe_num
* 2 + tve_sel
];
1034 pnv_phb4_translate_tve(ds
, addr
, flag
& IOMMU_WO
, tve
, &ret
);
1037 phb_error(ds
->phb
, "xlate on 64-bit MSI region");
1040 phb_error(ds
->phb
, "xlate on unsupported address 0x%"PRIx64
, addr
);
1045 #define TYPE_PNV_PHB4_IOMMU_MEMORY_REGION "pnv-phb4-iommu-memory-region"
1046 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion
, PNV_PHB4_IOMMU_MEMORY_REGION
,
1047 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION
)
1049 static void pnv_phb4_iommu_memory_region_class_init(ObjectClass
*klass
,
1052 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
1054 imrc
->translate
= pnv_phb4_translate_iommu
;
1057 static const TypeInfo pnv_phb4_iommu_memory_region_info
= {
1058 .parent
= TYPE_IOMMU_MEMORY_REGION
,
1059 .name
= TYPE_PNV_PHB4_IOMMU_MEMORY_REGION
,
1060 .class_init
= pnv_phb4_iommu_memory_region_class_init
,
1064 * MSI/MSIX memory region implementation.
1065 * The handler handles both MSI and MSIX.
1067 static void pnv_phb4_msi_write(void *opaque
, hwaddr addr
,
1068 uint64_t data
, unsigned size
)
1070 PnvPhb4DMASpace
*ds
= opaque
;
1071 PnvPHB4
*phb
= ds
->phb
;
1073 uint32_t src
= ((addr
>> 4) & 0xffff) | (data
& 0x1f);
1076 if (!pnv_phb4_resolve_pe(ds
)) {
1077 phb_error(phb
, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",
1078 ds
->bus
, pci_bus_num(ds
->bus
), ds
->devfn
);
1082 /* TODO: Check it doesn't collide with LSIs */
1083 if (src
>= phb
->xsrc
.nr_irqs
) {
1084 phb_error(phb
, "MSI %d out of bounds", src
);
1088 /* TODO: check PE/MSI assignement */
1090 qemu_irq_pulse(phb
->qirqs
[src
]);
1093 /* There is no .read as the read result is undefined by PCI spec */
1094 static uint64_t pnv_phb4_msi_read(void *opaque
, hwaddr addr
, unsigned size
)
1096 PnvPhb4DMASpace
*ds
= opaque
;
1098 phb_error(ds
->phb
, "Invalid MSI read @ 0x%" HWADDR_PRIx
, addr
);
1102 static const MemoryRegionOps pnv_phb4_msi_ops
= {
1103 .read
= pnv_phb4_msi_read
,
1104 .write
= pnv_phb4_msi_write
,
1105 .endianness
= DEVICE_LITTLE_ENDIAN
1108 static PnvPhb4DMASpace
*pnv_phb4_dma_find(PnvPHB4
*phb
, PCIBus
*bus
, int devfn
)
1110 PnvPhb4DMASpace
*ds
;
1112 QLIST_FOREACH(ds
, &phb
->dma_spaces
, list
) {
1113 if (ds
->bus
== bus
&& ds
->devfn
== devfn
) {
1120 static AddressSpace
*pnv_phb4_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
1122 PnvPHB4
*phb
= opaque
;
1123 PnvPhb4DMASpace
*ds
;
1126 ds
= pnv_phb4_dma_find(phb
, bus
, devfn
);
1129 ds
= g_malloc0(sizeof(PnvPhb4DMASpace
));
1132 ds
->pe_num
= PHB_INVALID_PE
;
1134 snprintf(name
, sizeof(name
), "phb4-%d.%d-iommu", phb
->chip_id
,
1136 memory_region_init_iommu(&ds
->dma_mr
, sizeof(ds
->dma_mr
),
1137 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION
,
1138 OBJECT(phb
), name
, UINT64_MAX
);
1139 address_space_init(&ds
->dma_as
, MEMORY_REGION(&ds
->dma_mr
),
1141 memory_region_init_io(&ds
->msi32_mr
, OBJECT(phb
), &pnv_phb4_msi_ops
,
1142 ds
, "msi32", 0x10000);
1143 memory_region_init_io(&ds
->msi64_mr
, OBJECT(phb
), &pnv_phb4_msi_ops
,
1144 ds
, "msi64", 0x100000);
1145 pnv_phb4_update_msi_regions(ds
);
1147 QLIST_INSERT_HEAD(&phb
->dma_spaces
, ds
, list
);
1152 static void pnv_phb4_instance_init(Object
*obj
)
1154 PnvPHB4
*phb
= PNV_PHB4(obj
);
1156 QLIST_INIT(&phb
->dma_spaces
);
1158 /* XIVE interrupt source object */
1159 object_initialize_child(obj
, "source", &phb
->xsrc
, TYPE_XIVE_SOURCE
);
1162 object_initialize_child(obj
, "root", &phb
->root
, TYPE_PNV_PHB4_ROOT_PORT
);
1164 qdev_prop_set_int32(DEVICE(&phb
->root
), "addr", PCI_DEVFN(0, 0));
1165 qdev_prop_set_bit(DEVICE(&phb
->root
), "multifunction", false);
1168 static void pnv_phb4_realize(DeviceState
*dev
, Error
**errp
)
1170 PnvPHB4
*phb
= PNV_PHB4(dev
);
1171 PCIHostState
*pci
= PCI_HOST_BRIDGE(dev
);
1172 XiveSource
*xsrc
= &phb
->xsrc
;
1178 /* Set the "big_phb" flag */
1179 phb
->big_phb
= phb
->phb_id
== 0 || phb
->phb_id
== 3;
1181 /* Controller Registers */
1182 snprintf(name
, sizeof(name
), "phb4-%d.%d-regs", phb
->chip_id
,
1184 memory_region_init_io(&phb
->mr_regs
, OBJECT(phb
), &pnv_phb4_reg_ops
, phb
,
1188 * PHB4 doesn't support IO space. However, qemu gets very upset if
1189 * we don't have an IO region to anchor IO BARs onto so we just
1190 * initialize one which we never hook up to anything
1193 snprintf(name
, sizeof(name
), "phb4-%d.%d-pci-io", phb
->chip_id
,
1195 memory_region_init(&phb
->pci_io
, OBJECT(phb
), name
, 0x10000);
1197 snprintf(name
, sizeof(name
), "phb4-%d.%d-pci-mmio", phb
->chip_id
,
1199 memory_region_init(&phb
->pci_mmio
, OBJECT(phb
), name
,
1200 PCI_MMIO_TOTAL_SIZE
);
1202 pci
->bus
= pci_register_root_bus(dev
, "root-bus",
1203 pnv_phb4_set_irq
, pnv_phb4_map_irq
, phb
,
1204 &phb
->pci_mmio
, &phb
->pci_io
,
1205 0, 4, TYPE_PNV_PHB4_ROOT_BUS
);
1206 pci_setup_iommu(pci
->bus
, pnv_phb4_dma_iommu
, phb
);
1208 /* Add a single Root port */
1209 qdev_prop_set_uint8(DEVICE(&phb
->root
), "chassis", phb
->chip_id
);
1210 qdev_prop_set_uint16(DEVICE(&phb
->root
), "slot", phb
->phb_id
);
1211 qdev_realize(DEVICE(&phb
->root
), BUS(pci
->bus
), &error_fatal
);
1213 /* Setup XIVE Source */
1215 nr_irqs
= PNV_PHB4_MAX_INTs
;
1217 nr_irqs
= PNV_PHB4_MAX_INTs
>> 1;
1219 object_property_set_int(OBJECT(xsrc
), "nr-irqs", nr_irqs
, &error_fatal
);
1220 object_property_set_link(OBJECT(xsrc
), "xive", OBJECT(phb
), &error_fatal
);
1221 if (!qdev_realize(DEVICE(xsrc
), NULL
, errp
)) {
1225 pnv_phb4_update_xsrc(phb
);
1227 phb
->qirqs
= qemu_allocate_irqs(xive_source_set_irq
, xsrc
, xsrc
->nr_irqs
);
1230 static void pnv_phb4_reset(DeviceState
*dev
)
1232 PnvPHB4
*phb
= PNV_PHB4(dev
);
1233 PCIDevice
*root_dev
= PCI_DEVICE(&phb
->root
);
1236 * Configure PCI device id at reset using a property.
1238 pci_config_set_vendor_id(root_dev
->config
, PCI_VENDOR_ID_IBM
);
1239 pci_config_set_device_id(root_dev
->config
, phb
->device_id
);
1242 static const char *pnv_phb4_root_bus_path(PCIHostState
*host_bridge
,
1245 PnvPHB4
*phb
= PNV_PHB4(host_bridge
);
1247 snprintf(phb
->bus_path
, sizeof(phb
->bus_path
), "00%02x:%02x",
1248 phb
->chip_id
, phb
->phb_id
);
1249 return phb
->bus_path
;
1252 static void pnv_phb4_xive_notify(XiveNotifier
*xf
, uint32_t srcno
)
1254 PnvPHB4
*phb
= PNV_PHB4(xf
);
1255 uint64_t notif_port
= phb
->regs
[PHB_INT_NOTIFY_ADDR
>> 3];
1256 uint32_t offset
= phb
->regs
[PHB_INT_NOTIFY_INDEX
>> 3];
1257 uint64_t data
= XIVE_TRIGGER_PQ
| offset
| srcno
;
1260 address_space_stq_be(&address_space_memory
, notif_port
, data
,
1261 MEMTXATTRS_UNSPECIFIED
, &result
);
1262 if (result
!= MEMTX_OK
) {
1263 phb_error(phb
, "trigger failed @%"HWADDR_PRIx
"\n", notif_port
);
1268 static Property pnv_phb4_properties
[] = {
1269 DEFINE_PROP_UINT32("index", PnvPHB4
, phb_id
, 0),
1270 DEFINE_PROP_UINT32("chip-id", PnvPHB4
, chip_id
, 0),
1271 DEFINE_PROP_UINT64("version", PnvPHB4
, version
, 0),
1272 DEFINE_PROP_UINT16("device-id", PnvPHB4
, device_id
, 0),
1273 DEFINE_PROP_LINK("stack", PnvPHB4
, stack
, TYPE_PNV_PHB4_PEC_STACK
,
1275 DEFINE_PROP_END_OF_LIST(),
1278 static void pnv_phb4_class_init(ObjectClass
*klass
, void *data
)
1280 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
1281 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1282 XiveNotifierClass
*xfc
= XIVE_NOTIFIER_CLASS(klass
);
1284 hc
->root_bus_path
= pnv_phb4_root_bus_path
;
1285 dc
->realize
= pnv_phb4_realize
;
1286 device_class_set_props(dc
, pnv_phb4_properties
);
1287 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1288 dc
->user_creatable
= false;
1289 dc
->reset
= pnv_phb4_reset
;
1291 xfc
->notify
= pnv_phb4_xive_notify
;
1294 static const TypeInfo pnv_phb4_type_info
= {
1295 .name
= TYPE_PNV_PHB4
,
1296 .parent
= TYPE_PCIE_HOST_BRIDGE
,
1297 .instance_init
= pnv_phb4_instance_init
,
1298 .instance_size
= sizeof(PnvPHB4
),
1299 .class_init
= pnv_phb4_class_init
,
1300 .interfaces
= (InterfaceInfo
[]) {
1301 { TYPE_XIVE_NOTIFIER
},
1306 static void pnv_phb4_root_bus_class_init(ObjectClass
*klass
, void *data
)
1308 BusClass
*k
= BUS_CLASS(klass
);
1311 * PHB4 has only a single root complex. Enforce the limit on the
1317 static const TypeInfo pnv_phb4_root_bus_info
= {
1318 .name
= TYPE_PNV_PHB4_ROOT_BUS
,
1319 .parent
= TYPE_PCIE_BUS
,
1320 .class_init
= pnv_phb4_root_bus_class_init
,
1321 .interfaces
= (InterfaceInfo
[]) {
1322 { INTERFACE_PCIE_DEVICE
},
1327 static void pnv_phb4_root_port_reset(DeviceState
*dev
)
1329 PCIERootPortClass
*rpc
= PCIE_ROOT_PORT_GET_CLASS(dev
);
1330 PCIDevice
*d
= PCI_DEVICE(dev
);
1331 uint8_t *conf
= d
->config
;
1333 rpc
->parent_reset(dev
);
1335 pci_byte_test_and_set_mask(conf
+ PCI_IO_BASE
,
1336 PCI_IO_RANGE_MASK
& 0xff);
1337 pci_byte_test_and_clear_mask(conf
+ PCI_IO_LIMIT
,
1338 PCI_IO_RANGE_MASK
& 0xff);
1339 pci_set_word(conf
+ PCI_MEMORY_BASE
, 0);
1340 pci_set_word(conf
+ PCI_MEMORY_LIMIT
, 0xfff0);
1341 pci_set_word(conf
+ PCI_PREF_MEMORY_BASE
, 0x1);
1342 pci_set_word(conf
+ PCI_PREF_MEMORY_LIMIT
, 0xfff1);
1343 pci_set_long(conf
+ PCI_PREF_BASE_UPPER32
, 0x1); /* Hack */
1344 pci_set_long(conf
+ PCI_PREF_LIMIT_UPPER32
, 0xffffffff);
1347 static void pnv_phb4_root_port_realize(DeviceState
*dev
, Error
**errp
)
1349 PCIERootPortClass
*rpc
= PCIE_ROOT_PORT_GET_CLASS(dev
);
1350 Error
*local_err
= NULL
;
1352 rpc
->parent_realize(dev
, &local_err
);
1354 error_propagate(errp
, local_err
);
1359 static void pnv_phb4_root_port_class_init(ObjectClass
*klass
, void *data
)
1361 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1362 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1363 PCIERootPortClass
*rpc
= PCIE_ROOT_PORT_CLASS(klass
);
1365 dc
->desc
= "IBM PHB4 PCIE Root Port";
1366 dc
->user_creatable
= false;
1368 device_class_set_parent_realize(dc
, pnv_phb4_root_port_realize
,
1369 &rpc
->parent_realize
);
1370 device_class_set_parent_reset(dc
, pnv_phb4_root_port_reset
,
1371 &rpc
->parent_reset
);
1373 k
->vendor_id
= PCI_VENDOR_ID_IBM
;
1374 k
->device_id
= PNV_PHB4_DEVICE_ID
;
1377 rpc
->exp_offset
= 0x48;
1378 rpc
->aer_offset
= 0x100;
1380 dc
->reset
= &pnv_phb4_root_port_reset
;
1383 static const TypeInfo pnv_phb4_root_port_info
= {
1384 .name
= TYPE_PNV_PHB4_ROOT_PORT
,
1385 .parent
= TYPE_PCIE_ROOT_PORT
,
1386 .instance_size
= sizeof(PnvPHB4RootPort
),
1387 .class_init
= pnv_phb4_root_port_class_init
,
1390 static void pnv_phb4_register_types(void)
1392 type_register_static(&pnv_phb4_root_bus_info
);
1393 type_register_static(&pnv_phb4_root_port_info
);
1394 type_register_static(&pnv_phb4_type_info
);
1395 type_register_static(&pnv_phb4_iommu_memory_region_info
);
1398 type_init(pnv_phb4_register_types
);
1400 void pnv_phb4_update_regions(PnvPhb4PecStack
*stack
)
1402 PnvPHB4
*phb
= &stack
->phb
;
1404 /* Unmap first always */
1405 if (memory_region_is_mapped(&phb
->mr_regs
)) {
1406 memory_region_del_subregion(&stack
->phbbar
, &phb
->mr_regs
);
1408 if (memory_region_is_mapped(&phb
->xsrc
.esb_mmio
)) {
1409 memory_region_del_subregion(&stack
->intbar
, &phb
->xsrc
.esb_mmio
);
1412 /* Map registers if enabled */
1413 if (memory_region_is_mapped(&stack
->phbbar
)) {
1414 memory_region_add_subregion(&stack
->phbbar
, 0, &phb
->mr_regs
);
1417 /* Map ESB if enabled */
1418 if (memory_region_is_mapped(&stack
->intbar
)) {
1419 memory_region_add_subregion(&stack
->intbar
, 0, &phb
->xsrc
.esb_mmio
);
1422 /* Check/update m32 */
1423 pnv_phb4_check_all_mbt(phb
);
1426 void pnv_phb4_pic_print_info(PnvPHB4
*phb
, Monitor
*mon
)
1428 uint32_t offset
= phb
->regs
[PHB_INT_NOTIFY_INDEX
>> 3];
1430 monitor_printf(mon
, "PHB4[%x:%x] Source %08x .. %08x\n",
1431 phb
->chip_id
, phb
->phb_id
,
1432 offset
, offset
+ phb
->xsrc
.nr_irqs
- 1);
1433 xive_source_pic_print_info(&phb
->xsrc
, 0, mon
);