hw/arm/xlnx-versal.c

   1 /*
   2  * Xilinx Versal SoC model.
   3  *
   4  * Copyright (c) 2018 Xilinx Inc.
   5  * Written by Edgar E. Iglesias
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu/log.h"
  15 #include "qemu/module.h"
  16 #include "hw/sysbus.h"
  17 #include "net/net.h"
  18 #include "sysemu/sysemu.h"
  19 #include "sysemu/kvm.h"
  20 #include "hw/arm/boot.h"
  21 #include "kvm_arm.h"
  22 #include "hw/misc/unimp.h"
  23 #include "hw/arm/xlnx-versal.h"
  24
  25 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
  26 #define GEM_REVISION        0x40070106
  27
  28 static void versal_create_apu_cpus(Versal *s)
  29 {
  30     int i;
  31
  32     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
  33         Object *obj;
  34
  35         object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
  36                                 XLNX_VERSAL_ACPU_TYPE);
  37         obj = OBJECT(&s->fpd.apu.cpu[i]);
  38         object_property_set_int(obj, s->cfg.psci_conduit,
  39                                 "psci-conduit", &error_abort);
  40         if (i) {
  41             /* Secondary CPUs start in PSCI powered-down state */
  42             object_property_set_bool(obj, true,
  43                                      "start-powered-off", &error_abort);
  44         }
  45
  46         object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),
  47                                 "core-count", &error_abort);
  48         object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
  49                                  &error_abort);
  50         object_property_set_bool(obj, true, "realized", &error_fatal);
  51     }
  52 }
  53
  54 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
  55 {
  56     static const uint64_t addrs[] = {
  57         MM_GIC_APU_DIST_MAIN,
  58         MM_GIC_APU_REDIST_0
  59     };
  60     SysBusDevice *gicbusdev;
  61     DeviceState *gicdev;
  62     int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
  63     int i;
  64
  65     sysbus_init_child_obj(OBJECT(s), "apu-gic",
  66                           &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
  67                           gicv3_class_name());
  68     gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
  69     gicdev = DEVICE(&s->fpd.apu.gic);
  70     qdev_prop_set_uint32(gicdev, "revision", 3);
  71     qdev_prop_set_uint32(gicdev, "num-cpu", 2);
  72     qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
  73     qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
  74     qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
  75     qdev_prop_set_bit(gicdev, "has-security-extensions", true);
  76
  77     object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
  78                                     &error_fatal);
  79
  80     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
  81         MemoryRegion *mr;
  82
  83         mr = sysbus_mmio_get_region(gicbusdev, i);
  84         memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
  85     }
  86
  87     for (i = 0; i < nr_apu_cpus; i++) {
  88         DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
  89         int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
  90         qemu_irq maint_irq;
  91         int ti;
  92         /* Mapping from the output timer irq lines from the CPU to the
  93          * GIC PPI inputs.
  94          */
  95         const int timer_irq[] = {
  96             [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
  97             [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
  98             [GTIMER_HYP]  = VERSAL_TIMER_NS_EL2_IRQ,
  99             [GTIMER_SEC]  = VERSAL_TIMER_S_EL1_IRQ,
 100         };
 101
 102         for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
 103             qdev_connect_gpio_out(cpudev, ti,
 104                                   qdev_get_gpio_in(gicdev,
 105                                                    ppibase + timer_irq[ti]));
 106         }
 107         maint_irq = qdev_get_gpio_in(gicdev,
 108                                         ppibase + VERSAL_GIC_MAINT_IRQ);
 109         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
 110                                     0, maint_irq);
 111         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 112         sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
 113                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 114         sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
 115                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 116         sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
 117                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 118     }
 119
 120     for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
 121         pic[i] = qdev_get_gpio_in(gicdev, i);
 122     }
 123 }
 124
 125 static void versal_create_uarts(Versal *s, qemu_irq *pic)
 126 {
 127     int i;
 128
 129     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
 130         static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
 131         static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
 132         char *name = g_strdup_printf("uart%d", i);
 133         DeviceState *dev;
 134         MemoryRegion *mr;
 135
 136         sysbus_init_child_obj(OBJECT(s), name,
 137                               &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),
 138                               TYPE_PL011);
 139         dev = DEVICE(&s->lpd.iou.uart[i]);
 140         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 141         qdev_init_nofail(dev);
 142
 143         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 144         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 145
 146         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
 147         g_free(name);
 148     }
 149 }
 150
 151 static void versal_create_gems(Versal *s, qemu_irq *pic)
 152 {
 153     int i;
 154
 155     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
 156         static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
 157         static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
 158         char *name = g_strdup_printf("gem%d", i);
 159         NICInfo *nd = &nd_table[i];
 160         DeviceState *dev;
 161         MemoryRegion *mr;
 162
 163         sysbus_init_child_obj(OBJECT(s), name,
 164                               &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
 165                               TYPE_CADENCE_GEM);
 166         dev = DEVICE(&s->lpd.iou.gem[i]);
 167         if (nd->used) {
 168             qemu_check_nic_model(nd, "cadence_gem");
 169             qdev_set_nic_properties(dev, nd);
 170         }
 171         object_property_set_int(OBJECT(dev),
 172                                 2, "num-priority-queues",
 173                                 &error_abort);
 174         object_property_set_link(OBJECT(dev),
 175                                  OBJECT(&s->mr_ps), "dma",
 176                                  &error_abort);
 177         qdev_init_nofail(dev);
 178
 179         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 180         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 181
 182         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
 183         g_free(name);
 184     }
 185 }
 186
 187 static void versal_create_admas(Versal *s, qemu_irq *pic)
 188 {
 189     int i;
 190
 191     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
 192         char *name = g_strdup_printf("adma%d", i);
 193         DeviceState *dev;
 194         MemoryRegion *mr;
 195
 196         sysbus_init_child_obj(OBJECT(s), name,
 197                               &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),
 198                               TYPE_XLNX_ZDMA);
 199         dev = DEVICE(&s->lpd.iou.adma[i]);
 200         object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);
 201         qdev_init_nofail(dev);
 202
 203         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 204         memory_region_add_subregion(&s->mr_ps,
 205                                     MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
 206
 207         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
 208         g_free(name);
 209     }
 210 }
 211
 212 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Same as on ZynqMP.  */
 213 static void versal_create_sds(Versal *s, qemu_irq *pic)
 214 {
 215     int i;
 216
 217     for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
 218         DeviceState *dev;
 219         MemoryRegion *mr;
 220
 221         sysbus_init_child_obj(OBJECT(s), "sd[*]",
 222                               &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
 223                               TYPE_SYSBUS_SDHCI);
 224         dev = DEVICE(&s->pmc.iou.sd[i]);
 225
 226         object_property_set_uint(OBJECT(dev),
 227                                  3, "sd-spec-version", &error_fatal);
 228         object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
 229                                  &error_fatal);
 230         object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
 231         qdev_init_nofail(dev);
 232
 233         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 234         memory_region_add_subregion(&s->mr_ps,
 235                                     MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
 236
 237         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 238                            pic[VERSAL_SD0_IRQ_0 + i * 2]);
 239     }
 240 }
 241
 242 static void versal_create_rtc(Versal *s, qemu_irq *pic)
 243 {
 244     SysBusDevice *sbd;
 245     MemoryRegion *mr;
 246
 247     sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
 248                           TYPE_XLNX_ZYNQMP_RTC);
 249     sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
 250     qdev_init_nofail(DEVICE(sbd));
 251
 252     mr = sysbus_mmio_get_region(sbd, 0);
 253     memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
 254
 255     /*
 256      * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
 257      * supports them.
 258      */
 259     sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
 260 }
 261
 262 /* This takes the board allocated linear DDR memory and creates aliases
 263  * for each split DDR range/aperture on the Versal address map.
 264  */
 265 static void versal_map_ddr(Versal *s)
 266 {
 267     uint64_t size = memory_region_size(s->cfg.mr_ddr);
 268     /* Describes the various split DDR access regions.  */
 269     static const struct {
 270         uint64_t base;
 271         uint64_t size;
 272     } addr_ranges[] = {
 273         { MM_TOP_DDR, MM_TOP_DDR_SIZE },
 274         { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
 275         { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
 276         { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
 277     };
 278     uint64_t offset = 0;
 279     int i;
 280
 281     assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
 282     for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
 283         char *name;
 284         uint64_t mapsize;
 285
 286         mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
 287         name = g_strdup_printf("noc-ddr-range%d", i);
 288         /* Create the MR alias.  */
 289         memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
 290                                  name, s->cfg.mr_ddr,
 291                                  offset, mapsize);
 292
 293         /* Map it onto the NoC MR.  */
 294         memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
 295                                     &s->noc.mr_ddr_ranges[i]);
 296         offset += mapsize;
 297         size -= mapsize;
 298         g_free(name);
 299     }
 300 }
 301
 302 static void versal_unimp_area(Versal *s, const char *name,
 303                                 MemoryRegion *mr,
 304                                 hwaddr base, hwaddr size)
 305 {
 306     DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 307     MemoryRegion *mr_dev;
 308
 309     qdev_prop_set_string(dev, "name", name);
 310     qdev_prop_set_uint64(dev, "size", size);
 311     object_property_add_child(OBJECT(s), name, OBJECT(dev));
 312     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 313
 314     mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 315     memory_region_add_subregion(mr, base, mr_dev);
 316 }
 317
 318 static void versal_unimp(Versal *s)
 319 {
 320     versal_unimp_area(s, "psm", &s->mr_ps,
 321                         MM_PSM_START, MM_PSM_END - MM_PSM_START);
 322     versal_unimp_area(s, "crl", &s->mr_ps,
 323                         MM_CRL, MM_CRL_SIZE);
 324     versal_unimp_area(s, "crf", &s->mr_ps,
 325                         MM_FPD_CRF, MM_FPD_CRF_SIZE);
 326     versal_unimp_area(s, "crp", &s->mr_ps,
 327                         MM_PMC_CRP, MM_PMC_CRP_SIZE);
 328     versal_unimp_area(s, "iou-scntr", &s->mr_ps,
 329                         MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
 330     versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
 331                         MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
 332 }
 333
 334 static void versal_realize(DeviceState *dev, Error **errp)
 335 {
 336     Versal *s = XLNX_VERSAL(dev);
 337     qemu_irq pic[XLNX_VERSAL_NR_IRQS];
 338
 339     versal_create_apu_cpus(s);
 340     versal_create_apu_gic(s, pic);
 341     versal_create_uarts(s, pic);
 342     versal_create_gems(s, pic);
 343     versal_create_admas(s, pic);
 344     versal_create_sds(s, pic);
 345     versal_create_rtc(s, pic);
 346     versal_map_ddr(s);
 347     versal_unimp(s);
 348
 349     /* Create the On Chip Memory (OCM).  */
 350     memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
 351                            MM_OCM_SIZE, &error_fatal);
 352
 353     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
 354     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
 355 }
 356
 357 static void versal_init(Object *obj)
 358 {
 359     Versal *s = XLNX_VERSAL(obj);
 360
 361     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
 362     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
 363 }
 364
 365 static Property versal_properties[] = {
 366     DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
 367                      MemoryRegion *),
 368     DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
 369     DEFINE_PROP_END_OF_LIST()
 370 };
 371
 372 static void versal_class_init(ObjectClass *klass, void *data)
 373 {
 374     DeviceClass *dc = DEVICE_CLASS(klass);
 375
 376     dc->realize = versal_realize;
 377     device_class_set_props(dc, versal_properties);
 378     /* No VMSD since we haven't got any top-level SoC state to save.  */
 379 }
 380
 381 static const TypeInfo versal_info = {
 382     .name = TYPE_XLNX_VERSAL,
 383     .parent = TYPE_SYS_BUS_DEVICE,
 384     .instance_size = sizeof(Versal),
 385     .instance_init = versal_init,
 386     .class_init = versal_class_init,
 387 };
 388
 389 static void versal_register_types(void)
 390 {
 391     type_register_static(&versal_info);
 392 }
 393
 394 type_init(versal_register_types);