hw/arm/pxa2xx_pic.c

   1 /*
   2  * Intel XScale PXA Programmable Interrupt Controller.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  * Written by Andrzej Zaborowski <balrog@zabor.org>
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qapi/error.h"
  13 #include "qemu/module.h"
  14 #include "cpu.h"
  15 #include "hw/arm/pxa.h"
  16 #include "hw/sysbus.h"
  17 #include "migration/vmstate.h"
  18
  19 #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  20 #define ICMR    0x04    /* Interrupt Controller Mask register */
  21 #define ICLR    0x08    /* Interrupt Controller Level register */
  22 #define ICFP    0x0c    /* Interrupt Controller FIQ Pending register */
  23 #define ICPR    0x10    /* Interrupt Controller Pending register */
  24 #define ICCR    0x14    /* Interrupt Controller Control register */
  25 #define ICHP    0x18    /* Interrupt Controller Highest Priority register */
  26 #define IPR0    0x1c    /* Interrupt Controller Priority register 0 */
  27 #define IPR31   0x98    /* Interrupt Controller Priority register 31 */
  28 #define ICIP2   0x9c    /* Interrupt Controller IRQ Pending register 2 */
  29 #define ICMR2   0xa0    /* Interrupt Controller Mask register 2 */
  30 #define ICLR2   0xa4    /* Interrupt Controller Level register 2 */
  31 #define ICFP2   0xa8    /* Interrupt Controller FIQ Pending register 2 */
  32 #define ICPR2   0xac    /* Interrupt Controller Pending register 2 */
  33 #define IPR32   0xb0    /* Interrupt Controller Priority register 32 */
  34 #define IPR39   0xcc    /* Interrupt Controller Priority register 39 */
  35
  36 #define PXA2XX_PIC_SRCS 40
  37
  38 #define TYPE_PXA2XX_PIC "pxa2xx_pic"
  39 #define PXA2XX_PIC(obj) \
  40     OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
  41
  42 typedef struct {
  43     /*< private >*/
  44     SysBusDevice parent_obj;
  45     /*< public >*/
  46
  47     MemoryRegion iomem;
  48     ARMCPU *cpu;
  49     uint32_t int_enabled[2];
  50     uint32_t int_pending[2];
  51     uint32_t is_fiq[2];
  52     uint32_t int_idle;
  53     uint32_t priority[PXA2XX_PIC_SRCS];
  54 } PXA2xxPICState;
  55
  56 static void pxa2xx_pic_update(void *opaque)
  57 {
  58     uint32_t mask[2];
  59     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  60     CPUState *cpu = CPU(s->cpu);
  61
  62     if (cpu->halted) {
  63         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
  64         mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
  65         if (mask[0] || mask[1]) {
  66             cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
  67         }
  68     }
  69
  70     mask[0] = s->int_pending[0] & s->int_enabled[0];
  71     mask[1] = s->int_pending[1] & s->int_enabled[1];
  72
  73     if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
  74         cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
  75     } else {
  76         cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
  77     }
  78
  79     if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
  80         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
  81     } else {
  82         cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
  83     }
  84 }
  85
  86 /* Note: Here level means state of the signal on a pin, not
  87  * IRQ/FIQ distinction as in PXA Developer Manual.  */
  88 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
  89 {
  90     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  91     int int_set = (irq >= 32);
  92     irq &= 31;
  93
  94     if (level)
  95         s->int_pending[int_set] |= 1 << irq;
  96     else
  97         s->int_pending[int_set] &= ~(1 << irq);
  98
  99     pxa2xx_pic_update(opaque);
 100 }
 101
 102 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
 103     int i, int_set, irq;
 104     uint32_t bit, mask[2];
 105     uint32_t ichp = 0x003f003f; /* Both IDs invalid */
 106
 107     mask[0] = s->int_pending[0] & s->int_enabled[0];
 108     mask[1] = s->int_pending[1] & s->int_enabled[1];
 109
 110     for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
 111         irq = s->priority[i] & 0x3f;
 112         if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
 113             /* Source peripheral ID is valid.  */
 114             bit = 1 << (irq & 31);
 115             int_set = (irq >= 32);
 116
 117             if (mask[int_set] & bit & s->is_fiq[int_set]) {
 118                 /* FIQ asserted */
 119                 ichp &= 0xffff0000;
 120                 ichp |= (1 << 15) | irq;
 121             }
 122
 123             if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
 124                 /* IRQ asserted */
 125                 ichp &= 0x0000ffff;
 126                 ichp |= (1U << 31) | (irq << 16);
 127             }
 128         }
 129     }
 130
 131     return ichp;
 132 }
 133
 134 static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
 135                                     unsigned size)
 136 {
 137     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 138
 139     switch (offset) {
 140     case ICIP:  /* IRQ Pending register */
 141         return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
 142     case ICIP2: /* IRQ Pending register 2 */
 143         return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
 144     case ICMR:  /* Mask register */
 145         return s->int_enabled[0];
 146     case ICMR2: /* Mask register 2 */
 147         return s->int_enabled[1];
 148     case ICLR:  /* Level register */
 149         return s->is_fiq[0];
 150     case ICLR2: /* Level register 2 */
 151         return s->is_fiq[1];
 152     case ICCR:  /* Idle mask */
 153         return (s->int_idle == 0);
 154     case ICFP:  /* FIQ Pending register */
 155         return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
 156     case ICFP2: /* FIQ Pending register 2 */
 157         return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
 158     case ICPR:  /* Pending register */
 159         return s->int_pending[0];
 160     case ICPR2: /* Pending register 2 */
 161         return s->int_pending[1];
 162     case IPR0  ... IPR31:
 163         return s->priority[0  + ((offset - IPR0 ) >> 2)];
 164     case IPR32 ... IPR39:
 165         return s->priority[32 + ((offset - IPR32) >> 2)];
 166     case ICHP:  /* Highest Priority register */
 167         return pxa2xx_pic_highest(s);
 168     default:
 169         printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
 170         return 0;
 171     }
 172 }
 173
 174 static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
 175                                  uint64_t value, unsigned size)
 176 {
 177     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 178
 179     switch (offset) {
 180     case ICMR:  /* Mask register */
 181         s->int_enabled[0] = value;
 182         break;
 183     case ICMR2: /* Mask register 2 */
 184         s->int_enabled[1] = value;
 185         break;
 186     case ICLR:  /* Level register */
 187         s->is_fiq[0] = value;
 188         break;
 189     case ICLR2: /* Level register 2 */
 190         s->is_fiq[1] = value;
 191         break;
 192     case ICCR:  /* Idle mask */
 193         s->int_idle = (value & 1) ? 0 : ~0;
 194         break;
 195     case IPR0  ... IPR31:
 196         s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
 197         break;
 198     case IPR32 ... IPR39:
 199         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
 200         break;
 201     default:
 202         printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
 203         return;
 204     }
 205     pxa2xx_pic_update(opaque);
 206 }
 207
 208 /* Interrupt Controller Coprocessor Space Register Mapping */
 209 static const int pxa2xx_cp_reg_map[0x10] = {
 210     [0x0 ... 0xf] = -1,
 211     [0x0] = ICIP,
 212     [0x1] = ICMR,
 213     [0x2] = ICLR,
 214     [0x3] = ICFP,
 215     [0x4] = ICPR,
 216     [0x5] = ICHP,
 217     [0x6] = ICIP2,
 218     [0x7] = ICMR2,
 219     [0x8] = ICLR2,
 220     [0x9] = ICFP2,
 221     [0xa] = ICPR2,
 222 };
 223
 224 static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
 225 {
 226     int offset = pxa2xx_cp_reg_map[ri->crn];
 227     return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
 228 }
 229
 230 static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
 231                                 uint64_t value)
 232 {
 233     int offset = pxa2xx_cp_reg_map[ri->crn];
 234     pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
 235 }
 236
 237 #define REGINFO_FOR_PIC_CP(NAME, CRN) \
 238     { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
 239       .access = PL1_RW, .type = ARM_CP_IO, \
 240       .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
 241
 242 static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
 243     REGINFO_FOR_PIC_CP("ICIP", 0),
 244     REGINFO_FOR_PIC_CP("ICMR", 1),
 245     REGINFO_FOR_PIC_CP("ICLR", 2),
 246     REGINFO_FOR_PIC_CP("ICFP", 3),
 247     REGINFO_FOR_PIC_CP("ICPR", 4),
 248     REGINFO_FOR_PIC_CP("ICHP", 5),
 249     REGINFO_FOR_PIC_CP("ICIP2", 6),
 250     REGINFO_FOR_PIC_CP("ICMR2", 7),
 251     REGINFO_FOR_PIC_CP("ICLR2", 8),
 252     REGINFO_FOR_PIC_CP("ICFP2", 9),
 253     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
 254     REGINFO_SENTINEL
 255 };
 256
 257 static const MemoryRegionOps pxa2xx_pic_ops = {
 258     .read = pxa2xx_pic_mem_read,
 259     .write = pxa2xx_pic_mem_write,
 260     .endianness = DEVICE_NATIVE_ENDIAN,
 261 };
 262
 263 static int pxa2xx_pic_post_load(void *opaque, int version_id)
 264 {
 265     pxa2xx_pic_update(opaque);
 266     return 0;
 267 }
 268
 269 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
 270 {
 271     DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
 272     PXA2xxPICState *s = PXA2XX_PIC(dev);
 273
 274     s->cpu = cpu;
 275
 276     s->int_pending[0] = 0;
 277     s->int_pending[1] = 0;
 278     s->int_enabled[0] = 0;
 279     s->int_enabled[1] = 0;
 280     s->is_fiq[0] = 0;
 281     s->is_fiq[1] = 0;
 282
 283     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 284
 285     qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
 286
 287     /* Enable IC memory-mapped registers access.  */
 288     memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
 289                           "pxa2xx-pic", 0x00100000);
 290     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 291     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 292
 293     /* Enable IC coprocessor access.  */
 294     define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
 295
 296     return dev;
 297 }
 298
 299 static VMStateDescription vmstate_pxa2xx_pic_regs = {
 300     .name = "pxa2xx_pic",
 301     .version_id = 0,
 302     .minimum_version_id = 0,
 303     .post_load = pxa2xx_pic_post_load,
 304     .fields = (VMStateField[]) {
 305         VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
 306         VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
 307         VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
 308         VMSTATE_UINT32(int_idle, PXA2xxPICState),
 309         VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
 310         VMSTATE_END_OF_LIST(),
 311     },
 312 };
 313
 314 static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
 315 {
 316     DeviceClass *dc = DEVICE_CLASS(klass);
 317
 318     dc->desc = "PXA2xx PIC";
 319     dc->vmsd = &vmstate_pxa2xx_pic_regs;
 320 }
 321
 322 static const TypeInfo pxa2xx_pic_info = {
 323     .name          = TYPE_PXA2XX_PIC,
 324     .parent        = TYPE_SYS_BUS_DEVICE,
 325     .instance_size = sizeof(PXA2xxPICState),
 326     .class_init    = pxa2xx_pic_class_init,
 327 };
 328
 329 static void pxa2xx_pic_register_types(void)
 330 {
 331     type_register_static(&pxa2xx_pic_info);
 332 }
 333
 334 type_init(pxa2xx_pic_register_types)