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tests/qtest/bios-tables-test: Check for dup2() failure
[qemu/ar7.git] / hw / i386 / pc.c
blobc6d8d0d84d915caddff88eaa743ad88c1109440b
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/reset.h"
62 #include "sysemu/runstate.h"
63 #include "kvm/kvm_i386.h"
64 #include "hw/xen/xen.h"
65 #include "hw/xen/start_info.h"
66 #include "ui/qemu-spice.h"
67 #include "exec/memory.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "qapi/error.h"
80 #include "qapi/qapi-visit-common.h"
81 #include "qapi/visitor.h"
82 #include "hw/core/cpu.h"
83 #include "hw/usb.h"
84 #include "hw/i386/intel_iommu.h"
85 #include "hw/net/ne2000-isa.h"
86 #include "standard-headers/asm-x86/bootparam.h"
87 #include "hw/virtio/virtio-pmem-pci.h"
88 #include "hw/virtio/virtio-mem-pci.h"
89 #include "hw/mem/memory-device.h"
90 #include "sysemu/replay.h"
91 #include "qapi/qmp/qerror.h"
92 #include "e820_memory_layout.h"
93 #include "fw_cfg.h"
94 #include "trace.h"
95 #include CONFIG_DEVICES
96
97 GlobalProperty pc_compat_6_0[] = {
98 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
99 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
100 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
101 };
102 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
103
104 GlobalProperty pc_compat_5_2[] = {
105 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
106 };
107 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
108
109 GlobalProperty pc_compat_5_1[] = {
110 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
111 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
112 };
113 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
114
115 GlobalProperty pc_compat_5_0[] = {
116 };
117 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
118
119 GlobalProperty pc_compat_4_2[] = {
120 { "mch", "smbase-smram", "off" },
121 };
122 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
123
124 GlobalProperty pc_compat_4_1[] = {};
125 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
126
127 GlobalProperty pc_compat_4_0[] = {};
128 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
129
130 GlobalProperty pc_compat_3_1[] = {
131 { "intel-iommu", "dma-drain", "off" },
132 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
133 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
134 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
135 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
136 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
137 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
138 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
139 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
140 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
141 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
142 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
143 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
144 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
145 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
146 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
147 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
148 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
149 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
150 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
151 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
152 };
153 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
154
155 GlobalProperty pc_compat_3_0[] = {
156 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
157 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
158 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
159 };
160 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
161
162 GlobalProperty pc_compat_2_12[] = {
163 { TYPE_X86_CPU, "legacy-cache", "on" },
164 { TYPE_X86_CPU, "topoext", "off" },
165 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
166 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
167 };
168 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
169
170 GlobalProperty pc_compat_2_11[] = {
171 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
172 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
173 };
174 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
175
176 GlobalProperty pc_compat_2_10[] = {
177 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
178 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
179 { "q35-pcihost", "x-pci-hole64-fix", "off" },
180 };
181 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
182
183 GlobalProperty pc_compat_2_9[] = {
184 { "mch", "extended-tseg-mbytes", "0" },
185 };
186 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
187
188 GlobalProperty pc_compat_2_8[] = {
189 { TYPE_X86_CPU, "tcg-cpuid", "off" },
190 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
191 { "ICH9-LPC", "x-smi-broadcast", "off" },
192 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
193 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
194 };
195 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
196
197 GlobalProperty pc_compat_2_7[] = {
198 { TYPE_X86_CPU, "l3-cache", "off" },
199 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
200 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
201 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
202 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
203 { "isa-pcspk", "migrate", "off" },
204 };
205 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
206
207 GlobalProperty pc_compat_2_6[] = {
208 { TYPE_X86_CPU, "cpuid-0xb", "off" },
209 { "vmxnet3", "romfile", "" },
210 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
211 { "apic-common", "legacy-instance-id", "on", }
212 };
213 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
214
215 GlobalProperty pc_compat_2_5[] = {};
216 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
217
218 GlobalProperty pc_compat_2_4[] = {
219 PC_CPU_MODEL_IDS("2.4.0")
220 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
221 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
222 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
223 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
224 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
225 { TYPE_X86_CPU, "check", "off" },
226 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
227 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
228 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
229 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
230 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
231 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
232 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
233 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
234 };
235 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
236
237 GlobalProperty pc_compat_2_3[] = {
238 PC_CPU_MODEL_IDS("2.3.0")
239 { TYPE_X86_CPU, "arat", "off" },
240 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
241 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
242 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
243 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
244 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
245 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
246 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
247 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
248 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
249 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
250 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
251 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
252 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
253 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
254 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
255 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
256 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
257 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
258 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
259 };
260 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
261
262 GlobalProperty pc_compat_2_2[] = {
263 PC_CPU_MODEL_IDS("2.2.0")
264 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
265 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
267 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
268 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
269 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
270 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
271 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
272 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
273 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
274 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
275 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
276 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
277 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
278 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
279 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
280 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
281 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
282 };
283 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
284
285 GlobalProperty pc_compat_2_1[] = {
286 PC_CPU_MODEL_IDS("2.1.0")
287 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
288 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
289 };
290 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
291
292 GlobalProperty pc_compat_2_0[] = {
293 PC_CPU_MODEL_IDS("2.0.0")
294 { "virtio-scsi-pci", "any_layout", "off" },
295 { "PIIX4_PM", "memory-hotplug-support", "off" },
296 { "apic", "version", "0x11" },
297 { "nec-usb-xhci", "superspeed-ports-first", "off" },
298 { "nec-usb-xhci", "force-pcie-endcap", "on" },
299 { "pci-serial", "prog_if", "0" },
300 { "pci-serial-2x", "prog_if", "0" },
301 { "pci-serial-4x", "prog_if", "0" },
302 { "virtio-net-pci", "guest_announce", "off" },
303 { "ICH9-LPC", "memory-hotplug-support", "off" },
304 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
305 { "ioh3420", COMPAT_PROP_PCP, "off" },
306 };
307 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
308
309 GlobalProperty pc_compat_1_7[] = {
310 PC_CPU_MODEL_IDS("1.7.0")
311 { TYPE_USB_DEVICE, "msos-desc", "no" },
312 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
313 { "hpet", HPET_INTCAP, "4" },
314 };
315 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
316
317 GlobalProperty pc_compat_1_6[] = {
318 PC_CPU_MODEL_IDS("1.6.0")
319 { "e1000", "mitigation", "off" },
320 { "qemu64-" TYPE_X86_CPU, "model", "2" },
321 { "qemu32-" TYPE_X86_CPU, "model", "3" },
322 { "i440FX-pcihost", "short_root_bus", "1" },
323 { "q35-pcihost", "short_root_bus", "1" },
324 };
325 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
326
327 GlobalProperty pc_compat_1_5[] = {
328 PC_CPU_MODEL_IDS("1.5.0")
329 { "Conroe-" TYPE_X86_CPU, "model", "2" },
330 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
331 { "Penryn-" TYPE_X86_CPU, "model", "2" },
332 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
333 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
334 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
335 { "virtio-net-pci", "any_layout", "off" },
336 { TYPE_X86_CPU, "pmu", "on" },
337 { "i440FX-pcihost", "short_root_bus", "0" },
338 { "q35-pcihost", "short_root_bus", "0" },
339 };
340 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
341
342 GlobalProperty pc_compat_1_4[] = {
343 PC_CPU_MODEL_IDS("1.4.0")
344 { "scsi-hd", "discard_granularity", "0" },
345 { "scsi-cd", "discard_granularity", "0" },
346 { "ide-hd", "discard_granularity", "0" },
347 { "ide-cd", "discard_granularity", "0" },
348 { "virtio-blk-pci", "discard_granularity", "0" },
349 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
350 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
351 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
352 { "e1000", "romfile", "pxe-e1000.rom" },
353 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
354 { "pcnet", "romfile", "pxe-pcnet.rom" },
355 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
356 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
357 { "486-" TYPE_X86_CPU, "model", "0" },
358 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
359 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
360 };
361 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
362
363 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
364 {
365 GSIState *s;
366
367 s = g_new0(GSIState, 1);
368 if (kvm_ioapic_in_kernel()) {
369 kvm_pc_setup_irq_routing(pci_enabled);
370 }
371 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
372
373 return s;
374 }
375
376 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
377 unsigned size)
378 {
379 }
380
381 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
382 {
383 return 0xffffffffffffffffULL;
384 }
385
386 /* MSDOS compatibility mode FPU exception support */
387 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
388 unsigned size)
389 {
390 if (tcg_enabled()) {
391 cpu_set_ignne();
392 }
393 }
394
395 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
396 {
397 return 0xffffffffffffffffULL;
398 }
399
400 /* PC cmos mappings */
401
402 #define REG_EQUIPMENT_BYTE 0x14
403
404 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
405 int16_t cylinders, int8_t heads, int8_t sectors)
406 {
407 rtc_set_memory(s, type_ofs, 47);
408 rtc_set_memory(s, info_ofs, cylinders);
409 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
410 rtc_set_memory(s, info_ofs + 2, heads);
411 rtc_set_memory(s, info_ofs + 3, 0xff);
412 rtc_set_memory(s, info_ofs + 4, 0xff);
413 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
414 rtc_set_memory(s, info_ofs + 6, cylinders);
415 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
416 rtc_set_memory(s, info_ofs + 8, sectors);
417 }
418
419 /* convert boot_device letter to something recognizable by the bios */
420 static int boot_device2nibble(char boot_device)
421 {
422 switch(boot_device) {
423 case 'a':
424 case 'b':
425 return 0x01; /* floppy boot */
426 case 'c':
427 return 0x02; /* hard drive boot */
428 case 'd':
429 return 0x03; /* CD-ROM boot */
430 case 'n':
431 return 0x04; /* Network boot */
432 }
433 return 0;
434 }
435
436 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
437 {
438 #define PC_MAX_BOOT_DEVICES 3
439 int nbds, bds[3] = { 0, };
440 int i;
441
442 nbds = strlen(boot_device);
443 if (nbds > PC_MAX_BOOT_DEVICES) {
444 error_setg(errp, "Too many boot devices for PC");
445 return;
446 }
447 for (i = 0; i < nbds; i++) {
448 bds[i] = boot_device2nibble(boot_device[i]);
449 if (bds[i] == 0) {
450 error_setg(errp, "Invalid boot device for PC: '%c'",
451 boot_device[i]);
452 return;
453 }
454 }
455 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
456 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
457 }
458
459 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
460 {
461 set_boot_dev(opaque, boot_device, errp);
462 }
463
464 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
465 {
466 int val, nb, i;
467 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
468 FLOPPY_DRIVE_TYPE_NONE };
469
470 /* floppy type */
471 if (floppy) {
472 for (i = 0; i < 2; i++) {
473 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
474 }
475 }
476 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
477 cmos_get_fd_drive_type(fd_type[1]);
478 rtc_set_memory(rtc_state, 0x10, val);
479
480 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
481 nb = 0;
482 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
483 nb++;
484 }
485 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
486 nb++;
487 }
488 switch (nb) {
489 case 0:
490 break;
491 case 1:
492 val |= 0x01; /* 1 drive, ready for boot */
493 break;
494 case 2:
495 val |= 0x41; /* 2 drives, ready for boot */
496 break;
497 }
498 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
499 }
500
501 typedef struct pc_cmos_init_late_arg {
502 ISADevice *rtc_state;
503 BusState *idebus[2];
504 } pc_cmos_init_late_arg;
505
506 typedef struct check_fdc_state {
507 ISADevice *floppy;
508 bool multiple;
509 } CheckFdcState;
510
511 static int check_fdc(Object *obj, void *opaque)
512 {
513 CheckFdcState *state = opaque;
514 Object *fdc;
515 uint32_t iobase;
516 Error *local_err = NULL;
517
518 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
519 if (!fdc) {
520 return 0;
521 }
522
523 iobase = object_property_get_uint(obj, "iobase", &local_err);
524 if (local_err || iobase != 0x3f0) {
525 error_free(local_err);
526 return 0;
527 }
528
529 if (state->floppy) {
530 state->multiple = true;
531 } else {
532 state->floppy = ISA_DEVICE(obj);
533 }
534 return 0;
535 }
536
537 static const char * const fdc_container_path[] = {
538 "/unattached", "/peripheral", "/peripheral-anon"
539 };
540
541 /*
542 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
543 * and ACPI objects.
544 */
545 ISADevice *pc_find_fdc0(void)
546 {
547 int i;
548 Object *container;
549 CheckFdcState state = { 0 };
550
551 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
552 container = container_get(qdev_get_machine(), fdc_container_path[i]);
553 object_child_foreach(container, check_fdc, &state);
554 }
555
556 if (state.multiple) {
557 warn_report("multiple floppy disk controllers with "
558 "iobase=0x3f0 have been found");
559 error_printf("the one being picked for CMOS setup might not reflect "
560 "your intent");
561 }
562
563 return state.floppy;
564 }
565
566 static void pc_cmos_init_late(void *opaque)
567 {
568 pc_cmos_init_late_arg *arg = opaque;
569 ISADevice *s = arg->rtc_state;
570 int16_t cylinders;
571 int8_t heads, sectors;
572 int val;
573 int i, trans;
574
575 val = 0;
576 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
577 &cylinders, &heads, &sectors) >= 0) {
578 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
579 val |= 0xf0;
580 }
581 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
582 &cylinders, &heads, &sectors) >= 0) {
583 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
584 val |= 0x0f;
585 }
586 rtc_set_memory(s, 0x12, val);
587
588 val = 0;
589 for (i = 0; i < 4; i++) {
590 /* NOTE: ide_get_geometry() returns the physical
591 geometry. It is always such that: 1 <= sects <= 63, 1
592 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
593 geometry can be different if a translation is done. */
594 if (arg->idebus[i / 2] &&
595 ide_get_geometry(arg->idebus[i / 2], i % 2,
596 &cylinders, &heads, &sectors) >= 0) {
597 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
598 assert((trans & ~3) == 0);
599 val |= trans << (i * 2);
600 }
601 }
602 rtc_set_memory(s, 0x39, val);
603
604 pc_cmos_init_floppy(s, pc_find_fdc0());
605
606 qemu_unregister_reset(pc_cmos_init_late, opaque);
607 }
608
609 void pc_cmos_init(PCMachineState *pcms,
610 BusState *idebus0, BusState *idebus1,
611 ISADevice *s)
612 {
613 int val;
614 static pc_cmos_init_late_arg arg;
615 X86MachineState *x86ms = X86_MACHINE(pcms);
616
617 /* various important CMOS locations needed by PC/Bochs bios */
618
619 /* memory size */
620 /* base memory (first MiB) */
621 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
622 rtc_set_memory(s, 0x15, val);
623 rtc_set_memory(s, 0x16, val >> 8);
624 /* extended memory (next 64MiB) */
625 if (x86ms->below_4g_mem_size > 1 * MiB) {
626 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
627 } else {
628 val = 0;
629 }
630 if (val > 65535)
631 val = 65535;
632 rtc_set_memory(s, 0x17, val);
633 rtc_set_memory(s, 0x18, val >> 8);
634 rtc_set_memory(s, 0x30, val);
635 rtc_set_memory(s, 0x31, val >> 8);
636 /* memory between 16MiB and 4GiB */
637 if (x86ms->below_4g_mem_size > 16 * MiB) {
638 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
639 } else {
640 val = 0;
641 }
642 if (val > 65535)
643 val = 65535;
644 rtc_set_memory(s, 0x34, val);
645 rtc_set_memory(s, 0x35, val >> 8);
646 /* memory above 4GiB */
647 val = x86ms->above_4g_mem_size / 65536;
648 rtc_set_memory(s, 0x5b, val);
649 rtc_set_memory(s, 0x5c, val >> 8);
650 rtc_set_memory(s, 0x5d, val >> 16);
651
652 object_property_add_link(OBJECT(pcms), "rtc_state",
653 TYPE_ISA_DEVICE,
654 (Object **)&x86ms->rtc,
655 object_property_allow_set_link,
656 OBJ_PROP_LINK_STRONG);
657 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
658 &error_abort);
659
660 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
661
662 val = 0;
663 val |= 0x02; /* FPU is there */
664 val |= 0x04; /* PS/2 mouse installed */
665 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
666
667 /* hard drives and FDC */
668 arg.rtc_state = s;
669 arg.idebus[0] = idebus0;
670 arg.idebus[1] = idebus1;
671 qemu_register_reset(pc_cmos_init_late, &arg);
672 }
673
674 static void handle_a20_line_change(void *opaque, int irq, int level)
675 {
676 X86CPU *cpu = opaque;
677
678 /* XXX: send to all CPUs ? */
679 /* XXX: add logic to handle multiple A20 line sources */
680 x86_cpu_set_a20(cpu, level);
681 }
682
683 #define NE2000_NB_MAX 6
684
685 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
686 0x280, 0x380 };
687 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
688
689 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
690 {
691 static int nb_ne2k = 0;
692
693 if (nb_ne2k == NE2000_NB_MAX)
694 return;
695 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
696 ne2000_irq[nb_ne2k], nd);
697 nb_ne2k++;
698 }
699
700 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
701 {
702 X86CPU *cpu = opaque;
703
704 if (level) {
705 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
706 }
707 }
708
709 /*
710 * This function is very similar to smp_parse()
711 * in hw/core/machine.c but includes CPU die support.
712 */
713 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
714 {
715 X86MachineState *x86ms = X86_MACHINE(ms);
716
717 if (opts) {
718 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
719 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
720 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
721 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
722 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
723
724 /* compute missing values, prefer sockets over cores over threads */
725 if (cpus == 0 || sockets == 0) {
726 cores = cores > 0 ? cores : 1;
727 threads = threads > 0 ? threads : 1;
728 if (cpus == 0) {
729 sockets = sockets > 0 ? sockets : 1;
730 cpus = cores * threads * dies * sockets;
731 } else {
732 ms->smp.max_cpus =
733 qemu_opt_get_number(opts, "maxcpus", cpus);
734 sockets = ms->smp.max_cpus / (cores * threads * dies);
735 }
736 } else if (cores == 0) {
737 threads = threads > 0 ? threads : 1;
738 cores = cpus / (sockets * dies * threads);
739 cores = cores > 0 ? cores : 1;
740 } else if (threads == 0) {
741 threads = cpus / (cores * dies * sockets);
742 threads = threads > 0 ? threads : 1;
743 } else if (sockets * dies * cores * threads < cpus) {
744 error_report("cpu topology: "
745 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
746 "smp_cpus (%u)",
747 sockets, dies, cores, threads, cpus);
748 exit(1);
749 }
750
751 ms->smp.max_cpus =
752 qemu_opt_get_number(opts, "maxcpus", cpus);
753
754 if (ms->smp.max_cpus < cpus) {
755 error_report("maxcpus must be equal to or greater than smp");
756 exit(1);
757 }
758
759 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
760 error_report("Invalid CPU topology deprecated: "
761 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
762 "!= maxcpus (%u)",
763 sockets, dies, cores, threads,
764 ms->smp.max_cpus);
765 exit(1);
766 }
767
768 ms->smp.cpus = cpus;
769 ms->smp.cores = cores;
770 ms->smp.threads = threads;
771 ms->smp.sockets = sockets;
772 x86ms->smp_dies = dies;
773 }
774
775 if (ms->smp.cpus > 1) {
776 Error *blocker = NULL;
777 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
778 replay_add_blocker(blocker);
779 }
780 }
781
782 static
783 void pc_machine_done(Notifier *notifier, void *data)
784 {
785 PCMachineState *pcms = container_of(notifier,
786 PCMachineState, machine_done);
787 X86MachineState *x86ms = X86_MACHINE(pcms);
788
789 /* set the number of CPUs */
790 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
791
792 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
793
794 acpi_setup();
795 if (x86ms->fw_cfg) {
796 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
797 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
798 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
799 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
800 }
801
802
803 if (x86ms->apic_id_limit > 255 && !xen_enabled() &&
804 !kvm_irqchip_in_kernel()) {
805 error_report("current -smp configuration requires kernel "
806 "irqchip support.");
807 exit(EXIT_FAILURE);
808 }
809 }
810
811 void pc_guest_info_init(PCMachineState *pcms)
812 {
813 int i;
814 MachineState *ms = MACHINE(pcms);
815 X86MachineState *x86ms = X86_MACHINE(pcms);
816
817 x86ms->apic_xrupt_override = true;
818 pcms->numa_nodes = ms->numa_state->num_nodes;
819 pcms->node_mem = g_malloc0(pcms->numa_nodes *
820 sizeof *pcms->node_mem);
821 for (i = 0; i < ms->numa_state->num_nodes; i++) {
822 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
823 }
824
825 pcms->machine_done.notify = pc_machine_done;
826 qemu_add_machine_init_done_notifier(&pcms->machine_done);
827 }
828
829 /* setup pci memory address space mapping into system address space */
830 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
831 MemoryRegion *pci_address_space)
832 {
833 /* Set to lower priority than RAM */
834 memory_region_add_subregion_overlap(system_memory, 0x0,
835 pci_address_space, -1);
836 }
837
838 void xen_load_linux(PCMachineState *pcms)
839 {
840 int i;
841 FWCfgState *fw_cfg;
842 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
843 X86MachineState *x86ms = X86_MACHINE(pcms);
844
845 assert(MACHINE(pcms)->kernel_filename != NULL);
846
847 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
848 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
849 rom_set_fw(fw_cfg);
850
851 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
852 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
853 for (i = 0; i < nb_option_roms; i++) {
854 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
855 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
856 !strcmp(option_rom[i].name, "pvh.bin") ||
857 !strcmp(option_rom[i].name, "multiboot.bin"));
858 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
859 }
860 x86ms->fw_cfg = fw_cfg;
861 }
862
863 void pc_memory_init(PCMachineState *pcms,
864 MemoryRegion *system_memory,
865 MemoryRegion *rom_memory,
866 MemoryRegion **ram_memory)
867 {
868 int linux_boot, i;
869 MemoryRegion *option_rom_mr;
870 MemoryRegion *ram_below_4g, *ram_above_4g;
871 FWCfgState *fw_cfg;
872 MachineState *machine = MACHINE(pcms);
873 MachineClass *mc = MACHINE_GET_CLASS(machine);
874 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
875 X86MachineState *x86ms = X86_MACHINE(pcms);
876
877 assert(machine->ram_size == x86ms->below_4g_mem_size +
878 x86ms->above_4g_mem_size);
879
880 linux_boot = (machine->kernel_filename != NULL);
881
882 /*
883 * Split single memory region and use aliases to address portions of it,
884 * done for backwards compatibility with older qemus.
885 */
886 *ram_memory = machine->ram;
887 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
888 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
889 0, x86ms->below_4g_mem_size);
890 memory_region_add_subregion(system_memory, 0, ram_below_4g);
891 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
892 if (x86ms->above_4g_mem_size > 0) {
893 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
894 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
895 machine->ram,
896 x86ms->below_4g_mem_size,
897 x86ms->above_4g_mem_size);
898 memory_region_add_subregion(system_memory, 0x100000000ULL,
899 ram_above_4g);
900 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
901 }
902
903 if (!pcmc->has_reserved_memory &&
904 (machine->ram_slots ||
905 (machine->maxram_size > machine->ram_size))) {
906
907 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
908 mc->name);
909 exit(EXIT_FAILURE);
910 }
911
912 /* always allocate the device memory information */
913 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
914
915 /* initialize device memory address space */
916 if (pcmc->has_reserved_memory &&
917 (machine->ram_size < machine->maxram_size)) {
918 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
919
920 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
921 error_report("unsupported amount of memory slots: %"PRIu64,
922 machine->ram_slots);
923 exit(EXIT_FAILURE);
924 }
925
926 if (QEMU_ALIGN_UP(machine->maxram_size,
927 TARGET_PAGE_SIZE) != machine->maxram_size) {
928 error_report("maximum memory size must by aligned to multiple of "
929 "%d bytes", TARGET_PAGE_SIZE);
930 exit(EXIT_FAILURE);
931 }
932
933 machine->device_memory->base =
934 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
935
936 if (pcmc->enforce_aligned_dimm) {
937 /* size device region assuming 1G page max alignment per slot */
938 device_mem_size += (1 * GiB) * machine->ram_slots;
939 }
940
941 if ((machine->device_memory->base + device_mem_size) <
942 device_mem_size) {
943 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
944 machine->maxram_size);
945 exit(EXIT_FAILURE);
946 }
947
948 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
949 "device-memory", device_mem_size);
950 memory_region_add_subregion(system_memory, machine->device_memory->base,
951 &machine->device_memory->mr);
952 }
953
954 /* Initialize PC system firmware */
955 pc_system_firmware_init(pcms, rom_memory);
956
957 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
958 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
959 &error_fatal);
960 if (pcmc->pci_enabled) {
961 memory_region_set_readonly(option_rom_mr, true);
962 }
963 memory_region_add_subregion_overlap(rom_memory,
964 PC_ROM_MIN_VGA,
965 option_rom_mr,
966 1);
967
968 fw_cfg = fw_cfg_arch_create(machine,
969 x86ms->boot_cpus, x86ms->apic_id_limit);
970
971 rom_set_fw(fw_cfg);
972
973 if (pcmc->has_reserved_memory && machine->device_memory->base) {
974 uint64_t *val = g_malloc(sizeof(*val));
975 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
976 uint64_t res_mem_end = machine->device_memory->base;
977
978 if (!pcmc->broken_reserved_end) {
979 res_mem_end += memory_region_size(&machine->device_memory->mr);
980 }
981 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
982 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
983 }
984
985 if (linux_boot) {
986 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
987 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
988 }
989
990 for (i = 0; i < nb_option_roms; i++) {
991 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
992 }
993 x86ms->fw_cfg = fw_cfg;
994
995 /* Init default IOAPIC address space */
996 x86ms->ioapic_as = &address_space_memory;
997
998 /* Init ACPI memory hotplug IO base address */
999 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1000 }
1001
1002 /*
1003 * The 64bit pci hole starts after "above 4G RAM" and
1004 * potentially the space reserved for memory hotplug.
1005 */
1006 uint64_t pc_pci_hole64_start(void)
1007 {
1008 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1009 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1010 MachineState *ms = MACHINE(pcms);
1011 X86MachineState *x86ms = X86_MACHINE(pcms);
1012 uint64_t hole64_start = 0;
1013
1014 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1015 hole64_start = ms->device_memory->base;
1016 if (!pcmc->broken_reserved_end) {
1017 hole64_start += memory_region_size(&ms->device_memory->mr);
1018 }
1019 } else {
1020 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1021 }
1022
1023 return ROUND_UP(hole64_start, 1 * GiB);
1024 }
1025
1026 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1027 {
1028 DeviceState *dev = NULL;
1029
1030 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1031 if (pci_bus) {
1032 PCIDevice *pcidev = pci_vga_init(pci_bus);
1033 dev = pcidev ? &pcidev->qdev : NULL;
1034 } else if (isa_bus) {
1035 ISADevice *isadev = isa_vga_init(isa_bus);
1036 dev = isadev ? DEVICE(isadev) : NULL;
1037 }
1038 rom_reset_order_override();
1039 return dev;
1040 }
1041
1042 static const MemoryRegionOps ioport80_io_ops = {
1043 .write = ioport80_write,
1044 .read = ioport80_read,
1045 .endianness = DEVICE_NATIVE_ENDIAN,
1046 .impl = {
1047 .min_access_size = 1,
1048 .max_access_size = 1,
1049 },
1050 };
1051
1052 static const MemoryRegionOps ioportF0_io_ops = {
1053 .write = ioportF0_write,
1054 .read = ioportF0_read,
1055 .endianness = DEVICE_NATIVE_ENDIAN,
1056 .impl = {
1057 .min_access_size = 1,
1058 .max_access_size = 1,
1059 },
1060 };
1061
1062 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1063 {
1064 int i;
1065 DriveInfo *fd[MAX_FD];
1066 qemu_irq *a20_line;
1067 ISADevice *fdc, *i8042, *port92, *vmmouse;
1068
1069 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1070 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1071
1072 for (i = 0; i < MAX_FD; i++) {
1073 fd[i] = drive_get(IF_FLOPPY, 0, i);
1074 create_fdctrl |= !!fd[i];
1075 }
1076 if (create_fdctrl) {
1077 fdc = isa_new(TYPE_ISA_FDC);
1078 if (fdc) {
1079 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1080 isa_fdc_init_drives(fdc, fd);
1081 }
1082 }
1083
1084 i8042 = isa_create_simple(isa_bus, "i8042");
1085 if (!no_vmport) {
1086 isa_create_simple(isa_bus, TYPE_VMPORT);
1087 vmmouse = isa_try_new("vmmouse");
1088 } else {
1089 vmmouse = NULL;
1090 }
1091 if (vmmouse) {
1092 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1093 &error_abort);
1094 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1095 }
1096 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1097
1098 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1099 i8042_setup_a20_line(i8042, a20_line[0]);
1100 qdev_connect_gpio_out_named(DEVICE(port92),
1101 PORT92_A20_LINE, 0, a20_line[1]);
1102 g_free(a20_line);
1103 }
1104
1105 void pc_basic_device_init(struct PCMachineState *pcms,
1106 ISABus *isa_bus, qemu_irq *gsi,
1107 ISADevice **rtc_state,
1108 bool create_fdctrl,
1109 uint32_t hpet_irqs)
1110 {
1111 int i;
1112 DeviceState *hpet = NULL;
1113 int pit_isa_irq = 0;
1114 qemu_irq pit_alt_irq = NULL;
1115 qemu_irq rtc_irq = NULL;
1116 ISADevice *pit = NULL;
1117 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1118 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1119
1120 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1121 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1122
1123 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1124 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1125
1126 /*
1127 * Check if an HPET shall be created.
1128 *
1129 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1130 * when the HPET wants to take over. Thus we have to disable the latter.
1131 */
1132 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1133 kvm_has_pit_state2())) {
1134 hpet = qdev_try_new(TYPE_HPET);
1135 if (!hpet) {
1136 error_report("couldn't create HPET device");
1137 exit(1);
1138 }
1139 /*
1140 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1141 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1142 * IRQ2.
1143 */
1144 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1145 HPET_INTCAP, NULL);
1146 if (!compat) {
1147 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1148 }
1149 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1150 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1151
1152 for (i = 0; i < GSI_NUM_PINS; i++) {
1153 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1154 }
1155 pit_isa_irq = -1;
1156 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1157 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1158 }
1159 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1160
1161 qemu_register_boot_set(pc_boot_set, *rtc_state);
1162
1163 if (!xen_enabled() && pcms->pit_enabled) {
1164 if (kvm_pit_in_kernel()) {
1165 pit = kvm_pit_init(isa_bus, 0x40);
1166 } else {
1167 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1168 }
1169 if (hpet) {
1170 /* connect PIT to output control line of the HPET */
1171 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1172 }
1173 pcspk_init(pcms->pcspk, isa_bus, pit);
1174 }
1175
1176 i8257_dma_init(isa_bus, 0);
1177
1178 /* Super I/O */
1179 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON);
1180 }
1181
1182 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1183 {
1184 int i;
1185
1186 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1187 for (i = 0; i < nb_nics; i++) {
1188 NICInfo *nd = &nd_table[i];
1189 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1190
1191 if (g_str_equal(model, "ne2k_isa")) {
1192 pc_init_ne2k_isa(isa_bus, nd);
1193 } else {
1194 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1195 }
1196 }
1197 rom_reset_order_override();
1198 }
1199
1200 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1201 {
1202 qemu_irq *i8259;
1203
1204 if (kvm_pic_in_kernel()) {
1205 i8259 = kvm_i8259_init(isa_bus);
1206 } else if (xen_enabled()) {
1207 i8259 = xen_interrupt_controller_init();
1208 } else {
1209 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1210 }
1211
1212 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1213 i8259_irqs[i] = i8259[i];
1214 }
1215
1216 g_free(i8259);
1217 }
1218
1219 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1220 Error **errp)
1221 {
1222 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1223 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1224 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1225 const MachineState *ms = MACHINE(hotplug_dev);
1226 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1227 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1228 Error *local_err = NULL;
1229
1230 /*
1231 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1232 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1233 * addition to cover this case.
1234 */
1235 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1236 error_setg(errp,
1237 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1238 return;
1239 }
1240
1241 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1242 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1243 return;
1244 }
1245
1246 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1247 if (local_err) {
1248 error_propagate(errp, local_err);
1249 return;
1250 }
1251
1252 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1253 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1254 }
1255
1256 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1257 DeviceState *dev, Error **errp)
1258 {
1259 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1260 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1261 MachineState *ms = MACHINE(hotplug_dev);
1262 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1263
1264 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1265
1266 if (is_nvdimm) {
1267 nvdimm_plug(ms->nvdimms_state);
1268 }
1269
1270 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1271 }
1272
1273 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1274 DeviceState *dev, Error **errp)
1275 {
1276 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1277
1278 /*
1279 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1280 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1281 * addition to cover this case.
1282 */
1283 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1284 error_setg(errp,
1285 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1286 return;
1287 }
1288
1289 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1290 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1291 return;
1292 }
1293
1294 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1295 errp);
1296 }
1297
1298 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1299 DeviceState *dev, Error **errp)
1300 {
1301 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1302 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1303 Error *local_err = NULL;
1304
1305 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1306 if (local_err) {
1307 goto out;
1308 }
1309
1310 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1311 qdev_unrealize(dev);
1312 out:
1313 error_propagate(errp, local_err);
1314 }
1315
1316 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1317 DeviceState *dev, Error **errp)
1318 {
1319 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1320 Error *local_err = NULL;
1321
1322 if (!hotplug_dev2 && dev->hotplugged) {
1323 /*
1324 * Without a bus hotplug handler, we cannot control the plug/unplug
1325 * order. We should never reach this point when hotplugging on x86,
1326 * however, better add a safety net.
1327 */
1328 error_setg(errp, "hotplug of virtio based memory devices not supported"
1329 " on this bus.");
1330 return;
1331 }
1332 /*
1333 * First, see if we can plug this memory device at all. If that
1334 * succeeds, branch of to the actual hotplug handler.
1335 */
1336 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1337 &local_err);
1338 if (!local_err && hotplug_dev2) {
1339 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1340 }
1341 error_propagate(errp, local_err);
1342 }
1343
1344 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1345 DeviceState *dev, Error **errp)
1346 {
1347 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1348 Error *local_err = NULL;
1349
1350 /*
1351 * Plug the memory device first and then branch off to the actual
1352 * hotplug handler. If that one fails, we can easily undo the memory
1353 * device bits.
1354 */
1355 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1356 if (hotplug_dev2) {
1357 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1358 if (local_err) {
1359 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1360 }
1361 }
1362 error_propagate(errp, local_err);
1363 }
1364
1365 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1366 DeviceState *dev, Error **errp)
1367 {
1368 /* We don't support hot unplug of virtio based memory devices */
1369 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1370 }
1371
1372 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1373 DeviceState *dev, Error **errp)
1374 {
1375 /* We don't support hot unplug of virtio based memory devices */
1376 }
1377
1378 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1379 DeviceState *dev, Error **errp)
1380 {
1381 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1382 pc_memory_pre_plug(hotplug_dev, dev, errp);
1383 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1384 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1385 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1386 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1387 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1388 }
1389 }
1390
1391 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1392 DeviceState *dev, Error **errp)
1393 {
1394 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1395 pc_memory_plug(hotplug_dev, dev, errp);
1396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1397 x86_cpu_plug(hotplug_dev, dev, errp);
1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1399 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1400 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1401 }
1402 }
1403
1404 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1405 DeviceState *dev, Error **errp)
1406 {
1407 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1408 pc_memory_unplug_request(hotplug_dev, dev, errp);
1409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1410 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1412 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1413 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1414 } else {
1415 error_setg(errp, "acpi: device unplug request for not supported device"
1416 " type: %s", object_get_typename(OBJECT(dev)));
1417 }
1418 }
1419
1420 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1421 DeviceState *dev, Error **errp)
1422 {
1423 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1424 pc_memory_unplug(hotplug_dev, dev, errp);
1425 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1426 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1427 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1428 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1429 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1430 } else {
1431 error_setg(errp, "acpi: device unplug for not supported device"
1432 " type: %s", object_get_typename(OBJECT(dev)));
1433 }
1434 }
1435
1436 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1437 DeviceState *dev)
1438 {
1439 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1440 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1441 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1442 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1443 return HOTPLUG_HANDLER(machine);
1444 }
1445
1446 return NULL;
1447 }
1448
1449 static void
1450 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1451 const char *name, void *opaque,
1452 Error **errp)
1453 {
1454 MachineState *ms = MACHINE(obj);
1455 int64_t value = 0;
1456
1457 if (ms->device_memory) {
1458 value = memory_region_size(&ms->device_memory->mr);
1459 }
1460
1461 visit_type_int(v, name, &value, errp);
1462 }
1463
1464 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1465 void *opaque, Error **errp)
1466 {
1467 PCMachineState *pcms = PC_MACHINE(obj);
1468 OnOffAuto vmport = pcms->vmport;
1469
1470 visit_type_OnOffAuto(v, name, &vmport, errp);
1471 }
1472
1473 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1474 void *opaque, Error **errp)
1475 {
1476 PCMachineState *pcms = PC_MACHINE(obj);
1477
1478 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1479 }
1480
1481 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1482 {
1483 PCMachineState *pcms = PC_MACHINE(obj);
1484
1485 return pcms->smbus_enabled;
1486 }
1487
1488 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1489 {
1490 PCMachineState *pcms = PC_MACHINE(obj);
1491
1492 pcms->smbus_enabled = value;
1493 }
1494
1495 static bool pc_machine_get_sata(Object *obj, Error **errp)
1496 {
1497 PCMachineState *pcms = PC_MACHINE(obj);
1498
1499 return pcms->sata_enabled;
1500 }
1501
1502 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1503 {
1504 PCMachineState *pcms = PC_MACHINE(obj);
1505
1506 pcms->sata_enabled = value;
1507 }
1508
1509 static bool pc_machine_get_pit(Object *obj, Error **errp)
1510 {
1511 PCMachineState *pcms = PC_MACHINE(obj);
1512
1513 return pcms->pit_enabled;
1514 }
1515
1516 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1517 {
1518 PCMachineState *pcms = PC_MACHINE(obj);
1519
1520 pcms->pit_enabled = value;
1521 }
1522
1523 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1524 {
1525 PCMachineState *pcms = PC_MACHINE(obj);
1526
1527 return pcms->hpet_enabled;
1528 }
1529
1530 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1531 {
1532 PCMachineState *pcms = PC_MACHINE(obj);
1533
1534 pcms->hpet_enabled = value;
1535 }
1536
1537 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1538 const char *name, void *opaque,
1539 Error **errp)
1540 {
1541 PCMachineState *pcms = PC_MACHINE(obj);
1542 uint64_t value = pcms->max_ram_below_4g;
1543
1544 visit_type_size(v, name, &value, errp);
1545 }
1546
1547 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1548 const char *name, void *opaque,
1549 Error **errp)
1550 {
1551 PCMachineState *pcms = PC_MACHINE(obj);
1552 uint64_t value;
1553
1554 if (!visit_type_size(v, name, &value, errp)) {
1555 return;
1556 }
1557 if (value > 4 * GiB) {
1558 error_setg(errp,
1559 "Machine option 'max-ram-below-4g=%"PRIu64
1560 "' expects size less than or equal to 4G", value);
1561 return;
1562 }
1563
1564 if (value < 1 * MiB) {
1565 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1566 "BIOS may not work with less than 1MiB", value);
1567 }
1568
1569 pcms->max_ram_below_4g = value;
1570 }
1571
1572 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1573 const char *name, void *opaque,
1574 Error **errp)
1575 {
1576 PCMachineState *pcms = PC_MACHINE(obj);
1577 uint64_t value = pcms->max_fw_size;
1578
1579 visit_type_size(v, name, &value, errp);
1580 }
1581
1582 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1583 const char *name, void *opaque,
1584 Error **errp)
1585 {
1586 PCMachineState *pcms = PC_MACHINE(obj);
1587 Error *error = NULL;
1588 uint64_t value;
1589
1590 visit_type_size(v, name, &value, &error);
1591 if (error) {
1592 error_propagate(errp, error);
1593 return;
1594 }
1595
1596 /*
1597 * We don't have a theoretically justifiable exact lower bound on the base
1598 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1599 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1600 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1601 * size.
1602 */
1603 if (value > 16 * MiB) {
1604 error_setg(errp,
1605 "User specified max allowed firmware size %" PRIu64 " is "
1606 "greater than 16MiB. If combined firwmare size exceeds "
1607 "16MiB the system may not boot, or experience intermittent"
1608 "stability issues.",
1609 value);
1610 return;
1611 }
1612
1613 pcms->max_fw_size = value;
1614 }
1615
1616
1617 static void pc_machine_initfn(Object *obj)
1618 {
1619 PCMachineState *pcms = PC_MACHINE(obj);
1620
1621 #ifdef CONFIG_VMPORT
1622 pcms->vmport = ON_OFF_AUTO_AUTO;
1623 #else
1624 pcms->vmport = ON_OFF_AUTO_OFF;
1625 #endif /* CONFIG_VMPORT */
1626 pcms->max_ram_below_4g = 0; /* use default */
1627 /* acpi build is enabled by default if machine supports it */
1628 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1629 pcms->smbus_enabled = true;
1630 pcms->sata_enabled = true;
1631 pcms->pit_enabled = true;
1632 pcms->max_fw_size = 8 * MiB;
1633 #ifdef CONFIG_HPET
1634 pcms->hpet_enabled = true;
1635 #endif
1636
1637 pc_system_flash_create(pcms);
1638 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1639 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1640 OBJECT(pcms->pcspk), "audiodev");
1641 }
1642
1643 static void pc_machine_reset(MachineState *machine)
1644 {
1645 CPUState *cs;
1646 X86CPU *cpu;
1647
1648 qemu_devices_reset();
1649
1650 /* Reset APIC after devices have been reset to cancel
1651 * any changes that qemu_devices_reset() might have done.
1652 */
1653 CPU_FOREACH(cs) {
1654 cpu = X86_CPU(cs);
1655
1656 if (cpu->apic_state) {
1657 device_legacy_reset(cpu->apic_state);
1658 }
1659 }
1660 }
1661
1662 static void pc_machine_wakeup(MachineState *machine)
1663 {
1664 cpu_synchronize_all_states();
1665 pc_machine_reset(machine);
1666 cpu_synchronize_all_post_reset();
1667 }
1668
1669 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1670 {
1671 X86IOMMUState *iommu = x86_iommu_get_default();
1672 IntelIOMMUState *intel_iommu;
1673
1674 if (iommu &&
1675 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1676 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1677 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1678 if (!intel_iommu->caching_mode) {
1679 error_setg(errp, "Device assignment is not allowed without "
1680 "enabling caching-mode=on for Intel IOMMU.");
1681 return false;
1682 }
1683 }
1684
1685 return true;
1686 }
1687
1688 static void pc_machine_class_init(ObjectClass *oc, void *data)
1689 {
1690 MachineClass *mc = MACHINE_CLASS(oc);
1691 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1692 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1693
1694 pcmc->pci_enabled = true;
1695 pcmc->has_acpi_build = true;
1696 pcmc->rsdp_in_ram = true;
1697 pcmc->smbios_defaults = true;
1698 pcmc->smbios_uuid_encoded = true;
1699 pcmc->gigabyte_align = true;
1700 pcmc->has_reserved_memory = true;
1701 pcmc->kvmclock_enabled = true;
1702 pcmc->enforce_aligned_dimm = true;
1703 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1704 * to be used at the moment, 32K should be enough for a while. */
1705 pcmc->acpi_data_size = 0x20000 + 0x8000;
1706 pcmc->linuxboot_dma_enabled = true;
1707 pcmc->pvh_enabled = true;
1708 pcmc->kvmclock_create_always = true;
1709 assert(!mc->get_hotplug_handler);
1710 mc->get_hotplug_handler = pc_get_hotplug_handler;
1711 mc->hotplug_allowed = pc_hotplug_allowed;
1712 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1713 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1714 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1715 mc->auto_enable_numa_with_memhp = true;
1716 mc->auto_enable_numa_with_memdev = true;
1717 mc->has_hotpluggable_cpus = true;
1718 mc->default_boot_order = "cad";
1719 mc->smp_parse = pc_smp_parse;
1720 mc->block_default_type = IF_IDE;
1721 mc->max_cpus = 255;
1722 mc->reset = pc_machine_reset;
1723 mc->wakeup = pc_machine_wakeup;
1724 hc->pre_plug = pc_machine_device_pre_plug_cb;
1725 hc->plug = pc_machine_device_plug_cb;
1726 hc->unplug_request = pc_machine_device_unplug_request_cb;
1727 hc->unplug = pc_machine_device_unplug_cb;
1728 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1729 mc->nvdimm_supported = true;
1730 mc->default_ram_id = "pc.ram";
1731
1732 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1733 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1734 NULL, NULL);
1735 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1736 "Maximum ram below the 4G boundary (32bit boundary)");
1737
1738 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1739 pc_machine_get_device_memory_region_size, NULL,
1740 NULL, NULL);
1741
1742 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1743 pc_machine_get_vmport, pc_machine_set_vmport,
1744 NULL, NULL);
1745 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1746 "Enable vmport (pc & q35)");
1747
1748 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1749 pc_machine_get_smbus, pc_machine_set_smbus);
1750
1751 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1752 pc_machine_get_sata, pc_machine_set_sata);
1753
1754 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1755 pc_machine_get_pit, pc_machine_set_pit);
1756
1757 object_class_property_add_bool(oc, "hpet",
1758 pc_machine_get_hpet, pc_machine_set_hpet);
1759
1760 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1761 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1762 NULL, NULL);
1763 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1764 "Maximum combined firmware size");
1765 }
1766
1767 static const TypeInfo pc_machine_info = {
1768 .name = TYPE_PC_MACHINE,
1769 .parent = TYPE_X86_MACHINE,
1770 .abstract = true,
1771 .instance_size = sizeof(PCMachineState),
1772 .instance_init = pc_machine_initfn,
1773 .class_size = sizeof(PCMachineClass),
1774 .class_init = pc_machine_class_init,
1775 .interfaces = (InterfaceInfo[]) {
1776 { TYPE_HOTPLUG_HANDLER },
1777 { }
1778 },
1779 };
1780
1781 static void pc_machine_register_types(void)
1782 {
1783 type_register_static(&pc_machine_info);
1784 }
1785
1786 type_init(pc_machine_register_types)
AR7 emulation for QEMU