4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2.1 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
22 #include "qemu/osdep.h"
23 #include "hw/i386/pc.h"
24 #include "hw/southbridge/piix.h"
26 #include "hw/isa/apm.h"
27 #include "hw/i2c/pm_smbus.h"
28 #include "hw/pci/pci.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/acpi/acpi.h"
31 #include "sysemu/runstate.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/xen.h"
34 #include "qapi/error.h"
35 #include "qemu/range.h"
36 #include "hw/acpi/pcihp.h"
37 #include "hw/acpi/cpu_hotplug.h"
38 #include "hw/acpi/cpu.h"
39 #include "hw/hotplug.h"
40 #include "hw/mem/pc-dimm.h"
41 #include "hw/mem/nvdimm.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/acpi_dev_interface.h"
44 #include "migration/vmstate.h"
45 #include "hw/core/cpu.h"
47 #include "qom/object.h"
49 #define GPE_BASE 0xafe0
53 uint32_t up
; /* deprecated, maintained for migration compatibility */
77 Notifier machine_ready
;
78 Notifier powerdown_notifier
;
80 AcpiPciHpState acpi_pci_hotplug
;
81 bool use_acpi_hotplug_bridge
;
82 bool use_acpi_root_pci_hotplug
;
88 bool cpu_hotplug_legacy
;
89 AcpiCpuHotplug gpe_cpu
;
90 CPUHotplugState cpuhp_state
;
92 MemHotplugState acpi_memory_hotplug
;
95 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState
, PIIX4_PM
)
97 static void piix4_acpi_system_hot_add_init(MemoryRegion
*parent
,
98 PCIBus
*bus
, PIIX4PMState
*s
);
100 #define ACPI_ENABLE 0xf1
101 #define ACPI_DISABLE 0xf0
103 static void pm_tmr_timer(ACPIREGS
*ar
)
105 PIIX4PMState
*s
= container_of(ar
, PIIX4PMState
, ar
);
106 acpi_update_sci(&s
->ar
, s
->irq
);
109 static void apm_ctrl_changed(uint32_t val
, void *arg
)
111 PIIX4PMState
*s
= arg
;
112 PCIDevice
*d
= PCI_DEVICE(s
);
114 /* ACPI specs 3.0, 4.7.2.5 */
115 acpi_pm1_cnt_update(&s
->ar
, val
== ACPI_ENABLE
, val
== ACPI_DISABLE
);
116 if (val
== ACPI_ENABLE
|| val
== ACPI_DISABLE
) {
120 if (d
->config
[0x5b] & (1 << 1)) {
122 qemu_irq_raise(s
->smi_irq
);
127 static void pm_io_space_update(PIIX4PMState
*s
)
129 PCIDevice
*d
= PCI_DEVICE(s
);
131 s
->io_base
= le32_to_cpu(*(uint32_t *)(d
->config
+ 0x40));
132 s
->io_base
&= 0xffc0;
134 memory_region_transaction_begin();
135 memory_region_set_enabled(&s
->io
, d
->config
[0x80] & 1);
136 memory_region_set_address(&s
->io
, s
->io_base
);
137 memory_region_transaction_commit();
140 static void smbus_io_space_update(PIIX4PMState
*s
)
142 PCIDevice
*d
= PCI_DEVICE(s
);
144 s
->smb_io_base
= le32_to_cpu(*(uint32_t *)(d
->config
+ 0x90));
145 s
->smb_io_base
&= 0xffc0;
147 memory_region_transaction_begin();
148 memory_region_set_enabled(&s
->smb
.io
, d
->config
[0xd2] & 1);
149 memory_region_set_address(&s
->smb
.io
, s
->smb_io_base
);
150 memory_region_transaction_commit();
153 static void pm_write_config(PCIDevice
*d
,
154 uint32_t address
, uint32_t val
, int len
)
156 pci_default_write_config(d
, address
, val
, len
);
157 if (range_covers_byte(address
, len
, 0x80) ||
158 ranges_overlap(address
, len
, 0x40, 4)) {
159 pm_io_space_update((PIIX4PMState
*)d
);
161 if (range_covers_byte(address
, len
, 0xd2) ||
162 ranges_overlap(address
, len
, 0x90, 4)) {
163 smbus_io_space_update((PIIX4PMState
*)d
);
167 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
169 PIIX4PMState
*s
= opaque
;
171 pm_io_space_update(s
);
172 smbus_io_space_update(s
);
176 #define VMSTATE_GPE_ARRAY(_field, _state) \
178 .name = (stringify(_field)), \
180 .info = &vmstate_info_uint16, \
181 .size = sizeof(uint16_t), \
182 .flags = VMS_SINGLE | VMS_POINTER, \
183 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
186 static const VMStateDescription vmstate_gpe
= {
189 .minimum_version_id
= 1,
190 .fields
= (VMStateField
[]) {
191 VMSTATE_GPE_ARRAY(sts
, ACPIGPE
),
192 VMSTATE_GPE_ARRAY(en
, ACPIGPE
),
193 VMSTATE_END_OF_LIST()
197 static const VMStateDescription vmstate_pci_status
= {
198 .name
= "pci_status",
200 .minimum_version_id
= 1,
201 .fields
= (VMStateField
[]) {
202 VMSTATE_UINT32(up
, struct AcpiPciHpPciStatus
),
203 VMSTATE_UINT32(down
, struct AcpiPciHpPciStatus
),
204 VMSTATE_END_OF_LIST()
208 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque
, int version_id
)
210 PIIX4PMState
*s
= opaque
;
211 return s
->use_acpi_hotplug_bridge
;
214 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque
,
217 PIIX4PMState
*s
= opaque
;
218 return !s
->use_acpi_hotplug_bridge
;
221 static bool vmstate_test_use_memhp(void *opaque
)
223 PIIX4PMState
*s
= opaque
;
224 return s
->acpi_memory_hotplug
.is_enabled
;
227 static const VMStateDescription vmstate_memhp_state
= {
228 .name
= "piix4_pm/memhp",
230 .minimum_version_id
= 1,
231 .minimum_version_id_old
= 1,
232 .needed
= vmstate_test_use_memhp
,
233 .fields
= (VMStateField
[]) {
234 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug
, PIIX4PMState
),
235 VMSTATE_END_OF_LIST()
239 static bool vmstate_test_use_cpuhp(void *opaque
)
241 PIIX4PMState
*s
= opaque
;
242 return !s
->cpu_hotplug_legacy
;
245 static int vmstate_cpuhp_pre_load(void *opaque
)
247 Object
*obj
= OBJECT(opaque
);
248 object_property_set_bool(obj
, "cpu-hotplug-legacy", false, &error_abort
);
252 static const VMStateDescription vmstate_cpuhp_state
= {
253 .name
= "piix4_pm/cpuhp",
255 .minimum_version_id
= 1,
256 .minimum_version_id_old
= 1,
257 .needed
= vmstate_test_use_cpuhp
,
258 .pre_load
= vmstate_cpuhp_pre_load
,
259 .fields
= (VMStateField
[]) {
260 VMSTATE_CPU_HOTPLUG(cpuhp_state
, PIIX4PMState
),
261 VMSTATE_END_OF_LIST()
265 static bool piix4_vmstate_need_smbus(void *opaque
, int version_id
)
267 return pm_smbus_vmstate_needed();
270 /* qemu-kvm 1.2 uses version 3 but advertised as 2
271 * To support incoming qemu-kvm 1.2 migration, change version_id
272 * and minimum_version_id to 2 below (which breaks migration from
276 static const VMStateDescription vmstate_acpi
= {
279 .minimum_version_id
= 3,
280 .post_load
= vmstate_acpi_post_load
,
281 .fields
= (VMStateField
[]) {
282 VMSTATE_PCI_DEVICE(parent_obj
, PIIX4PMState
),
283 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, PIIX4PMState
),
284 VMSTATE_UINT16(ar
.pm1
.evt
.en
, PIIX4PMState
),
285 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, PIIX4PMState
),
286 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
287 VMSTATE_STRUCT_TEST(smb
, PIIX4PMState
, piix4_vmstate_need_smbus
, 3,
288 pmsmb_vmstate
, PMSMBus
),
289 VMSTATE_TIMER_PTR(ar
.tmr
.timer
, PIIX4PMState
),
290 VMSTATE_INT64(ar
.tmr
.overflow_time
, PIIX4PMState
),
291 VMSTATE_STRUCT(ar
.gpe
, PIIX4PMState
, 2, vmstate_gpe
, ACPIGPE
),
293 acpi_pci_hotplug
.acpi_pcihp_pci_status
[ACPI_PCIHP_BSEL_DEFAULT
],
295 vmstate_test_no_use_acpi_hotplug_bridge
,
296 2, vmstate_pci_status
,
297 struct AcpiPciHpPciStatus
),
298 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug
, PIIX4PMState
,
299 vmstate_test_use_acpi_hotplug_bridge
,
300 vmstate_acpi_pcihp_use_acpi_index
),
301 VMSTATE_END_OF_LIST()
303 .subsections
= (const VMStateDescription
*[]) {
304 &vmstate_memhp_state
,
305 &vmstate_cpuhp_state
,
310 static void piix4_pm_reset(DeviceState
*dev
)
312 PIIX4PMState
*s
= PIIX4_PM(dev
);
313 PCIDevice
*d
= PCI_DEVICE(s
);
314 uint8_t *pci_conf
= d
->config
;
321 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
324 if (!s
->smm_enabled
) {
325 /* Mark SMM as already inited (until KVM supports SMM). */
326 pci_conf
[0x5B] = 0x02;
329 acpi_pm1_evt_reset(&s
->ar
);
330 acpi_pm1_cnt_reset(&s
->ar
);
331 acpi_pm_tmr_reset(&s
->ar
);
332 acpi_gpe_reset(&s
->ar
);
333 acpi_update_sci(&s
->ar
, s
->irq
);
335 pm_io_space_update(s
);
336 acpi_pcihp_reset(&s
->acpi_pci_hotplug
, !s
->use_acpi_root_pci_hotplug
);
339 static void piix4_pm_powerdown_req(Notifier
*n
, void *opaque
)
341 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, powerdown_notifier
);
344 acpi_pm1_evt_power_down(&s
->ar
);
347 static void piix4_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
348 DeviceState
*dev
, Error
**errp
)
350 PIIX4PMState
*s
= PIIX4_PM(hotplug_dev
);
352 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
353 acpi_pcihp_device_pre_plug_cb(hotplug_dev
, dev
, errp
);
354 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
355 if (!s
->acpi_memory_hotplug
.is_enabled
) {
357 "memory hotplug is not enabled: %s.memory-hotplug-support "
358 "is not set", object_get_typename(OBJECT(s
)));
361 !object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
362 error_setg(errp
, "acpi: device pre plug request for not supported"
363 " device type: %s", object_get_typename(OBJECT(dev
)));
367 static void piix4_device_plug_cb(HotplugHandler
*hotplug_dev
,
368 DeviceState
*dev
, Error
**errp
)
370 PIIX4PMState
*s
= PIIX4_PM(hotplug_dev
);
372 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
373 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
374 nvdimm_acpi_plug_cb(hotplug_dev
, dev
);
376 acpi_memory_plug_cb(hotplug_dev
, &s
->acpi_memory_hotplug
,
379 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
380 acpi_pcihp_device_plug_cb(hotplug_dev
, &s
->acpi_pci_hotplug
, dev
, errp
);
381 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
382 if (s
->cpu_hotplug_legacy
) {
383 legacy_acpi_cpu_plug_cb(hotplug_dev
, &s
->gpe_cpu
, dev
, errp
);
385 acpi_cpu_plug_cb(hotplug_dev
, &s
->cpuhp_state
, dev
, errp
);
388 g_assert_not_reached();
392 static void piix4_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
393 DeviceState
*dev
, Error
**errp
)
395 PIIX4PMState
*s
= PIIX4_PM(hotplug_dev
);
397 if (s
->acpi_memory_hotplug
.is_enabled
&&
398 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
399 acpi_memory_unplug_request_cb(hotplug_dev
, &s
->acpi_memory_hotplug
,
401 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
402 acpi_pcihp_device_unplug_request_cb(hotplug_dev
, &s
->acpi_pci_hotplug
,
404 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
) &&
405 !s
->cpu_hotplug_legacy
) {
406 acpi_cpu_unplug_request_cb(hotplug_dev
, &s
->cpuhp_state
, dev
, errp
);
408 error_setg(errp
, "acpi: device unplug request for not supported device"
409 " type: %s", object_get_typename(OBJECT(dev
)));
413 static void piix4_device_unplug_cb(HotplugHandler
*hotplug_dev
,
414 DeviceState
*dev
, Error
**errp
)
416 PIIX4PMState
*s
= PIIX4_PM(hotplug_dev
);
418 if (s
->acpi_memory_hotplug
.is_enabled
&&
419 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
420 acpi_memory_unplug_cb(&s
->acpi_memory_hotplug
, dev
, errp
);
421 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
422 acpi_pcihp_device_unplug_cb(hotplug_dev
, &s
->acpi_pci_hotplug
, dev
,
424 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
) &&
425 !s
->cpu_hotplug_legacy
) {
426 acpi_cpu_unplug_cb(&s
->cpuhp_state
, dev
, errp
);
428 error_setg(errp
, "acpi: device unplug for not supported device"
429 " type: %s", object_get_typename(OBJECT(dev
)));
433 static void piix4_pm_machine_ready(Notifier
*n
, void *opaque
)
435 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, machine_ready
);
436 PCIDevice
*d
= PCI_DEVICE(s
);
437 MemoryRegion
*io_as
= pci_address_space_io(d
);
440 pci_conf
= d
->config
;
441 pci_conf
[0x5f] = 0x10 |
442 (memory_region_present(io_as
, 0x378) ? 0x80 : 0);
443 pci_conf
[0x63] = 0x60;
444 pci_conf
[0x67] = (memory_region_present(io_as
, 0x3f8) ? 0x08 : 0) |
445 (memory_region_present(io_as
, 0x2f8) ? 0x90 : 0);
448 static void piix4_pm_add_properties(PIIX4PMState
*s
)
450 static const uint8_t acpi_enable_cmd
= ACPI_ENABLE
;
451 static const uint8_t acpi_disable_cmd
= ACPI_DISABLE
;
452 static const uint32_t gpe0_blk
= GPE_BASE
;
453 static const uint32_t gpe0_blk_len
= GPE_LEN
;
454 static const uint16_t sci_int
= 9;
456 object_property_add_uint8_ptr(OBJECT(s
), ACPI_PM_PROP_ACPI_ENABLE_CMD
,
457 &acpi_enable_cmd
, OBJ_PROP_FLAG_READ
);
458 object_property_add_uint8_ptr(OBJECT(s
), ACPI_PM_PROP_ACPI_DISABLE_CMD
,
459 &acpi_disable_cmd
, OBJ_PROP_FLAG_READ
);
460 object_property_add_uint32_ptr(OBJECT(s
), ACPI_PM_PROP_GPE0_BLK
,
461 &gpe0_blk
, OBJ_PROP_FLAG_READ
);
462 object_property_add_uint32_ptr(OBJECT(s
), ACPI_PM_PROP_GPE0_BLK_LEN
,
463 &gpe0_blk_len
, OBJ_PROP_FLAG_READ
);
464 object_property_add_uint16_ptr(OBJECT(s
), ACPI_PM_PROP_SCI_INT
,
465 &sci_int
, OBJ_PROP_FLAG_READ
);
466 object_property_add_uint32_ptr(OBJECT(s
), ACPI_PM_PROP_PM_IO_BASE
,
467 &s
->io_base
, OBJ_PROP_FLAG_READ
);
470 static void piix4_pm_realize(PCIDevice
*dev
, Error
**errp
)
472 PIIX4PMState
*s
= PIIX4_PM(dev
);
475 pci_conf
= dev
->config
;
476 pci_conf
[0x06] = 0x80;
477 pci_conf
[0x07] = 0x02;
478 pci_conf
[0x09] = 0x00;
479 pci_conf
[0x3d] = 0x01; // interrupt pin 1
482 apm_init(dev
, &s
->apm
, apm_ctrl_changed
, s
);
484 if (!s
->smm_enabled
) {
485 /* Mark SMM as already inited to prevent SMM from running. KVM does not
486 * support SMM mode. */
487 pci_conf
[0x5B] = 0x02;
490 /* XXX: which specification is used ? The i82731AB has different
492 pci_conf
[0x90] = s
->smb_io_base
| 1;
493 pci_conf
[0x91] = s
->smb_io_base
>> 8;
494 pci_conf
[0xd2] = 0x09;
495 pm_smbus_init(DEVICE(dev
), &s
->smb
, true);
496 memory_region_set_enabled(&s
->smb
.io
, pci_conf
[0xd2] & 1);
497 memory_region_add_subregion(pci_address_space_io(dev
),
498 s
->smb_io_base
, &s
->smb
.io
);
500 memory_region_init(&s
->io
, OBJECT(s
), "piix4-pm", 64);
501 memory_region_set_enabled(&s
->io
, false);
502 memory_region_add_subregion(pci_address_space_io(dev
),
505 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
506 acpi_pm1_evt_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
507 acpi_pm1_cnt_init(&s
->ar
, &s
->io
, s
->disable_s3
, s
->disable_s4
, s
->s4_val
,
508 !s
->smm_compat
&& !s
->smm_enabled
);
509 acpi_gpe_init(&s
->ar
, GPE_LEN
);
511 s
->powerdown_notifier
.notify
= piix4_pm_powerdown_req
;
512 qemu_register_powerdown_notifier(&s
->powerdown_notifier
);
514 s
->machine_ready
.notify
= piix4_pm_machine_ready
;
515 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
517 piix4_acpi_system_hot_add_init(pci_address_space_io(dev
),
518 pci_get_bus(dev
), s
);
519 qbus_set_hotplug_handler(BUS(pci_get_bus(dev
)), OBJECT(s
));
521 piix4_pm_add_properties(s
);
524 I2CBus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
525 qemu_irq sci_irq
, qemu_irq smi_irq
,
526 int smm_enabled
, DeviceState
**piix4_pm
)
532 pci_dev
= pci_new(devfn
, TYPE_PIIX4_PM
);
533 dev
= DEVICE(pci_dev
);
534 qdev_prop_set_uint32(dev
, "smb_io_base", smb_io_base
);
541 s
->smi_irq
= smi_irq
;
542 s
->smm_enabled
= smm_enabled
;
544 s
->use_acpi_hotplug_bridge
= false;
547 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
552 static uint64_t gpe_readb(void *opaque
, hwaddr addr
, unsigned width
)
554 PIIX4PMState
*s
= opaque
;
555 uint32_t val
= acpi_gpe_ioport_readb(&s
->ar
, addr
);
557 trace_piix4_gpe_readb(addr
, width
, val
);
561 static void gpe_writeb(void *opaque
, hwaddr addr
, uint64_t val
,
564 PIIX4PMState
*s
= opaque
;
566 trace_piix4_gpe_writeb(addr
, width
, val
);
567 acpi_gpe_ioport_writeb(&s
->ar
, addr
, val
);
568 acpi_update_sci(&s
->ar
, s
->irq
);
571 static const MemoryRegionOps piix4_gpe_ops
= {
574 .valid
.min_access_size
= 1,
575 .valid
.max_access_size
= 4,
576 .impl
.min_access_size
= 1,
577 .impl
.max_access_size
= 1,
578 .endianness
= DEVICE_LITTLE_ENDIAN
,
582 static bool piix4_get_cpu_hotplug_legacy(Object
*obj
, Error
**errp
)
584 PIIX4PMState
*s
= PIIX4_PM(obj
);
586 return s
->cpu_hotplug_legacy
;
589 static void piix4_set_cpu_hotplug_legacy(Object
*obj
, bool value
, Error
**errp
)
591 PIIX4PMState
*s
= PIIX4_PM(obj
);
594 if (s
->cpu_hotplug_legacy
&& value
== false) {
595 acpi_switch_to_modern_cphp(&s
->gpe_cpu
, &s
->cpuhp_state
,
596 PIIX4_CPU_HOTPLUG_IO_BASE
);
598 s
->cpu_hotplug_legacy
= value
;
601 static void piix4_acpi_system_hot_add_init(MemoryRegion
*parent
,
602 PCIBus
*bus
, PIIX4PMState
*s
)
604 memory_region_init_io(&s
->io_gpe
, OBJECT(s
), &piix4_gpe_ops
, s
,
605 "acpi-gpe0", GPE_LEN
);
606 memory_region_add_subregion(parent
, GPE_BASE
, &s
->io_gpe
);
608 if (s
->use_acpi_hotplug_bridge
|| s
->use_acpi_root_pci_hotplug
) {
609 acpi_pcihp_init(OBJECT(s
), &s
->acpi_pci_hotplug
, bus
, parent
,
610 s
->use_acpi_hotplug_bridge
);
613 s
->cpu_hotplug_legacy
= true;
614 object_property_add_bool(OBJECT(s
), "cpu-hotplug-legacy",
615 piix4_get_cpu_hotplug_legacy
,
616 piix4_set_cpu_hotplug_legacy
);
617 legacy_acpi_cpu_hotplug_init(parent
, OBJECT(s
), &s
->gpe_cpu
,
618 PIIX4_CPU_HOTPLUG_IO_BASE
);
620 if (s
->acpi_memory_hotplug
.is_enabled
) {
621 acpi_memory_hotplug_init(parent
, OBJECT(s
), &s
->acpi_memory_hotplug
,
622 ACPI_MEMORY_HOTPLUG_BASE
);
626 static void piix4_ospm_status(AcpiDeviceIf
*adev
, ACPIOSTInfoList
***list
)
628 PIIX4PMState
*s
= PIIX4_PM(adev
);
630 acpi_memory_ospm_status(&s
->acpi_memory_hotplug
, list
);
631 if (!s
->cpu_hotplug_legacy
) {
632 acpi_cpu_ospm_status(&s
->cpuhp_state
, list
);
636 static void piix4_send_gpe(AcpiDeviceIf
*adev
, AcpiEventStatusBits ev
)
638 PIIX4PMState
*s
= PIIX4_PM(adev
);
640 acpi_send_gpe_event(&s
->ar
, s
->irq
, ev
);
643 static Property piix4_pm_properties
[] = {
644 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
645 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED
, PIIX4PMState
, disable_s3
, 0),
646 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED
, PIIX4PMState
, disable_s4
, 0),
647 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL
, PIIX4PMState
, s4_val
, 2),
648 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState
,
649 use_acpi_hotplug_bridge
, true),
650 DEFINE_PROP_BOOL("acpi-root-pci-hotplug", PIIX4PMState
,
651 use_acpi_root_pci_hotplug
, true),
652 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState
,
653 acpi_memory_hotplug
.is_enabled
, true),
654 DEFINE_PROP_BOOL("smm-compat", PIIX4PMState
, smm_compat
, false),
655 DEFINE_PROP_END_OF_LIST(),
658 static void piix4_pm_class_init(ObjectClass
*klass
, void *data
)
660 DeviceClass
*dc
= DEVICE_CLASS(klass
);
661 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
662 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(klass
);
663 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_CLASS(klass
);
665 k
->realize
= piix4_pm_realize
;
666 k
->config_write
= pm_write_config
;
667 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
668 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_3
;
670 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
671 dc
->reset
= piix4_pm_reset
;
673 dc
->vmsd
= &vmstate_acpi
;
674 device_class_set_props(dc
, piix4_pm_properties
);
676 * Reason: part of PIIX4 southbridge, needs to be wired up,
677 * e.g. by mips_malta_init()
679 dc
->user_creatable
= false;
680 dc
->hotpluggable
= false;
681 hc
->pre_plug
= piix4_device_pre_plug_cb
;
682 hc
->plug
= piix4_device_plug_cb
;
683 hc
->unplug_request
= piix4_device_unplug_request_cb
;
684 hc
->unplug
= piix4_device_unplug_cb
;
685 adevc
->ospm_status
= piix4_ospm_status
;
686 adevc
->send_event
= piix4_send_gpe
;
687 adevc
->madt_cpu
= pc_madt_cpu_entry
;
690 static const TypeInfo piix4_pm_info
= {
691 .name
= TYPE_PIIX4_PM
,
692 .parent
= TYPE_PCI_DEVICE
,
693 .instance_size
= sizeof(PIIX4PMState
),
694 .class_init
= piix4_pm_class_init
,
695 .interfaces
= (InterfaceInfo
[]) {
696 { TYPE_HOTPLUG_HANDLER
},
697 { TYPE_ACPI_DEVICE_IF
},
698 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
703 static void piix4_pm_register_types(void)
705 type_register_static(&piix4_pm_info
);
708 type_init(piix4_pm_register_types
)