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migration/dirtyrate: Add trace_calls to make it easier to debug
[qemu/ar7.git] / hw / riscv / sifive_u.c
blob6ad975d6923ff00550b341d2baf7233099977c28
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 *
19 * This board currently generates devicetree dynamically that indicates at least
20 * two harts and up to five harts.
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms and conditions of the GNU General Public License,
24 * version 2 or later, as published by the Free Software Foundation.
25 *
26 * This program is distributed in the hope it will be useful, but WITHOUT
27 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
28 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
29 * more details.
30 *
31 * You should have received a copy of the GNU General Public License along with
32 * this program. If not, see <http://www.gnu.org/licenses/>.
33 */
34
35 #include "qemu/osdep.h"
36 #include "qemu/log.h"
37 #include "qemu/error-report.h"
38 #include "qapi/error.h"
39 #include "qapi/visitor.h"
40 #include "hw/boards.h"
41 #include "hw/irq.h"
42 #include "hw/loader.h"
43 #include "hw/sysbus.h"
44 #include "hw/char/serial.h"
45 #include "hw/cpu/cluster.h"
46 #include "hw/misc/unimp.h"
47 #include "target/riscv/cpu.h"
48 #include "hw/riscv/riscv_hart.h"
49 #include "hw/riscv/sifive_u.h"
50 #include "hw/riscv/boot.h"
51 #include "hw/char/sifive_uart.h"
52 #include "hw/intc/sifive_clint.h"
53 #include "hw/intc/sifive_plic.h"
54 #include "chardev/char.h"
55 #include "net/eth.h"
56 #include "sysemu/arch_init.h"
57 #include "sysemu/device_tree.h"
58 #include "sysemu/runstate.h"
59 #include "sysemu/sysemu.h"
60
61 #include <libfdt.h>
62
63 #if defined(TARGET_RISCV32)
64 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
65 #else
66 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
67 #endif
68
69 static const struct MemmapEntry {
70 hwaddr base;
71 hwaddr size;
72 } sifive_u_memmap[] = {
73 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
74 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
75 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
76 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
77 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
78 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
79 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
80 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
81 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
82 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
83 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
84 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
85 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
86 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
87 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
88 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
90 };
91
92 #define OTP_SERIAL 1
93 #define GEM_REVISION 0x10070109
94
95 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
96 uint64_t mem_size, const char *cmdline)
97 {
98 MachineState *ms = MACHINE(qdev_get_machine());
99 void *fdt;
100 int cpu;
101 uint32_t *cells;
102 char *nodename;
103 char ethclk_names[] = "pclk\0hclk";
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
105 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
106
107 fdt = s->fdt = create_device_tree(&s->fdt_size);
108 if (!fdt) {
109 error_report("create_device_tree() failed");
110 exit(1);
111 }
112
113 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
114 qemu_fdt_setprop_string(fdt, "/", "compatible",
115 "sifive,hifive-unleashed-a00");
116 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
117 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
118
119 qemu_fdt_add_subnode(fdt, "/soc");
120 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
121 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
122 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
123 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
124
125 hfclk_phandle = phandle++;
126 nodename = g_strdup_printf("/hfclk");
127 qemu_fdt_add_subnode(fdt, nodename);
128 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
129 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
130 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
131 SIFIVE_U_HFCLK_FREQ);
132 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
133 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
134 g_free(nodename);
135
136 rtcclk_phandle = phandle++;
137 nodename = g_strdup_printf("/rtcclk");
138 qemu_fdt_add_subnode(fdt, nodename);
139 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
140 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
141 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
142 SIFIVE_U_RTCCLK_FREQ);
143 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
144 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
145 g_free(nodename);
146
147 nodename = g_strdup_printf("/memory@%lx",
148 (long)memmap[SIFIVE_U_DEV_DRAM].base);
149 qemu_fdt_add_subnode(fdt, nodename);
150 qemu_fdt_setprop_cells(fdt, nodename, "reg",
151 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
152 mem_size >> 32, mem_size);
153 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
154 g_free(nodename);
155
156 qemu_fdt_add_subnode(fdt, "/cpus");
157 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
158 SIFIVE_CLINT_TIMEBASE_FREQ);
159 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
160 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
161
162 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
163 int cpu_phandle = phandle++;
164 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
165 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
166 char *isa;
167 qemu_fdt_add_subnode(fdt, nodename);
168 /* cpu 0 is the management hart that does not have mmu */
169 if (cpu != 0) {
170 #if defined(TARGET_RISCV32)
171 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
172 #else
173 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
174 #endif
175 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
176 } else {
177 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
178 }
179 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
180 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
181 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
182 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
183 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
184 qemu_fdt_add_subnode(fdt, intc);
185 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
186 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
187 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
188 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
189 g_free(isa);
190 g_free(intc);
191 g_free(nodename);
192 }
193
194 cells = g_new0(uint32_t, ms->smp.cpus * 4);
195 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
196 nodename =
197 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
198 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
199 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
200 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
201 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
202 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
203 g_free(nodename);
204 }
205 nodename = g_strdup_printf("/soc/clint@%lx",
206 (long)memmap[SIFIVE_U_DEV_CLINT].base);
207 qemu_fdt_add_subnode(fdt, nodename);
208 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
209 qemu_fdt_setprop_cells(fdt, nodename, "reg",
210 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
211 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
212 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
213 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
214 g_free(cells);
215 g_free(nodename);
216
217 nodename = g_strdup_printf("/soc/otp@%lx",
218 (long)memmap[SIFIVE_U_DEV_OTP].base);
219 qemu_fdt_add_subnode(fdt, nodename);
220 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
221 qemu_fdt_setprop_cells(fdt, nodename, "reg",
222 0x0, memmap[SIFIVE_U_DEV_OTP].base,
223 0x0, memmap[SIFIVE_U_DEV_OTP].size);
224 qemu_fdt_setprop_string(fdt, nodename, "compatible",
225 "sifive,fu540-c000-otp");
226 g_free(nodename);
227
228 prci_phandle = phandle++;
229 nodename = g_strdup_printf("/soc/clock-controller@%lx",
230 (long)memmap[SIFIVE_U_DEV_PRCI].base);
231 qemu_fdt_add_subnode(fdt, nodename);
232 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
233 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
234 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
235 hfclk_phandle, rtcclk_phandle);
236 qemu_fdt_setprop_cells(fdt, nodename, "reg",
237 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
238 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
239 qemu_fdt_setprop_string(fdt, nodename, "compatible",
240 "sifive,fu540-c000-prci");
241 g_free(nodename);
242
243 plic_phandle = phandle++;
244 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
245 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
246 nodename =
247 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
248 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
249 /* cpu 0 is the management hart that does not have S-mode */
250 if (cpu == 0) {
251 cells[0] = cpu_to_be32(intc_phandle);
252 cells[1] = cpu_to_be32(IRQ_M_EXT);
253 } else {
254 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
255 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
256 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
257 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
258 }
259 g_free(nodename);
260 }
261 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
262 (long)memmap[SIFIVE_U_DEV_PLIC].base);
263 qemu_fdt_add_subnode(fdt, nodename);
264 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
265 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
266 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
267 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
268 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
269 qemu_fdt_setprop_cells(fdt, nodename, "reg",
270 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
271 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
272 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
273 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
274 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
275 g_free(cells);
276 g_free(nodename);
277
278 gpio_phandle = phandle++;
279 nodename = g_strdup_printf("/soc/gpio@%lx",
280 (long)memmap[SIFIVE_U_DEV_GPIO].base);
281 qemu_fdt_add_subnode(fdt, nodename);
282 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
283 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
284 prci_phandle, PRCI_CLK_TLCLK);
285 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
286 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
287 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
288 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
289 qemu_fdt_setprop_cells(fdt, nodename, "reg",
290 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
291 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
292 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
293 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
294 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
295 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
296 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
297 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
298 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
299 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
300 g_free(nodename);
301
302 nodename = g_strdup_printf("/gpio-restart");
303 qemu_fdt_add_subnode(fdt, nodename);
304 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
305 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
306 g_free(nodename);
307
308 nodename = g_strdup_printf("/soc/dma@%lx",
309 (long)memmap[SIFIVE_U_DEV_PDMA].base);
310 qemu_fdt_add_subnode(fdt, nodename);
311 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
312 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
313 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
314 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
315 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
316 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
317 qemu_fdt_setprop_cells(fdt, nodename, "reg",
318 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
319 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
320 qemu_fdt_setprop_string(fdt, nodename, "compatible",
321 "sifive,fu540-c000-pdma");
322 g_free(nodename);
323
324 nodename = g_strdup_printf("/soc/cache-controller@%lx",
325 (long)memmap[SIFIVE_U_DEV_L2CC].base);
326 qemu_fdt_add_subnode(fdt, nodename);
327 qemu_fdt_setprop_cells(fdt, nodename, "reg",
328 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
329 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
330 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
331 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
332 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
333 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
334 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
335 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
336 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
337 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
338 qemu_fdt_setprop_string(fdt, nodename, "compatible",
339 "sifive,fu540-c000-ccache");
340 g_free(nodename);
341
342 phy_phandle = phandle++;
343 nodename = g_strdup_printf("/soc/ethernet@%lx",
344 (long)memmap[SIFIVE_U_DEV_GEM].base);
345 qemu_fdt_add_subnode(fdt, nodename);
346 qemu_fdt_setprop_string(fdt, nodename, "compatible",
347 "sifive,fu540-c000-gem");
348 qemu_fdt_setprop_cells(fdt, nodename, "reg",
349 0x0, memmap[SIFIVE_U_DEV_GEM].base,
350 0x0, memmap[SIFIVE_U_DEV_GEM].size,
351 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
352 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
353 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
354 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
355 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
356 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
357 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
358 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
359 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
360 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
361 sizeof(ethclk_names));
362 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
363 s->soc.gem.conf.macaddr.a, ETH_ALEN);
364 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
365 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
366
367 qemu_fdt_add_subnode(fdt, "/aliases");
368 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
369
370 g_free(nodename);
371
372 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
373 (long)memmap[SIFIVE_U_DEV_GEM].base);
374 qemu_fdt_add_subnode(fdt, nodename);
375 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
376 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
377 g_free(nodename);
378
379 nodename = g_strdup_printf("/soc/serial@%lx",
380 (long)memmap[SIFIVE_U_DEV_UART0].base);
381 qemu_fdt_add_subnode(fdt, nodename);
382 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
383 qemu_fdt_setprop_cells(fdt, nodename, "reg",
384 0x0, memmap[SIFIVE_U_DEV_UART0].base,
385 0x0, memmap[SIFIVE_U_DEV_UART0].size);
386 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
387 prci_phandle, PRCI_CLK_TLCLK);
388 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
389 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
390
391 qemu_fdt_add_subnode(fdt, "/chosen");
392 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
393 if (cmdline) {
394 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
395 }
396
397 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
398
399 g_free(nodename);
400 }
401
402 static void sifive_u_machine_reset(void *opaque, int n, int level)
403 {
404 /* gpio pin active low triggers reset */
405 if (!level) {
406 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
407 }
408 }
409
410 static void sifive_u_machine_init(MachineState *machine)
411 {
412 const struct MemmapEntry *memmap = sifive_u_memmap;
413 SiFiveUState *s = RISCV_U_MACHINE(machine);
414 MemoryRegion *system_memory = get_system_memory();
415 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
416 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
417 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
418 uint32_t start_addr_hi32 = 0x00000000;
419 int i;
420 uint32_t fdt_load_addr;
421 uint64_t kernel_entry;
422
423 /* Initialize SoC */
424 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
425 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
426 &error_abort);
427 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
428
429 /* register RAM */
430 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
431 machine->ram_size, &error_fatal);
432 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
433 main_mem);
434
435 /* register QSPI0 Flash */
436 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
437 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
438 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
439 flash0);
440
441 /* register gpio-restart */
442 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
443 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
444
445 /* create device tree */
446 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
447
448 if (s->start_in_flash) {
449 /*
450 * If start_in_flash property is given, assign s->msel to a value
451 * that representing booting from QSPI0 memory-mapped flash.
452 *
453 * This also means that when both start_in_flash and msel properties
454 * are given, start_in_flash takes the precedence over msel.
455 *
456 * Note this is to keep backward compatibility not to break existing
457 * users that use start_in_flash property.
458 */
459 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
460 }
461
462 switch (s->msel) {
463 case MSEL_MEMMAP_QSPI0_FLASH:
464 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
465 break;
466 case MSEL_L2LIM_QSPI0_FLASH:
467 case MSEL_L2LIM_QSPI2_SD:
468 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
469 break;
470 default:
471 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
472 break;
473 }
474
475 riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
476
477 if (machine->kernel_filename) {
478 kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
479
480 if (machine->initrd_filename) {
481 hwaddr start;
482 hwaddr end = riscv_load_initrd(machine->initrd_filename,
483 machine->ram_size, kernel_entry,
484 &start);
485 qemu_fdt_setprop_cell(s->fdt, "/chosen",
486 "linux,initrd-start", start);
487 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
488 end);
489 }
490 } else {
491 /*
492 * If dynamic firmware is used, it doesn't know where is the next mode
493 * if kernel argument is not set.
494 */
495 kernel_entry = 0;
496 }
497
498 /* Compute the fdt load address in dram */
499 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
500 machine->ram_size, s->fdt);
501 #if defined(TARGET_RISCV64)
502 start_addr_hi32 = start_addr >> 32;
503 #endif
504
505 /* reset vector */
506 uint32_t reset_vec[11] = {
507 s->msel, /* MSEL pin state */
508 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
509 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
510 0xf1402573, /* csrr a0, mhartid */
511 #if defined(TARGET_RISCV32)
512 0x0202a583, /* lw a1, 32(t0) */
513 0x0182a283, /* lw t0, 24(t0) */
514 #elif defined(TARGET_RISCV64)
515 0x0202b583, /* ld a1, 32(t0) */
516 0x0182b283, /* ld t0, 24(t0) */
517 #endif
518 0x00028067, /* jr t0 */
519 start_addr, /* start: .dword */
520 start_addr_hi32,
521 fdt_load_addr, /* fdt_laddr: .dword */
522 0x00000000,
523 /* fw_dyn: */
524 };
525
526 /* copy in the reset vector in little_endian byte order */
527 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
528 reset_vec[i] = cpu_to_le32(reset_vec[i]);
529 }
530 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
531 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
532
533 riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
534 memmap[SIFIVE_U_DEV_MROM].size,
535 sizeof(reset_vec), kernel_entry);
536 }
537
538 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
539 {
540 SiFiveUState *s = RISCV_U_MACHINE(obj);
541
542 return s->start_in_flash;
543 }
544
545 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
546 {
547 SiFiveUState *s = RISCV_U_MACHINE(obj);
548
549 s->start_in_flash = value;
550 }
551
552 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
553 const char *name, void *opaque,
554 Error **errp)
555 {
556 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
557 }
558
559 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
560 const char *name, void *opaque,
561 Error **errp)
562 {
563 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
564 }
565
566 static void sifive_u_machine_instance_init(Object *obj)
567 {
568 SiFiveUState *s = RISCV_U_MACHINE(obj);
569
570 s->start_in_flash = false;
571 s->msel = 0;
572 object_property_add(obj, "msel", "uint32",
573 sifive_u_machine_get_uint32_prop,
574 sifive_u_machine_set_uint32_prop, NULL, &s->msel);
575 object_property_set_description(obj, "msel",
576 "Mode Select (MSEL[3:0]) pin state");
577
578 s->serial = OTP_SERIAL;
579 object_property_add(obj, "serial", "uint32",
580 sifive_u_machine_get_uint32_prop,
581 sifive_u_machine_set_uint32_prop, NULL, &s->serial);
582 object_property_set_description(obj, "serial", "Board serial number");
583 }
584
585 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
586 {
587 MachineClass *mc = MACHINE_CLASS(oc);
588
589 mc->desc = "RISC-V Board compatible with SiFive U SDK";
590 mc->init = sifive_u_machine_init;
591 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
592 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
593 mc->default_cpus = mc->min_cpus;
594
595 object_class_property_add_bool(oc, "start-in-flash",
596 sifive_u_machine_get_start_in_flash,
597 sifive_u_machine_set_start_in_flash);
598 object_class_property_set_description(oc, "start-in-flash",
599 "Set on to tell QEMU's ROM to jump to "
600 "flash. Otherwise QEMU will jump to DRAM "
601 "or L2LIM depending on the msel value");
602 }
603
604 static const TypeInfo sifive_u_machine_typeinfo = {
605 .name = MACHINE_TYPE_NAME("sifive_u"),
606 .parent = TYPE_MACHINE,
607 .class_init = sifive_u_machine_class_init,
608 .instance_init = sifive_u_machine_instance_init,
609 .instance_size = sizeof(SiFiveUState),
610 };
611
612 static void sifive_u_machine_init_register_types(void)
613 {
614 type_register_static(&sifive_u_machine_typeinfo);
615 }
616
617 type_init(sifive_u_machine_init_register_types)
618
619 static void sifive_u_soc_instance_init(Object *obj)
620 {
621 MachineState *ms = MACHINE(qdev_get_machine());
622 SiFiveUSoCState *s = RISCV_U_SOC(obj);
623
624 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
625 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
626
627 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
628 TYPE_RISCV_HART_ARRAY);
629 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
630 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
631 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
632 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
633
634 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
635 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
636
637 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
638 TYPE_RISCV_HART_ARRAY);
639 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
640 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
641 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
642 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
643
644 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
645 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
646 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
647 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
648 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
649 }
650
651 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
652 {
653 MachineState *ms = MACHINE(qdev_get_machine());
654 SiFiveUSoCState *s = RISCV_U_SOC(dev);
655 const struct MemmapEntry *memmap = sifive_u_memmap;
656 MemoryRegion *system_memory = get_system_memory();
657 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
658 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
659 char *plic_hart_config;
660 size_t plic_hart_config_len;
661 int i;
662 NICInfo *nd = &nd_table[0];
663
664 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
665 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
666 /*
667 * The cluster must be realized after the RISC-V hart array container,
668 * as the container's CPU object is only created on realize, and the
669 * CPU must exist and have been parented into the cluster before the
670 * cluster is realized.
671 */
672 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
673 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
674
675 /* boot rom */
676 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
677 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
678 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
679 mask_rom);
680
681 /*
682 * Add L2-LIM at reset size.
683 * This should be reduced in size as the L2 Cache Controller WayEnable
684 * register is incremented. Unfortunately I don't see a nice (or any) way
685 * to handle reducing or blocking out the L2 LIM while still allowing it
686 * be re returned to all enabled after a reset. For the time being, just
687 * leave it enabled all the time. This won't break anything, but will be
688 * too generous to misbehaving guests.
689 */
690 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
691 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
692 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
693 l2lim_mem);
694
695 /* create PLIC hart topology configuration string */
696 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
697 ms->smp.cpus;
698 plic_hart_config = g_malloc0(plic_hart_config_len);
699 for (i = 0; i < ms->smp.cpus; i++) {
700 if (i != 0) {
701 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
702 plic_hart_config_len);
703 } else {
704 strncat(plic_hart_config, "M", plic_hart_config_len);
705 }
706 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
707 }
708
709 /* MMIO */
710 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
711 plic_hart_config, 0,
712 SIFIVE_U_PLIC_NUM_SOURCES,
713 SIFIVE_U_PLIC_NUM_PRIORITIES,
714 SIFIVE_U_PLIC_PRIORITY_BASE,
715 SIFIVE_U_PLIC_PENDING_BASE,
716 SIFIVE_U_PLIC_ENABLE_BASE,
717 SIFIVE_U_PLIC_ENABLE_STRIDE,
718 SIFIVE_U_PLIC_CONTEXT_BASE,
719 SIFIVE_U_PLIC_CONTEXT_STRIDE,
720 memmap[SIFIVE_U_DEV_PLIC].size);
721 g_free(plic_hart_config);
722 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
723 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
724 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
725 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
726 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
727 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
728 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
729 SIFIVE_CLINT_TIMEBASE_FREQ, false);
730
731 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
732 return;
733 }
734 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
735
736 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
737 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
738 return;
739 }
740 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
741
742 /* Pass all GPIOs to the SOC layer so they are available to the board */
743 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
744
745 /* Connect GPIO interrupts to the PLIC */
746 for (i = 0; i < 16; i++) {
747 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
748 qdev_get_gpio_in(DEVICE(s->plic),
749 SIFIVE_U_GPIO_IRQ0 + i));
750 }
751
752 /* PDMA */
753 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
754 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
755
756 /* Connect PDMA interrupts to the PLIC */
757 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
758 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
759 qdev_get_gpio_in(DEVICE(s->plic),
760 SIFIVE_U_PDMA_IRQ0 + i));
761 }
762
763 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
764 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
765 return;
766 }
767 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
768
769 /* FIXME use qdev NIC properties instead of nd_table[] */
770 if (nd->used) {
771 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
772 qdev_set_nic_properties(DEVICE(&s->gem), nd);
773 }
774 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
775 &error_abort);
776 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
777 return;
778 }
779 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
780 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
781 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
782
783 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
784 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
785
786 create_unimplemented_device("riscv.sifive.u.dmc",
787 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
788
789 create_unimplemented_device("riscv.sifive.u.l2cc",
790 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
791 }
792
793 static Property sifive_u_soc_props[] = {
794 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
795 DEFINE_PROP_END_OF_LIST()
796 };
797
798 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
799 {
800 DeviceClass *dc = DEVICE_CLASS(oc);
801
802 device_class_set_props(dc, sifive_u_soc_props);
803 dc->realize = sifive_u_soc_realize;
804 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
805 dc->user_creatable = false;
806 }
807
808 static const TypeInfo sifive_u_soc_type_info = {
809 .name = TYPE_RISCV_U_SOC,
810 .parent = TYPE_DEVICE,
811 .instance_size = sizeof(SiFiveUSoCState),
812 .instance_init = sifive_u_soc_instance_init,
813 .class_init = sifive_u_soc_class_init,
814 };
815
816 static void sifive_u_soc_register_types(void)
817 {
818 type_register_static(&sifive_u_soc_type_info);
819 }
820
821 type_init(sifive_u_soc_register_types)
AR7 emulation for QEMU