2 * PA-RISC emulation cpu definitions for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
26 #include "qemu/interval-tree.h"
27 #include "hw/registerfields.h"
29 #define MMU_ABS_W_IDX 6
31 #define MMU_KERNEL_IDX 8
32 #define MMU_KERNEL_P_IDX 9
33 #define MMU_PL1_IDX 10
34 #define MMU_PL1_P_IDX 11
35 #define MMU_PL2_IDX 12
36 #define MMU_PL2_P_IDX 13
37 #define MMU_USER_IDX 14
38 #define MMU_USER_P_IDX 15
40 #define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX)
41 #define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
42 #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
43 #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
48 #define TARGET_INSN_START_EXTRA_WORDS 2
50 /* No need to flush MMU_ABS*_IDX */
51 #define HPPA_MMU_FLUSH_MASK \
52 (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \
53 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \
54 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
55 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
57 /* Indices to flush for access_id changes. */
58 #define HPPA_MMU_FLUSH_P_MASK \
59 (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
60 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)
62 /* Hardware exceptions, interrupts, faults, and traps. */
63 #define EXCP_HPMC 1 /* high priority machine check */
64 #define EXCP_POWER_FAIL 2
65 #define EXCP_RC 3 /* recovery counter */
66 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */
67 #define EXCP_LPMC 5 /* low priority machine check */
68 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
69 #define EXCP_IMP 7 /* instruction memory protection trap */
70 #define EXCP_ILL 8 /* illegal instruction trap */
71 #define EXCP_BREAK 9 /* break instruction */
72 #define EXCP_PRIV_OPR 10 /* privileged operation trap */
73 #define EXCP_PRIV_REG 11 /* privileged register trap */
74 #define EXCP_OVERFLOW 12 /* signed overflow trap */
75 #define EXCP_COND 13 /* trap-on-condition */
76 #define EXCP_ASSIST 14 /* assist exception trap */
77 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
78 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
79 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
80 #define EXCP_DMP 18 /* data memory protection trap */
81 #define EXCP_DMB 19 /* data memory break trap */
82 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
83 #define EXCP_PAGE_REF 21 /* page reference trap */
84 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */
85 #define EXCP_HPT 23 /* high-privilege transfer trap */
86 #define EXCP_LPT 24 /* low-privilege transfer trap */
87 #define EXCP_TB 25 /* taken branch trap */
88 #define EXCP_DMAR 26 /* data memory access rights trap */
89 #define EXCP_DMPI 27 /* data memory protection id trap */
90 #define EXCP_UNALIGN 28 /* unaligned data reference trap */
91 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
93 /* Exceptions for linux-user emulation. */
94 #define EXCP_SYSCALL 30
95 #define EXCP_SYSCALL_LWS 31
97 /* Emulated hardware TOC button */
98 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
100 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
102 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
103 #define PSW_I 0x00000001
104 #define PSW_D 0x00000002
105 #define PSW_P 0x00000004
106 #define PSW_Q 0x00000008
107 #define PSW_R 0x00000010
108 #define PSW_F 0x00000020
109 #define PSW_G 0x00000040 /* PA1.x only */
110 #define PSW_O 0x00000080 /* PA2.0 only */
111 #define PSW_CB 0x0000ff00
112 #define PSW_M 0x00010000
113 #define PSW_V 0x00020000
114 #define PSW_C 0x00040000
115 #define PSW_B 0x00080000
116 #define PSW_X 0x00100000
117 #define PSW_N 0x00200000
118 #define PSW_L 0x00400000
119 #define PSW_H 0x00800000
120 #define PSW_T 0x01000000
121 #define PSW_S 0x02000000
122 #define PSW_E 0x04000000
123 #define PSW_W 0x08000000 /* PA2.0 only */
124 #define PSW_Z 0x40000000 /* PA1.x only */
125 #define PSW_Y 0x80000000 /* PA1.x only */
127 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
128 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
130 /* ssm/rsm instructions number PSW_W and PSW_E differently */
131 #define PSW_SM_I PSW_I /* Enable External Interrupts */
132 #define PSW_SM_D PSW_D
133 #define PSW_SM_P PSW_P
134 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
135 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
136 #define PSW_SM_E 0x100
137 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
140 #define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */
141 #define PDC_PSW_WIDE_BIT 2
159 FIELD(FPSR
, ENA_I
, 0, 1)
160 FIELD(FPSR
, ENA_U
, 1, 1)
161 FIELD(FPSR
, ENA_O
, 2, 1)
162 FIELD(FPSR
, ENA_Z
, 3, 1)
163 FIELD(FPSR
, ENA_V
, 4, 1)
164 FIELD(FPSR
, ENABLES
, 0, 5)
167 FIELD(FPSR
, RM
, 9, 2)
168 FIELD(FPSR
, CQ
, 11, 11)
169 FIELD(FPSR
, CQ0_6
, 15, 7)
170 FIELD(FPSR
, CQ0_4
, 17, 5)
171 FIELD(FPSR
, CQ0_2
, 19, 3)
172 FIELD(FPSR
, CQ0
, 21, 1)
173 FIELD(FPSR
, CA
, 15, 7)
174 FIELD(FPSR
, CA0
, 21, 1)
175 FIELD(FPSR
, C
, 26, 1)
176 FIELD(FPSR
, FLG_I
, 27, 1)
177 FIELD(FPSR
, FLG_U
, 28, 1)
178 FIELD(FPSR
, FLG_O
, 29, 1)
179 FIELD(FPSR
, FLG_Z
, 30, 1)
180 FIELD(FPSR
, FLG_V
, 31, 1)
181 FIELD(FPSR
, FLAGS
, 27, 5)
183 typedef struct HPPATLBEntry
{
185 IntervalTreeNode itree
;
186 struct HPPATLBEntry
*unused_next
;
191 unsigned entry_valid
: 1;
197 unsigned ar_type
: 3;
200 unsigned access_id
: 16;
203 typedef struct CPUArchState
{
204 target_ulong iaoq_f
; /* front */
205 target_ulong iaoq_b
; /* back, aka next instruction */
209 uint64_t sr
[8]; /* stored shifted into place for gva */
211 uint32_t psw
; /* All psw bits except the following: */
212 uint32_t psw_xb
; /* X and B, in their normal positions */
213 target_ulong psw_n
; /* boolean */
214 target_long psw_v
; /* in most significant bit */
216 /* Splitting the carry-borrow field into the MSB and "the rest", allows
217 * for "the rest" to be deleted when it is unused, but the MSB is in use.
218 * In addition, it's easier to compute carry-in for bit B+1 than it is to
219 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
220 * host has the appropriate add-with-carry insn to compute the msb).
221 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
223 target_ulong psw_cb
; /* in least significant bit of next nibble */
224 target_ulong psw_cb_msb
; /* boolean */
229 uint32_t fr0_shadow
; /* flags, c, ca/cq, rm, d, enables */
230 float_status fp_status
;
232 target_ulong cr
[32]; /* control registers */
233 target_ulong cr_back
[2]; /* back of cr17/cr18 */
234 target_ulong shadow
[7]; /* shadow registers */
237 * During unwind of a memory insn, the base register of the address.
238 * This is used to construct CR_IOR for pa2.0.
240 uint32_t unwind_breg
;
243 * ??? The number of entries isn't specified by the architecture.
244 * BTLBs are not supported in 64-bit machines.
246 #define PA10_BTLB_FIXED 16
247 #define PA10_BTLB_VARIABLE 0
248 #define HPPA_TLB_ENTRIES 256
250 /* Index for round-robin tlb eviction. */
254 * For pa1.x, the partial initialized, still invalid tlb entry
255 * which has had ITLBA performed, but not yet ITLBP.
257 HPPATLBEntry
*tlb_partial
;
259 /* Linked list of all invalid (unused) tlb entries. */
260 HPPATLBEntry
*tlb_unused
;
262 /* Root of the search tree for all valid tlb entries. */
263 IntervalTreeRoot tlb_root
;
265 HPPATLBEntry tlb
[HPPA_TLB_ENTRIES
];
270 * @env: #CPUHPPAState
278 QEMUTimer
*alarm_timer
;
283 * @parent_realize: The parent class' realize handler.
284 * @parent_reset: The parent class' reset handler.
288 struct HPPACPUClass
{
289 CPUClass parent_class
;
291 DeviceRealize parent_realize
;
292 DeviceReset parent_reset
;
295 #include "exec/cpu-all.h"
297 static inline bool hppa_is_pa20(CPUHPPAState
*env
)
299 return object_dynamic_cast(OBJECT(env_cpu(env
)), TYPE_HPPA64_CPU
) != NULL
;
302 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState
*env
)
304 return hppa_is_pa20(env
) ? 0 : PA10_BTLB_FIXED
+ PA10_BTLB_VARIABLE
;
307 void hppa_translate_init(void);
309 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
311 static inline uint64_t gva_offset_mask(target_ulong psw
)
314 ? MAKE_64BIT_MASK(0, 62)
315 : MAKE_64BIT_MASK(0, 32));
318 static inline target_ulong
hppa_form_gva_psw(target_ulong psw
, uint64_t spc
,
321 #ifdef CONFIG_USER_ONLY
324 return spc
| (off
& gva_offset_mask(psw
));
328 static inline target_ulong
hppa_form_gva(CPUHPPAState
*env
, uint64_t spc
,
331 return hppa_form_gva_psw(env
->psw
, spc
, off
);
334 hwaddr
hppa_abs_to_phys_pa2_w0(vaddr addr
);
335 hwaddr
hppa_abs_to_phys_pa2_w1(vaddr addr
);
338 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
339 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
342 #define TB_FLAG_SR_SAME PSW_I
343 #define TB_FLAG_PRIV_SHIFT 8
344 #define TB_FLAG_UNALIGN 0x400
345 #define CS_BASE_DIFFPAGE (1 << 12)
346 #define CS_BASE_DIFFSPACE (1 << 13)
348 void cpu_get_tb_cpu_state(CPUHPPAState
*env
, vaddr
*pc
,
349 uint64_t *cs_base
, uint32_t *pflags
);
351 target_ulong
cpu_hppa_get_psw(CPUHPPAState
*env
);
352 void cpu_hppa_put_psw(CPUHPPAState
*env
, target_ulong
);
353 void cpu_hppa_loaded_fr0(CPUHPPAState
*env
);
355 #ifdef CONFIG_USER_ONLY
356 static inline void cpu_hppa_change_prot_id(CPUHPPAState
*env
) { }
358 void cpu_hppa_change_prot_id(CPUHPPAState
*env
);
361 int hppa_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
362 int hppa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
363 void hppa_cpu_dump_state(CPUState
*cs
, FILE *f
, int);
364 #ifndef CONFIG_USER_ONLY
365 void hppa_ptlbe(CPUHPPAState
*env
);
366 hwaddr
hppa_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
);
367 void hppa_set_ior_and_isr(CPUHPPAState
*env
, vaddr addr
, bool mmu_disabled
);
368 bool hppa_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
369 MMUAccessType access_type
, int mmu_idx
,
370 bool probe
, uintptr_t retaddr
);
371 void hppa_cpu_do_interrupt(CPUState
*cpu
);
372 bool hppa_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
373 int hppa_get_physical_address(CPUHPPAState
*env
, vaddr addr
, int mmu_idx
,
374 int type
, hwaddr
*pphys
, int *pprot
);
375 void hppa_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
376 vaddr addr
, unsigned size
,
377 MMUAccessType access_type
,
378 int mmu_idx
, MemTxAttrs attrs
,
379 MemTxResult response
, uintptr_t retaddr
);
380 extern const MemoryRegionOps hppa_io_eir_ops
;
381 extern const VMStateDescription vmstate_hppa_cpu
;
382 void hppa_cpu_alarm_timer(void *);
384 G_NORETURN
void hppa_dynamic_excp(CPUHPPAState
*env
, int excp
, uintptr_t ra
);
386 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
388 #endif /* HPPA_CPU_H */