target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/helper-proto.h"
  30 #include "qemu/host-utils.h"
  31 #include "exec/cpu_ldst.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/timer.h"
  34
  35 void xtensa_cpu_do_unaligned_access(CPUState *cs,
  36         vaddr addr, int is_write, int is_user, uintptr_t retaddr)
  37 {
  38     XtensaCPU *cpu = XTENSA_CPU(cs);
  39     CPUXtensaState *env = &cpu->env;
  40
  41     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  42             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  43         cpu_restore_state(CPU(cpu), retaddr);
  44         HELPER(exception_cause_vaddr)(env,
  45                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  46     }
  47 }
  48
  49 void tlb_fill(CPUState *cs,
  50               target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  51 {
  52     XtensaCPU *cpu = XTENSA_CPU(cs);
  53     CPUXtensaState *env = &cpu->env;
  54     uint32_t paddr;
  55     uint32_t page_size;
  56     unsigned access;
  57     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  58             &paddr, &page_size, &access);
  59
  60     qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
  61                   __func__, vaddr, is_write, mmu_idx, paddr, ret);
  62
  63     if (ret == 0) {
  64         tlb_set_page(cs,
  65                      vaddr & TARGET_PAGE_MASK,
  66                      paddr & TARGET_PAGE_MASK,
  67                      access, mmu_idx, page_size);
  68     } else {
  69         cpu_restore_state(cs, retaddr);
  70         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  71     }
  72 }
  73
  74 void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,
  75                                      bool is_write, bool is_exec, int opaque,
  76                                      unsigned size)
  77 {
  78     XtensaCPU *cpu = XTENSA_CPU(cs);
  79     CPUXtensaState *env = &cpu->env;
  80
  81     HELPER(exception_cause_vaddr)(env, env->pc,
  82                                   is_exec ?
  83                                   INSTR_PIF_ADDR_ERROR_CAUSE :
  84                                   LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
  85                                   is_exec ? addr : cs->mem_io_vaddr);
  86 }
  87
  88 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  89 {
  90     uint32_t paddr;
  91     uint32_t page_size;
  92     unsigned access;
  93     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  94             &paddr, &page_size, &access);
  95     if (ret == 0) {
  96         tb_invalidate_phys_addr(&address_space_memory, paddr);
  97     }
  98 }
  99
 100 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
 101 {
 102     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 103
 104     cs->exception_index = excp;
 105     if (excp == EXCP_DEBUG) {
 106         env->exception_taken = 0;
 107     }
 108     cpu_loop_exit(cs);
 109 }
 110
 111 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 112 {
 113     uint32_t vector;
 114
 115     env->pc = pc;
 116     if (env->sregs[PS] & PS_EXCM) {
 117         if (env->config->ndepc) {
 118             env->sregs[DEPC] = pc;
 119         } else {
 120             env->sregs[EPC1] = pc;
 121         }
 122         vector = EXC_DOUBLE;
 123     } else {
 124         env->sregs[EPC1] = pc;
 125         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 126     }
 127
 128     env->sregs[EXCCAUSE] = cause;
 129     env->sregs[PS] |= PS_EXCM;
 130
 131     HELPER(exception)(env, vector);
 132 }
 133
 134 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 135         uint32_t pc, uint32_t cause, uint32_t vaddr)
 136 {
 137     env->sregs[EXCVADDR] = vaddr;
 138     HELPER(exception_cause)(env, pc, cause);
 139 }
 140
 141 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 142 {
 143     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 144         HELPER(debug_exception)(env, env->pc, cause);
 145     }
 146 }
 147
 148 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 149 {
 150     unsigned level = env->config->debug_level;
 151
 152     env->pc = pc;
 153     env->sregs[DEBUGCAUSE] = cause;
 154     env->sregs[EPC1 + level - 1] = pc;
 155     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 156     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 157         (level << PS_INTLEVEL_SHIFT);
 158     HELPER(exception)(env, EXC_DEBUG);
 159 }
 160
 161 uint32_t HELPER(nsa)(uint32_t v)
 162 {
 163     if (v & 0x80000000) {
 164         v = ~v;
 165     }
 166     return v ? clz32(v) - 1 : 31;
 167 }
 168
 169 uint32_t HELPER(nsau)(uint32_t v)
 170 {
 171     return v ? clz32(v) : 32;
 172 }
 173
 174 static void copy_window_from_phys(CPUXtensaState *env,
 175         uint32_t window, uint32_t phys, uint32_t n)
 176 {
 177     assert(phys < env->config->nareg);
 178     if (phys + n <= env->config->nareg) {
 179         memcpy(env->regs + window, env->phys_regs + phys,
 180                 n * sizeof(uint32_t));
 181     } else {
 182         uint32_t n1 = env->config->nareg - phys;
 183         memcpy(env->regs + window, env->phys_regs + phys,
 184                 n1 * sizeof(uint32_t));
 185         memcpy(env->regs + window + n1, env->phys_regs,
 186                 (n - n1) * sizeof(uint32_t));
 187     }
 188 }
 189
 190 static void copy_phys_from_window(CPUXtensaState *env,
 191         uint32_t phys, uint32_t window, uint32_t n)
 192 {
 193     assert(phys < env->config->nareg);
 194     if (phys + n <= env->config->nareg) {
 195         memcpy(env->phys_regs + phys, env->regs + window,
 196                 n * sizeof(uint32_t));
 197     } else {
 198         uint32_t n1 = env->config->nareg - phys;
 199         memcpy(env->phys_regs + phys, env->regs + window,
 200                 n1 * sizeof(uint32_t));
 201         memcpy(env->phys_regs, env->regs + window + n1,
 202                 (n - n1) * sizeof(uint32_t));
 203     }
 204 }
 205
 206
 207 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 208 {
 209     return a & (env->config->nareg / 4 - 1);
 210 }
 211
 212 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 213 {
 214     return 1 << windowbase_bound(a, env);
 215 }
 216
 217 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 218 {
 219     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 220 }
 221
 222 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 223 {
 224     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 225 }
 226
 227 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 228 {
 229     xtensa_sync_phys_from_window(env);
 230     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 231     xtensa_sync_window_from_phys(env);
 232 }
 233
 234 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 235 {
 236     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 237 }
 238
 239 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 240 {
 241     rotate_window_abs(env, v);
 242 }
 243
 244 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 245 {
 246     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 247     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 248         qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n",
 249                       pc, env->sregs[PS]);
 250         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 251     } else {
 252         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 253             (env->sregs[WINDOW_BASE] + 1);
 254
 255         if (windowstart & ((1 << callinc) - 1)) {
 256             HELPER(window_check)(env, pc, callinc);
 257         }
 258         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 259         rotate_window(env, callinc);
 260         env->sregs[WINDOW_START] |=
 261             windowstart_bit(env->sregs[WINDOW_BASE], env);
 262     }
 263 }
 264
 265 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 266 {
 267     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 268     uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 269         (env->sregs[WINDOW_BASE] + 1);
 270     uint32_t n = ctz32(windowstart) + 1;
 271
 272     assert(n <= w);
 273
 274     rotate_window(env, n);
 275     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 276         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 277     env->sregs[EPC1] = env->pc = pc;
 278
 279     switch (ctz32(windowstart >> n)) {
 280     case 0:
 281         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 282         break;
 283     case 1:
 284         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 285         break;
 286     default:
 287         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 288         break;
 289     }
 290 }
 291
 292 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 293 {
 294     int n = (env->regs[0] >> 30) & 0x3;
 295     int m = 0;
 296     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 297     uint32_t windowstart = env->sregs[WINDOW_START];
 298     uint32_t ret_pc = 0;
 299
 300     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 301         m = 1;
 302     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 303         m = 2;
 304     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 305         m = 3;
 306     }
 307
 308     if (n == 0 || (m != 0 && m != n) ||
 309             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 310         qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), "
 311                       "PS = %08x, m = %d, n = %d\n",
 312                       pc, env->sregs[PS], m, n);
 313         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 314     } else {
 315         int owb = windowbase;
 316
 317         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 318
 319         rotate_window(env, -n);
 320         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 321             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 322         } else {
 323             /* window underflow */
 324             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 325                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 326             env->sregs[EPC1] = env->pc = pc;
 327
 328             if (n == 1) {
 329                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 330             } else if (n == 2) {
 331                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 332             } else if (n == 3) {
 333                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 334             }
 335         }
 336     }
 337     return ret_pc;
 338 }
 339
 340 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 341 {
 342     rotate_window(env, imm4);
 343 }
 344
 345 void HELPER(restore_owb)(CPUXtensaState *env)
 346 {
 347     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 348 }
 349
 350 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 351 {
 352     if ((env->sregs[WINDOW_START] &
 353             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 354              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 355              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 356         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 357     }
 358 }
 359
 360 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 361 {
 362     if (env->sregs[LBEG] != v) {
 363         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 364         env->sregs[LBEG] = v;
 365     }
 366 }
 367
 368 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 369 {
 370     if (env->sregs[LEND] != v) {
 371         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 372         env->sregs[LEND] = v;
 373         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 374     }
 375 }
 376
 377 void HELPER(dump_state)(CPUXtensaState *env)
 378 {
 379     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 380
 381     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
 382 }
 383
 384 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 385 {
 386     CPUState *cpu;
 387
 388     env->pc = pc;
 389     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 390         (intlevel << PS_INTLEVEL_SHIFT);
 391     check_interrupts(env);
 392     if (env->pending_irq_level) {
 393         cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
 394         return;
 395     }
 396
 397     cpu = CPU(xtensa_env_get_cpu(env));
 398     env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 399     cpu->halted = 1;
 400     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 401         xtensa_rearm_ccompare_timer(env);
 402     }
 403     HELPER(exception)(env, EXCP_HLT);
 404 }
 405
 406 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 407 {
 408     xtensa_timer_irq(env, id, active);
 409 }
 410
 411 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 412 {
 413     xtensa_advance_ccount(env, d);
 414 }
 415
 416 void HELPER(check_interrupts)(CPUXtensaState *env)
 417 {
 418     check_interrupts(env);
 419 }
 420
 421 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
 422 {
 423     get_page_addr_code(env, vaddr);
 424 }
 425
 426 /*!
 427  * Check vaddr accessibility/cache attributes and raise an exception if
 428  * specified by the ATOMCTL SR.
 429  *
 430  * Note: local memory exclusion is not implemented
 431  */
 432 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 433 {
 434     uint32_t paddr, page_size, access;
 435     uint32_t atomctl = env->sregs[ATOMCTL];
 436     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 437             xtensa_get_cring(env), &paddr, &page_size, &access);
 438
 439     /*
 440      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 441      * see opcode description in the ISA
 442      */
 443     if (rc == 0 &&
 444             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 445         rc = STORE_PROHIBITED_CAUSE;
 446     }
 447
 448     if (rc) {
 449         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 450     }
 451
 452     /*
 453      * When data cache is not configured use ATOMCTL bypass field.
 454      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 455      * under the Conditional Store Option.
 456      */
 457     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 458         access = PAGE_CACHE_BYPASS;
 459     }
 460
 461     switch (access & PAGE_CACHE_MASK) {
 462     case PAGE_CACHE_WB:
 463         atomctl >>= 2;
 464         /* fall through */
 465     case PAGE_CACHE_WT:
 466         atomctl >>= 2;
 467         /* fall through */
 468     case PAGE_CACHE_BYPASS:
 469         if ((atomctl & 0x3) == 0) {
 470             HELPER(exception_cause_vaddr)(env, pc,
 471                     LOAD_STORE_ERROR_CAUSE, vaddr);
 472         }
 473         break;
 474
 475     case PAGE_CACHE_ISOLATE:
 476         HELPER(exception_cause_vaddr)(env, pc,
 477                 LOAD_STORE_ERROR_CAUSE, vaddr);
 478         break;
 479
 480     default:
 481         break;
 482     }
 483 }
 484
 485 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 486 {
 487     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 488
 489     v = (v & 0xffffff00) | 0x1;
 490     if (v != env->sregs[RASID]) {
 491         env->sregs[RASID] = v;
 492         tlb_flush(CPU(cpu), 1);
 493     }
 494 }
 495
 496 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 497 {
 498     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 499
 500     switch (way) {
 501     case 4:
 502         return (tlbcfg >> 16) & 0x3;
 503
 504     case 5:
 505         return (tlbcfg >> 20) & 0x1;
 506
 507     case 6:
 508         return (tlbcfg >> 24) & 0x1;
 509
 510     default:
 511         return 0;
 512     }
 513 }
 514
 515 /*!
 516  * Get bit mask for the virtual address bits translated by the TLB way
 517  */
 518 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 519 {
 520     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 521         bool varway56 = dtlb ?
 522             env->config->dtlb.varway56 :
 523             env->config->itlb.varway56;
 524
 525         switch (way) {
 526         case 4:
 527             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 528
 529         case 5:
 530             if (varway56) {
 531                 return 0xf8000000 << get_page_size(env, dtlb, way);
 532             } else {
 533                 return 0xf8000000;
 534             }
 535
 536         case 6:
 537             if (varway56) {
 538                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 539             } else {
 540                 return 0xf0000000;
 541             }
 542
 543         default:
 544             return 0xfffff000;
 545         }
 546     } else {
 547         return REGION_PAGE_MASK;
 548     }
 549 }
 550
 551 /*!
 552  * Get bit mask for the 'VPN without index' field.
 553  * See ISA, 4.6.5.6, data format for RxTLB0
 554  */
 555 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 556 {
 557     if (way < 4) {
 558         bool is32 = (dtlb ?
 559                 env->config->dtlb.nrefillentries :
 560                 env->config->itlb.nrefillentries) == 32;
 561         return is32 ? 0xffff8000 : 0xffffc000;
 562     } else if (way == 4) {
 563         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 564     } else if (way <= 6) {
 565         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 566         bool varway56 = dtlb ?
 567             env->config->dtlb.varway56 :
 568             env->config->itlb.varway56;
 569
 570         if (varway56) {
 571             return mask << (way == 5 ? 2 : 3);
 572         } else {
 573             return mask << 1;
 574         }
 575     } else {
 576         return 0xfffff000;
 577     }
 578 }
 579
 580 /*!
 581  * Split virtual address into VPN (with index) and entry index
 582  * for the given TLB way
 583  */
 584 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 585         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 586 {
 587     bool varway56 = dtlb ?
 588         env->config->dtlb.varway56 :
 589         env->config->itlb.varway56;
 590
 591     if (!dtlb) {
 592         wi &= 7;
 593     }
 594
 595     if (wi < 4) {
 596         bool is32 = (dtlb ?
 597                 env->config->dtlb.nrefillentries :
 598                 env->config->itlb.nrefillentries) == 32;
 599         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 600     } else {
 601         switch (wi) {
 602         case 4:
 603             {
 604                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 605                 *ei = (v >> eibase) & 0x3;
 606             }
 607             break;
 608
 609         case 5:
 610             if (varway56) {
 611                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 612                 *ei = (v >> eibase) & 0x3;
 613             } else {
 614                 *ei = (v >> 27) & 0x1;
 615             }
 616             break;
 617
 618         case 6:
 619             if (varway56) {
 620                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 621                 *ei = (v >> eibase) & 0x7;
 622             } else {
 623                 *ei = (v >> 28) & 0x1;
 624             }
 625             break;
 626
 627         default:
 628             *ei = 0;
 629             break;
 630         }
 631     }
 632     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 633 }
 634
 635 /*!
 636  * Split TLB address into TLB way, entry index and VPN (with index).
 637  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 638  */
 639 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 640         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 641 {
 642     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 643         *wi = v & (dtlb ? 0xf : 0x7);
 644         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 645     } else {
 646         *vpn = v & REGION_PAGE_MASK;
 647         *wi = 0;
 648         *ei = (v >> 29) & 0x7;
 649     }
 650 }
 651
 652 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 653         uint32_t v, bool dtlb, uint32_t *pwi)
 654 {
 655     uint32_t vpn;
 656     uint32_t wi;
 657     uint32_t ei;
 658
 659     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 660     if (pwi) {
 661         *pwi = wi;
 662     }
 663     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 664 }
 665
 666 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 667 {
 668     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 669         uint32_t wi;
 670         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 671         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 672     } else {
 673         return v & REGION_PAGE_MASK;
 674     }
 675 }
 676
 677 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 678 {
 679     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 680     return entry->paddr | entry->attr;
 681 }
 682
 683 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 684 {
 685     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 686         uint32_t wi;
 687         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 688         if (entry->variable && entry->asid) {
 689             tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
 690             entry->asid = 0;
 691         }
 692     }
 693 }
 694
 695 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 696 {
 697     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 698         uint32_t wi;
 699         uint32_t ei;
 700         uint8_t ring;
 701         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 702
 703         switch (res) {
 704         case 0:
 705             if (ring >= xtensa_get_ring(env)) {
 706                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 707             }
 708             break;
 709
 710         case INST_TLB_MULTI_HIT_CAUSE:
 711         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 712             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 713             break;
 714         }
 715         return 0;
 716     } else {
 717         return (v & REGION_PAGE_MASK) | 0x1;
 718     }
 719 }
 720
 721 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 722         xtensa_tlb_entry *entry, bool dtlb,
 723         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 724 {
 725     entry->vaddr = vpn;
 726     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 727     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 728     entry->attr = pte & 0xf;
 729 }
 730
 731 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 732         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 733 {
 734     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 735     CPUState *cs = CPU(cpu);
 736     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 737
 738     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 739         if (entry->variable) {
 740             if (entry->asid) {
 741                 tlb_flush_page(cs, entry->vaddr);
 742             }
 743             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 744             tlb_flush_page(cs, entry->vaddr);
 745         } else {
 746             qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set immutable entry\n",
 747                           __func__, dtlb, wi, ei);
 748         }
 749     } else {
 750         tlb_flush_page(cs, entry->vaddr);
 751         if (xtensa_option_enabled(env->config,
 752                     XTENSA_OPTION_REGION_TRANSLATION)) {
 753             entry->paddr = pte & REGION_PAGE_MASK;
 754         }
 755         entry->attr = pte & 0xf;
 756     }
 757 }
 758
 759 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 760 {
 761     uint32_t vpn;
 762     uint32_t wi;
 763     uint32_t ei;
 764     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 765     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 766 }
 767
 768
 769 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 770 {
 771     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 772     unsigned i;
 773
 774     for (i = 0; i < env->config->nibreak; ++i) {
 775         if (change & (1 << i)) {
 776             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 777         }
 778     }
 779     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 780 }
 781
 782 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 783 {
 784     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 785         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 786         tb_invalidate_virtual_addr(env, v);
 787     }
 788     env->sregs[IBREAKA + i] = v;
 789 }
 790
 791 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 792         uint32_t dbreakc)
 793 {
 794     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 795     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 796     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 797
 798     if (env->cpu_watchpoint[i]) {
 799         cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 800     }
 801     if (dbreakc & DBREAKC_SB) {
 802         flags |= BP_MEM_WRITE;
 803     }
 804     if (dbreakc & DBREAKC_LB) {
 805         flags |= BP_MEM_READ;
 806     }
 807     /* contiguous mask after inversion is one less than some power of 2 */
 808     if ((~mask + 1) & ~mask) {
 809         qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 810         /* cut mask after the first zero bit */
 811         mask = 0xffffffff << (32 - clo32(mask));
 812     }
 813     if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
 814             flags, &env->cpu_watchpoint[i])) {
 815         env->cpu_watchpoint[i] = NULL;
 816         qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n",
 817                       dbreaka & mask, ~mask + 1);
 818     }
 819 }
 820
 821 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 822 {
 823     uint32_t dbreakc = env->sregs[DBREAKC + i];
 824
 825     if ((dbreakc & DBREAKC_SB_LB) &&
 826             env->sregs[DBREAKA + i] != v) {
 827         set_dbreak(env, i, v, dbreakc);
 828     }
 829     env->sregs[DBREAKA + i] = v;
 830 }
 831
 832 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 833 {
 834     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 835         if (v & DBREAKC_SB_LB) {
 836             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 837         } else {
 838             if (env->cpu_watchpoint[i]) {
 839                 CPUState *cs = CPU(xtensa_env_get_cpu(env));
 840
 841                 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 842                 env->cpu_watchpoint[i] = NULL;
 843             }
 844         }
 845     }
 846     env->sregs[DBREAKC + i] = v;
 847 }
 848
 849 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 850 {
 851     static const int rounding_mode[] = {
 852         float_round_nearest_even,
 853         float_round_to_zero,
 854         float_round_up,
 855         float_round_down,
 856     };
 857
 858     env->uregs[FCR] = v & 0xfffff07f;
 859     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 860 }
 861
 862 float32 HELPER(abs_s)(float32 v)
 863 {
 864     return float32_abs(v);
 865 }
 866
 867 float32 HELPER(neg_s)(float32 v)
 868 {
 869     return float32_chs(v);
 870 }
 871
 872 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 873 {
 874     return float32_add(a, b, &env->fp_status);
 875 }
 876
 877 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 878 {
 879     return float32_sub(a, b, &env->fp_status);
 880 }
 881
 882 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 883 {
 884     return float32_mul(a, b, &env->fp_status);
 885 }
 886
 887 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 888 {
 889     return float32_muladd(b, c, a, 0,
 890             &env->fp_status);
 891 }
 892
 893 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 894 {
 895     return float32_muladd(b, c, a, float_muladd_negate_product,
 896             &env->fp_status);
 897 }
 898
 899 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 900 {
 901     float_status fp_status = {0};
 902
 903     set_float_rounding_mode(rounding_mode, &fp_status);
 904     return float32_to_int32(
 905             float32_scalbn(v, scale, &fp_status), &fp_status);
 906 }
 907
 908 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 909 {
 910     float_status fp_status = {0};
 911     float32 res;
 912
 913     set_float_rounding_mode(rounding_mode, &fp_status);
 914
 915     res = float32_scalbn(v, scale, &fp_status);
 916
 917     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 918         return float32_to_int32(res, &fp_status);
 919     } else {
 920         return float32_to_uint32(res, &fp_status);
 921     }
 922 }
 923
 924 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 925 {
 926     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 927             (int32_t)scale, &env->fp_status);
 928 }
 929
 930 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 931 {
 932     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 933             (int32_t)scale, &env->fp_status);
 934 }
 935
 936 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 937 {
 938     if (v) {
 939         env->sregs[BR] |= br;
 940     } else {
 941         env->sregs[BR] &= ~br;
 942     }
 943 }
 944
 945 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 946 {
 947     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 948 }
 949
 950 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 951 {
 952     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 953 }
 954
 955 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 956 {
 957     int v = float32_compare_quiet(a, b, &env->fp_status);
 958     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 959 }
 960
 961 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 962 {
 963     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 964 }
 965
 966 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 967 {
 968     int v = float32_compare_quiet(a, b, &env->fp_status);
 969     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 970 }
 971
 972 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 973 {
 974     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 975 }
 976
 977 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 978 {
 979     int v = float32_compare_quiet(a, b, &env->fp_status);
 980     set_br(env, v != float_relation_greater, br);
 981 }