target-sparc/cpu.h

   1 #ifndef CPU_SPARC_H
   2 #define CPU_SPARC_H
   3
   4 #include "config.h"
   5
   6 #if !defined(TARGET_SPARC64)
   7 #define TARGET_LONG_BITS 32
   8 #define TARGET_FPREGS 32
   9 #define TARGET_PAGE_BITS 12 /* 4k */
  10 #else
  11 #define TARGET_LONG_BITS 64
  12 #define TARGET_FPREGS 64
  13 #define TARGET_PAGE_BITS 13 /* 8k */
  14 #endif
  15
  16 #define CPUState struct CPUSPARCState
  17
  18 #include "cpu-defs.h"
  19
  20 #include "softfloat.h"
  21
  22 #define TARGET_HAS_ICE 1
  23
  24 #if !defined(TARGET_SPARC64)
  25 #define ELF_MACHINE     EM_SPARC
  26 #else
  27 #define ELF_MACHINE     EM_SPARCV9
  28 #endif
  29
  30 /*#define EXCP_INTERRUPT 0x100*/
  31
  32 /* trap definitions */
  33 #ifndef TARGET_SPARC64
  34 #define TT_TFAULT   0x01
  35 #define TT_ILL_INSN 0x02
  36 #define TT_PRIV_INSN 0x03
  37 #define TT_NFPU_INSN 0x04
  38 #define TT_WIN_OVF  0x05
  39 #define TT_WIN_UNF  0x06
  40 #define TT_UNALIGNED 0x07
  41 #define TT_FP_EXCP  0x08
  42 #define TT_DFAULT   0x09
  43 #define TT_TOVF     0x0a
  44 #define TT_EXTINT   0x10
  45 #define TT_CODE_ACCESS 0x21
  46 #define TT_UNIMP_FLUSH 0x25
  47 #define TT_DATA_ACCESS 0x29
  48 #define TT_DIV_ZERO 0x2a
  49 #define TT_NCP_INSN 0x24
  50 #define TT_TRAP     0x80
  51 #else
  52 #define TT_POWER_ON_RESET 0x01
  53 #define TT_TFAULT   0x08
  54 #define TT_CODE_ACCESS 0x0a
  55 #define TT_ILL_INSN 0x10
  56 #define TT_UNIMP_FLUSH TT_ILL_INSN
  57 #define TT_PRIV_INSN 0x11
  58 #define TT_NFPU_INSN 0x20
  59 #define TT_FP_EXCP  0x21
  60 #define TT_TOVF     0x23
  61 #define TT_CLRWIN   0x24
  62 #define TT_DIV_ZERO 0x28
  63 #define TT_DFAULT   0x30
  64 #define TT_DATA_ACCESS 0x32
  65 #define TT_UNALIGNED 0x34
  66 #define TT_PRIV_ACT 0x37
  67 #define TT_EXTINT   0x40
  68 #define TT_IVEC     0x60
  69 #define TT_TMISS    0x64
  70 #define TT_DMISS    0x68
  71 #define TT_DPROT    0x6c
  72 #define TT_SPILL    0x80
  73 #define TT_FILL     0xc0
  74 #define TT_WOTHER   0x10
  75 #define TT_TRAP     0x100
  76 #endif
  77
  78 #define PSR_NEG_SHIFT 23
  79 #define PSR_NEG   (1 << PSR_NEG_SHIFT)
  80 #define PSR_ZERO_SHIFT 22
  81 #define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  82 #define PSR_OVF_SHIFT 21
  83 #define PSR_OVF   (1 << PSR_OVF_SHIFT)
  84 #define PSR_CARRY_SHIFT 20
  85 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  86 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  87 #define PSR_EF    (1<<12)
  88 #define PSR_PIL   0xf00
  89 #define PSR_S     (1<<7)
  90 #define PSR_PS    (1<<6)
  91 #define PSR_ET    (1<<5)
  92 #define PSR_CWP   0x1f
  93
  94 #define CC_SRC (env->cc_src)
  95 #define CC_SRC2 (env->cc_src2)
  96 #define CC_DST (env->cc_dst)
  97 #define CC_OP  (env->cc_op)
  98
  99 enum {
 100     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 101     CC_OP_FLAGS,   /* all cc are back in status register */
 102     CC_OP_DIV,     /* modify N, Z and V, C = 0*/
 103     CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 104     CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 105     CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 106     CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 107     CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 108     CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 109     CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 110     CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 111     CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 112     CC_OP_NB,
 113 };
 114
 115 /* Trap base register */
 116 #define TBR_BASE_MASK 0xfffff000
 117
 118 #if defined(TARGET_SPARC64)
 119 #define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 120 #define PS_IG    (1<<11) /* v9, zero on UA2007 */
 121 #define PS_MG    (1<<10) /* v9, zero on UA2007 */
 122 #define PS_CLE   (1<<9) /* UA2007 */
 123 #define PS_TLE   (1<<8) /* UA2007 */
 124 #define PS_RMO   (1<<7)
 125 #define PS_RED   (1<<5) /* v9, zero on UA2007 */
 126 #define PS_PEF   (1<<4) /* enable fpu */
 127 #define PS_AM    (1<<3) /* address mask */
 128 #define PS_PRIV  (1<<2)
 129 #define PS_IE    (1<<1)
 130 #define PS_AG    (1<<0) /* v9, zero on UA2007 */
 131
 132 #define FPRS_FEF (1<<2)
 133
 134 #define HS_PRIV  (1<<2)
 135 #endif
 136
 137 /* Fcc */
 138 #define FSR_RD1        (1ULL << 31)
 139 #define FSR_RD0        (1ULL << 30)
 140 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 141 #define FSR_RD_NEAREST 0
 142 #define FSR_RD_ZERO    FSR_RD0
 143 #define FSR_RD_POS     FSR_RD1
 144 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 145
 146 #define FSR_NVM   (1ULL << 27)
 147 #define FSR_OFM   (1ULL << 26)
 148 #define FSR_UFM   (1ULL << 25)
 149 #define FSR_DZM   (1ULL << 24)
 150 #define FSR_NXM   (1ULL << 23)
 151 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 152
 153 #define FSR_NVA   (1ULL << 9)
 154 #define FSR_OFA   (1ULL << 8)
 155 #define FSR_UFA   (1ULL << 7)
 156 #define FSR_DZA   (1ULL << 6)
 157 #define FSR_NXA   (1ULL << 5)
 158 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 159
 160 #define FSR_NVC   (1ULL << 4)
 161 #define FSR_OFC   (1ULL << 3)
 162 #define FSR_UFC   (1ULL << 2)
 163 #define FSR_DZC   (1ULL << 1)
 164 #define FSR_NXC   (1ULL << 0)
 165 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 166
 167 #define FSR_FTT2   (1ULL << 16)
 168 #define FSR_FTT1   (1ULL << 15)
 169 #define FSR_FTT0   (1ULL << 14)
 170 //gcc warns about constant overflow for ~FSR_FTT_MASK
 171 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 172 #ifdef TARGET_SPARC64
 173 #define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 174 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 175 #define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 176 #define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 177 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 178 #else
 179 #define FSR_FTT_NMASK      0xfffe3fffULL
 180 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 181 #define FSR_LDFSR_OLDMASK  0x000fc000ULL
 182 #endif
 183 #define FSR_LDFSR_MASK     0xcfc00fffULL
 184 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
 185 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
 186 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
 187 #define FSR_FTT_INVAL_FPR (6ULL << 14)
 188
 189 #define FSR_FCC1_SHIFT 11
 190 #define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 191 #define FSR_FCC0_SHIFT 10
 192 #define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 193
 194 /* MMU */
 195 #define MMU_E     (1<<0)
 196 #define MMU_NF    (1<<1)
 197
 198 #define PTE_ENTRYTYPE_MASK 3
 199 #define PTE_ACCESS_MASK    0x1c
 200 #define PTE_ACCESS_SHIFT   2
 201 #define PTE_PPN_SHIFT      7
 202 #define PTE_ADDR_MASK      0xffffff00
 203
 204 #define PG_ACCESSED_BIT 5
 205 #define PG_MODIFIED_BIT 6
 206 #define PG_CACHE_BIT    7
 207
 208 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 209 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 210 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 211
 212 /* 3 <= NWINDOWS <= 32. */
 213 #define MIN_NWINDOWS 3
 214 #define MAX_NWINDOWS 32
 215
 216 #if !defined(TARGET_SPARC64)
 217 #define NB_MMU_MODES 2
 218 #else
 219 #define NB_MMU_MODES 3
 220 typedef struct trap_state {
 221     uint64_t tpc;
 222     uint64_t tnpc;
 223     uint64_t tstate;
 224     uint32_t tt;
 225 } trap_state;
 226 #endif
 227
 228 typedef struct sparc_def_t {
 229     const char *name;
 230     target_ulong iu_version;
 231     uint32_t fpu_version;
 232     uint32_t mmu_version;
 233     uint32_t mmu_bm;
 234     uint32_t mmu_ctpr_mask;
 235     uint32_t mmu_cxr_mask;
 236     uint32_t mmu_sfsr_mask;
 237     uint32_t mmu_trcr_mask;
 238     uint32_t mxcc_version;
 239     uint32_t features;
 240     uint32_t nwindows;
 241     uint32_t maxtl;
 242 } sparc_def_t;
 243
 244 #define CPU_FEATURE_FLOAT    (1 << 0)
 245 #define CPU_FEATURE_FLOAT128 (1 << 1)
 246 #define CPU_FEATURE_SWAP     (1 << 2)
 247 #define CPU_FEATURE_MUL      (1 << 3)
 248 #define CPU_FEATURE_DIV      (1 << 4)
 249 #define CPU_FEATURE_FLUSH    (1 << 5)
 250 #define CPU_FEATURE_FSQRT    (1 << 6)
 251 #define CPU_FEATURE_FMUL     (1 << 7)
 252 #define CPU_FEATURE_VIS1     (1 << 8)
 253 #define CPU_FEATURE_VIS2     (1 << 9)
 254 #define CPU_FEATURE_FSMULD   (1 << 10)
 255 #define CPU_FEATURE_HYPV     (1 << 11)
 256 #define CPU_FEATURE_CMT      (1 << 12)
 257 #define CPU_FEATURE_GL       (1 << 13)
 258 #ifndef TARGET_SPARC64
 259 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 260                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 261                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 262                               CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 263 #else
 264 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 265                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 266                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 267                               CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 268                               CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
 269 enum {
 270     mmu_us_12, // Ultrasparc < III (64 entry TLB)
 271     mmu_us_3,  // Ultrasparc III (512 entry TLB)
 272     mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 273     mmu_sun4v, // T1, T2
 274 };
 275 #endif
 276
 277 #define TTE_VALID_BIT       (1ULL << 63)
 278 #define TTE_USED_BIT        (1ULL << 41)
 279 #define TTE_LOCKED_BIT      (1ULL <<  6)
 280 #define TTE_GLOBAL_BIT      (1ULL <<  0)
 281
 282 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 283 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 284 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 285 #define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 286
 287 #define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 288 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 289
 290 typedef struct SparcTLBEntry {
 291     uint64_t tag;
 292     uint64_t tte;
 293 } SparcTLBEntry;
 294
 295 typedef struct CPUSPARCState {
 296     target_ulong gregs[8]; /* general registers */
 297     target_ulong *regwptr; /* pointer to current register window */
 298     target_ulong pc;       /* program counter */
 299     target_ulong npc;      /* next program counter */
 300     target_ulong y;        /* multiply/divide register */
 301
 302     /* emulator internal flags handling */
 303     target_ulong cc_src, cc_src2;
 304     target_ulong cc_dst;
 305     uint32_t cc_op;
 306
 307     target_ulong t0, t1; /* temporaries live across basic blocks */
 308     target_ulong cond; /* conditional branch result (XXX: save it in a
 309                           temporary register when possible) */
 310
 311     uint32_t psr;      /* processor state register */
 312     target_ulong fsr;      /* FPU state register */
 313     float32 fpr[TARGET_FPREGS];  /* floating point registers */
 314     uint32_t cwp;      /* index of current register window (extracted
 315                           from PSR) */
 316 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 317     uint32_t wim;      /* window invalid mask */
 318 #endif
 319     target_ulong tbr;  /* trap base register */
 320     int      psrs;     /* supervisor mode (extracted from PSR) */
 321     int      psrps;    /* previous supervisor mode */
 322 #if !defined(TARGET_SPARC64)
 323     int      psret;    /* enable traps */
 324 #endif
 325     uint32_t psrpil;   /* interrupt blocking level */
 326     uint32_t pil_in;   /* incoming interrupt level bitmap */
 327     int      psref;    /* enable fpu */
 328     target_ulong version;
 329     int interrupt_index;
 330     uint32_t nwindows;
 331     /* NOTE: we allow 8 more registers to handle wrapping */
 332     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 333
 334     CPU_COMMON
 335
 336     /* MMU regs */
 337 #if defined(TARGET_SPARC64)
 338     uint64_t lsu;
 339 #define DMMU_E 0x8
 340 #define IMMU_E 0x4
 341     //typedef struct SparcMMU
 342     union {
 343         uint64_t immuregs[16];
 344         struct {
 345             uint64_t tsb_tag_target;
 346             uint64_t unused_mmu_primary_context;   // use DMMU
 347             uint64_t unused_mmu_secondary_context; // use DMMU
 348             uint64_t sfsr;
 349             uint64_t sfar;
 350             uint64_t tsb;
 351             uint64_t tag_access;
 352         } immu;
 353     };
 354     union {
 355         uint64_t dmmuregs[16];
 356         struct {
 357             uint64_t tsb_tag_target;
 358             uint64_t mmu_primary_context;
 359             uint64_t mmu_secondary_context;
 360             uint64_t sfsr;
 361             uint64_t sfar;
 362             uint64_t tsb;
 363             uint64_t tag_access;
 364         } dmmu;
 365     };
 366     SparcTLBEntry itlb[64];
 367     SparcTLBEntry dtlb[64];
 368     uint32_t mmu_version;
 369 #else
 370     uint32_t mmuregs[32];
 371     uint64_t mxccdata[4];
 372     uint64_t mxccregs[8];
 373     uint64_t mmubpregs[4];
 374     uint64_t prom_addr;
 375 #endif
 376     /* temporary float registers */
 377     float64 dt0, dt1;
 378     float128 qt0, qt1;
 379     float_status fp_status;
 380 #if defined(TARGET_SPARC64)
 381 #define MAXTL_MAX 8
 382 #define MAXTL_MASK (MAXTL_MAX - 1)
 383     trap_state ts[MAXTL_MAX];
 384     uint32_t xcc;               /* Extended integer condition codes */
 385     uint32_t asi;
 386     uint32_t pstate;
 387     uint32_t tl;
 388     uint32_t maxtl;
 389     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 390     uint64_t agregs[8]; /* alternate general registers */
 391     uint64_t bgregs[8]; /* backup for normal global registers */
 392     uint64_t igregs[8]; /* interrupt general registers */
 393     uint64_t mgregs[8]; /* mmu general registers */
 394     uint64_t fprs;
 395     uint64_t tick_cmpr, stick_cmpr;
 396     void *tick, *stick;
 397     uint64_t gsr;
 398     uint32_t gl; // UA2005
 399     /* UA 2005 hyperprivileged registers */
 400     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 401     void *hstick; // UA 2005
 402     uint32_t softint;
 403 #define SOFTINT_TIMER   1
 404 #define SOFTINT_STIMER  (1 << 16)
 405 #endif
 406     sparc_def_t *def;
 407 } CPUSPARCState;
 408
 409 /* helper.c */
 410 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
 411 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 412 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 413                                                  ...));
 414 void cpu_lock(void);
 415 void cpu_unlock(void);
 416 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
 417                                int mmu_idx, int is_softmmu);
 418 #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
 419 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 420 void dump_mmu(CPUSPARCState *env);
 421
 422 /* translate.c */
 423 void gen_intermediate_code_init(CPUSPARCState *env);
 424
 425 /* cpu-exec.c */
 426 int cpu_sparc_exec(CPUSPARCState *s);
 427
 428 #if !defined (TARGET_SPARC64)
 429 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
 430                       (env->psref? PSR_EF : 0) |                        \
 431                       (env->psrpil << 8) |                              \
 432                       (env->psrs? PSR_S : 0) |                          \
 433                       (env->psrps? PSR_PS : 0) |                        \
 434                       (env->psret? PSR_ET : 0) | env->cwp)
 435 #else
 436 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
 437                       (env->psref? PSR_EF : 0) |                        \
 438                       (env->psrpil << 8) |                              \
 439                       (env->psrs? PSR_S : 0) |                          \
 440                       (env->psrps? PSR_PS : 0) |                        \
 441                       env->cwp)
 442 #endif
 443
 444 #ifndef NO_CPU_IO_DEFS
 445
 446 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
 447 {
 448     if (unlikely(cwp >= env1->nwindows))
 449         cwp -= env1->nwindows;
 450     return cwp;
 451 }
 452
 453 static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
 454 {
 455     if (unlikely(cwp < 0))
 456         cwp += env1->nwindows;
 457     return cwp;
 458 }
 459 #endif
 460
 461 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
 462 {
 463     dst[0] = src[0];
 464     dst[1] = src[1];
 465     dst[2] = src[2];
 466     dst[3] = src[3];
 467     dst[4] = src[4];
 468     dst[5] = src[5];
 469     dst[6] = src[6];
 470     dst[7] = src[7];
 471 }
 472
 473 static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
 474 {
 475     /* put the modified wrap registers at their proper location */
 476     if (env1->cwp == env1->nwindows - 1)
 477         memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
 478     env1->cwp = new_cwp;
 479     /* put the wrap registers at their temporary location */
 480     if (new_cwp == env1->nwindows - 1)
 481         memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
 482     env1->regwptr = env1->regbase + (new_cwp * 16);
 483 }
 484
 485 /* sun4m.c, sun4u.c */
 486 void cpu_check_irqs(CPUSPARCState *env);
 487
 488 static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val)
 489 {
 490     env1->psr = val & PSR_ICC;
 491     env1->psref = (val & PSR_EF)? 1 : 0;
 492     env1->psrpil = (val & PSR_PIL) >> 8;
 493 #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
 494     cpu_check_irqs(env1);
 495 #endif
 496     env1->psrs = (val & PSR_S)? 1 : 0;
 497     env1->psrps = (val & PSR_PS)? 1 : 0;
 498 #if !defined (TARGET_SPARC64)
 499     env1->psret = (val & PSR_ET)? 1 : 0;
 500 #endif
 501     cpu_set_cwp(env1, val & PSR_CWP);
 502     env1->cc_op = CC_OP_FLAGS;
 503 }
 504
 505 #ifdef TARGET_SPARC64
 506 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
 507 #define PUT_CCR(env, val) do { int _tmp = val;                          \
 508         env->xcc = (_tmp >> 4) << 20;                                   \
 509         env->psr = (_tmp & 0xf) << 20;                                  \
 510         CC_OP = CC_OP_FLAGS;                                            \
 511     } while (0)
 512 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
 513
 514 #ifndef NO_CPU_IO_DEFS
 515 static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
 516 {
 517     if (unlikely(cwp >= env1->nwindows || cwp < 0))
 518         cwp = 0;
 519     cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
 520 }
 521 #endif
 522 #endif
 523
 524 /* cpu-exec.c */
 525 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 526                           int is_asi, int size);
 527 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 528
 529 #define cpu_init cpu_sparc_init
 530 #define cpu_exec cpu_sparc_exec
 531 #define cpu_gen_code cpu_sparc_gen_code
 532 #define cpu_signal_handler cpu_sparc_signal_handler
 533 #define cpu_list sparc_cpu_list
 534
 535 #define CPU_SAVE_VERSION 5
 536
 537 /* MMU modes definitions */
 538 #define MMU_MODE0_SUFFIX _user
 539 #define MMU_MODE1_SUFFIX _kernel
 540 #ifdef TARGET_SPARC64
 541 #define MMU_MODE2_SUFFIX _hypv
 542 #endif
 543 #define MMU_USER_IDX   0
 544 #define MMU_KERNEL_IDX 1
 545 #define MMU_HYPV_IDX   2
 546
 547 static inline int cpu_mmu_index(CPUState *env1)
 548 {
 549 #if defined(CONFIG_USER_ONLY)
 550     return MMU_USER_IDX;
 551 #elif !defined(TARGET_SPARC64)
 552     return env1->psrs;
 553 #else
 554     if (!env1->psrs)
 555         return MMU_USER_IDX;
 556     else if ((env1->hpstate & HS_PRIV) == 0)
 557         return MMU_KERNEL_IDX;
 558     else
 559         return MMU_HYPV_IDX;
 560 #endif
 561 }
 562
 563 static inline int cpu_fpu_enabled(CPUState *env1)
 564 {
 565 #if defined(CONFIG_USER_ONLY)
 566     return 1;
 567 #elif !defined(TARGET_SPARC64)
 568     return env1->psref;
 569 #else
 570     return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
 571 #endif
 572 }
 573
 574 #if defined(CONFIG_USER_ONLY)
 575 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 576 {
 577     if (newsp)
 578         env->regwptr[22] = newsp;
 579     env->regwptr[0] = 0;
 580     /* FIXME: Do we also need to clear CF?  */
 581     /* XXXXX */
 582     printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
 583 }
 584 #endif
 585
 586 #include "cpu-all.h"
 587 #include "exec-all.h"
 588
 589 #ifdef TARGET_SPARC64
 590 /* sun4u.c */
 591 void cpu_tick_set_count(void *opaque, uint64_t count);
 592 uint64_t cpu_tick_get_count(void *opaque);
 593 void cpu_tick_set_limit(void *opaque, uint64_t limit);
 594 trap_state* cpu_tsptr(CPUState* env);
 595 #endif
 596
 597 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 598 {
 599     env->pc = tb->pc;
 600     env->npc = tb->cs_base;
 601 }
 602
 603 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 604                                         target_ulong *cs_base, int *flags)
 605 {
 606     *pc = env->pc;
 607     *cs_base = env->npc;
 608 #ifdef TARGET_SPARC64
 609     // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
 610     *flags = ((env->pstate & PS_AM) << 2)
 611         | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
 612         | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
 613 #else
 614     // FPU enable . Supervisor
 615     *flags = (env->psref << 4) | env->psrs;
 616 #endif
 617 }
 618
 619 #endif