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monitor: do_balloon(): Use 'M' argument type
[qemu/ar7.git] / hw / pci.c
blob9cc5a6a3efd20b1518ded5f8a87d88bc202ad1dd
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29 #include "loader.h"
30
31 //#define DEBUG_PCI
32 #ifdef DEBUG_PCI
33 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
34 #else
35 # define PCI_DPRINTF(format, ...) do { } while (0)
36 #endif
37
38 struct PCIBus {
39 BusState qbus;
40 int devfn_min;
41 pci_set_irq_fn set_irq;
42 pci_map_irq_fn map_irq;
43 pci_hotplug_fn hotplug;
44 uint32_t config_reg; /* XXX: suppress */
45 void *irq_opaque;
46 PCIDevice *devices[256];
47 PCIDevice *parent_dev;
48
49 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
50 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
51
52 /* The bus IRQ state is the logical OR of the connected devices.
53 Keep a count of the number of devices with raised IRQs. */
54 int nirq;
55 int *irq_count;
56 };
57
58 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
59
60 static struct BusInfo pci_bus_info = {
61 .name = "PCI",
62 .size = sizeof(PCIBus),
63 .print_dev = pcibus_dev_print,
64 .props = (Property[]) {
65 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
66 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
67 DEFINE_PROP_END_OF_LIST()
68 }
69 };
70
71 static void pci_update_mappings(PCIDevice *d);
72 static void pci_set_irq(void *opaque, int irq_num, int level);
73 static int pci_add_option_rom(PCIDevice *pdev);
74
75 target_phys_addr_t pci_mem_base;
76 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
77 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
78
79 struct PCIHostBus {
80 int domain;
81 struct PCIBus *bus;
82 QLIST_ENTRY(PCIHostBus) next;
83 };
84 static QLIST_HEAD(, PCIHostBus) host_buses;
85
86 static const VMStateDescription vmstate_pcibus = {
87 .name = "PCIBUS",
88 .version_id = 1,
89 .minimum_version_id = 1,
90 .minimum_version_id_old = 1,
91 .fields = (VMStateField []) {
92 VMSTATE_INT32_EQUAL(nirq, PCIBus),
93 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
94 VMSTATE_END_OF_LIST()
95 }
96 };
97
98 static int pci_bar(PCIDevice *d, int reg)
99 {
100 uint8_t type;
101
102 if (reg != PCI_ROM_SLOT)
103 return PCI_BASE_ADDRESS_0 + reg * 4;
104
105 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
106 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
107 }
108
109 static inline int pci_irq_state(PCIDevice *d, int irq_num)
110 {
111 return (d->irq_state >> irq_num) & 0x1;
112 }
113
114 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
115 {
116 d->irq_state &= ~(0x1 << irq_num);
117 d->irq_state |= level << irq_num;
118 }
119
120 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
121 {
122 PCIBus *bus;
123 for (;;) {
124 bus = pci_dev->bus;
125 irq_num = bus->map_irq(pci_dev, irq_num);
126 if (bus->set_irq)
127 break;
128 pci_dev = bus->parent_dev;
129 }
130 bus->irq_count[irq_num] += change;
131 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
132 }
133
134 /* Update interrupt status bit in config space on interrupt
135 * state change. */
136 static void pci_update_irq_status(PCIDevice *dev)
137 {
138 if (dev->irq_state) {
139 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
140 } else {
141 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
142 }
143 }
144
145 static void pci_device_reset(PCIDevice *dev)
146 {
147 int r;
148
149 dev->irq_state = 0;
150 pci_update_irq_status(dev);
151 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
152 PCI_COMMAND_MASTER);
153 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
154 dev->config[PCI_INTERRUPT_LINE] = 0x0;
155 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
156 if (!dev->io_regions[r].size) {
157 continue;
158 }
159 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
160 }
161 pci_update_mappings(dev);
162 }
163
164 static void pci_bus_reset(void *opaque)
165 {
166 PCIBus *bus = opaque;
167 int i;
168
169 for (i = 0; i < bus->nirq; i++) {
170 bus->irq_count[i] = 0;
171 }
172 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
173 if (bus->devices[i]) {
174 pci_device_reset(bus->devices[i]);
175 }
176 }
177 }
178
179 static void pci_host_bus_register(int domain, PCIBus *bus)
180 {
181 struct PCIHostBus *host;
182 host = qemu_mallocz(sizeof(*host));
183 host->domain = domain;
184 host->bus = bus;
185 QLIST_INSERT_HEAD(&host_buses, host, next);
186 }
187
188 PCIBus *pci_find_root_bus(int domain)
189 {
190 struct PCIHostBus *host;
191
192 QLIST_FOREACH(host, &host_buses, next) {
193 if (host->domain == domain) {
194 return host->bus;
195 }
196 }
197
198 return NULL;
199 }
200
201 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
202 const char *name, int devfn_min)
203 {
204 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
205 bus->devfn_min = devfn_min;
206
207 /* host bridge */
208 QLIST_INIT(&bus->child);
209 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
210
211 vmstate_register(-1, &vmstate_pcibus, bus);
212 qemu_register_reset(pci_bus_reset, bus);
213 }
214
215 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
216 {
217 PCIBus *bus;
218
219 bus = qemu_mallocz(sizeof(*bus));
220 bus->qbus.qdev_allocated = 1;
221 pci_bus_new_inplace(bus, parent, name, devfn_min);
222 return bus;
223 }
224
225 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
226 void *irq_opaque, int nirq)
227 {
228 bus->set_irq = set_irq;
229 bus->map_irq = map_irq;
230 bus->irq_opaque = irq_opaque;
231 bus->nirq = nirq;
232 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
233 }
234
235 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
236 {
237 bus->qbus.allow_hotplug = 1;
238 bus->hotplug = hotplug;
239 }
240
241 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
242 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
243 void *irq_opaque, int devfn_min, int nirq)
244 {
245 PCIBus *bus;
246
247 bus = pci_bus_new(parent, name, devfn_min);
248 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
249 return bus;
250 }
251
252 static void pci_register_secondary_bus(PCIBus *parent,
253 PCIBus *bus,
254 PCIDevice *dev,
255 pci_map_irq_fn map_irq,
256 const char *name)
257 {
258 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
259 bus->map_irq = map_irq;
260 bus->parent_dev = dev;
261
262 QLIST_INIT(&bus->child);
263 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
264 }
265
266 static void pci_unregister_secondary_bus(PCIBus *bus)
267 {
268 assert(QLIST_EMPTY(&bus->child));
269 QLIST_REMOVE(bus, sibling);
270 }
271
272 int pci_bus_num(PCIBus *s)
273 {
274 if (!s->parent_dev)
275 return 0; /* pci host bridge */
276 return s->parent_dev->config[PCI_SECONDARY_BUS];
277 }
278
279 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
280 {
281 PCIDevice *s = container_of(pv, PCIDevice, config);
282 uint8_t *config;
283 int i;
284
285 assert(size == pci_config_size(s));
286 config = qemu_malloc(size);
287
288 qemu_get_buffer(f, config, size);
289 for (i = 0; i < size; ++i) {
290 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
291 qemu_free(config);
292 return -EINVAL;
293 }
294 }
295 memcpy(s->config, config, size);
296
297 pci_update_mappings(s);
298
299 qemu_free(config);
300 return 0;
301 }
302
303 /* just put buffer */
304 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
305 {
306 const uint8_t **v = pv;
307 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
308 qemu_put_buffer(f, *v, size);
309 }
310
311 static VMStateInfo vmstate_info_pci_config = {
312 .name = "pci config",
313 .get = get_pci_config_device,
314 .put = put_pci_config_device,
315 };
316
317 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
318 {
319 PCIDevice *s = container_of(pv, PCIDevice, config);
320 uint32_t irq_state[PCI_NUM_PINS];
321 int i;
322 for (i = 0; i < PCI_NUM_PINS; ++i) {
323 irq_state[i] = qemu_get_be32(f);
324 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
325 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
326 irq_state[i]);
327 return -EINVAL;
328 }
329 }
330
331 for (i = 0; i < PCI_NUM_PINS; ++i) {
332 pci_set_irq_state(s, i, irq_state[i]);
333 }
334
335 return 0;
336 }
337
338 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
339 {
340 int i;
341 PCIDevice *s = container_of(pv, PCIDevice, config);
342
343 for (i = 0; i < PCI_NUM_PINS; ++i) {
344 qemu_put_be32(f, pci_irq_state(s, i));
345 }
346 }
347
348 static VMStateInfo vmstate_info_pci_irq_state = {
349 .name = "pci irq state",
350 .get = get_pci_irq_state,
351 .put = put_pci_irq_state,
352 };
353
354 const VMStateDescription vmstate_pci_device = {
355 .name = "PCIDevice",
356 .version_id = 2,
357 .minimum_version_id = 1,
358 .minimum_version_id_old = 1,
359 .fields = (VMStateField []) {
360 VMSTATE_INT32_LE(version_id, PCIDevice),
361 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
362 vmstate_info_pci_config,
363 PCI_CONFIG_SPACE_SIZE),
364 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
365 vmstate_info_pci_irq_state,
366 PCI_NUM_PINS * sizeof(int32_t)),
367 VMSTATE_END_OF_LIST()
368 }
369 };
370
371 const VMStateDescription vmstate_pcie_device = {
372 .name = "PCIDevice",
373 .version_id = 2,
374 .minimum_version_id = 1,
375 .minimum_version_id_old = 1,
376 .fields = (VMStateField []) {
377 VMSTATE_INT32_LE(version_id, PCIDevice),
378 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
379 vmstate_info_pci_config,
380 PCIE_CONFIG_SPACE_SIZE),
381 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
382 vmstate_info_pci_irq_state,
383 PCI_NUM_PINS * sizeof(int32_t)),
384 VMSTATE_END_OF_LIST()
385 }
386 };
387
388 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
389 {
390 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
391 }
392
393 void pci_device_save(PCIDevice *s, QEMUFile *f)
394 {
395 /* Clear interrupt status bit: it is implicit
396 * in irq_state which we are saving.
397 * This makes us compatible with old devices
398 * which never set or clear this bit. */
399 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
400 vmstate_save_state(f, pci_get_vmstate(s), s);
401 /* Restore the interrupt status bit. */
402 pci_update_irq_status(s);
403 }
404
405 int pci_device_load(PCIDevice *s, QEMUFile *f)
406 {
407 int ret;
408 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
409 /* Restore the interrupt status bit. */
410 pci_update_irq_status(s);
411 return ret;
412 }
413
414 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
415 {
416 uint16_t *id;
417
418 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
419 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
420 id[1] = cpu_to_le16(pci_default_sub_device_id);
421 return 0;
422 }
423
424 /*
425 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
426 */
427 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
428 {
429 const char *p;
430 char *e;
431 unsigned long val;
432 unsigned long dom = 0, bus = 0;
433 unsigned slot = 0;
434
435 p = addr;
436 val = strtoul(p, &e, 16);
437 if (e == p)
438 return -1;
439 if (*e == ':') {
440 bus = val;
441 p = e + 1;
442 val = strtoul(p, &e, 16);
443 if (e == p)
444 return -1;
445 if (*e == ':') {
446 dom = bus;
447 bus = val;
448 p = e + 1;
449 val = strtoul(p, &e, 16);
450 if (e == p)
451 return -1;
452 }
453 }
454
455 if (dom > 0xffff || bus > 0xff || val > 0x1f)
456 return -1;
457
458 slot = val;
459
460 if (*e)
461 return -1;
462
463 /* Note: QEMU doesn't implement domains other than 0 */
464 if (!pci_find_bus(pci_find_root_bus(dom), bus))
465 return -1;
466
467 *domp = dom;
468 *busp = bus;
469 *slotp = slot;
470 return 0;
471 }
472
473 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
474 unsigned *slotp)
475 {
476 /* strip legacy tag */
477 if (!strncmp(addr, "pci_addr=", 9)) {
478 addr += 9;
479 }
480 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
481 monitor_printf(mon, "Invalid pci address\n");
482 return -1;
483 }
484 return 0;
485 }
486
487 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
488 {
489 int dom, bus;
490 unsigned slot;
491
492 if (!devaddr) {
493 *devfnp = -1;
494 return pci_find_bus(pci_find_root_bus(0), 0);
495 }
496
497 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
498 return NULL;
499 }
500
501 *devfnp = slot << 3;
502 return pci_find_bus(pci_find_root_bus(0), bus);
503 }
504
505 static void pci_init_cmask(PCIDevice *dev)
506 {
507 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
508 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
509 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
510 dev->cmask[PCI_REVISION_ID] = 0xff;
511 dev->cmask[PCI_CLASS_PROG] = 0xff;
512 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
513 dev->cmask[PCI_HEADER_TYPE] = 0xff;
514 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
515 }
516
517 static void pci_init_wmask(PCIDevice *dev)
518 {
519 int config_size = pci_config_size(dev);
520
521 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
522 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
523 pci_set_word(dev->wmask + PCI_COMMAND,
524 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
525
526 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
527 config_size - PCI_CONFIG_HEADER_SIZE);
528 }
529
530 static void pci_init_wmask_bridge(PCIDevice *d)
531 {
532 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
533 PCI_SEC_LETENCY_TIMER */
534 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
535
536 /* base and limit */
537 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
538 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
539 pci_set_word(d->wmask + PCI_MEMORY_BASE,
540 PCI_MEMORY_RANGE_MASK & 0xffff);
541 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
542 PCI_MEMORY_RANGE_MASK & 0xffff);
543 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
544 PCI_PREF_RANGE_MASK & 0xffff);
545 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
546 PCI_PREF_RANGE_MASK & 0xffff);
547
548 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
549 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
550
551 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
552 }
553
554 static void pci_config_alloc(PCIDevice *pci_dev)
555 {
556 int config_size = pci_config_size(pci_dev);
557
558 pci_dev->config = qemu_mallocz(config_size);
559 pci_dev->cmask = qemu_mallocz(config_size);
560 pci_dev->wmask = qemu_mallocz(config_size);
561 pci_dev->used = qemu_mallocz(config_size);
562 }
563
564 static void pci_config_free(PCIDevice *pci_dev)
565 {
566 qemu_free(pci_dev->config);
567 qemu_free(pci_dev->cmask);
568 qemu_free(pci_dev->wmask);
569 qemu_free(pci_dev->used);
570 }
571
572 /* -1 for devfn means auto assign */
573 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
574 const char *name, int devfn,
575 PCIConfigReadFunc *config_read,
576 PCIConfigWriteFunc *config_write,
577 uint8_t header_type)
578 {
579 if (devfn < 0) {
580 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
581 devfn += 8) {
582 if (!bus->devices[devfn])
583 goto found;
584 }
585 qemu_error("PCI: no devfn available for %s, all in use\n", name);
586 return NULL;
587 found: ;
588 } else if (bus->devices[devfn]) {
589 qemu_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
590 name, bus->devices[devfn]->name);
591 return NULL;
592 }
593 pci_dev->bus = bus;
594 pci_dev->devfn = devfn;
595 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
596 pci_dev->irq_state = 0;
597 pci_config_alloc(pci_dev);
598
599 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
600 if (header_type == PCI_HEADER_TYPE_NORMAL) {
601 pci_set_default_subsystem_id(pci_dev);
602 }
603 pci_init_cmask(pci_dev);
604 pci_init_wmask(pci_dev);
605 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
606 pci_init_wmask_bridge(pci_dev);
607 }
608
609 if (!config_read)
610 config_read = pci_default_read_config;
611 if (!config_write)
612 config_write = pci_default_write_config;
613 pci_dev->config_read = config_read;
614 pci_dev->config_write = config_write;
615 bus->devices[devfn] = pci_dev;
616 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
617 pci_dev->version_id = 2; /* Current pci device vmstate version */
618 return pci_dev;
619 }
620
621 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
622 int instance_size, int devfn,
623 PCIConfigReadFunc *config_read,
624 PCIConfigWriteFunc *config_write)
625 {
626 PCIDevice *pci_dev;
627
628 pci_dev = qemu_mallocz(instance_size);
629 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
630 config_read, config_write,
631 PCI_HEADER_TYPE_NORMAL);
632 if (pci_dev == NULL) {
633 hw_error("PCI: can't register device\n");
634 }
635 return pci_dev;
636 }
637 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
638 {
639 return addr + pci_mem_base;
640 }
641
642 static void pci_unregister_io_regions(PCIDevice *pci_dev)
643 {
644 PCIIORegion *r;
645 int i;
646
647 for(i = 0; i < PCI_NUM_REGIONS; i++) {
648 r = &pci_dev->io_regions[i];
649 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
650 continue;
651 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
652 isa_unassign_ioport(r->addr, r->filtered_size);
653 } else {
654 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
655 r->filtered_size,
656 IO_MEM_UNASSIGNED);
657 }
658 }
659 }
660
661 static int pci_unregister_device(DeviceState *dev)
662 {
663 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
664 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
665 int ret = 0;
666
667 if (info->exit)
668 ret = info->exit(pci_dev);
669 if (ret)
670 return ret;
671
672 pci_unregister_io_regions(pci_dev);
673
674 qemu_free_irqs(pci_dev->irq);
675 pci_dev->bus->devices[pci_dev->devfn] = NULL;
676 pci_config_free(pci_dev);
677 return 0;
678 }
679
680 void pci_register_bar(PCIDevice *pci_dev, int region_num,
681 pcibus_t size, int type,
682 PCIMapIORegionFunc *map_func)
683 {
684 PCIIORegion *r;
685 uint32_t addr;
686 pcibus_t wmask;
687
688 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
689 return;
690
691 if (size & (size-1)) {
692 fprintf(stderr, "ERROR: PCI region size must be pow2 "
693 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
694 exit(1);
695 }
696
697 r = &pci_dev->io_regions[region_num];
698 r->addr = PCI_BAR_UNMAPPED;
699 r->size = size;
700 r->filtered_size = size;
701 r->type = type;
702 r->map_func = map_func;
703
704 wmask = ~(size - 1);
705 addr = pci_bar(pci_dev, region_num);
706 if (region_num == PCI_ROM_SLOT) {
707 /* ROM enable bit is writeable */
708 wmask |= PCI_ROM_ADDRESS_ENABLE;
709 }
710 pci_set_long(pci_dev->config + addr, type);
711 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
712 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
713 pci_set_quad(pci_dev->wmask + addr, wmask);
714 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
715 } else {
716 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
717 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
718 }
719 }
720
721 static uint32_t pci_config_get_io_base(PCIDevice *d,
722 uint32_t base, uint32_t base_upper16)
723 {
724 uint32_t val;
725
726 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
727 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
728 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
729 }
730 return val;
731 }
732
733 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
734 {
735 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
736 << 16;
737 }
738
739 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
740 uint32_t base, uint32_t upper)
741 {
742 pcibus_t tmp;
743 pcibus_t val;
744
745 tmp = (pcibus_t)pci_get_word(d->config + base);
746 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
747 if (tmp & PCI_PREF_RANGE_TYPE_64) {
748 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
749 }
750 return val;
751 }
752
753 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
754 {
755 pcibus_t base;
756 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
757 base = pci_config_get_io_base(bridge,
758 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
759 } else {
760 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
761 base = pci_config_get_pref_base(
762 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
763 } else {
764 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
765 }
766 }
767
768 return base;
769 }
770
771 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
772 {
773 pcibus_t limit;
774 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
775 limit = pci_config_get_io_base(bridge,
776 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
777 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
778 } else {
779 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
780 limit = pci_config_get_pref_base(
781 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
782 } else {
783 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
784 }
785 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
786 }
787 return limit;
788 }
789
790 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
791 uint8_t type)
792 {
793 pcibus_t base = *addr;
794 pcibus_t limit = *addr + *size - 1;
795 PCIDevice *br;
796
797 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
798 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
799
800 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
801 if (!(cmd & PCI_COMMAND_IO)) {
802 goto no_map;
803 }
804 } else {
805 if (!(cmd & PCI_COMMAND_MEMORY)) {
806 goto no_map;
807 }
808 }
809
810 base = MAX(base, pci_bridge_get_base(br, type));
811 limit = MIN(limit, pci_bridge_get_limit(br, type));
812 }
813
814 if (base > limit) {
815 goto no_map;
816 }
817 *addr = base;
818 *size = limit - base + 1;
819 return;
820 no_map:
821 *addr = PCI_BAR_UNMAPPED;
822 *size = 0;
823 }
824
825 static pcibus_t pci_bar_address(PCIDevice *d,
826 int reg, uint8_t type, pcibus_t size)
827 {
828 pcibus_t new_addr, last_addr;
829 int bar = pci_bar(d, reg);
830 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
831
832 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
833 if (!(cmd & PCI_COMMAND_IO)) {
834 return PCI_BAR_UNMAPPED;
835 }
836 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
837 last_addr = new_addr + size - 1;
838 /* NOTE: we have only 64K ioports on PC */
839 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
840 return PCI_BAR_UNMAPPED;
841 }
842 return new_addr;
843 }
844
845 if (!(cmd & PCI_COMMAND_MEMORY)) {
846 return PCI_BAR_UNMAPPED;
847 }
848 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
849 new_addr = pci_get_quad(d->config + bar);
850 } else {
851 new_addr = pci_get_long(d->config + bar);
852 }
853 /* the ROM slot has a specific enable bit */
854 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
855 return PCI_BAR_UNMAPPED;
856 }
857 new_addr &= ~(size - 1);
858 last_addr = new_addr + size - 1;
859 /* NOTE: we do not support wrapping */
860 /* XXX: as we cannot support really dynamic
861 mappings, we handle specific values as invalid
862 mappings. */
863 if (last_addr <= new_addr || new_addr == 0 ||
864 last_addr == PCI_BAR_UNMAPPED) {
865 return PCI_BAR_UNMAPPED;
866 }
867
868 /* Now pcibus_t is 64bit.
869 * Check if 32 bit BAR wraps around explicitly.
870 * Without this, PC ide doesn't work well.
871 * TODO: remove this work around.
872 */
873 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
874 return PCI_BAR_UNMAPPED;
875 }
876
877 /*
878 * OS is allowed to set BAR beyond its addressable
879 * bits. For example, 32 bit OS can set 64bit bar
880 * to >4G. Check it. TODO: we might need to support
881 * it in the future for e.g. PAE.
882 */
883 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
884 return PCI_BAR_UNMAPPED;
885 }
886
887 return new_addr;
888 }
889
890 static void pci_update_mappings(PCIDevice *d)
891 {
892 PCIIORegion *r;
893 int i;
894 pcibus_t new_addr, filtered_size;
895
896 for(i = 0; i < PCI_NUM_REGIONS; i++) {
897 r = &d->io_regions[i];
898
899 /* this region isn't registered */
900 if (!r->size)
901 continue;
902
903 new_addr = pci_bar_address(d, i, r->type, r->size);
904
905 /* bridge filtering */
906 filtered_size = r->size;
907 if (new_addr != PCI_BAR_UNMAPPED) {
908 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
909 }
910
911 /* This bar isn't changed */
912 if (new_addr == r->addr && filtered_size == r->filtered_size)
913 continue;
914
915 /* now do the real mapping */
916 if (r->addr != PCI_BAR_UNMAPPED) {
917 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
918 int class;
919 /* NOTE: specific hack for IDE in PC case:
920 only one byte must be mapped. */
921 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
922 if (class == 0x0101 && r->size == 4) {
923 isa_unassign_ioport(r->addr + 2, 1);
924 } else {
925 isa_unassign_ioport(r->addr, r->filtered_size);
926 }
927 } else {
928 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
929 r->filtered_size,
930 IO_MEM_UNASSIGNED);
931 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
932 }
933 }
934 r->addr = new_addr;
935 r->filtered_size = filtered_size;
936 if (r->addr != PCI_BAR_UNMAPPED) {
937 /*
938 * TODO: currently almost all the map funcions assumes
939 * filtered_size == size and addr & ~(size - 1) == addr.
940 * However with bridge filtering, they aren't always true.
941 * Teach them such cases, such that filtered_size < size and
942 * addr & (size - 1) != 0.
943 */
944 r->map_func(d, i, r->addr, r->filtered_size, r->type);
945 }
946 }
947 }
948
949 uint32_t pci_default_read_config(PCIDevice *d,
950 uint32_t address, int len)
951 {
952 uint32_t val = 0;
953 assert(len == 1 || len == 2 || len == 4);
954 len = MIN(len, pci_config_size(d) - address);
955 memcpy(&val, d->config + address, len);
956 return le32_to_cpu(val);
957 }
958
959 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
960 {
961 int i;
962 uint32_t config_size = pci_config_size(d);
963
964 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
965 uint8_t wmask = d->wmask[addr + i];
966 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
967 }
968 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
969 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
970 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
971 range_covers_byte(addr, l, PCI_COMMAND))
972 pci_update_mappings(d);
973 }
974
975 /***********************************************************/
976 /* generic PCI irq support */
977
978 /* 0 <= irq_num <= 3. level must be 0 or 1 */
979 static void pci_set_irq(void *opaque, int irq_num, int level)
980 {
981 PCIDevice *pci_dev = opaque;
982 int change;
983
984 change = level - pci_irq_state(pci_dev, irq_num);
985 if (!change)
986 return;
987
988 pci_set_irq_state(pci_dev, irq_num, level);
989 pci_update_irq_status(pci_dev);
990 pci_change_irq_level(pci_dev, irq_num, change);
991 }
992
993 /***********************************************************/
994 /* monitor info on PCI */
995
996 typedef struct {
997 uint16_t class;
998 const char *desc;
999 } pci_class_desc;
1000
1001 static const pci_class_desc pci_class_descriptions[] =
1002 {
1003 { 0x0100, "SCSI controller"},
1004 { 0x0101, "IDE controller"},
1005 { 0x0102, "Floppy controller"},
1006 { 0x0103, "IPI controller"},
1007 { 0x0104, "RAID controller"},
1008 { 0x0106, "SATA controller"},
1009 { 0x0107, "SAS controller"},
1010 { 0x0180, "Storage controller"},
1011 { 0x0200, "Ethernet controller"},
1012 { 0x0201, "Token Ring controller"},
1013 { 0x0202, "FDDI controller"},
1014 { 0x0203, "ATM controller"},
1015 { 0x0280, "Network controller"},
1016 { 0x0300, "VGA controller"},
1017 { 0x0301, "XGA controller"},
1018 { 0x0302, "3D controller"},
1019 { 0x0380, "Display controller"},
1020 { 0x0400, "Video controller"},
1021 { 0x0401, "Audio controller"},
1022 { 0x0402, "Phone"},
1023 { 0x0480, "Multimedia controller"},
1024 { 0x0500, "RAM controller"},
1025 { 0x0501, "Flash controller"},
1026 { 0x0580, "Memory controller"},
1027 { 0x0600, "Host bridge"},
1028 { 0x0601, "ISA bridge"},
1029 { 0x0602, "EISA bridge"},
1030 { 0x0603, "MC bridge"},
1031 { 0x0604, "PCI bridge"},
1032 { 0x0605, "PCMCIA bridge"},
1033 { 0x0606, "NUBUS bridge"},
1034 { 0x0607, "CARDBUS bridge"},
1035 { 0x0608, "RACEWAY bridge"},
1036 { 0x0680, "Bridge"},
1037 { 0x0c03, "USB controller"},
1038 { 0, NULL}
1039 };
1040
1041 static void pci_info_device(PCIBus *bus, PCIDevice *d)
1042 {
1043 Monitor *mon = cur_mon;
1044 int i, class;
1045 PCIIORegion *r;
1046 const pci_class_desc *desc;
1047
1048 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
1049 pci_bus_num(d->bus),
1050 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1051 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1052 monitor_printf(mon, " ");
1053 desc = pci_class_descriptions;
1054 while (desc->desc && class != desc->class)
1055 desc++;
1056 if (desc->desc) {
1057 monitor_printf(mon, "%s", desc->desc);
1058 } else {
1059 monitor_printf(mon, "Class %04x", class);
1060 }
1061 monitor_printf(mon, ": PCI device %04x:%04x\n",
1062 pci_get_word(d->config + PCI_VENDOR_ID),
1063 pci_get_word(d->config + PCI_DEVICE_ID));
1064
1065 if (d->config[PCI_INTERRUPT_PIN] != 0) {
1066 monitor_printf(mon, " IRQ %d.\n",
1067 d->config[PCI_INTERRUPT_LINE]);
1068 }
1069 if (class == 0x0604) {
1070 uint64_t base;
1071 uint64_t limit;
1072
1073 monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
1074 monitor_printf(mon, " secondary bus %d.\n",
1075 d->config[PCI_SECONDARY_BUS]);
1076 monitor_printf(mon, " subordinate bus %d.\n",
1077 d->config[PCI_SUBORDINATE_BUS]);
1078
1079 base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
1080 limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
1081 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1082 base, limit);
1083
1084 base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
1085 limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
1086 monitor_printf(mon,
1087 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1088 base, limit);
1089
1090 base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1091 PCI_BASE_ADDRESS_MEM_PREFETCH);
1092 limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1093 PCI_BASE_ADDRESS_MEM_PREFETCH);
1094 monitor_printf(mon, " prefetchable memory range "
1095 "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
1096 }
1097 for(i = 0;i < PCI_NUM_REGIONS; i++) {
1098 r = &d->io_regions[i];
1099 if (r->size != 0) {
1100 monitor_printf(mon, " BAR%d: ", i);
1101 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1102 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1103 " [0x%04"FMT_PCIBUS"].\n",
1104 r->addr, r->addr + r->size - 1);
1105 } else {
1106 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
1107 "64 bit" : "32 bit";
1108 const char *prefetch =
1109 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
1110 " prefetchable" : "";
1111
1112 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1113 " [0x%08"FMT_PCIBUS"].\n",
1114 type, prefetch,
1115 r->addr, r->addr + r->size - 1);
1116 }
1117 }
1118 }
1119 monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
1120 if (class == 0x0604 && d->config[0x19] != 0) {
1121 pci_for_each_device(bus, d->config[0x19], pci_info_device);
1122 }
1123 }
1124
1125 static void pci_for_each_device_under_bus(PCIBus *bus,
1126 void (*fn)(PCIBus *b, PCIDevice *d))
1127 {
1128 PCIDevice *d;
1129 int devfn;
1130
1131 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1132 d = bus->devices[devfn];
1133 if (d)
1134 fn(bus, d);
1135 }
1136 }
1137
1138 void pci_for_each_device(PCIBus *bus, int bus_num,
1139 void (*fn)(PCIBus *b, PCIDevice *d))
1140 {
1141 bus = pci_find_bus(bus, bus_num);
1142
1143 if (bus) {
1144 pci_for_each_device_under_bus(bus, fn);
1145 }
1146 }
1147
1148 void pci_info(Monitor *mon)
1149 {
1150 struct PCIHostBus *host;
1151 QLIST_FOREACH(host, &host_buses, next) {
1152 pci_for_each_device(host->bus, 0, pci_info_device);
1153 }
1154 }
1155
1156 static const char * const pci_nic_models[] = {
1157 "ne2k_pci",
1158 "i82551",
1159 "i82557b",
1160 "i82559er",
1161 "rtl8139",
1162 "e1000",
1163 "pcnet",
1164 "virtio",
1165 NULL
1166 };
1167
1168 static const char * const pci_nic_names[] = {
1169 "ne2k_pci",
1170 "i82551",
1171 "i82557b",
1172 "i82559er",
1173 "rtl8139",
1174 "e1000",
1175 "pcnet",
1176 "virtio-net-pci",
1177 NULL
1178 };
1179
1180 /* Initialize a PCI NIC. */
1181 /* FIXME callers should check for failure, but don't */
1182 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1183 const char *default_devaddr)
1184 {
1185 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1186 PCIBus *bus;
1187 int devfn;
1188 PCIDevice *pci_dev;
1189 DeviceState *dev;
1190 int i;
1191
1192 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1193 if (i < 0)
1194 return NULL;
1195
1196 bus = pci_get_bus_devfn(&devfn, devaddr);
1197 if (!bus) {
1198 qemu_error("Invalid PCI device address %s for device %s\n",
1199 devaddr, pci_nic_names[i]);
1200 return NULL;
1201 }
1202
1203 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1204 dev = &pci_dev->qdev;
1205 if (nd->name)
1206 dev->id = qemu_strdup(nd->name);
1207 qdev_set_nic_properties(dev, nd);
1208 if (qdev_init(dev) < 0)
1209 return NULL;
1210 return pci_dev;
1211 }
1212
1213 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1214 const char *default_devaddr)
1215 {
1216 PCIDevice *res;
1217
1218 if (qemu_show_nic_models(nd->model, pci_nic_models))
1219 exit(0);
1220
1221 res = pci_nic_init(nd, default_model, default_devaddr);
1222 if (!res)
1223 exit(1);
1224 return res;
1225 }
1226
1227 typedef struct {
1228 PCIDevice dev;
1229 PCIBus bus;
1230 uint32_t vid;
1231 uint32_t did;
1232 } PCIBridge;
1233
1234
1235 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1236 {
1237 pci_update_mappings(d);
1238 }
1239
1240 static void pci_bridge_update_mappings(PCIBus *b)
1241 {
1242 PCIBus *child;
1243
1244 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1245
1246 QLIST_FOREACH(child, &b->child, sibling) {
1247 pci_bridge_update_mappings(child);
1248 }
1249 }
1250
1251 static void pci_bridge_write_config(PCIDevice *d,
1252 uint32_t address, uint32_t val, int len)
1253 {
1254 pci_default_write_config(d, address, val, len);
1255
1256 if (/* io base/limit */
1257 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1258
1259 /* memory base/limit, prefetchable base/limit and
1260 io base/limit upper 16 */
1261 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1262 pci_bridge_update_mappings(d->bus);
1263 }
1264 }
1265
1266 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1267 {
1268 PCIBus *sec;
1269
1270 if (!bus)
1271 return NULL;
1272
1273 if (pci_bus_num(bus) == bus_num) {
1274 return bus;
1275 }
1276
1277 /* try child bus */
1278 QLIST_FOREACH(sec, &bus->child, sibling) {
1279
1280 if (!bus->parent_dev /* pci host bridge */
1281 || (pci_bus_num(sec) <= bus_num &&
1282 bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1283 return pci_find_bus(sec, bus_num);
1284 }
1285 }
1286
1287 return NULL;
1288 }
1289
1290 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1291 {
1292 bus = pci_find_bus(bus, bus_num);
1293
1294 if (!bus)
1295 return NULL;
1296
1297 return bus->devices[PCI_DEVFN(slot, function)];
1298 }
1299
1300 static int pci_bridge_initfn(PCIDevice *dev)
1301 {
1302 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1303
1304 pci_config_set_vendor_id(s->dev.config, s->vid);
1305 pci_config_set_device_id(s->dev.config, s->did);
1306
1307 pci_set_word(dev->config + PCI_STATUS,
1308 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1309 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1310 dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1311 pci_set_word(dev->config + PCI_SEC_STATUS,
1312 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1313 return 0;
1314 }
1315
1316 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1317 {
1318 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1319 PCIBus *bus = &s->bus;
1320 pci_unregister_secondary_bus(bus);
1321 return 0;
1322 }
1323
1324 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1325 pci_map_irq_fn map_irq, const char *name)
1326 {
1327 PCIDevice *dev;
1328 PCIBridge *s;
1329
1330 dev = pci_create(bus, devfn, "pci-bridge");
1331 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1332 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1333 qdev_init_nofail(&dev->qdev);
1334
1335 s = DO_UPCAST(PCIBridge, dev, dev);
1336 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1337 return &s->bus;
1338 }
1339
1340 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1341 {
1342 return bus->parent_dev;
1343 }
1344
1345 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1346 {
1347 PCIDevice *pci_dev = (PCIDevice *)qdev;
1348 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1349 PCIBus *bus;
1350 int devfn, rc;
1351
1352 /* initialize cap_present for pci_is_express() and pci_config_size() */
1353 if (info->is_express) {
1354 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1355 }
1356
1357 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1358 devfn = pci_dev->devfn;
1359 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1360 info->config_read, info->config_write,
1361 info->header_type);
1362 if (pci_dev == NULL)
1363 return -1;
1364 rc = info->init(pci_dev);
1365 if (rc != 0)
1366 return rc;
1367
1368 /* rom loading */
1369 if (pci_dev->romfile == NULL && info->romfile != NULL)
1370 pci_dev->romfile = qemu_strdup(info->romfile);
1371 pci_add_option_rom(pci_dev);
1372
1373 if (qdev->hotplugged)
1374 bus->hotplug(pci_dev, 1);
1375 return 0;
1376 }
1377
1378 static int pci_unplug_device(DeviceState *qdev)
1379 {
1380 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1381
1382 dev->bus->hotplug(dev, 0);
1383 return 0;
1384 }
1385
1386 void pci_qdev_register(PCIDeviceInfo *info)
1387 {
1388 info->qdev.init = pci_qdev_init;
1389 info->qdev.unplug = pci_unplug_device;
1390 info->qdev.exit = pci_unregister_device;
1391 info->qdev.bus_info = &pci_bus_info;
1392 qdev_register(&info->qdev);
1393 }
1394
1395 void pci_qdev_register_many(PCIDeviceInfo *info)
1396 {
1397 while (info->qdev.name) {
1398 pci_qdev_register(info);
1399 info++;
1400 }
1401 }
1402
1403 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1404 {
1405 DeviceState *dev;
1406
1407 dev = qdev_create(&bus->qbus, name);
1408 qdev_prop_set_uint32(dev, "addr", devfn);
1409 return DO_UPCAST(PCIDevice, qdev, dev);
1410 }
1411
1412 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1413 {
1414 PCIDevice *dev = pci_create(bus, devfn, name);
1415 qdev_init_nofail(&dev->qdev);
1416 return dev;
1417 }
1418
1419 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1420 {
1421 int config_size = pci_config_size(pdev);
1422 int offset = PCI_CONFIG_HEADER_SIZE;
1423 int i;
1424 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1425 if (pdev->used[i])
1426 offset = i + 1;
1427 else if (i - offset + 1 == size)
1428 return offset;
1429 return 0;
1430 }
1431
1432 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1433 uint8_t *prev_p)
1434 {
1435 uint8_t next, prev;
1436
1437 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1438 return 0;
1439
1440 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1441 prev = next + PCI_CAP_LIST_NEXT)
1442 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1443 break;
1444
1445 if (prev_p)
1446 *prev_p = prev;
1447 return next;
1448 }
1449
1450 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1451 {
1452 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1453 }
1454
1455 /* Add an option rom for the device */
1456 static int pci_add_option_rom(PCIDevice *pdev)
1457 {
1458 int size;
1459 char *path;
1460 void *ptr;
1461
1462 if (!pdev->romfile)
1463 return 0;
1464 if (strlen(pdev->romfile) == 0)
1465 return 0;
1466
1467 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1468 if (path == NULL) {
1469 path = qemu_strdup(pdev->romfile);
1470 }
1471
1472 size = get_image_size(path);
1473 if (size < 0) {
1474 qemu_error("%s: failed to find romfile \"%s\"\n", __FUNCTION__,
1475 pdev->romfile);
1476 return -1;
1477 }
1478 if (size & (size - 1)) {
1479 size = 1 << qemu_fls(size);
1480 }
1481
1482 pdev->rom_offset = qemu_ram_alloc(size);
1483
1484 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1485 load_image(path, ptr);
1486 qemu_free(path);
1487
1488 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1489 0, pci_map_option_rom);
1490
1491 return 0;
1492 }
1493
1494 /* Reserve space and add capability to the linked list in pci config space */
1495 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1496 {
1497 uint8_t offset = pci_find_space(pdev, size);
1498 uint8_t *config = pdev->config + offset;
1499 if (!offset)
1500 return -ENOSPC;
1501 config[PCI_CAP_LIST_ID] = cap_id;
1502 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1503 pdev->config[PCI_CAPABILITY_LIST] = offset;
1504 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1505 memset(pdev->used + offset, 0xFF, size);
1506 /* Make capability read-only by default */
1507 memset(pdev->wmask + offset, 0, size);
1508 /* Check capability by default */
1509 memset(pdev->cmask + offset, 0xFF, size);
1510 return offset;
1511 }
1512
1513 /* Unlink capability from the pci config space. */
1514 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1515 {
1516 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1517 if (!offset)
1518 return;
1519 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1520 /* Make capability writeable again */
1521 memset(pdev->wmask + offset, 0xff, size);
1522 /* Clear cmask as device-specific registers can't be checked */
1523 memset(pdev->cmask + offset, 0, size);
1524 memset(pdev->used + offset, 0, size);
1525
1526 if (!pdev->config[PCI_CAPABILITY_LIST])
1527 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1528 }
1529
1530 /* Reserve space for capability at a known offset (to call after load). */
1531 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1532 {
1533 memset(pdev->used + offset, 0xff, size);
1534 }
1535
1536 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1537 {
1538 return pci_find_capability_list(pdev, cap_id, NULL);
1539 }
1540
1541 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1542 {
1543 PCIDevice *d = (PCIDevice *)dev;
1544 const pci_class_desc *desc;
1545 char ctxt[64];
1546 PCIIORegion *r;
1547 int i, class;
1548
1549 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1550 desc = pci_class_descriptions;
1551 while (desc->desc && class != desc->class)
1552 desc++;
1553 if (desc->desc) {
1554 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1555 } else {
1556 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1557 }
1558
1559 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1560 "pci id %04x:%04x (sub %04x:%04x)\n",
1561 indent, "", ctxt,
1562 d->config[PCI_SECONDARY_BUS],
1563 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1564 pci_get_word(d->config + PCI_VENDOR_ID),
1565 pci_get_word(d->config + PCI_DEVICE_ID),
1566 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1567 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1568 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1569 r = &d->io_regions[i];
1570 if (!r->size)
1571 continue;
1572 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1573 " [0x%"FMT_PCIBUS"]\n",
1574 indent, "",
1575 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1576 r->addr, r->addr + r->size - 1);
1577 }
1578 }
1579
1580 static PCIDeviceInfo bridge_info = {
1581 .qdev.name = "pci-bridge",
1582 .qdev.size = sizeof(PCIBridge),
1583 .init = pci_bridge_initfn,
1584 .exit = pci_bridge_exitfn,
1585 .config_write = pci_bridge_write_config,
1586 .qdev.props = (Property[]) {
1587 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1588 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1589 DEFINE_PROP_END_OF_LIST(),
1590 }
1591 };
1592
1593 static void pci_register_devices(void)
1594 {
1595 pci_qdev_register(&bridge_info);
1596 }
1597
1598 device_init(pci_register_devices)
AR7 emulation for QEMU