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memory: update coalesced_range on transaction_commit
[qemu/ar7.git] / memory.c
blob5759f74034b28332b19917a05d0e022ed90d45be
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qom/object.h"
26 #include "trace-root.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/qdev-properties.h"
33 #include "migration/vmstate.h"
34
35 //#define DEBUG_UNASSIGNED
36
37 static unsigned memory_region_transaction_depth;
38 static bool memory_region_update_pending;
39 static bool ioeventfd_update_pending;
40 static bool global_dirty_log = false;
41
42 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
43 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
44
45 static QTAILQ_HEAD(, AddressSpace) address_spaces
46 = QTAILQ_HEAD_INITIALIZER(address_spaces);
47
48 static GHashTable *flat_views;
49
50 typedef struct AddrRange AddrRange;
51
52 /*
53 * Note that signed integers are needed for negative offsetting in aliases
54 * (large MemoryRegion::alias_offset).
55 */
56 struct AddrRange {
57 Int128 start;
58 Int128 size;
59 };
60
61 static AddrRange addrrange_make(Int128 start, Int128 size)
62 {
63 return (AddrRange) { start, size };
64 }
65
66 static bool addrrange_equal(AddrRange r1, AddrRange r2)
67 {
68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
69 }
70
71 static Int128 addrrange_end(AddrRange r)
72 {
73 return int128_add(r.start, r.size);
74 }
75
76 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
77 {
78 int128_addto(&range.start, delta);
79 return range;
80 }
81
82 static bool addrrange_contains(AddrRange range, Int128 addr)
83 {
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86 }
87
88 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89 {
90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
92 }
93
94 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95 {
96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
99 }
100
101 enum ListenerDirection { Forward, Reverse };
102
103 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
128 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
129 do { \
130 MemoryListener *_listener; \
131 struct memory_listeners_as *list = &(_as)->listeners; \
132 \
133 switch (_direction) { \
134 case Forward: \
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
154 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
155 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
160 } while(0)
161
162 struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165 };
166
167 struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
171 EventNotifier *e;
172 };
173
174 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
176 {
177 if (int128_lt(a->addr.start, b->addr.start)) {
178 return true;
179 } else if (int128_gt(a->addr.start, b->addr.start)) {
180 return false;
181 } else if (int128_lt(a->addr.size, b->addr.size)) {
182 return true;
183 } else if (int128_gt(a->addr.size, b->addr.size)) {
184 return false;
185 } else if (a->match_data < b->match_data) {
186 return true;
187 } else if (a->match_data > b->match_data) {
188 return false;
189 } else if (a->match_data) {
190 if (a->data < b->data) {
191 return true;
192 } else if (a->data > b->data) {
193 return false;
194 }
195 }
196 if (a->e < b->e) {
197 return true;
198 } else if (a->e > b->e) {
199 return false;
200 }
201 return false;
202 }
203
204 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
206 {
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209 }
210
211 /* Range of memory in the global map. Addresses are absolute. */
212 struct FlatRange {
213 MemoryRegion *mr;
214 hwaddr offset_in_region;
215 AddrRange addr;
216 uint8_t dirty_log_mask;
217 bool romd_mode;
218 bool readonly;
219 bool nonvolatile;
220 int has_coalesced_range;
221 };
222
223 #define FOR_EACH_FLAT_RANGE(var, view) \
224 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
225
226 static inline MemoryRegionSection
227 section_from_flat_range(FlatRange *fr, FlatView *fv)
228 {
229 return (MemoryRegionSection) {
230 .mr = fr->mr,
231 .fv = fv,
232 .offset_within_region = fr->offset_in_region,
233 .size = fr->addr.size,
234 .offset_within_address_space = int128_get64(fr->addr.start),
235 .readonly = fr->readonly,
236 .nonvolatile = fr->nonvolatile,
237 };
238 }
239
240 static bool flatrange_equal(FlatRange *a, FlatRange *b)
241 {
242 return a->mr == b->mr
243 && addrrange_equal(a->addr, b->addr)
244 && a->offset_in_region == b->offset_in_region
245 && a->romd_mode == b->romd_mode
246 && a->readonly == b->readonly
247 && a->nonvolatile == b->nonvolatile;
248 }
249
250 static FlatView *flatview_new(MemoryRegion *mr_root)
251 {
252 FlatView *view;
253
254 view = g_new0(FlatView, 1);
255 view->ref = 1;
256 view->root = mr_root;
257 memory_region_ref(mr_root);
258 trace_flatview_new(view, mr_root);
259
260 return view;
261 }
262
263 /* Insert a range into a given position. Caller is responsible for maintaining
264 * sorting order.
265 */
266 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
267 {
268 if (view->nr == view->nr_allocated) {
269 view->nr_allocated = MAX(2 * view->nr, 10);
270 view->ranges = g_realloc(view->ranges,
271 view->nr_allocated * sizeof(*view->ranges));
272 }
273 memmove(view->ranges + pos + 1, view->ranges + pos,
274 (view->nr - pos) * sizeof(FlatRange));
275 view->ranges[pos] = *range;
276 memory_region_ref(range->mr);
277 ++view->nr;
278 }
279
280 static void flatview_destroy(FlatView *view)
281 {
282 int i;
283
284 trace_flatview_destroy(view, view->root);
285 if (view->dispatch) {
286 address_space_dispatch_free(view->dispatch);
287 }
288 for (i = 0; i < view->nr; i++) {
289 memory_region_unref(view->ranges[i].mr);
290 }
291 g_free(view->ranges);
292 memory_region_unref(view->root);
293 g_free(view);
294 }
295
296 static bool flatview_ref(FlatView *view)
297 {
298 return atomic_fetch_inc_nonzero(&view->ref) > 0;
299 }
300
301 void flatview_unref(FlatView *view)
302 {
303 if (atomic_fetch_dec(&view->ref) == 1) {
304 trace_flatview_destroy_rcu(view, view->root);
305 assert(view->root);
306 call_rcu(view, flatview_destroy, rcu);
307 }
308 }
309
310 static bool can_merge(FlatRange *r1, FlatRange *r2)
311 {
312 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
313 && r1->mr == r2->mr
314 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
315 r1->addr.size),
316 int128_make64(r2->offset_in_region))
317 && r1->dirty_log_mask == r2->dirty_log_mask
318 && r1->romd_mode == r2->romd_mode
319 && r1->readonly == r2->readonly
320 && r1->nonvolatile == r2->nonvolatile;
321 }
322
323 /* Attempt to simplify a view by merging adjacent ranges */
324 static void flatview_simplify(FlatView *view)
325 {
326 unsigned i, j;
327
328 i = 0;
329 while (i < view->nr) {
330 j = i + 1;
331 while (j < view->nr
332 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
333 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
334 ++j;
335 }
336 ++i;
337 memmove(&view->ranges[i], &view->ranges[j],
338 (view->nr - j) * sizeof(view->ranges[j]));
339 view->nr -= j - i;
340 }
341 }
342
343 static bool memory_region_big_endian(MemoryRegion *mr)
344 {
345 #ifdef TARGET_WORDS_BIGENDIAN
346 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
347 #else
348 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
349 #endif
350 }
351
352 static bool memory_region_wrong_endianness(MemoryRegion *mr)
353 {
354 #ifdef TARGET_WORDS_BIGENDIAN
355 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
356 #else
357 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
358 #endif
359 }
360
361 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
362 {
363 if (memory_region_wrong_endianness(mr)) {
364 switch (size) {
365 case 1:
366 break;
367 case 2:
368 *data = bswap16(*data);
369 break;
370 case 4:
371 *data = bswap32(*data);
372 break;
373 case 8:
374 *data = bswap64(*data);
375 break;
376 default:
377 abort();
378 }
379 }
380 }
381
382 static inline void memory_region_shift_read_access(uint64_t *value,
383 signed shift,
384 uint64_t mask,
385 uint64_t tmp)
386 {
387 if (shift >= 0) {
388 *value |= (tmp & mask) << shift;
389 } else {
390 *value |= (tmp & mask) >> -shift;
391 }
392 }
393
394 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
395 signed shift,
396 uint64_t mask)
397 {
398 uint64_t tmp;
399
400 if (shift >= 0) {
401 tmp = (*value >> shift) & mask;
402 } else {
403 tmp = (*value << -shift) & mask;
404 }
405
406 return tmp;
407 }
408
409 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
410 {
411 MemoryRegion *root;
412 hwaddr abs_addr = offset;
413
414 abs_addr += mr->addr;
415 for (root = mr; root->container; ) {
416 root = root->container;
417 abs_addr += root->addr;
418 }
419
420 return abs_addr;
421 }
422
423 static int get_cpu_index(void)
424 {
425 if (current_cpu) {
426 return current_cpu->cpu_index;
427 }
428 return -1;
429 }
430
431 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
432 hwaddr addr,
433 uint64_t *value,
434 unsigned size,
435 signed shift,
436 uint64_t mask,
437 MemTxAttrs attrs)
438 {
439 uint64_t tmp;
440
441 tmp = mr->ops->read(mr->opaque, addr, size);
442 if (mr->subpage) {
443 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
444 } else if (mr == &io_mem_notdirty) {
445 /* Accesses to code which has previously been translated into a TB show
446 * up in the MMIO path, as accesses to the io_mem_notdirty
447 * MemoryRegion. */
448 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
449 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
450 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
451 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
452 }
453 memory_region_shift_read_access(value, shift, mask, tmp);
454 return MEMTX_OK;
455 }
456
457 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
458 hwaddr addr,
459 uint64_t *value,
460 unsigned size,
461 signed shift,
462 uint64_t mask,
463 MemTxAttrs attrs)
464 {
465 uint64_t tmp = 0;
466 MemTxResult r;
467
468 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
469 if (mr->subpage) {
470 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
471 } else if (mr == &io_mem_notdirty) {
472 /* Accesses to code which has previously been translated into a TB show
473 * up in the MMIO path, as accesses to the io_mem_notdirty
474 * MemoryRegion. */
475 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
476 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
477 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
478 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
479 }
480 memory_region_shift_read_access(value, shift, mask, tmp);
481 return r;
482 }
483
484 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
485 hwaddr addr,
486 uint64_t *value,
487 unsigned size,
488 signed shift,
489 uint64_t mask,
490 MemTxAttrs attrs)
491 {
492 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
493
494 if (mr->subpage) {
495 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
496 } else if (mr == &io_mem_notdirty) {
497 /* Accesses to code which has previously been translated into a TB show
498 * up in the MMIO path, as accesses to the io_mem_notdirty
499 * MemoryRegion. */
500 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
501 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
502 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
503 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
504 }
505 mr->ops->write(mr->opaque, addr, tmp, size);
506 return MEMTX_OK;
507 }
508
509 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
510 hwaddr addr,
511 uint64_t *value,
512 unsigned size,
513 signed shift,
514 uint64_t mask,
515 MemTxAttrs attrs)
516 {
517 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
518
519 if (mr->subpage) {
520 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
521 } else if (mr == &io_mem_notdirty) {
522 /* Accesses to code which has previously been translated into a TB show
523 * up in the MMIO path, as accesses to the io_mem_notdirty
524 * MemoryRegion. */
525 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
526 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
527 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
528 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
529 }
530 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
531 }
532
533 static MemTxResult access_with_adjusted_size(hwaddr addr,
534 uint64_t *value,
535 unsigned size,
536 unsigned access_size_min,
537 unsigned access_size_max,
538 MemTxResult (*access_fn)
539 (MemoryRegion *mr,
540 hwaddr addr,
541 uint64_t *value,
542 unsigned size,
543 signed shift,
544 uint64_t mask,
545 MemTxAttrs attrs),
546 MemoryRegion *mr,
547 MemTxAttrs attrs)
548 {
549 uint64_t access_mask;
550 unsigned access_size;
551 unsigned i;
552 MemTxResult r = MEMTX_OK;
553
554 if (!access_size_min) {
555 access_size_min = 1;
556 }
557 if (!access_size_max) {
558 access_size_max = 4;
559 }
560
561 /* FIXME: support unaligned access? */
562 access_size = MAX(MIN(size, access_size_max), access_size_min);
563 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
564 if (memory_region_big_endian(mr)) {
565 for (i = 0; i < size; i += access_size) {
566 r |= access_fn(mr, addr + i, value, access_size,
567 (size - access_size - i) * 8, access_mask, attrs);
568 }
569 } else {
570 for (i = 0; i < size; i += access_size) {
571 r |= access_fn(mr, addr + i, value, access_size, i * 8,
572 access_mask, attrs);
573 }
574 }
575 return r;
576 }
577
578 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
579 {
580 AddressSpace *as;
581
582 while (mr->container) {
583 mr = mr->container;
584 }
585 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
586 if (mr == as->root) {
587 return as;
588 }
589 }
590 return NULL;
591 }
592
593 /* Render a memory region into the global view. Ranges in @view obscure
594 * ranges in @mr.
595 */
596 static void render_memory_region(FlatView *view,
597 MemoryRegion *mr,
598 Int128 base,
599 AddrRange clip,
600 bool readonly,
601 bool nonvolatile)
602 {
603 MemoryRegion *subregion;
604 unsigned i;
605 hwaddr offset_in_region;
606 Int128 remain;
607 Int128 now;
608 FlatRange fr;
609 AddrRange tmp;
610
611 if (!mr->enabled) {
612 return;
613 }
614
615 int128_addto(&base, int128_make64(mr->addr));
616 readonly |= mr->readonly;
617 nonvolatile |= mr->nonvolatile;
618
619 tmp = addrrange_make(base, mr->size);
620
621 if (!addrrange_intersects(tmp, clip)) {
622 return;
623 }
624
625 clip = addrrange_intersection(tmp, clip);
626
627 if (mr->alias) {
628 int128_subfrom(&base, int128_make64(mr->alias->addr));
629 int128_subfrom(&base, int128_make64(mr->alias_offset));
630 render_memory_region(view, mr->alias, base, clip,
631 readonly, nonvolatile);
632 return;
633 }
634
635 /* Render subregions in priority order. */
636 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
637 render_memory_region(view, subregion, base, clip,
638 readonly, nonvolatile);
639 }
640
641 if (!mr->terminates) {
642 return;
643 }
644
645 offset_in_region = int128_get64(int128_sub(clip.start, base));
646 base = clip.start;
647 remain = clip.size;
648
649 fr.mr = mr;
650 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
651 fr.romd_mode = mr->romd_mode;
652 fr.readonly = readonly;
653 fr.nonvolatile = nonvolatile;
654 fr.has_coalesced_range = 0;
655
656 /* Render the region itself into any gaps left by the current view. */
657 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
658 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
659 continue;
660 }
661 if (int128_lt(base, view->ranges[i].addr.start)) {
662 now = int128_min(remain,
663 int128_sub(view->ranges[i].addr.start, base));
664 fr.offset_in_region = offset_in_region;
665 fr.addr = addrrange_make(base, now);
666 flatview_insert(view, i, &fr);
667 ++i;
668 int128_addto(&base, now);
669 offset_in_region += int128_get64(now);
670 int128_subfrom(&remain, now);
671 }
672 now = int128_sub(int128_min(int128_add(base, remain),
673 addrrange_end(view->ranges[i].addr)),
674 base);
675 int128_addto(&base, now);
676 offset_in_region += int128_get64(now);
677 int128_subfrom(&remain, now);
678 }
679 if (int128_nz(remain)) {
680 fr.offset_in_region = offset_in_region;
681 fr.addr = addrrange_make(base, remain);
682 flatview_insert(view, i, &fr);
683 }
684 }
685
686 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
687 {
688 while (mr->enabled) {
689 if (mr->alias) {
690 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
691 /* The alias is included in its entirety. Use it as
692 * the "real" root, so that we can share more FlatViews.
693 */
694 mr = mr->alias;
695 continue;
696 }
697 } else if (!mr->terminates) {
698 unsigned int found = 0;
699 MemoryRegion *child, *next = NULL;
700 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
701 if (child->enabled) {
702 if (++found > 1) {
703 next = NULL;
704 break;
705 }
706 if (!child->addr && int128_ge(mr->size, child->size)) {
707 /* A child is included in its entirety. If it's the only
708 * enabled one, use it in the hope of finding an alias down the
709 * way. This will also let us share FlatViews.
710 */
711 next = child;
712 }
713 }
714 }
715 if (found == 0) {
716 return NULL;
717 }
718 if (next) {
719 mr = next;
720 continue;
721 }
722 }
723
724 return mr;
725 }
726
727 return NULL;
728 }
729
730 /* Render a memory topology into a list of disjoint absolute ranges. */
731 static FlatView *generate_memory_topology(MemoryRegion *mr)
732 {
733 int i;
734 FlatView *view;
735
736 view = flatview_new(mr);
737
738 if (mr) {
739 render_memory_region(view, mr, int128_zero(),
740 addrrange_make(int128_zero(), int128_2_64()),
741 false, false);
742 }
743 flatview_simplify(view);
744
745 view->dispatch = address_space_dispatch_new(view);
746 for (i = 0; i < view->nr; i++) {
747 MemoryRegionSection mrs =
748 section_from_flat_range(&view->ranges[i], view);
749 flatview_add_to_dispatch(view, &mrs);
750 }
751 address_space_dispatch_compact(view->dispatch);
752 g_hash_table_replace(flat_views, mr, view);
753
754 return view;
755 }
756
757 static void address_space_add_del_ioeventfds(AddressSpace *as,
758 MemoryRegionIoeventfd *fds_new,
759 unsigned fds_new_nb,
760 MemoryRegionIoeventfd *fds_old,
761 unsigned fds_old_nb)
762 {
763 unsigned iold, inew;
764 MemoryRegionIoeventfd *fd;
765 MemoryRegionSection section;
766
767 /* Generate a symmetric difference of the old and new fd sets, adding
768 * and deleting as necessary.
769 */
770
771 iold = inew = 0;
772 while (iold < fds_old_nb || inew < fds_new_nb) {
773 if (iold < fds_old_nb
774 && (inew == fds_new_nb
775 || memory_region_ioeventfd_before(&fds_old[iold],
776 &fds_new[inew]))) {
777 fd = &fds_old[iold];
778 section = (MemoryRegionSection) {
779 .fv = address_space_to_flatview(as),
780 .offset_within_address_space = int128_get64(fd->addr.start),
781 .size = fd->addr.size,
782 };
783 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
784 fd->match_data, fd->data, fd->e);
785 ++iold;
786 } else if (inew < fds_new_nb
787 && (iold == fds_old_nb
788 || memory_region_ioeventfd_before(&fds_new[inew],
789 &fds_old[iold]))) {
790 fd = &fds_new[inew];
791 section = (MemoryRegionSection) {
792 .fv = address_space_to_flatview(as),
793 .offset_within_address_space = int128_get64(fd->addr.start),
794 .size = fd->addr.size,
795 };
796 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
797 fd->match_data, fd->data, fd->e);
798 ++inew;
799 } else {
800 ++iold;
801 ++inew;
802 }
803 }
804 }
805
806 FlatView *address_space_get_flatview(AddressSpace *as)
807 {
808 FlatView *view;
809
810 rcu_read_lock();
811 do {
812 view = address_space_to_flatview(as);
813 /* If somebody has replaced as->current_map concurrently,
814 * flatview_ref returns false.
815 */
816 } while (!flatview_ref(view));
817 rcu_read_unlock();
818 return view;
819 }
820
821 static void address_space_update_ioeventfds(AddressSpace *as)
822 {
823 FlatView *view;
824 FlatRange *fr;
825 unsigned ioeventfd_nb = 0;
826 MemoryRegionIoeventfd *ioeventfds = NULL;
827 AddrRange tmp;
828 unsigned i;
829
830 view = address_space_get_flatview(as);
831 FOR_EACH_FLAT_RANGE(fr, view) {
832 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
833 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
834 int128_sub(fr->addr.start,
835 int128_make64(fr->offset_in_region)));
836 if (addrrange_intersects(fr->addr, tmp)) {
837 ++ioeventfd_nb;
838 ioeventfds = g_realloc(ioeventfds,
839 ioeventfd_nb * sizeof(*ioeventfds));
840 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
841 ioeventfds[ioeventfd_nb-1].addr = tmp;
842 }
843 }
844 }
845
846 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
847 as->ioeventfds, as->ioeventfd_nb);
848
849 g_free(as->ioeventfds);
850 as->ioeventfds = ioeventfds;
851 as->ioeventfd_nb = ioeventfd_nb;
852 flatview_unref(view);
853 }
854
855 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
856 {
857 if (!fr->has_coalesced_range) {
858 return;
859 }
860
861 if (--fr->has_coalesced_range > 0) {
862 return;
863 }
864
865 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
866 int128_get64(fr->addr.start),
867 int128_get64(fr->addr.size));
868 }
869
870 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
871 {
872 MemoryRegion *mr = fr->mr;
873 CoalescedMemoryRange *cmr;
874 AddrRange tmp;
875
876 if (QTAILQ_EMPTY(&mr->coalesced)) {
877 return;
878 }
879
880 if (fr->has_coalesced_range++) {
881 return;
882 }
883
884 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
885 tmp = addrrange_shift(cmr->addr,
886 int128_sub(fr->addr.start,
887 int128_make64(fr->offset_in_region)));
888 if (!addrrange_intersects(tmp, fr->addr)) {
889 continue;
890 }
891 tmp = addrrange_intersection(tmp, fr->addr);
892 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
893 int128_get64(tmp.start),
894 int128_get64(tmp.size));
895 }
896 }
897
898 static void address_space_update_topology_pass(AddressSpace *as,
899 const FlatView *old_view,
900 const FlatView *new_view,
901 bool adding)
902 {
903 unsigned iold, inew;
904 FlatRange *frold, *frnew;
905
906 /* Generate a symmetric difference of the old and new memory maps.
907 * Kill ranges in the old map, and instantiate ranges in the new map.
908 */
909 iold = inew = 0;
910 while (iold < old_view->nr || inew < new_view->nr) {
911 if (iold < old_view->nr) {
912 frold = &old_view->ranges[iold];
913 } else {
914 frold = NULL;
915 }
916 if (inew < new_view->nr) {
917 frnew = &new_view->ranges[inew];
918 } else {
919 frnew = NULL;
920 }
921
922 if (frold
923 && (!frnew
924 || int128_lt(frold->addr.start, frnew->addr.start)
925 || (int128_eq(frold->addr.start, frnew->addr.start)
926 && !flatrange_equal(frold, frnew)))) {
927 /* In old but not in new, or in both but attributes changed. */
928
929 if (!adding) {
930 flat_range_coalesced_io_del(frold, as);
931 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
932 }
933
934 ++iold;
935 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
936 /* In both and unchanged (except logging may have changed) */
937
938 if (!adding) {
939 flat_range_coalesced_io_del(frold, as);
940 } else {
941 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
942 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
943 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
944 frold->dirty_log_mask,
945 frnew->dirty_log_mask);
946 }
947 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
948 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
949 frold->dirty_log_mask,
950 frnew->dirty_log_mask);
951 }
952 flat_range_coalesced_io_add(frnew, as);
953 }
954
955 ++iold;
956 ++inew;
957 } else {
958 /* In new */
959
960 if (adding) {
961 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
962 flat_range_coalesced_io_add(frnew, as);
963 }
964
965 ++inew;
966 }
967 }
968 }
969
970 static void flatviews_init(void)
971 {
972 static FlatView *empty_view;
973
974 if (flat_views) {
975 return;
976 }
977
978 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
979 (GDestroyNotify) flatview_unref);
980 if (!empty_view) {
981 empty_view = generate_memory_topology(NULL);
982 /* We keep it alive forever in the global variable. */
983 flatview_ref(empty_view);
984 } else {
985 g_hash_table_replace(flat_views, NULL, empty_view);
986 flatview_ref(empty_view);
987 }
988 }
989
990 static void flatviews_reset(void)
991 {
992 AddressSpace *as;
993
994 if (flat_views) {
995 g_hash_table_unref(flat_views);
996 flat_views = NULL;
997 }
998 flatviews_init();
999
1000 /* Render unique FVs */
1001 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1002 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1003
1004 if (g_hash_table_lookup(flat_views, physmr)) {
1005 continue;
1006 }
1007
1008 generate_memory_topology(physmr);
1009 }
1010 }
1011
1012 static void address_space_set_flatview(AddressSpace *as)
1013 {
1014 FlatView *old_view = address_space_to_flatview(as);
1015 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1016 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1017
1018 assert(new_view);
1019
1020 if (old_view == new_view) {
1021 return;
1022 }
1023
1024 if (old_view) {
1025 flatview_ref(old_view);
1026 }
1027
1028 flatview_ref(new_view);
1029
1030 if (!QTAILQ_EMPTY(&as->listeners)) {
1031 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1032
1033 if (!old_view2) {
1034 old_view2 = &tmpview;
1035 }
1036 address_space_update_topology_pass(as, old_view2, new_view, false);
1037 address_space_update_topology_pass(as, old_view2, new_view, true);
1038 }
1039
1040 /* Writes are protected by the BQL. */
1041 atomic_rcu_set(&as->current_map, new_view);
1042 if (old_view) {
1043 flatview_unref(old_view);
1044 }
1045
1046 /* Note that all the old MemoryRegions are still alive up to this
1047 * point. This relieves most MemoryListeners from the need to
1048 * ref/unref the MemoryRegions they get---unless they use them
1049 * outside the iothread mutex, in which case precise reference
1050 * counting is necessary.
1051 */
1052 if (old_view) {
1053 flatview_unref(old_view);
1054 }
1055 }
1056
1057 static void address_space_update_topology(AddressSpace *as)
1058 {
1059 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1060
1061 flatviews_init();
1062 if (!g_hash_table_lookup(flat_views, physmr)) {
1063 generate_memory_topology(physmr);
1064 }
1065 address_space_set_flatview(as);
1066 }
1067
1068 void memory_region_transaction_begin(void)
1069 {
1070 qemu_flush_coalesced_mmio_buffer();
1071 ++memory_region_transaction_depth;
1072 }
1073
1074 void memory_region_transaction_commit(void)
1075 {
1076 AddressSpace *as;
1077
1078 assert(memory_region_transaction_depth);
1079 assert(qemu_mutex_iothread_locked());
1080
1081 --memory_region_transaction_depth;
1082 if (!memory_region_transaction_depth) {
1083 if (memory_region_update_pending) {
1084 flatviews_reset();
1085
1086 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1087
1088 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1089 address_space_set_flatview(as);
1090 address_space_update_ioeventfds(as);
1091 }
1092 memory_region_update_pending = false;
1093 ioeventfd_update_pending = false;
1094 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1095 } else if (ioeventfd_update_pending) {
1096 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1097 address_space_update_ioeventfds(as);
1098 }
1099 ioeventfd_update_pending = false;
1100 }
1101 }
1102 }
1103
1104 static void memory_region_destructor_none(MemoryRegion *mr)
1105 {
1106 }
1107
1108 static void memory_region_destructor_ram(MemoryRegion *mr)
1109 {
1110 qemu_ram_free(mr->ram_block);
1111 }
1112
1113 static bool memory_region_need_escape(char c)
1114 {
1115 return c == '/' || c == '[' || c == '\\' || c == ']';
1116 }
1117
1118 static char *memory_region_escape_name(const char *name)
1119 {
1120 const char *p;
1121 char *escaped, *q;
1122 uint8_t c;
1123 size_t bytes = 0;
1124
1125 for (p = name; *p; p++) {
1126 bytes += memory_region_need_escape(*p) ? 4 : 1;
1127 }
1128 if (bytes == p - name) {
1129 return g_memdup(name, bytes + 1);
1130 }
1131
1132 escaped = g_malloc(bytes + 1);
1133 for (p = name, q = escaped; *p; p++) {
1134 c = *p;
1135 if (unlikely(memory_region_need_escape(c))) {
1136 *q++ = '\\';
1137 *q++ = 'x';
1138 *q++ = "0123456789abcdef"[c >> 4];
1139 c = "0123456789abcdef"[c & 15];
1140 }
1141 *q++ = c;
1142 }
1143 *q = 0;
1144 return escaped;
1145 }
1146
1147 static void memory_region_do_init(MemoryRegion *mr,
1148 Object *owner,
1149 const char *name,
1150 uint64_t size)
1151 {
1152 mr->size = int128_make64(size);
1153 if (size == UINT64_MAX) {
1154 mr->size = int128_2_64();
1155 }
1156 mr->name = g_strdup(name);
1157 mr->owner = owner;
1158 mr->ram_block = NULL;
1159
1160 if (name) {
1161 char *escaped_name = memory_region_escape_name(name);
1162 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1163
1164 if (!owner) {
1165 owner = container_get(qdev_get_machine(), "/unattached");
1166 }
1167
1168 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1169 object_unref(OBJECT(mr));
1170 g_free(name_array);
1171 g_free(escaped_name);
1172 }
1173 }
1174
1175 void memory_region_init(MemoryRegion *mr,
1176 Object *owner,
1177 const char *name,
1178 uint64_t size)
1179 {
1180 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1181 memory_region_do_init(mr, owner, name, size);
1182 }
1183
1184 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1185 void *opaque, Error **errp)
1186 {
1187 MemoryRegion *mr = MEMORY_REGION(obj);
1188 uint64_t value = mr->addr;
1189
1190 visit_type_uint64(v, name, &value, errp);
1191 }
1192
1193 static void memory_region_get_container(Object *obj, Visitor *v,
1194 const char *name, void *opaque,
1195 Error **errp)
1196 {
1197 MemoryRegion *mr = MEMORY_REGION(obj);
1198 gchar *path = (gchar *)"";
1199
1200 if (mr->container) {
1201 path = object_get_canonical_path(OBJECT(mr->container));
1202 }
1203 visit_type_str(v, name, &path, errp);
1204 if (mr->container) {
1205 g_free(path);
1206 }
1207 }
1208
1209 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1210 const char *part)
1211 {
1212 MemoryRegion *mr = MEMORY_REGION(obj);
1213
1214 return OBJECT(mr->container);
1215 }
1216
1217 static void memory_region_get_priority(Object *obj, Visitor *v,
1218 const char *name, void *opaque,
1219 Error **errp)
1220 {
1221 MemoryRegion *mr = MEMORY_REGION(obj);
1222 int32_t value = mr->priority;
1223
1224 visit_type_int32(v, name, &value, errp);
1225 }
1226
1227 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1228 void *opaque, Error **errp)
1229 {
1230 MemoryRegion *mr = MEMORY_REGION(obj);
1231 uint64_t value = memory_region_size(mr);
1232
1233 visit_type_uint64(v, name, &value, errp);
1234 }
1235
1236 static void memory_region_initfn(Object *obj)
1237 {
1238 MemoryRegion *mr = MEMORY_REGION(obj);
1239 ObjectProperty *op;
1240
1241 mr->ops = &unassigned_mem_ops;
1242 mr->enabled = true;
1243 mr->romd_mode = true;
1244 mr->global_locking = true;
1245 mr->destructor = memory_region_destructor_none;
1246 QTAILQ_INIT(&mr->subregions);
1247 QTAILQ_INIT(&mr->coalesced);
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL, &error_abort);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add(OBJECT(mr), "addr", "uint64",
1257 memory_region_get_addr,
1258 NULL, /* memory_region_set_addr */
1259 NULL, NULL, &error_abort);
1260 object_property_add(OBJECT(mr), "priority", "uint32",
1261 memory_region_get_priority,
1262 NULL, /* memory_region_set_priority */
1263 NULL, NULL, &error_abort);
1264 object_property_add(OBJECT(mr), "size", "uint64",
1265 memory_region_get_size,
1266 NULL, /* memory_region_set_size, */
1267 NULL, NULL, &error_abort);
1268 }
1269
1270 static void iommu_memory_region_initfn(Object *obj)
1271 {
1272 MemoryRegion *mr = MEMORY_REGION(obj);
1273
1274 mr->is_iommu = true;
1275 }
1276
1277 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1278 unsigned size)
1279 {
1280 #ifdef DEBUG_UNASSIGNED
1281 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1282 #endif
1283 if (current_cpu != NULL) {
1284 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1285 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1286 }
1287 return 0;
1288 }
1289
1290 static void unassigned_mem_write(void *opaque, hwaddr addr,
1291 uint64_t val, unsigned size)
1292 {
1293 #ifdef DEBUG_UNASSIGNED
1294 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1295 #endif
1296 if (current_cpu != NULL) {
1297 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1298 }
1299 }
1300
1301 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1302 unsigned size, bool is_write,
1303 MemTxAttrs attrs)
1304 {
1305 return false;
1306 }
1307
1308 const MemoryRegionOps unassigned_mem_ops = {
1309 .valid.accepts = unassigned_mem_accepts,
1310 .endianness = DEVICE_NATIVE_ENDIAN,
1311 };
1312
1313 static uint64_t memory_region_ram_device_read(void *opaque,
1314 hwaddr addr, unsigned size)
1315 {
1316 MemoryRegion *mr = opaque;
1317 uint64_t data = (uint64_t)~0;
1318
1319 switch (size) {
1320 case 1:
1321 data = *(uint8_t *)(mr->ram_block->host + addr);
1322 break;
1323 case 2:
1324 data = *(uint16_t *)(mr->ram_block->host + addr);
1325 break;
1326 case 4:
1327 data = *(uint32_t *)(mr->ram_block->host + addr);
1328 break;
1329 case 8:
1330 data = *(uint64_t *)(mr->ram_block->host + addr);
1331 break;
1332 }
1333
1334 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1335
1336 return data;
1337 }
1338
1339 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1340 uint64_t data, unsigned size)
1341 {
1342 MemoryRegion *mr = opaque;
1343
1344 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1345
1346 switch (size) {
1347 case 1:
1348 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1349 break;
1350 case 2:
1351 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1352 break;
1353 case 4:
1354 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1355 break;
1356 case 8:
1357 *(uint64_t *)(mr->ram_block->host + addr) = data;
1358 break;
1359 }
1360 }
1361
1362 static const MemoryRegionOps ram_device_mem_ops = {
1363 .read = memory_region_ram_device_read,
1364 .write = memory_region_ram_device_write,
1365 .endianness = DEVICE_HOST_ENDIAN,
1366 .valid = {
1367 .min_access_size = 1,
1368 .max_access_size = 8,
1369 .unaligned = true,
1370 },
1371 .impl = {
1372 .min_access_size = 1,
1373 .max_access_size = 8,
1374 .unaligned = true,
1375 },
1376 };
1377
1378 bool memory_region_access_valid(MemoryRegion *mr,
1379 hwaddr addr,
1380 unsigned size,
1381 bool is_write,
1382 MemTxAttrs attrs)
1383 {
1384 int access_size_min, access_size_max;
1385 int access_size, i;
1386
1387 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1388 return false;
1389 }
1390
1391 if (!mr->ops->valid.accepts) {
1392 return true;
1393 }
1394
1395 access_size_min = mr->ops->valid.min_access_size;
1396 if (!mr->ops->valid.min_access_size) {
1397 access_size_min = 1;
1398 }
1399
1400 access_size_max = mr->ops->valid.max_access_size;
1401 if (!mr->ops->valid.max_access_size) {
1402 access_size_max = 4;
1403 }
1404
1405 access_size = MAX(MIN(size, access_size_max), access_size_min);
1406 for (i = 0; i < size; i += access_size) {
1407 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1408 is_write, attrs)) {
1409 return false;
1410 }
1411 }
1412
1413 return true;
1414 }
1415
1416 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1417 hwaddr addr,
1418 uint64_t *pval,
1419 unsigned size,
1420 MemTxAttrs attrs)
1421 {
1422 *pval = 0;
1423
1424 if (mr->ops->read) {
1425 return access_with_adjusted_size(addr, pval, size,
1426 mr->ops->impl.min_access_size,
1427 mr->ops->impl.max_access_size,
1428 memory_region_read_accessor,
1429 mr, attrs);
1430 } else {
1431 return access_with_adjusted_size(addr, pval, size,
1432 mr->ops->impl.min_access_size,
1433 mr->ops->impl.max_access_size,
1434 memory_region_read_with_attrs_accessor,
1435 mr, attrs);
1436 }
1437 }
1438
1439 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1440 hwaddr addr,
1441 uint64_t *pval,
1442 unsigned size,
1443 MemTxAttrs attrs)
1444 {
1445 MemTxResult r;
1446
1447 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1448 *pval = unassigned_mem_read(mr, addr, size);
1449 return MEMTX_DECODE_ERROR;
1450 }
1451
1452 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1453 adjust_endianness(mr, pval, size);
1454 return r;
1455 }
1456
1457 /* Return true if an eventfd was signalled */
1458 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1459 hwaddr addr,
1460 uint64_t data,
1461 unsigned size,
1462 MemTxAttrs attrs)
1463 {
1464 MemoryRegionIoeventfd ioeventfd = {
1465 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1466 .data = data,
1467 };
1468 unsigned i;
1469
1470 for (i = 0; i < mr->ioeventfd_nb; i++) {
1471 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1472 ioeventfd.e = mr->ioeventfds[i].e;
1473
1474 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1475 event_notifier_set(ioeventfd.e);
1476 return true;
1477 }
1478 }
1479
1480 return false;
1481 }
1482
1483 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1484 hwaddr addr,
1485 uint64_t data,
1486 unsigned size,
1487 MemTxAttrs attrs)
1488 {
1489 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1490 unassigned_mem_write(mr, addr, data, size);
1491 return MEMTX_DECODE_ERROR;
1492 }
1493
1494 adjust_endianness(mr, &data, size);
1495
1496 if ((!kvm_eventfds_enabled()) &&
1497 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1498 return MEMTX_OK;
1499 }
1500
1501 if (mr->ops->write) {
1502 return access_with_adjusted_size(addr, &data, size,
1503 mr->ops->impl.min_access_size,
1504 mr->ops->impl.max_access_size,
1505 memory_region_write_accessor, mr,
1506 attrs);
1507 } else {
1508 return
1509 access_with_adjusted_size(addr, &data, size,
1510 mr->ops->impl.min_access_size,
1511 mr->ops->impl.max_access_size,
1512 memory_region_write_with_attrs_accessor,
1513 mr, attrs);
1514 }
1515 }
1516
1517 void memory_region_init_io(MemoryRegion *mr,
1518 Object *owner,
1519 const MemoryRegionOps *ops,
1520 void *opaque,
1521 const char *name,
1522 uint64_t size)
1523 {
1524 memory_region_init(mr, owner, name, size);
1525 mr->ops = ops ? ops : &unassigned_mem_ops;
1526 mr->opaque = opaque;
1527 mr->terminates = true;
1528 }
1529
1530 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1531 Object *owner,
1532 const char *name,
1533 uint64_t size,
1534 Error **errp)
1535 {
1536 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1537 }
1538
1539 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1540 Object *owner,
1541 const char *name,
1542 uint64_t size,
1543 bool share,
1544 Error **errp)
1545 {
1546 Error *err = NULL;
1547 memory_region_init(mr, owner, name, size);
1548 mr->ram = true;
1549 mr->terminates = true;
1550 mr->destructor = memory_region_destructor_ram;
1551 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1552 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1553 if (err) {
1554 mr->size = int128_zero();
1555 object_unparent(OBJECT(mr));
1556 error_propagate(errp, err);
1557 }
1558 }
1559
1560 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1561 Object *owner,
1562 const char *name,
1563 uint64_t size,
1564 uint64_t max_size,
1565 void (*resized)(const char*,
1566 uint64_t length,
1567 void *host),
1568 Error **errp)
1569 {
1570 Error *err = NULL;
1571 memory_region_init(mr, owner, name, size);
1572 mr->ram = true;
1573 mr->terminates = true;
1574 mr->destructor = memory_region_destructor_ram;
1575 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1576 mr, &err);
1577 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1578 if (err) {
1579 mr->size = int128_zero();
1580 object_unparent(OBJECT(mr));
1581 error_propagate(errp, err);
1582 }
1583 }
1584
1585 #ifdef CONFIG_POSIX
1586 void memory_region_init_ram_from_file(MemoryRegion *mr,
1587 struct Object *owner,
1588 const char *name,
1589 uint64_t size,
1590 uint64_t align,
1591 uint32_t ram_flags,
1592 const char *path,
1593 Error **errp)
1594 {
1595 Error *err = NULL;
1596 memory_region_init(mr, owner, name, size);
1597 mr->ram = true;
1598 mr->terminates = true;
1599 mr->destructor = memory_region_destructor_ram;
1600 mr->align = align;
1601 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1602 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1603 if (err) {
1604 mr->size = int128_zero();
1605 object_unparent(OBJECT(mr));
1606 error_propagate(errp, err);
1607 }
1608 }
1609
1610 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1611 struct Object *owner,
1612 const char *name,
1613 uint64_t size,
1614 bool share,
1615 int fd,
1616 Error **errp)
1617 {
1618 Error *err = NULL;
1619 memory_region_init(mr, owner, name, size);
1620 mr->ram = true;
1621 mr->terminates = true;
1622 mr->destructor = memory_region_destructor_ram;
1623 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1624 share ? RAM_SHARED : 0,
1625 fd, &err);
1626 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1627 if (err) {
1628 mr->size = int128_zero();
1629 object_unparent(OBJECT(mr));
1630 error_propagate(errp, err);
1631 }
1632 }
1633 #endif
1634
1635 void memory_region_init_ram_ptr(MemoryRegion *mr,
1636 Object *owner,
1637 const char *name,
1638 uint64_t size,
1639 void *ptr)
1640 {
1641 memory_region_init(mr, owner, name, size);
1642 mr->ram = true;
1643 mr->terminates = true;
1644 mr->destructor = memory_region_destructor_ram;
1645 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1646
1647 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1648 assert(ptr != NULL);
1649 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1650 }
1651
1652 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1653 Object *owner,
1654 const char *name,
1655 uint64_t size,
1656 void *ptr)
1657 {
1658 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1659 mr->ram_device = true;
1660 mr->ops = &ram_device_mem_ops;
1661 mr->opaque = mr;
1662 }
1663
1664 void memory_region_init_alias(MemoryRegion *mr,
1665 Object *owner,
1666 const char *name,
1667 MemoryRegion *orig,
1668 hwaddr offset,
1669 uint64_t size)
1670 {
1671 memory_region_init(mr, owner, name, size);
1672 mr->alias = orig;
1673 mr->alias_offset = offset;
1674 }
1675
1676 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1677 struct Object *owner,
1678 const char *name,
1679 uint64_t size,
1680 Error **errp)
1681 {
1682 Error *err = NULL;
1683 memory_region_init(mr, owner, name, size);
1684 mr->ram = true;
1685 mr->readonly = true;
1686 mr->terminates = true;
1687 mr->destructor = memory_region_destructor_ram;
1688 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1689 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1690 if (err) {
1691 mr->size = int128_zero();
1692 object_unparent(OBJECT(mr));
1693 error_propagate(errp, err);
1694 }
1695 }
1696
1697 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1698 Object *owner,
1699 const MemoryRegionOps *ops,
1700 void *opaque,
1701 const char *name,
1702 uint64_t size,
1703 Error **errp)
1704 {
1705 Error *err = NULL;
1706 assert(ops);
1707 memory_region_init(mr, owner, name, size);
1708 mr->ops = ops;
1709 mr->opaque = opaque;
1710 mr->terminates = true;
1711 mr->rom_device = true;
1712 mr->destructor = memory_region_destructor_ram;
1713 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1714 if (err) {
1715 mr->size = int128_zero();
1716 object_unparent(OBJECT(mr));
1717 error_propagate(errp, err);
1718 }
1719 }
1720
1721 void memory_region_init_iommu(void *_iommu_mr,
1722 size_t instance_size,
1723 const char *mrtypename,
1724 Object *owner,
1725 const char *name,
1726 uint64_t size)
1727 {
1728 struct IOMMUMemoryRegion *iommu_mr;
1729 struct MemoryRegion *mr;
1730
1731 object_initialize(_iommu_mr, instance_size, mrtypename);
1732 mr = MEMORY_REGION(_iommu_mr);
1733 memory_region_do_init(mr, owner, name, size);
1734 iommu_mr = IOMMU_MEMORY_REGION(mr);
1735 mr->terminates = true; /* then re-forwards */
1736 QLIST_INIT(&iommu_mr->iommu_notify);
1737 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1738 }
1739
1740 static void memory_region_finalize(Object *obj)
1741 {
1742 MemoryRegion *mr = MEMORY_REGION(obj);
1743
1744 assert(!mr->container);
1745
1746 /* We know the region is not visible in any address space (it
1747 * does not have a container and cannot be a root either because
1748 * it has no references, so we can blindly clear mr->enabled.
1749 * memory_region_set_enabled instead could trigger a transaction
1750 * and cause an infinite loop.
1751 */
1752 mr->enabled = false;
1753 memory_region_transaction_begin();
1754 while (!QTAILQ_EMPTY(&mr->subregions)) {
1755 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1756 memory_region_del_subregion(mr, subregion);
1757 }
1758 memory_region_transaction_commit();
1759
1760 mr->destructor(mr);
1761 memory_region_clear_coalescing(mr);
1762 g_free((char *)mr->name);
1763 g_free(mr->ioeventfds);
1764 }
1765
1766 Object *memory_region_owner(MemoryRegion *mr)
1767 {
1768 Object *obj = OBJECT(mr);
1769 return obj->parent;
1770 }
1771
1772 void memory_region_ref(MemoryRegion *mr)
1773 {
1774 /* MMIO callbacks most likely will access data that belongs
1775 * to the owner, hence the need to ref/unref the owner whenever
1776 * the memory region is in use.
1777 *
1778 * The memory region is a child of its owner. As long as the
1779 * owner doesn't call unparent itself on the memory region,
1780 * ref-ing the owner will also keep the memory region alive.
1781 * Memory regions without an owner are supposed to never go away;
1782 * we do not ref/unref them because it slows down DMA sensibly.
1783 */
1784 if (mr && mr->owner) {
1785 object_ref(mr->owner);
1786 }
1787 }
1788
1789 void memory_region_unref(MemoryRegion *mr)
1790 {
1791 if (mr && mr->owner) {
1792 object_unref(mr->owner);
1793 }
1794 }
1795
1796 uint64_t memory_region_size(MemoryRegion *mr)
1797 {
1798 if (int128_eq(mr->size, int128_2_64())) {
1799 return UINT64_MAX;
1800 }
1801 return int128_get64(mr->size);
1802 }
1803
1804 const char *memory_region_name(const MemoryRegion *mr)
1805 {
1806 if (!mr->name) {
1807 ((MemoryRegion *)mr)->name =
1808 object_get_canonical_path_component(OBJECT(mr));
1809 }
1810 return mr->name;
1811 }
1812
1813 bool memory_region_is_ram_device(MemoryRegion *mr)
1814 {
1815 return mr->ram_device;
1816 }
1817
1818 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1819 {
1820 uint8_t mask = mr->dirty_log_mask;
1821 if (global_dirty_log && mr->ram_block) {
1822 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1823 }
1824 return mask;
1825 }
1826
1827 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1828 {
1829 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1830 }
1831
1832 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1833 {
1834 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1835 IOMMUNotifier *iommu_notifier;
1836 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1837
1838 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1839 flags |= iommu_notifier->notifier_flags;
1840 }
1841
1842 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1843 imrc->notify_flag_changed(iommu_mr,
1844 iommu_mr->iommu_notify_flags,
1845 flags);
1846 }
1847
1848 iommu_mr->iommu_notify_flags = flags;
1849 }
1850
1851 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1852 IOMMUNotifier *n)
1853 {
1854 IOMMUMemoryRegion *iommu_mr;
1855
1856 if (mr->alias) {
1857 memory_region_register_iommu_notifier(mr->alias, n);
1858 return;
1859 }
1860
1861 /* We need to register for at least one bitfield */
1862 iommu_mr = IOMMU_MEMORY_REGION(mr);
1863 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1864 assert(n->start <= n->end);
1865 assert(n->iommu_idx >= 0 &&
1866 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1867
1868 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1869 memory_region_update_iommu_notify_flags(iommu_mr);
1870 }
1871
1872 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1873 {
1874 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1875
1876 if (imrc->get_min_page_size) {
1877 return imrc->get_min_page_size(iommu_mr);
1878 }
1879 return TARGET_PAGE_SIZE;
1880 }
1881
1882 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1883 {
1884 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1885 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1886 hwaddr addr, granularity;
1887 IOMMUTLBEntry iotlb;
1888
1889 /* If the IOMMU has its own replay callback, override */
1890 if (imrc->replay) {
1891 imrc->replay(iommu_mr, n);
1892 return;
1893 }
1894
1895 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1896
1897 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1898 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1899 if (iotlb.perm != IOMMU_NONE) {
1900 n->notify(n, &iotlb);
1901 }
1902
1903 /* if (2^64 - MR size) < granularity, it's possible to get an
1904 * infinite loop here. This should catch such a wraparound */
1905 if ((addr + granularity) < addr) {
1906 break;
1907 }
1908 }
1909 }
1910
1911 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1912 {
1913 IOMMUNotifier *notifier;
1914
1915 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1916 memory_region_iommu_replay(iommu_mr, notifier);
1917 }
1918 }
1919
1920 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1921 IOMMUNotifier *n)
1922 {
1923 IOMMUMemoryRegion *iommu_mr;
1924
1925 if (mr->alias) {
1926 memory_region_unregister_iommu_notifier(mr->alias, n);
1927 return;
1928 }
1929 QLIST_REMOVE(n, node);
1930 iommu_mr = IOMMU_MEMORY_REGION(mr);
1931 memory_region_update_iommu_notify_flags(iommu_mr);
1932 }
1933
1934 void memory_region_notify_one(IOMMUNotifier *notifier,
1935 IOMMUTLBEntry *entry)
1936 {
1937 IOMMUNotifierFlag request_flags;
1938
1939 /*
1940 * Skip the notification if the notification does not overlap
1941 * with registered range.
1942 */
1943 if (notifier->start > entry->iova + entry->addr_mask ||
1944 notifier->end < entry->iova) {
1945 return;
1946 }
1947
1948 if (entry->perm & IOMMU_RW) {
1949 request_flags = IOMMU_NOTIFIER_MAP;
1950 } else {
1951 request_flags = IOMMU_NOTIFIER_UNMAP;
1952 }
1953
1954 if (notifier->notifier_flags & request_flags) {
1955 notifier->notify(notifier, entry);
1956 }
1957 }
1958
1959 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1960 int iommu_idx,
1961 IOMMUTLBEntry entry)
1962 {
1963 IOMMUNotifier *iommu_notifier;
1964
1965 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1966
1967 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1968 if (iommu_notifier->iommu_idx == iommu_idx) {
1969 memory_region_notify_one(iommu_notifier, &entry);
1970 }
1971 }
1972 }
1973
1974 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1975 enum IOMMUMemoryRegionAttr attr,
1976 void *data)
1977 {
1978 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1979
1980 if (!imrc->get_attr) {
1981 return -EINVAL;
1982 }
1983
1984 return imrc->get_attr(iommu_mr, attr, data);
1985 }
1986
1987 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1988 MemTxAttrs attrs)
1989 {
1990 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1991
1992 if (!imrc->attrs_to_index) {
1993 return 0;
1994 }
1995
1996 return imrc->attrs_to_index(iommu_mr, attrs);
1997 }
1998
1999 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2000 {
2001 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2002
2003 if (!imrc->num_indexes) {
2004 return 1;
2005 }
2006
2007 return imrc->num_indexes(iommu_mr);
2008 }
2009
2010 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2011 {
2012 uint8_t mask = 1 << client;
2013 uint8_t old_logging;
2014
2015 assert(client == DIRTY_MEMORY_VGA);
2016 old_logging = mr->vga_logging_count;
2017 mr->vga_logging_count += log ? 1 : -1;
2018 if (!!old_logging == !!mr->vga_logging_count) {
2019 return;
2020 }
2021
2022 memory_region_transaction_begin();
2023 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2024 memory_region_update_pending |= mr->enabled;
2025 memory_region_transaction_commit();
2026 }
2027
2028 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
2029 hwaddr size, unsigned client)
2030 {
2031 assert(mr->ram_block);
2032 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
2033 size, client);
2034 }
2035
2036 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2037 hwaddr size)
2038 {
2039 assert(mr->ram_block);
2040 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2041 size,
2042 memory_region_get_dirty_log_mask(mr));
2043 }
2044
2045 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2046 {
2047 MemoryListener *listener;
2048 AddressSpace *as;
2049 FlatView *view;
2050 FlatRange *fr;
2051
2052 /* If the same address space has multiple log_sync listeners, we
2053 * visit that address space's FlatView multiple times. But because
2054 * log_sync listeners are rare, it's still cheaper than walking each
2055 * address space once.
2056 */
2057 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2058 if (!listener->log_sync) {
2059 continue;
2060 }
2061 as = listener->address_space;
2062 view = address_space_get_flatview(as);
2063 FOR_EACH_FLAT_RANGE(fr, view) {
2064 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2065 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2066 listener->log_sync(listener, &mrs);
2067 }
2068 }
2069 flatview_unref(view);
2070 }
2071 }
2072
2073 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2074 hwaddr addr,
2075 hwaddr size,
2076 unsigned client)
2077 {
2078 assert(mr->ram_block);
2079 memory_region_sync_dirty_bitmap(mr);
2080 return cpu_physical_memory_snapshot_and_clear_dirty(
2081 memory_region_get_ram_addr(mr) + addr, size, client);
2082 }
2083
2084 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2085 hwaddr addr, hwaddr size)
2086 {
2087 assert(mr->ram_block);
2088 return cpu_physical_memory_snapshot_get_dirty(snap,
2089 memory_region_get_ram_addr(mr) + addr, size);
2090 }
2091
2092 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2093 {
2094 if (mr->readonly != readonly) {
2095 memory_region_transaction_begin();
2096 mr->readonly = readonly;
2097 memory_region_update_pending |= mr->enabled;
2098 memory_region_transaction_commit();
2099 }
2100 }
2101
2102 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2103 {
2104 if (mr->nonvolatile != nonvolatile) {
2105 memory_region_transaction_begin();
2106 mr->nonvolatile = nonvolatile;
2107 memory_region_update_pending |= mr->enabled;
2108 memory_region_transaction_commit();
2109 }
2110 }
2111
2112 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2113 {
2114 if (mr->romd_mode != romd_mode) {
2115 memory_region_transaction_begin();
2116 mr->romd_mode = romd_mode;
2117 memory_region_update_pending |= mr->enabled;
2118 memory_region_transaction_commit();
2119 }
2120 }
2121
2122 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2123 hwaddr size, unsigned client)
2124 {
2125 assert(mr->ram_block);
2126 cpu_physical_memory_test_and_clear_dirty(
2127 memory_region_get_ram_addr(mr) + addr, size, client);
2128 }
2129
2130 int memory_region_get_fd(MemoryRegion *mr)
2131 {
2132 int fd;
2133
2134 rcu_read_lock();
2135 while (mr->alias) {
2136 mr = mr->alias;
2137 }
2138 fd = mr->ram_block->fd;
2139 rcu_read_unlock();
2140
2141 return fd;
2142 }
2143
2144 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2145 {
2146 void *ptr;
2147 uint64_t offset = 0;
2148
2149 rcu_read_lock();
2150 while (mr->alias) {
2151 offset += mr->alias_offset;
2152 mr = mr->alias;
2153 }
2154 assert(mr->ram_block);
2155 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2156 rcu_read_unlock();
2157
2158 return ptr;
2159 }
2160
2161 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2162 {
2163 RAMBlock *block;
2164
2165 block = qemu_ram_block_from_host(ptr, false, offset);
2166 if (!block) {
2167 return NULL;
2168 }
2169
2170 return block->mr;
2171 }
2172
2173 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2174 {
2175 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2176 }
2177
2178 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2179 {
2180 assert(mr->ram_block);
2181
2182 qemu_ram_resize(mr->ram_block, newsize, errp);
2183 }
2184
2185 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2186 {
2187 FlatView *view;
2188 FlatRange *fr;
2189
2190 view = address_space_get_flatview(as);
2191 FOR_EACH_FLAT_RANGE(fr, view) {
2192 if (fr->mr == mr) {
2193 flat_range_coalesced_io_del(fr, as);
2194 flat_range_coalesced_io_add(fr, as);
2195 }
2196 }
2197 flatview_unref(view);
2198 }
2199
2200 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2201 {
2202 AddressSpace *as;
2203
2204 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2205 memory_region_update_coalesced_range_as(mr, as);
2206 }
2207 }
2208
2209 void memory_region_set_coalescing(MemoryRegion *mr)
2210 {
2211 memory_region_clear_coalescing(mr);
2212 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2213 }
2214
2215 void memory_region_add_coalescing(MemoryRegion *mr,
2216 hwaddr offset,
2217 uint64_t size)
2218 {
2219 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2220
2221 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2222 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2223 memory_region_update_coalesced_range(mr);
2224 memory_region_set_flush_coalesced(mr);
2225 }
2226
2227 void memory_region_clear_coalescing(MemoryRegion *mr)
2228 {
2229 CoalescedMemoryRange *cmr;
2230 bool updated = false;
2231
2232 qemu_flush_coalesced_mmio_buffer();
2233 mr->flush_coalesced_mmio = false;
2234
2235 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2236 cmr = QTAILQ_FIRST(&mr->coalesced);
2237 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2238 g_free(cmr);
2239 updated = true;
2240 }
2241
2242 if (updated) {
2243 memory_region_update_coalesced_range(mr);
2244 }
2245 }
2246
2247 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2248 {
2249 mr->flush_coalesced_mmio = true;
2250 }
2251
2252 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2253 {
2254 qemu_flush_coalesced_mmio_buffer();
2255 if (QTAILQ_EMPTY(&mr->coalesced)) {
2256 mr->flush_coalesced_mmio = false;
2257 }
2258 }
2259
2260 void memory_region_clear_global_locking(MemoryRegion *mr)
2261 {
2262 mr->global_locking = false;
2263 }
2264
2265 static bool userspace_eventfd_warning;
2266
2267 void memory_region_add_eventfd(MemoryRegion *mr,
2268 hwaddr addr,
2269 unsigned size,
2270 bool match_data,
2271 uint64_t data,
2272 EventNotifier *e)
2273 {
2274 MemoryRegionIoeventfd mrfd = {
2275 .addr.start = int128_make64(addr),
2276 .addr.size = int128_make64(size),
2277 .match_data = match_data,
2278 .data = data,
2279 .e = e,
2280 };
2281 unsigned i;
2282
2283 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2284 userspace_eventfd_warning))) {
2285 userspace_eventfd_warning = true;
2286 error_report("Using eventfd without MMIO binding in KVM. "
2287 "Suboptimal performance expected");
2288 }
2289
2290 if (size) {
2291 adjust_endianness(mr, &mrfd.data, size);
2292 }
2293 memory_region_transaction_begin();
2294 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2295 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2296 break;
2297 }
2298 }
2299 ++mr->ioeventfd_nb;
2300 mr->ioeventfds = g_realloc(mr->ioeventfds,
2301 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2302 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2303 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2304 mr->ioeventfds[i] = mrfd;
2305 ioeventfd_update_pending |= mr->enabled;
2306 memory_region_transaction_commit();
2307 }
2308
2309 void memory_region_del_eventfd(MemoryRegion *mr,
2310 hwaddr addr,
2311 unsigned size,
2312 bool match_data,
2313 uint64_t data,
2314 EventNotifier *e)
2315 {
2316 MemoryRegionIoeventfd mrfd = {
2317 .addr.start = int128_make64(addr),
2318 .addr.size = int128_make64(size),
2319 .match_data = match_data,
2320 .data = data,
2321 .e = e,
2322 };
2323 unsigned i;
2324
2325 if (size) {
2326 adjust_endianness(mr, &mrfd.data, size);
2327 }
2328 memory_region_transaction_begin();
2329 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2330 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2331 break;
2332 }
2333 }
2334 assert(i != mr->ioeventfd_nb);
2335 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2336 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2337 --mr->ioeventfd_nb;
2338 mr->ioeventfds = g_realloc(mr->ioeventfds,
2339 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2340 ioeventfd_update_pending |= mr->enabled;
2341 memory_region_transaction_commit();
2342 }
2343
2344 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2345 {
2346 MemoryRegion *mr = subregion->container;
2347 MemoryRegion *other;
2348
2349 memory_region_transaction_begin();
2350
2351 memory_region_ref(subregion);
2352 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2353 if (subregion->priority >= other->priority) {
2354 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2355 goto done;
2356 }
2357 }
2358 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2359 done:
2360 memory_region_update_pending |= mr->enabled && subregion->enabled;
2361 memory_region_transaction_commit();
2362 }
2363
2364 static void memory_region_add_subregion_common(MemoryRegion *mr,
2365 hwaddr offset,
2366 MemoryRegion *subregion)
2367 {
2368 assert(!subregion->container);
2369 subregion->container = mr;
2370 subregion->addr = offset;
2371 memory_region_update_container_subregions(subregion);
2372 }
2373
2374 void memory_region_add_subregion(MemoryRegion *mr,
2375 hwaddr offset,
2376 MemoryRegion *subregion)
2377 {
2378 subregion->priority = 0;
2379 memory_region_add_subregion_common(mr, offset, subregion);
2380 }
2381
2382 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2383 hwaddr offset,
2384 MemoryRegion *subregion,
2385 int priority)
2386 {
2387 subregion->priority = priority;
2388 memory_region_add_subregion_common(mr, offset, subregion);
2389 }
2390
2391 void memory_region_del_subregion(MemoryRegion *mr,
2392 MemoryRegion *subregion)
2393 {
2394 memory_region_transaction_begin();
2395 assert(subregion->container == mr);
2396 subregion->container = NULL;
2397 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2398 memory_region_unref(subregion);
2399 memory_region_update_pending |= mr->enabled && subregion->enabled;
2400 memory_region_transaction_commit();
2401 }
2402
2403 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2404 {
2405 if (enabled == mr->enabled) {
2406 return;
2407 }
2408 memory_region_transaction_begin();
2409 mr->enabled = enabled;
2410 memory_region_update_pending = true;
2411 memory_region_transaction_commit();
2412 }
2413
2414 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2415 {
2416 Int128 s = int128_make64(size);
2417
2418 if (size == UINT64_MAX) {
2419 s = int128_2_64();
2420 }
2421 if (int128_eq(s, mr->size)) {
2422 return;
2423 }
2424 memory_region_transaction_begin();
2425 mr->size = s;
2426 memory_region_update_pending = true;
2427 memory_region_transaction_commit();
2428 }
2429
2430 static void memory_region_readd_subregion(MemoryRegion *mr)
2431 {
2432 MemoryRegion *container = mr->container;
2433
2434 if (container) {
2435 memory_region_transaction_begin();
2436 memory_region_ref(mr);
2437 memory_region_del_subregion(container, mr);
2438 mr->container = container;
2439 memory_region_update_container_subregions(mr);
2440 memory_region_unref(mr);
2441 memory_region_transaction_commit();
2442 }
2443 }
2444
2445 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2446 {
2447 if (addr != mr->addr) {
2448 mr->addr = addr;
2449 memory_region_readd_subregion(mr);
2450 }
2451 }
2452
2453 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2454 {
2455 assert(mr->alias);
2456
2457 if (offset == mr->alias_offset) {
2458 return;
2459 }
2460
2461 memory_region_transaction_begin();
2462 mr->alias_offset = offset;
2463 memory_region_update_pending |= mr->enabled;
2464 memory_region_transaction_commit();
2465 }
2466
2467 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2468 {
2469 return mr->align;
2470 }
2471
2472 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2473 {
2474 const AddrRange *addr = addr_;
2475 const FlatRange *fr = fr_;
2476
2477 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2478 return -1;
2479 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2480 return 1;
2481 }
2482 return 0;
2483 }
2484
2485 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2486 {
2487 return bsearch(&addr, view->ranges, view->nr,
2488 sizeof(FlatRange), cmp_flatrange_addr);
2489 }
2490
2491 bool memory_region_is_mapped(MemoryRegion *mr)
2492 {
2493 return mr->container ? true : false;
2494 }
2495
2496 /* Same as memory_region_find, but it does not add a reference to the
2497 * returned region. It must be called from an RCU critical section.
2498 */
2499 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2500 hwaddr addr, uint64_t size)
2501 {
2502 MemoryRegionSection ret = { .mr = NULL };
2503 MemoryRegion *root;
2504 AddressSpace *as;
2505 AddrRange range;
2506 FlatView *view;
2507 FlatRange *fr;
2508
2509 addr += mr->addr;
2510 for (root = mr; root->container; ) {
2511 root = root->container;
2512 addr += root->addr;
2513 }
2514
2515 as = memory_region_to_address_space(root);
2516 if (!as) {
2517 return ret;
2518 }
2519 range = addrrange_make(int128_make64(addr), int128_make64(size));
2520
2521 view = address_space_to_flatview(as);
2522 fr = flatview_lookup(view, range);
2523 if (!fr) {
2524 return ret;
2525 }
2526
2527 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2528 --fr;
2529 }
2530
2531 ret.mr = fr->mr;
2532 ret.fv = view;
2533 range = addrrange_intersection(range, fr->addr);
2534 ret.offset_within_region = fr->offset_in_region;
2535 ret.offset_within_region += int128_get64(int128_sub(range.start,
2536 fr->addr.start));
2537 ret.size = range.size;
2538 ret.offset_within_address_space = int128_get64(range.start);
2539 ret.readonly = fr->readonly;
2540 ret.nonvolatile = fr->nonvolatile;
2541 return ret;
2542 }
2543
2544 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2545 hwaddr addr, uint64_t size)
2546 {
2547 MemoryRegionSection ret;
2548 rcu_read_lock();
2549 ret = memory_region_find_rcu(mr, addr, size);
2550 if (ret.mr) {
2551 memory_region_ref(ret.mr);
2552 }
2553 rcu_read_unlock();
2554 return ret;
2555 }
2556
2557 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2558 {
2559 MemoryRegion *mr;
2560
2561 rcu_read_lock();
2562 mr = memory_region_find_rcu(container, addr, 1).mr;
2563 rcu_read_unlock();
2564 return mr && mr != container;
2565 }
2566
2567 void memory_global_dirty_log_sync(void)
2568 {
2569 memory_region_sync_dirty_bitmap(NULL);
2570 }
2571
2572 static VMChangeStateEntry *vmstate_change;
2573
2574 void memory_global_dirty_log_start(void)
2575 {
2576 if (vmstate_change) {
2577 qemu_del_vm_change_state_handler(vmstate_change);
2578 vmstate_change = NULL;
2579 }
2580
2581 global_dirty_log = true;
2582
2583 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2584
2585 /* Refresh DIRTY_LOG_MIGRATION bit. */
2586 memory_region_transaction_begin();
2587 memory_region_update_pending = true;
2588 memory_region_transaction_commit();
2589 }
2590
2591 static void memory_global_dirty_log_do_stop(void)
2592 {
2593 global_dirty_log = false;
2594
2595 /* Refresh DIRTY_LOG_MIGRATION bit. */
2596 memory_region_transaction_begin();
2597 memory_region_update_pending = true;
2598 memory_region_transaction_commit();
2599
2600 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2601 }
2602
2603 static void memory_vm_change_state_handler(void *opaque, int running,
2604 RunState state)
2605 {
2606 if (running) {
2607 memory_global_dirty_log_do_stop();
2608
2609 if (vmstate_change) {
2610 qemu_del_vm_change_state_handler(vmstate_change);
2611 vmstate_change = NULL;
2612 }
2613 }
2614 }
2615
2616 void memory_global_dirty_log_stop(void)
2617 {
2618 if (!runstate_is_running()) {
2619 if (vmstate_change) {
2620 return;
2621 }
2622 vmstate_change = qemu_add_vm_change_state_handler(
2623 memory_vm_change_state_handler, NULL);
2624 return;
2625 }
2626
2627 memory_global_dirty_log_do_stop();
2628 }
2629
2630 static void listener_add_address_space(MemoryListener *listener,
2631 AddressSpace *as)
2632 {
2633 FlatView *view;
2634 FlatRange *fr;
2635
2636 if (listener->begin) {
2637 listener->begin(listener);
2638 }
2639 if (global_dirty_log) {
2640 if (listener->log_global_start) {
2641 listener->log_global_start(listener);
2642 }
2643 }
2644
2645 view = address_space_get_flatview(as);
2646 FOR_EACH_FLAT_RANGE(fr, view) {
2647 MemoryRegionSection section = section_from_flat_range(fr, view);
2648
2649 if (listener->region_add) {
2650 listener->region_add(listener, &section);
2651 }
2652 if (fr->dirty_log_mask && listener->log_start) {
2653 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2654 }
2655 }
2656 if (listener->commit) {
2657 listener->commit(listener);
2658 }
2659 flatview_unref(view);
2660 }
2661
2662 static void listener_del_address_space(MemoryListener *listener,
2663 AddressSpace *as)
2664 {
2665 FlatView *view;
2666 FlatRange *fr;
2667
2668 if (listener->begin) {
2669 listener->begin(listener);
2670 }
2671 view = address_space_get_flatview(as);
2672 FOR_EACH_FLAT_RANGE(fr, view) {
2673 MemoryRegionSection section = section_from_flat_range(fr, view);
2674
2675 if (fr->dirty_log_mask && listener->log_stop) {
2676 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2677 }
2678 if (listener->region_del) {
2679 listener->region_del(listener, &section);
2680 }
2681 }
2682 if (listener->commit) {
2683 listener->commit(listener);
2684 }
2685 flatview_unref(view);
2686 }
2687
2688 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2689 {
2690 MemoryListener *other = NULL;
2691
2692 listener->address_space = as;
2693 if (QTAILQ_EMPTY(&memory_listeners)
2694 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2695 memory_listeners)->priority) {
2696 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2697 } else {
2698 QTAILQ_FOREACH(other, &memory_listeners, link) {
2699 if (listener->priority < other->priority) {
2700 break;
2701 }
2702 }
2703 QTAILQ_INSERT_BEFORE(other, listener, link);
2704 }
2705
2706 if (QTAILQ_EMPTY(&as->listeners)
2707 || listener->priority >= QTAILQ_LAST(&as->listeners,
2708 memory_listeners)->priority) {
2709 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2710 } else {
2711 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2712 if (listener->priority < other->priority) {
2713 break;
2714 }
2715 }
2716 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2717 }
2718
2719 listener_add_address_space(listener, as);
2720 }
2721
2722 void memory_listener_unregister(MemoryListener *listener)
2723 {
2724 if (!listener->address_space) {
2725 return;
2726 }
2727
2728 listener_del_address_space(listener, listener->address_space);
2729 QTAILQ_REMOVE(&memory_listeners, listener, link);
2730 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2731 listener->address_space = NULL;
2732 }
2733
2734 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2735 {
2736 memory_region_ref(root);
2737 as->root = root;
2738 as->current_map = NULL;
2739 as->ioeventfd_nb = 0;
2740 as->ioeventfds = NULL;
2741 QTAILQ_INIT(&as->listeners);
2742 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2743 as->name = g_strdup(name ? name : "anonymous");
2744 address_space_update_topology(as);
2745 address_space_update_ioeventfds(as);
2746 }
2747
2748 static void do_address_space_destroy(AddressSpace *as)
2749 {
2750 assert(QTAILQ_EMPTY(&as->listeners));
2751
2752 flatview_unref(as->current_map);
2753 g_free(as->name);
2754 g_free(as->ioeventfds);
2755 memory_region_unref(as->root);
2756 }
2757
2758 void address_space_destroy(AddressSpace *as)
2759 {
2760 MemoryRegion *root = as->root;
2761
2762 /* Flush out anything from MemoryListeners listening in on this */
2763 memory_region_transaction_begin();
2764 as->root = NULL;
2765 memory_region_transaction_commit();
2766 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2767
2768 /* At this point, as->dispatch and as->current_map are dummy
2769 * entries that the guest should never use. Wait for the old
2770 * values to expire before freeing the data.
2771 */
2772 as->root = root;
2773 call_rcu(as, do_address_space_destroy, rcu);
2774 }
2775
2776 static const char *memory_region_type(MemoryRegion *mr)
2777 {
2778 if (memory_region_is_ram_device(mr)) {
2779 return "ramd";
2780 } else if (memory_region_is_romd(mr)) {
2781 return "romd";
2782 } else if (memory_region_is_rom(mr)) {
2783 return "rom";
2784 } else if (memory_region_is_ram(mr)) {
2785 return "ram";
2786 } else {
2787 return "i/o";
2788 }
2789 }
2790
2791 typedef struct MemoryRegionList MemoryRegionList;
2792
2793 struct MemoryRegionList {
2794 const MemoryRegion *mr;
2795 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2796 };
2797
2798 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2799
2800 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2801 int128_sub((size), int128_one())) : 0)
2802 #define MTREE_INDENT " "
2803
2804 static void mtree_expand_owner(fprintf_function mon_printf, void *f,
2805 const char *label, Object *obj)
2806 {
2807 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2808
2809 mon_printf(f, " %s:{%s", label, dev ? "dev" : "obj");
2810 if (dev && dev->id) {
2811 mon_printf(f, " id=%s", dev->id);
2812 } else {
2813 gchar *canonical_path = object_get_canonical_path(obj);
2814 if (canonical_path) {
2815 mon_printf(f, " path=%s", canonical_path);
2816 g_free(canonical_path);
2817 } else {
2818 mon_printf(f, " type=%s", object_get_typename(obj));
2819 }
2820 }
2821 mon_printf(f, "}");
2822 }
2823
2824 static void mtree_print_mr_owner(fprintf_function mon_printf, void *f,
2825 const MemoryRegion *mr)
2826 {
2827 Object *owner = mr->owner;
2828 Object *parent = memory_region_owner((MemoryRegion *)mr);
2829
2830 if (!owner && !parent) {
2831 mon_printf(f, " orphan");
2832 return;
2833 }
2834 if (owner) {
2835 mtree_expand_owner(mon_printf, f, "owner", owner);
2836 }
2837 if (parent && parent != owner) {
2838 mtree_expand_owner(mon_printf, f, "parent", parent);
2839 }
2840 }
2841
2842 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2843 const MemoryRegion *mr, unsigned int level,
2844 hwaddr base,
2845 MemoryRegionListHead *alias_print_queue,
2846 bool owner)
2847 {
2848 MemoryRegionList *new_ml, *ml, *next_ml;
2849 MemoryRegionListHead submr_print_queue;
2850 const MemoryRegion *submr;
2851 unsigned int i;
2852 hwaddr cur_start, cur_end;
2853
2854 if (!mr) {
2855 return;
2856 }
2857
2858 for (i = 0; i < level; i++) {
2859 mon_printf(f, MTREE_INDENT);
2860 }
2861
2862 cur_start = base + mr->addr;
2863 cur_end = cur_start + MR_SIZE(mr->size);
2864
2865 /*
2866 * Try to detect overflow of memory region. This should never
2867 * happen normally. When it happens, we dump something to warn the
2868 * user who is observing this.
2869 */
2870 if (cur_start < base || cur_end < cur_start) {
2871 mon_printf(f, "[DETECTED OVERFLOW!] ");
2872 }
2873
2874 if (mr->alias) {
2875 MemoryRegionList *ml;
2876 bool found = false;
2877
2878 /* check if the alias is already in the queue */
2879 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2880 if (ml->mr == mr->alias) {
2881 found = true;
2882 }
2883 }
2884
2885 if (!found) {
2886 ml = g_new(MemoryRegionList, 1);
2887 ml->mr = mr->alias;
2888 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2889 }
2890 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2891 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2892 "-" TARGET_FMT_plx "%s",
2893 cur_start, cur_end,
2894 mr->priority,
2895 mr->nonvolatile ? "nv-" : "",
2896 memory_region_type((MemoryRegion *)mr),
2897 memory_region_name(mr),
2898 memory_region_name(mr->alias),
2899 mr->alias_offset,
2900 mr->alias_offset + MR_SIZE(mr->size),
2901 mr->enabled ? "" : " [disabled]");
2902 if (owner) {
2903 mtree_print_mr_owner(mon_printf, f, mr);
2904 }
2905 } else {
2906 mon_printf(f,
2907 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s%s): %s%s",
2908 cur_start, cur_end,
2909 mr->priority,
2910 mr->nonvolatile ? "nv-" : "",
2911 memory_region_type((MemoryRegion *)mr),
2912 memory_region_name(mr),
2913 mr->enabled ? "" : " [disabled]");
2914 if (owner) {
2915 mtree_print_mr_owner(mon_printf, f, mr);
2916 }
2917 }
2918 mon_printf(f, "\n");
2919
2920 QTAILQ_INIT(&submr_print_queue);
2921
2922 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2923 new_ml = g_new(MemoryRegionList, 1);
2924 new_ml->mr = submr;
2925 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2926 if (new_ml->mr->addr < ml->mr->addr ||
2927 (new_ml->mr->addr == ml->mr->addr &&
2928 new_ml->mr->priority > ml->mr->priority)) {
2929 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2930 new_ml = NULL;
2931 break;
2932 }
2933 }
2934 if (new_ml) {
2935 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2936 }
2937 }
2938
2939 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2940 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2941 alias_print_queue, owner);
2942 }
2943
2944 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2945 g_free(ml);
2946 }
2947 }
2948
2949 struct FlatViewInfo {
2950 fprintf_function mon_printf;
2951 void *f;
2952 int counter;
2953 bool dispatch_tree;
2954 bool owner;
2955 };
2956
2957 static void mtree_print_flatview(gpointer key, gpointer value,
2958 gpointer user_data)
2959 {
2960 FlatView *view = key;
2961 GArray *fv_address_spaces = value;
2962 struct FlatViewInfo *fvi = user_data;
2963 fprintf_function p = fvi->mon_printf;
2964 void *f = fvi->f;
2965 FlatRange *range = &view->ranges[0];
2966 MemoryRegion *mr;
2967 int n = view->nr;
2968 int i;
2969 AddressSpace *as;
2970
2971 p(f, "FlatView #%d\n", fvi->counter);
2972 ++fvi->counter;
2973
2974 for (i = 0; i < fv_address_spaces->len; ++i) {
2975 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2976 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2977 if (as->root->alias) {
2978 p(f, ", alias %s", memory_region_name(as->root->alias));
2979 }
2980 p(f, "\n");
2981 }
2982
2983 p(f, " Root memory region: %s\n",
2984 view->root ? memory_region_name(view->root) : "(none)");
2985
2986 if (n <= 0) {
2987 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2988 return;
2989 }
2990
2991 while (n--) {
2992 mr = range->mr;
2993 if (range->offset_in_region) {
2994 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2995 TARGET_FMT_plx " (prio %d, %s%s): %s @" TARGET_FMT_plx,
2996 int128_get64(range->addr.start),
2997 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2998 mr->priority,
2999 range->nonvolatile ? "nv-" : "",
3000 range->readonly ? "rom" : memory_region_type(mr),
3001 memory_region_name(mr),
3002 range->offset_in_region);
3003 } else {
3004 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3005 TARGET_FMT_plx " (prio %d, %s%s): %s",
3006 int128_get64(range->addr.start),
3007 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3008 mr->priority,
3009 range->nonvolatile ? "nv-" : "",
3010 range->readonly ? "rom" : memory_region_type(mr),
3011 memory_region_name(mr));
3012 }
3013 if (fvi->owner) {
3014 mtree_print_mr_owner(p, f, mr);
3015 }
3016 p(f, "\n");
3017 range++;
3018 }
3019
3020 #if !defined(CONFIG_USER_ONLY)
3021 if (fvi->dispatch_tree && view->root) {
3022 mtree_print_dispatch(p, f, view->dispatch, view->root);
3023 }
3024 #endif
3025
3026 p(f, "\n");
3027 }
3028
3029 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3030 gpointer user_data)
3031 {
3032 FlatView *view = key;
3033 GArray *fv_address_spaces = value;
3034
3035 g_array_unref(fv_address_spaces);
3036 flatview_unref(view);
3037
3038 return true;
3039 }
3040
3041 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3042 bool dispatch_tree, bool owner)
3043 {
3044 MemoryRegionListHead ml_head;
3045 MemoryRegionList *ml, *ml2;
3046 AddressSpace *as;
3047
3048 if (flatview) {
3049 FlatView *view;
3050 struct FlatViewInfo fvi = {
3051 .mon_printf = mon_printf,
3052 .f = f,
3053 .counter = 0,
3054 .dispatch_tree = dispatch_tree,
3055 .owner = owner,
3056 };
3057 GArray *fv_address_spaces;
3058 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3059
3060 /* Gather all FVs in one table */
3061 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3062 view = address_space_get_flatview(as);
3063
3064 fv_address_spaces = g_hash_table_lookup(views, view);
3065 if (!fv_address_spaces) {
3066 fv_address_spaces = g_array_new(false, false, sizeof(as));
3067 g_hash_table_insert(views, view, fv_address_spaces);
3068 }
3069
3070 g_array_append_val(fv_address_spaces, as);
3071 }
3072
3073 /* Print */
3074 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3075
3076 /* Free */
3077 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3078 g_hash_table_unref(views);
3079
3080 return;
3081 }
3082
3083 QTAILQ_INIT(&ml_head);
3084
3085 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3086 mon_printf(f, "address-space: %s\n", as->name);
3087 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head, owner);
3088 mon_printf(f, "\n");
3089 }
3090
3091 /* print aliased regions */
3092 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3093 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3094 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head, owner);
3095 mon_printf(f, "\n");
3096 }
3097
3098 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3099 g_free(ml);
3100 }
3101 }
3102
3103 void memory_region_init_ram(MemoryRegion *mr,
3104 struct Object *owner,
3105 const char *name,
3106 uint64_t size,
3107 Error **errp)
3108 {
3109 DeviceState *owner_dev;
3110 Error *err = NULL;
3111
3112 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3113 if (err) {
3114 error_propagate(errp, err);
3115 return;
3116 }
3117 /* This will assert if owner is neither NULL nor a DeviceState.
3118 * We only want the owner here for the purposes of defining a
3119 * unique name for migration. TODO: Ideally we should implement
3120 * a naming scheme for Objects which are not DeviceStates, in
3121 * which case we can relax this restriction.
3122 */
3123 owner_dev = DEVICE(owner);
3124 vmstate_register_ram(mr, owner_dev);
3125 }
3126
3127 void memory_region_init_rom(MemoryRegion *mr,
3128 struct Object *owner,
3129 const char *name,
3130 uint64_t size,
3131 Error **errp)
3132 {
3133 DeviceState *owner_dev;
3134 Error *err = NULL;
3135
3136 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3137 if (err) {
3138 error_propagate(errp, err);
3139 return;
3140 }
3141 /* This will assert if owner is neither NULL nor a DeviceState.
3142 * We only want the owner here for the purposes of defining a
3143 * unique name for migration. TODO: Ideally we should implement
3144 * a naming scheme for Objects which are not DeviceStates, in
3145 * which case we can relax this restriction.
3146 */
3147 owner_dev = DEVICE(owner);
3148 vmstate_register_ram(mr, owner_dev);
3149 }
3150
3151 void memory_region_init_rom_device(MemoryRegion *mr,
3152 struct Object *owner,
3153 const MemoryRegionOps *ops,
3154 void *opaque,
3155 const char *name,
3156 uint64_t size,
3157 Error **errp)
3158 {
3159 DeviceState *owner_dev;
3160 Error *err = NULL;
3161
3162 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3163 name, size, &err);
3164 if (err) {
3165 error_propagate(errp, err);
3166 return;
3167 }
3168 /* This will assert if owner is neither NULL nor a DeviceState.
3169 * We only want the owner here for the purposes of defining a
3170 * unique name for migration. TODO: Ideally we should implement
3171 * a naming scheme for Objects which are not DeviceStates, in
3172 * which case we can relax this restriction.
3173 */
3174 owner_dev = DEVICE(owner);
3175 vmstate_register_ram(mr, owner_dev);
3176 }
3177
3178 static const TypeInfo memory_region_info = {
3179 .parent = TYPE_OBJECT,
3180 .name = TYPE_MEMORY_REGION,
3181 .instance_size = sizeof(MemoryRegion),
3182 .instance_init = memory_region_initfn,
3183 .instance_finalize = memory_region_finalize,
3184 };
3185
3186 static const TypeInfo iommu_memory_region_info = {
3187 .parent = TYPE_MEMORY_REGION,
3188 .name = TYPE_IOMMU_MEMORY_REGION,
3189 .class_size = sizeof(IOMMUMemoryRegionClass),
3190 .instance_size = sizeof(IOMMUMemoryRegion),
3191 .instance_init = iommu_memory_region_initfn,
3192 .abstract = true,
3193 };
3194
3195 static void memory_register_types(void)
3196 {
3197 type_register_static(&memory_region_info);
3198 type_register_static(&iommu_memory_region_info);
3199 }
3200
3201 type_init(memory_register_types)
AR7 emulation for QEMU