2 * QEMU MIPS Jazz support
4 * Copyright (c) 2007-2008 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
29 #include "hw/mips/mips.h"
30 #include "hw/mips/cpudevs.h"
31 #include "hw/intc/i8259.h"
32 #include "hw/dma/i8257.h"
33 #include "hw/char/serial.h"
34 #include "hw/char/parallel.h"
35 #include "hw/isa/isa.h"
36 #include "hw/block/fdc.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/boards.h"
40 #include "hw/scsi/esp.h"
41 #include "hw/mips/bios.h"
42 #include "hw/loader.h"
43 #include "hw/rtc/mc146818rtc.h"
44 #include "hw/timer/i8254.h"
45 #include "hw/display/vga.h"
46 #include "hw/audio/pcspk.h"
47 #include "hw/input/i8042.h"
48 #include "hw/sysbus.h"
49 #include "sysemu/qtest.h"
50 #include "sysemu/reset.h"
51 #include "qapi/error.h"
52 #include "qemu/error-report.h"
53 #include "qemu/help_option.h"
55 #include "hw/core/tcg-cpu-ops.h"
56 #endif /* CONFIG_TCG */
63 static void main_cpu_reset(void *opaque
)
65 MIPSCPU
*cpu
= opaque
;
70 static uint64_t rtc_read(void *opaque
, hwaddr addr
, unsigned size
)
73 address_space_read(&address_space_memory
, 0x90000071,
74 MEMTXATTRS_UNSPECIFIED
, &val
, 1);
78 static void rtc_write(void *opaque
, hwaddr addr
,
79 uint64_t val
, unsigned size
)
81 uint8_t buf
= val
& 0xff;
82 address_space_write(&address_space_memory
, 0x90000071,
83 MEMTXATTRS_UNSPECIFIED
, &buf
, 1);
86 static const MemoryRegionOps rtc_ops
= {
89 .endianness
= DEVICE_NATIVE_ENDIAN
,
92 static uint64_t dma_dummy_read(void *opaque
, hwaddr addr
,
96 * Nothing to do. That is only to ensure that
97 * the current DMA acknowledge cycle is completed.
102 static void dma_dummy_write(void *opaque
, hwaddr addr
,
103 uint64_t val
, unsigned size
)
106 * Nothing to do. That is only to ensure that
107 * the current DMA acknowledge cycle is completed.
111 static const MemoryRegionOps dma_dummy_ops
= {
112 .read
= dma_dummy_read
,
113 .write
= dma_dummy_write
,
114 .endianness
= DEVICE_NATIVE_ENDIAN
,
117 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
118 #define MAGNUM_BIOS_SIZE \
119 (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
121 #define SONIC_PROM_SIZE 0x1000
123 static void mips_jazz_init(MachineState
*machine
,
124 enum jazz_model_e jazz_model
)
126 MemoryRegion
*address_space
= get_system_memory();
128 int bios_size
, n
, big_endian
;
135 IOMMUMemoryRegion
*rc4030_dma_mr
;
136 MemoryRegion
*isa_mem
= g_new(MemoryRegion
, 1);
137 MemoryRegion
*isa_io
= g_new(MemoryRegion
, 1);
138 MemoryRegion
*rtc
= g_new(MemoryRegion
, 1);
139 MemoryRegion
*i8042
= g_new(MemoryRegion
, 1);
140 MemoryRegion
*dma_dummy
= g_new(MemoryRegion
, 1);
141 MemoryRegion
*dp8393x_prom
= g_new(MemoryRegion
, 1);
143 DeviceState
*dev
, *rc4030
;
144 SysBusDevice
*sysbus
;
147 DriveInfo
*fds
[MAX_FD
];
148 MemoryRegion
*bios
= g_new(MemoryRegion
, 1);
149 MemoryRegion
*bios2
= g_new(MemoryRegion
, 1);
150 SysBusESPState
*sysbus_esp
;
152 static const struct {
156 [JAZZ_MAGNUM
] = {50000000, 2},
157 [JAZZ_PICA61
] = {33333333, 4},
160 #ifdef TARGET_WORDS_BIGENDIAN
166 if (machine
->ram_size
> 256 * MiB
) {
167 error_report("RAM size more than 256Mb is not supported");
171 cpuclk
= clock_new(OBJECT(machine
), "cpu-refclk");
172 clock_set_hz(cpuclk
, ext_clk
[jazz_model
].freq_hz
173 * ext_clk
[jazz_model
].pll_mult
);
176 cpu
= mips_cpu_create_with_clock(machine
->cpu_type
, cpuclk
);
178 qemu_register_reset(main_cpu_reset
, cpu
);
181 * Chipset returns 0 in invalid reads and do not raise data exceptions.
182 * However, we can't simply add a global memory region to catch
183 * everything, as this would make all accesses including instruction
184 * accesses be ignored and not raise exceptions.
186 * NOTE: this behaviour of raising exceptions for bad instruction
187 * fetches but not bad data accesses was added in commit 54e755588cf1e9
188 * to restore behaviour broken by c658b94f6e8c206, but it is not clear
189 * whether the real hardware behaves this way. It is possible that
190 * real hardware ignores bad instruction fetches as well -- if so then
191 * we could replace this hijacking of CPU methods with a simple global
192 * memory region that catches all memory accesses, as we do on Malta.
194 mcc
= MIPS_CPU_GET_CLASS(cpu
);
195 mcc
->no_data_aborts
= true;
198 memory_region_add_subregion(address_space
, 0, machine
->ram
);
200 memory_region_init_rom(bios
, NULL
, "mips_jazz.bios", MAGNUM_BIOS_SIZE
,
202 memory_region_init_alias(bios2
, NULL
, "mips_jazz.bios", bios
,
203 0, MAGNUM_BIOS_SIZE
);
204 memory_region_add_subregion(address_space
, 0x1fc00000LL
, bios
);
205 memory_region_add_subregion(address_space
, 0xfff00000LL
, bios2
);
207 /* load the BIOS image. */
208 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, machine
->firmware
?: BIOS_FILENAME
);
210 bios_size
= load_image_targphys(filename
, 0xfff00000LL
,
216 if ((bios_size
< 0 || bios_size
> MAGNUM_BIOS_SIZE
)
217 && machine
->firmware
&& !qtest_enabled()) {
218 error_report("Could not load MIPS bios '%s'", machine
->firmware
);
222 /* Init CPU internal devices */
223 cpu_mips_irq_init_cpu(cpu
);
224 cpu_mips_clock_init(cpu
);
227 rc4030
= rc4030_init(&dmas
, &rc4030_dma_mr
);
228 sysbus
= SYS_BUS_DEVICE(rc4030
);
229 sysbus_connect_irq(sysbus
, 0, env
->irq
[6]);
230 sysbus_connect_irq(sysbus
, 1, env
->irq
[3]);
231 memory_region_add_subregion(address_space
, 0x80000000,
232 sysbus_mmio_get_region(sysbus
, 0));
233 memory_region_add_subregion(address_space
, 0xf0000000,
234 sysbus_mmio_get_region(sysbus
, 1));
235 memory_region_init_io(dma_dummy
, NULL
, &dma_dummy_ops
,
236 NULL
, "dummy_dma", 0x1000);
237 memory_region_add_subregion(address_space
, 0x8000d000, dma_dummy
);
239 memory_region_init_rom(dp8393x_prom
, NULL
, "dp8393x-jazz.prom",
240 SONIC_PROM_SIZE
, &error_fatal
);
241 memory_region_add_subregion(address_space
, 0x8000b000, dp8393x_prom
);
243 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
244 memory_region_init(isa_io
, NULL
, "isa-io", 0x00010000);
245 memory_region_init(isa_mem
, NULL
, "isa-mem", 0x01000000);
246 memory_region_add_subregion(address_space
, 0x90000000, isa_io
);
247 memory_region_add_subregion(address_space
, 0x91000000, isa_mem
);
248 isa_bus
= isa_bus_new(NULL
, isa_mem
, isa_io
, &error_abort
);
251 i8259
= i8259_init(isa_bus
, env
->irq
[4]);
252 isa_bus_irqs(isa_bus
, i8259
);
253 i8257_dma_init(isa_bus
, 0);
254 pit
= i8254_pit_init(isa_bus
, 0x40, 0, NULL
);
255 pcspk_init(isa_new(TYPE_PC_SPEAKER
), isa_bus
, pit
);
258 switch (jazz_model
) {
260 dev
= qdev_new("sysbus-g364");
261 sysbus
= SYS_BUS_DEVICE(dev
);
262 sysbus_realize_and_unref(sysbus
, &error_fatal
);
263 sysbus_mmio_map(sysbus
, 0, 0x60080000);
264 sysbus_mmio_map(sysbus
, 1, 0x40000000);
265 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(rc4030
, 3));
267 /* Simple ROM, so user doesn't have to provide one */
268 MemoryRegion
*rom_mr
= g_new(MemoryRegion
, 1);
269 memory_region_init_rom(rom_mr
, NULL
, "g364fb.rom", 0x80000,
271 uint8_t *rom
= memory_region_get_ram_ptr(rom_mr
);
272 memory_region_add_subregion(address_space
, 0x60000000, rom_mr
);
273 rom
[0] = 0x10; /* Mips G364 */
277 vga_mmio_init(0x40000000, 0x60000000, 0, get_system_memory());
283 /* Network controller */
284 for (n
= 0; n
< nb_nics
; n
++) {
287 nd
->model
= g_strdup("dp83932");
289 if (strcmp(nd
->model
, "dp83932") == 0) {
293 qemu_check_nic_model(nd
, "dp83932");
295 dev
= qdev_new("dp8393x");
296 qdev_set_nic_properties(dev
, nd
);
297 qdev_prop_set_uint8(dev
, "it_shift", 2);
298 qdev_prop_set_bit(dev
, "big_endian", big_endian
> 0);
299 object_property_set_link(OBJECT(dev
), "dma_mr",
300 OBJECT(rc4030_dma_mr
), &error_abort
);
301 sysbus
= SYS_BUS_DEVICE(dev
);
302 sysbus_realize_and_unref(sysbus
, &error_fatal
);
303 sysbus_mmio_map(sysbus
, 0, 0x80001000);
304 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(rc4030
, 4));
306 /* Add MAC address with valid checksum to PROM */
307 prom
= memory_region_get_ram_ptr(dp8393x_prom
);
309 for (i
= 0; i
< 6; i
++) {
310 prom
[i
] = nd
->macaddr
.a
[i
];
312 if (checksum
> 0xff) {
313 checksum
= (checksum
+ 1) & 0xff;
316 prom
[7] = 0xff - checksum
;
318 } else if (is_help_option(nd
->model
)) {
319 error_report("Supported NICs: dp83932");
322 error_report("Unsupported NIC: %s", nd
->model
);
328 dev
= qdev_new(TYPE_SYSBUS_ESP
);
329 sysbus_esp
= SYSBUS_ESP(dev
);
330 esp
= &sysbus_esp
->esp
;
331 esp
->dma_memory_read
= rc4030_dma_read
;
332 esp
->dma_memory_write
= rc4030_dma_write
;
333 esp
->dma_opaque
= dmas
[0];
334 sysbus_esp
->it_shift
= 0;
335 /* XXX for now until rc4030 has been changed to use DMA enable signal */
336 esp
->dma_enabled
= 1;
338 sysbus
= SYS_BUS_DEVICE(dev
);
339 sysbus_realize_and_unref(sysbus
, &error_fatal
);
340 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(rc4030
, 5));
341 sysbus_mmio_map(sysbus
, 0, 0x80002000);
343 scsi_bus_legacy_handle_cmdline(&esp
->bus
);
346 for (n
= 0; n
< MAX_FD
; n
++) {
347 fds
[n
] = drive_get(IF_FLOPPY
, 0, n
);
349 /* FIXME: we should enable DMA with a custom IsaDma device */
350 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030
, 1), -1, 0x80003000, fds
);
352 /* Real time clock */
353 mc146818_rtc_init(isa_bus
, 1980, NULL
);
354 memory_region_init_io(rtc
, NULL
, &rtc_ops
, NULL
, "rtc", 0x1000);
355 memory_region_add_subregion(address_space
, 0x80004000, rtc
);
357 /* Keyboard (i8042) */
358 i8042_mm_init(qdev_get_gpio_in(rc4030
, 6), qdev_get_gpio_in(rc4030
, 7),
360 memory_region_add_subregion(address_space
, 0x80005000, i8042
);
363 serial_mm_init(address_space
, 0x80006000, 0,
364 qdev_get_gpio_in(rc4030
, 8), 8000000 / 16,
365 serial_hd(0), DEVICE_NATIVE_ENDIAN
);
366 serial_mm_init(address_space
, 0x80007000, 0,
367 qdev_get_gpio_in(rc4030
, 9), 8000000 / 16,
368 serial_hd(1), DEVICE_NATIVE_ENDIAN
);
372 parallel_mm_init(address_space
, 0x80008000, 0,
373 qdev_get_gpio_in(rc4030
, 0), parallel_hds
[0]);
375 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
378 dev
= qdev_new("ds1225y");
379 sysbus
= SYS_BUS_DEVICE(dev
);
380 sysbus_realize_and_unref(sysbus
, &error_fatal
);
381 sysbus_mmio_map(sysbus
, 0, 0x80009000);
384 sysbus_create_simple("jazz-led", 0x8000f000, NULL
);
390 void mips_magnum_init(MachineState
*machine
)
392 mips_jazz_init(machine
, JAZZ_MAGNUM
);
396 void mips_pica61_init(MachineState
*machine
)
398 mips_jazz_init(machine
, JAZZ_PICA61
);
401 static void mips_magnum_class_init(ObjectClass
*oc
, void *data
)
403 MachineClass
*mc
= MACHINE_CLASS(oc
);
405 mc
->desc
= "MIPS Magnum";
406 mc
->init
= mips_magnum_init
;
407 mc
->block_default_type
= IF_SCSI
;
408 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("R4000");
409 mc
->default_ram_id
= "mips_jazz.ram";
412 static const TypeInfo mips_magnum_type
= {
413 .name
= MACHINE_TYPE_NAME("magnum"),
414 .parent
= TYPE_MACHINE
,
415 .class_init
= mips_magnum_class_init
,
418 static void mips_pica61_class_init(ObjectClass
*oc
, void *data
)
420 MachineClass
*mc
= MACHINE_CLASS(oc
);
422 mc
->desc
= "Acer Pica 61";
423 mc
->init
= mips_pica61_init
;
424 mc
->block_default_type
= IF_SCSI
;
425 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("R4000");
426 mc
->default_ram_id
= "mips_jazz.ram";
429 static const TypeInfo mips_pica61_type
= {
430 .name
= MACHINE_TYPE_NAME("pica61"),
431 .parent
= TYPE_MACHINE
,
432 .class_init
= mips_pica61_class_init
,
435 static void mips_jazz_machine_init(void)
437 type_register_static(&mips_magnum_type
);
438 type_register_static(&mips_pica61_type
);
441 type_init(mips_jazz_machine_init
)