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hw/usb: Constify VMState
[qemu/ar7.git] / hw / usb / hcd-uhci.c
blob7d3c026daeda374420e7a39f0d57854c2d443928
1 /*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28
29 #include "qemu/osdep.h"
30 #include "hw/usb.h"
31 #include "hw/usb/uhci-regs.h"
32 #include "migration/vmstate.h"
33 #include "hw/pci/pci.h"
34 #include "hw/irq.h"
35 #include "hw/qdev-properties.h"
36 #include "qapi/error.h"
37 #include "qemu/timer.h"
38 #include "qemu/iov.h"
39 #include "sysemu/dma.h"
40 #include "trace.h"
41 #include "qemu/main-loop.h"
42 #include "qemu/module.h"
43 #include "qom/object.h"
44 #include "hcd-uhci.h"
45
46 #define FRAME_TIMER_FREQ 1000
47
48 #define FRAME_MAX_LOOPS 256
49
50 /* Must be large enough to handle 10 frame delay for initial isoc requests */
51 #define QH_VALID 32
52
53 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
54
55 enum {
56 TD_RESULT_STOP_FRAME = 10,
57 TD_RESULT_COMPLETE,
58 TD_RESULT_NEXT_QH,
59 TD_RESULT_ASYNC_START,
60 TD_RESULT_ASYNC_CONT,
61 };
62
63 typedef struct UHCIAsync UHCIAsync;
64
65 struct UHCIPCIDeviceClass {
66 PCIDeviceClass parent_class;
67 UHCIInfo info;
68 };
69
70 /*
71 * Pending async transaction.
72 * 'packet' must be the first field because completion
73 * handler does "(UHCIAsync *) pkt" cast.
74 */
75
76 struct UHCIAsync {
77 USBPacket packet;
78 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */
79 uint8_t *buf;
80 UHCIQueue *queue;
81 QTAILQ_ENTRY(UHCIAsync) next;
82 uint32_t td_addr;
83 uint8_t done;
84 };
85
86 struct UHCIQueue {
87 uint32_t qh_addr;
88 uint32_t token;
89 UHCIState *uhci;
90 USBEndpoint *ep;
91 QTAILQ_ENTRY(UHCIQueue) next;
92 QTAILQ_HEAD(, UHCIAsync) asyncs;
93 int8_t valid;
94 };
95
96 typedef struct UHCI_TD {
97 uint32_t link;
98 uint32_t ctrl; /* see TD_CTRL_xxx */
99 uint32_t token;
100 uint32_t buffer;
101 } UHCI_TD;
102
103 typedef struct UHCI_QH {
104 uint32_t link;
105 uint32_t el_link;
106 } UHCI_QH;
107
108 static void uhci_async_cancel(UHCIAsync *async);
109 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
110 static void uhci_resume(void *opaque);
111
112 static inline int32_t uhci_queue_token(UHCI_TD *td)
113 {
114 if ((td->token & (0xf << 15)) == 0) {
115 /* ctrl ep, cover ep and dev, not pid! */
116 return td->token & 0x7ff00;
117 } else {
118 /* covers ep, dev, pid -> identifies the endpoint */
119 return td->token & 0x7ffff;
120 }
121 }
122
123 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
124 USBEndpoint *ep)
125 {
126 UHCIQueue *queue;
127
128 queue = g_new0(UHCIQueue, 1);
129 queue->uhci = s;
130 queue->qh_addr = qh_addr;
131 queue->token = uhci_queue_token(td);
132 queue->ep = ep;
133 QTAILQ_INIT(&queue->asyncs);
134 QTAILQ_INSERT_HEAD(&s->queues, queue, next);
135 queue->valid = QH_VALID;
136 trace_usb_uhci_queue_add(queue->token);
137 return queue;
138 }
139
140 static void uhci_queue_free(UHCIQueue *queue, const char *reason)
141 {
142 UHCIState *s = queue->uhci;
143 UHCIAsync *async;
144
145 while (!QTAILQ_EMPTY(&queue->asyncs)) {
146 async = QTAILQ_FIRST(&queue->asyncs);
147 uhci_async_cancel(async);
148 }
149 usb_device_ep_stopped(queue->ep->dev, queue->ep);
150
151 trace_usb_uhci_queue_del(queue->token, reason);
152 QTAILQ_REMOVE(&s->queues, queue, next);
153 g_free(queue);
154 }
155
156 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
157 {
158 uint32_t token = uhci_queue_token(td);
159 UHCIQueue *queue;
160
161 QTAILQ_FOREACH(queue, &s->queues, next) {
162 if (queue->token == token) {
163 return queue;
164 }
165 }
166 return NULL;
167 }
168
169 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
170 uint32_t td_addr, bool queuing)
171 {
172 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
173 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f;
174
175 return queue->qh_addr == qh_addr &&
176 queue->token == uhci_queue_token(td) &&
177 queue_token_addr == queue->ep->dev->addr &&
178 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
179 first->td_addr == td_addr);
180 }
181
182 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
183 {
184 UHCIAsync *async = g_new0(UHCIAsync, 1);
185
186 async->queue = queue;
187 async->td_addr = td_addr;
188 usb_packet_init(&async->packet);
189 trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
190
191 return async;
192 }
193
194 static void uhci_async_free(UHCIAsync *async)
195 {
196 trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
197 usb_packet_cleanup(&async->packet);
198 if (async->buf != async->static_buf) {
199 g_free(async->buf);
200 }
201 g_free(async);
202 }
203
204 static void uhci_async_link(UHCIAsync *async)
205 {
206 UHCIQueue *queue = async->queue;
207 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
208 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
209 }
210
211 static void uhci_async_unlink(UHCIAsync *async)
212 {
213 UHCIQueue *queue = async->queue;
214 QTAILQ_REMOVE(&queue->asyncs, async, next);
215 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
216 }
217
218 static void uhci_async_cancel(UHCIAsync *async)
219 {
220 uhci_async_unlink(async);
221 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
222 async->done);
223 if (!async->done)
224 usb_cancel_packet(&async->packet);
225 uhci_async_free(async);
226 }
227
228 /*
229 * Mark all outstanding async packets as invalid.
230 * This is used for canceling them when TDs are removed by the HCD.
231 */
232 static void uhci_async_validate_begin(UHCIState *s)
233 {
234 UHCIQueue *queue;
235
236 QTAILQ_FOREACH(queue, &s->queues, next) {
237 queue->valid--;
238 }
239 }
240
241 /*
242 * Cancel async packets that are no longer valid
243 */
244 static void uhci_async_validate_end(UHCIState *s)
245 {
246 UHCIQueue *queue, *n;
247
248 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
249 if (!queue->valid) {
250 uhci_queue_free(queue, "validate-end");
251 }
252 }
253 }
254
255 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
256 {
257 UHCIQueue *queue, *n;
258
259 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
260 if (queue->ep->dev == dev) {
261 uhci_queue_free(queue, "cancel-device");
262 }
263 }
264 }
265
266 static void uhci_async_cancel_all(UHCIState *s)
267 {
268 UHCIQueue *queue, *nq;
269
270 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
271 uhci_queue_free(queue, "cancel-all");
272 }
273 }
274
275 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
276 {
277 UHCIQueue *queue;
278 UHCIAsync *async;
279
280 QTAILQ_FOREACH(queue, &s->queues, next) {
281 QTAILQ_FOREACH(async, &queue->asyncs, next) {
282 if (async->td_addr == td_addr) {
283 return async;
284 }
285 }
286 }
287 return NULL;
288 }
289
290 static void uhci_update_irq(UHCIState *s)
291 {
292 int level = 0;
293 if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
294 ((s->status2 & 2) && (s->intr & (1 << 3))) ||
295 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
296 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
297 (s->status & UHCI_STS_HSERR) ||
298 (s->status & UHCI_STS_HCPERR)) {
299 level = 1;
300 }
301 qemu_set_irq(s->irq, level);
302 }
303
304 static void uhci_reset(DeviceState *dev)
305 {
306 PCIDevice *d = PCI_DEVICE(dev);
307 UHCIState *s = UHCI(d);
308 uint8_t *pci_conf;
309 int i;
310 UHCIPort *port;
311
312 trace_usb_uhci_reset();
313
314 pci_conf = s->dev.config;
315
316 pci_conf[0x6a] = 0x01; /* usb clock */
317 pci_conf[0x6b] = 0x00;
318 s->cmd = 0;
319 s->status = UHCI_STS_HCHALTED;
320 s->status2 = 0;
321 s->intr = 0;
322 s->fl_base_addr = 0;
323 s->sof_timing = 64;
324
325 for(i = 0; i < NB_PORTS; i++) {
326 port = &s->ports[i];
327 port->ctrl = 0x0080;
328 if (port->port.dev && port->port.dev->attached) {
329 usb_port_reset(&port->port);
330 }
331 }
332
333 uhci_async_cancel_all(s);
334 qemu_bh_cancel(s->bh);
335 uhci_update_irq(s);
336 }
337
338 static const VMStateDescription vmstate_uhci_port = {
339 .name = "uhci port",
340 .version_id = 1,
341 .minimum_version_id = 1,
342 .fields = (const VMStateField[]) {
343 VMSTATE_UINT16(ctrl, UHCIPort),
344 VMSTATE_END_OF_LIST()
345 }
346 };
347
348 static int uhci_post_load(void *opaque, int version_id)
349 {
350 UHCIState *s = opaque;
351
352 if (version_id < 2) {
353 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
354 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
355 }
356 return 0;
357 }
358
359 static const VMStateDescription vmstate_uhci = {
360 .name = "uhci",
361 .version_id = 3,
362 .minimum_version_id = 1,
363 .post_load = uhci_post_load,
364 .fields = (const VMStateField[]) {
365 VMSTATE_PCI_DEVICE(dev, UHCIState),
366 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL),
367 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
368 vmstate_uhci_port, UHCIPort),
369 VMSTATE_UINT16(cmd, UHCIState),
370 VMSTATE_UINT16(status, UHCIState),
371 VMSTATE_UINT16(intr, UHCIState),
372 VMSTATE_UINT16(frnum, UHCIState),
373 VMSTATE_UINT32(fl_base_addr, UHCIState),
374 VMSTATE_UINT8(sof_timing, UHCIState),
375 VMSTATE_UINT8(status2, UHCIState),
376 VMSTATE_TIMER_PTR(frame_timer, UHCIState),
377 VMSTATE_INT64_V(expire_time, UHCIState, 2),
378 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3),
379 VMSTATE_END_OF_LIST()
380 }
381 };
382
383 static void uhci_port_write(void *opaque, hwaddr addr,
384 uint64_t val, unsigned size)
385 {
386 UHCIState *s = opaque;
387
388 trace_usb_uhci_mmio_writew(addr, val);
389
390 switch(addr) {
391 case 0x00:
392 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
393 /* start frame processing */
394 trace_usb_uhci_schedule_start();
395 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
396 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
397 timer_mod(s->frame_timer, s->expire_time);
398 s->status &= ~UHCI_STS_HCHALTED;
399 } else if (!(val & UHCI_CMD_RS)) {
400 s->status |= UHCI_STS_HCHALTED;
401 }
402 if (val & UHCI_CMD_GRESET) {
403 UHCIPort *port;
404 int i;
405
406 /* send reset on the USB bus */
407 for(i = 0; i < NB_PORTS; i++) {
408 port = &s->ports[i];
409 usb_device_reset(port->port.dev);
410 }
411 uhci_reset(DEVICE(s));
412 return;
413 }
414 if (val & UHCI_CMD_HCRESET) {
415 uhci_reset(DEVICE(s));
416 return;
417 }
418 s->cmd = val;
419 if (val & UHCI_CMD_EGSM) {
420 if ((s->ports[0].ctrl & UHCI_PORT_RD) ||
421 (s->ports[1].ctrl & UHCI_PORT_RD)) {
422 uhci_resume(s);
423 }
424 }
425 break;
426 case 0x02:
427 s->status &= ~val;
428 /* XXX: the chip spec is not coherent, so we add a hidden
429 register to distinguish between IOC and SPD */
430 if (val & UHCI_STS_USBINT)
431 s->status2 = 0;
432 uhci_update_irq(s);
433 break;
434 case 0x04:
435 s->intr = val;
436 uhci_update_irq(s);
437 break;
438 case 0x06:
439 if (s->status & UHCI_STS_HCHALTED)
440 s->frnum = val & 0x7ff;
441 break;
442 case 0x08:
443 s->fl_base_addr &= 0xffff0000;
444 s->fl_base_addr |= val & ~0xfff;
445 break;
446 case 0x0a:
447 s->fl_base_addr &= 0x0000ffff;
448 s->fl_base_addr |= (val << 16);
449 break;
450 case 0x0c:
451 s->sof_timing = val & 0xff;
452 break;
453 case 0x10 ... 0x1f:
454 {
455 UHCIPort *port;
456 USBDevice *dev;
457 int n;
458
459 n = (addr >> 1) & 7;
460 if (n >= NB_PORTS)
461 return;
462 port = &s->ports[n];
463 dev = port->port.dev;
464 if (dev && dev->attached) {
465 /* port reset */
466 if ( (val & UHCI_PORT_RESET) &&
467 !(port->ctrl & UHCI_PORT_RESET) ) {
468 usb_device_reset(dev);
469 }
470 }
471 port->ctrl &= UHCI_PORT_READ_ONLY;
472 /* enabled may only be set if a device is connected */
473 if (!(port->ctrl & UHCI_PORT_CCS)) {
474 val &= ~UHCI_PORT_EN;
475 }
476 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
477 /* some bits are reset when a '1' is written to them */
478 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
479 }
480 break;
481 }
482 }
483
484 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
485 {
486 UHCIState *s = opaque;
487 uint32_t val;
488
489 switch(addr) {
490 case 0x00:
491 val = s->cmd;
492 break;
493 case 0x02:
494 val = s->status;
495 break;
496 case 0x04:
497 val = s->intr;
498 break;
499 case 0x06:
500 val = s->frnum;
501 break;
502 case 0x08:
503 val = s->fl_base_addr & 0xffff;
504 break;
505 case 0x0a:
506 val = (s->fl_base_addr >> 16) & 0xffff;
507 break;
508 case 0x0c:
509 val = s->sof_timing;
510 break;
511 case 0x10 ... 0x1f:
512 {
513 UHCIPort *port;
514 int n;
515 n = (addr >> 1) & 7;
516 if (n >= NB_PORTS)
517 goto read_default;
518 port = &s->ports[n];
519 val = port->ctrl;
520 }
521 break;
522 default:
523 read_default:
524 val = 0xff7f; /* disabled port */
525 break;
526 }
527
528 trace_usb_uhci_mmio_readw(addr, val);
529
530 return val;
531 }
532
533 /* signal resume if controller suspended */
534 static void uhci_resume (void *opaque)
535 {
536 UHCIState *s = (UHCIState *)opaque;
537
538 if (!s)
539 return;
540
541 if (s->cmd & UHCI_CMD_EGSM) {
542 s->cmd |= UHCI_CMD_FGR;
543 s->status |= UHCI_STS_RD;
544 uhci_update_irq(s);
545 }
546 }
547
548 static void uhci_attach(USBPort *port1)
549 {
550 UHCIState *s = port1->opaque;
551 UHCIPort *port = &s->ports[port1->index];
552
553 /* set connect status */
554 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
555
556 /* update speed */
557 if (port->port.dev->speed == USB_SPEED_LOW) {
558 port->ctrl |= UHCI_PORT_LSDA;
559 } else {
560 port->ctrl &= ~UHCI_PORT_LSDA;
561 }
562
563 uhci_resume(s);
564 }
565
566 static void uhci_detach(USBPort *port1)
567 {
568 UHCIState *s = port1->opaque;
569 UHCIPort *port = &s->ports[port1->index];
570
571 uhci_async_cancel_device(s, port1->dev);
572
573 /* set connect status */
574 if (port->ctrl & UHCI_PORT_CCS) {
575 port->ctrl &= ~UHCI_PORT_CCS;
576 port->ctrl |= UHCI_PORT_CSC;
577 }
578 /* disable port */
579 if (port->ctrl & UHCI_PORT_EN) {
580 port->ctrl &= ~UHCI_PORT_EN;
581 port->ctrl |= UHCI_PORT_ENC;
582 }
583
584 uhci_resume(s);
585 }
586
587 static void uhci_child_detach(USBPort *port1, USBDevice *child)
588 {
589 UHCIState *s = port1->opaque;
590
591 uhci_async_cancel_device(s, child);
592 }
593
594 static void uhci_wakeup(USBPort *port1)
595 {
596 UHCIState *s = port1->opaque;
597 UHCIPort *port = &s->ports[port1->index];
598
599 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
600 port->ctrl |= UHCI_PORT_RD;
601 uhci_resume(s);
602 }
603 }
604
605 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
606 {
607 USBDevice *dev;
608 int i;
609
610 for (i = 0; i < NB_PORTS; i++) {
611 UHCIPort *port = &s->ports[i];
612 if (!(port->ctrl & UHCI_PORT_EN)) {
613 continue;
614 }
615 dev = usb_find_device(&port->port, addr);
616 if (dev != NULL) {
617 return dev;
618 }
619 }
620 return NULL;
621 }
622
623 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
624 {
625 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
626 le32_to_cpus(&td->link);
627 le32_to_cpus(&td->ctrl);
628 le32_to_cpus(&td->token);
629 le32_to_cpus(&td->buffer);
630 }
631
632 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
633 int status, uint32_t *int_mask)
634 {
635 uint32_t queue_token = uhci_queue_token(td);
636 int ret;
637
638 switch (status) {
639 case USB_RET_NAK:
640 td->ctrl |= TD_CTRL_NAK;
641 return TD_RESULT_NEXT_QH;
642
643 case USB_RET_STALL:
644 td->ctrl |= TD_CTRL_STALL;
645 trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
646 ret = TD_RESULT_NEXT_QH;
647 break;
648
649 case USB_RET_BABBLE:
650 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
651 /* frame interrupted */
652 trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
653 ret = TD_RESULT_STOP_FRAME;
654 break;
655
656 case USB_RET_IOERROR:
657 case USB_RET_NODEV:
658 default:
659 td->ctrl |= TD_CTRL_TIMEOUT;
660 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
661 trace_usb_uhci_packet_complete_error(queue_token, td_addr);
662 ret = TD_RESULT_NEXT_QH;
663 break;
664 }
665
666 td->ctrl &= ~TD_CTRL_ACTIVE;
667 s->status |= UHCI_STS_USBERR;
668 if (td->ctrl & TD_CTRL_IOC) {
669 *int_mask |= 0x01;
670 }
671 uhci_update_irq(s);
672 return ret;
673 }
674
675 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
676 {
677 int len = 0, max_len;
678 uint8_t pid;
679
680 max_len = ((td->token >> 21) + 1) & 0x7ff;
681 pid = td->token & 0xff;
682
683 if (td->ctrl & TD_CTRL_IOS)
684 td->ctrl &= ~TD_CTRL_ACTIVE;
685
686 if (async->packet.status != USB_RET_SUCCESS) {
687 return uhci_handle_td_error(s, td, async->td_addr,
688 async->packet.status, int_mask);
689 }
690
691 len = async->packet.actual_length;
692 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
693
694 /* The NAK bit may have been set by a previous frame, so clear it
695 here. The docs are somewhat unclear, but win2k relies on this
696 behavior. */
697 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
698 if (td->ctrl & TD_CTRL_IOC)
699 *int_mask |= 0x01;
700
701 if (pid == USB_TOKEN_IN) {
702 pci_dma_write(&s->dev, td->buffer, async->buf, len);
703 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
704 *int_mask |= 0x02;
705 /* short packet: do not update QH */
706 trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
707 async->td_addr);
708 return TD_RESULT_NEXT_QH;
709 }
710 }
711
712 /* success */
713 trace_usb_uhci_packet_complete_success(async->queue->token,
714 async->td_addr);
715 return TD_RESULT_COMPLETE;
716 }
717
718 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
719 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
720 {
721 int ret, max_len;
722 bool spd;
723 bool queuing = (q != NULL);
724 uint8_t pid = td->token & 0xff;
725 UHCIAsync *async;
726
727 async = uhci_async_find_td(s, td_addr);
728 if (async) {
729 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
730 assert(q == NULL || q == async->queue);
731 q = async->queue;
732 } else {
733 uhci_queue_free(async->queue, "guest re-used pending td");
734 async = NULL;
735 }
736 }
737
738 if (q == NULL) {
739 q = uhci_queue_find(s, td);
740 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
741 uhci_queue_free(q, "guest re-used qh");
742 q = NULL;
743 }
744 }
745
746 if (q) {
747 q->valid = QH_VALID;
748 }
749
750 /* Is active ? */
751 if (!(td->ctrl & TD_CTRL_ACTIVE)) {
752 if (async) {
753 /* Guest marked a pending td non-active, cancel the queue */
754 uhci_queue_free(async->queue, "pending td non-active");
755 }
756 /*
757 * ehci11d spec page 22: "Even if the Active bit in the TD is already
758 * cleared when the TD is fetched ... an IOC interrupt is generated"
759 */
760 if (td->ctrl & TD_CTRL_IOC) {
761 *int_mask |= 0x01;
762 }
763 return TD_RESULT_NEXT_QH;
764 }
765
766 switch (pid) {
767 case USB_TOKEN_OUT:
768 case USB_TOKEN_SETUP:
769 case USB_TOKEN_IN:
770 break;
771 default:
772 /* invalid pid : frame interrupted */
773 s->status |= UHCI_STS_HCPERR;
774 s->cmd &= ~UHCI_CMD_RS;
775 uhci_update_irq(s);
776 return TD_RESULT_STOP_FRAME;
777 }
778
779 if (async) {
780 if (queuing) {
781 /* we are busy filling the queue, we are not prepared
782 to consume completed packages then, just leave them
783 in async state */
784 return TD_RESULT_ASYNC_CONT;
785 }
786 if (!async->done) {
787 UHCI_TD last_td;
788 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs);
789 /*
790 * While we are waiting for the current td to complete, the guest
791 * may have added more tds to the queue. Note we re-read the td
792 * rather then caching it, as we want to see guest made changes!
793 */
794 uhci_read_td(s, &last_td, last->td_addr);
795 uhci_queue_fill(async->queue, &last_td);
796
797 return TD_RESULT_ASYNC_CONT;
798 }
799 uhci_async_unlink(async);
800 goto done;
801 }
802
803 if (s->completions_only) {
804 return TD_RESULT_ASYNC_CONT;
805 }
806
807 /* Allocate new packet */
808 if (q == NULL) {
809 USBDevice *dev;
810 USBEndpoint *ep;
811
812 dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
813 if (dev == NULL) {
814 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
815 int_mask);
816 }
817 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
818 q = uhci_queue_new(s, qh_addr, td, ep);
819 }
820 async = uhci_async_alloc(q, td_addr);
821
822 max_len = ((td->token >> 21) + 1) & 0x7ff;
823 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
824 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd,
825 (td->ctrl & TD_CTRL_IOC) != 0);
826 if (max_len <= sizeof(async->static_buf)) {
827 async->buf = async->static_buf;
828 } else {
829 async->buf = g_malloc(max_len);
830 }
831 usb_packet_addbuf(&async->packet, async->buf, max_len);
832
833 switch(pid) {
834 case USB_TOKEN_OUT:
835 case USB_TOKEN_SETUP:
836 pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
837 usb_handle_packet(q->ep->dev, &async->packet);
838 if (async->packet.status == USB_RET_SUCCESS) {
839 async->packet.actual_length = max_len;
840 }
841 break;
842
843 case USB_TOKEN_IN:
844 usb_handle_packet(q->ep->dev, &async->packet);
845 break;
846
847 default:
848 abort(); /* Never to execute */
849 }
850
851 if (async->packet.status == USB_RET_ASYNC) {
852 uhci_async_link(async);
853 if (!queuing) {
854 uhci_queue_fill(q, td);
855 }
856 return TD_RESULT_ASYNC_START;
857 }
858
859 done:
860 ret = uhci_complete_td(s, td, async, int_mask);
861 uhci_async_free(async);
862 return ret;
863 }
864
865 static void uhci_async_complete(USBPort *port, USBPacket *packet)
866 {
867 UHCIAsync *async = container_of(packet, UHCIAsync, packet);
868 UHCIState *s = async->queue->uhci;
869
870 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
871 uhci_async_cancel(async);
872 return;
873 }
874
875 async->done = 1;
876 /* Force processing of this packet *now*, needed for migration */
877 s->completions_only = true;
878 qemu_bh_schedule(s->bh);
879 }
880
881 static int is_valid(uint32_t link)
882 {
883 return (link & 1) == 0;
884 }
885
886 static int is_qh(uint32_t link)
887 {
888 return (link & 2) != 0;
889 }
890
891 static int depth_first(uint32_t link)
892 {
893 return (link & 4) != 0;
894 }
895
896 /* QH DB used for detecting QH loops */
897 #define UHCI_MAX_QUEUES 128
898 typedef struct {
899 uint32_t addr[UHCI_MAX_QUEUES];
900 int count;
901 } QhDb;
902
903 static void qhdb_reset(QhDb *db)
904 {
905 db->count = 0;
906 }
907
908 /* Add QH to DB. Returns 1 if already present or DB is full. */
909 static int qhdb_insert(QhDb *db, uint32_t addr)
910 {
911 int i;
912 for (i = 0; i < db->count; i++)
913 if (db->addr[i] == addr)
914 return 1;
915
916 if (db->count >= UHCI_MAX_QUEUES)
917 return 1;
918
919 db->addr[db->count++] = addr;
920 return 0;
921 }
922
923 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
924 {
925 uint32_t int_mask = 0;
926 uint32_t plink = td->link;
927 UHCI_TD ptd;
928 int ret;
929
930 while (is_valid(plink)) {
931 uhci_read_td(q->uhci, &ptd, plink);
932 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
933 break;
934 }
935 if (uhci_queue_token(&ptd) != q->token) {
936 break;
937 }
938 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
939 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
940 if (ret == TD_RESULT_ASYNC_CONT) {
941 break;
942 }
943 assert(ret == TD_RESULT_ASYNC_START);
944 assert(int_mask == 0);
945 plink = ptd.link;
946 }
947 usb_device_flush_ep_queue(q->ep->dev, q->ep);
948 }
949
950 static void uhci_process_frame(UHCIState *s)
951 {
952 uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
953 uint32_t curr_qh, td_count = 0;
954 int cnt, ret;
955 UHCI_TD td;
956 UHCI_QH qh;
957 QhDb qhdb;
958
959 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
960
961 pci_dma_read(&s->dev, frame_addr, &link, 4);
962 le32_to_cpus(&link);
963
964 int_mask = 0;
965 curr_qh = 0;
966
967 qhdb_reset(&qhdb);
968
969 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
970 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
971 /* We've reached the usb 1.1 bandwidth, which is
972 1280 bytes/frame, stop processing */
973 trace_usb_uhci_frame_stop_bandwidth();
974 break;
975 }
976 if (is_qh(link)) {
977 /* QH */
978 trace_usb_uhci_qh_load(link & ~0xf);
979
980 if (qhdb_insert(&qhdb, link)) {
981 /*
982 * We're going in circles. Which is not a bug because
983 * HCD is allowed to do that as part of the BW management.
984 *
985 * Stop processing here if no transaction has been done
986 * since we've been here last time.
987 */
988 if (td_count == 0) {
989 trace_usb_uhci_frame_loop_stop_idle();
990 break;
991 } else {
992 trace_usb_uhci_frame_loop_continue();
993 td_count = 0;
994 qhdb_reset(&qhdb);
995 qhdb_insert(&qhdb, link);
996 }
997 }
998
999 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1000 le32_to_cpus(&qh.link);
1001 le32_to_cpus(&qh.el_link);
1002
1003 if (!is_valid(qh.el_link)) {
1004 /* QH w/o elements */
1005 curr_qh = 0;
1006 link = qh.link;
1007 } else {
1008 /* QH with elements */
1009 curr_qh = link;
1010 link = qh.el_link;
1011 }
1012 continue;
1013 }
1014
1015 /* TD */
1016 uhci_read_td(s, &td, link);
1017 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1018
1019 old_td_ctrl = td.ctrl;
1020 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
1021 if (old_td_ctrl != td.ctrl) {
1022 /* update the status bits of the TD */
1023 val = cpu_to_le32(td.ctrl);
1024 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1025 }
1026
1027 switch (ret) {
1028 case TD_RESULT_STOP_FRAME: /* interrupted frame */
1029 goto out;
1030
1031 case TD_RESULT_NEXT_QH:
1032 case TD_RESULT_ASYNC_CONT:
1033 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1034 link = curr_qh ? qh.link : td.link;
1035 continue;
1036
1037 case TD_RESULT_ASYNC_START:
1038 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1039 link = curr_qh ? qh.link : td.link;
1040 continue;
1041
1042 case TD_RESULT_COMPLETE:
1043 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1044 link = td.link;
1045 td_count++;
1046 s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1047
1048 if (curr_qh) {
1049 /* update QH element link */
1050 qh.el_link = link;
1051 val = cpu_to_le32(qh.el_link);
1052 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1053
1054 if (!depth_first(link)) {
1055 /* done with this QH */
1056 curr_qh = 0;
1057 link = qh.link;
1058 }
1059 }
1060 break;
1061
1062 default:
1063 assert(!"unknown return code");
1064 }
1065
1066 /* go to the next entry */
1067 }
1068
1069 out:
1070 s->pending_int_mask |= int_mask;
1071 }
1072
1073 static void uhci_bh(void *opaque)
1074 {
1075 UHCIState *s = opaque;
1076 uhci_process_frame(s);
1077 }
1078
1079 static void uhci_frame_timer(void *opaque)
1080 {
1081 UHCIState *s = opaque;
1082 uint64_t t_now, t_last_run;
1083 int i, frames;
1084 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ;
1085
1086 s->completions_only = false;
1087 qemu_bh_cancel(s->bh);
1088
1089 if (!(s->cmd & UHCI_CMD_RS)) {
1090 /* Full stop */
1091 trace_usb_uhci_schedule_stop();
1092 timer_del(s->frame_timer);
1093 uhci_async_cancel_all(s);
1094 /* set hchalted bit in status - UHCI11D 2.1.2 */
1095 s->status |= UHCI_STS_HCHALTED;
1096 return;
1097 }
1098
1099 /* We still store expire_time in our state, for migration */
1100 t_last_run = s->expire_time - frame_t;
1101 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1102
1103 /* Process up to MAX_FRAMES_PER_TICK frames */
1104 frames = (t_now - t_last_run) / frame_t;
1105 if (frames > s->maxframes) {
1106 int skipped = frames - s->maxframes;
1107 s->expire_time += skipped * frame_t;
1108 s->frnum = (s->frnum + skipped) & 0x7ff;
1109 frames -= skipped;
1110 }
1111 if (frames > MAX_FRAMES_PER_TICK) {
1112 frames = MAX_FRAMES_PER_TICK;
1113 }
1114
1115 for (i = 0; i < frames; i++) {
1116 s->frame_bytes = 0;
1117 trace_usb_uhci_frame_start(s->frnum);
1118 uhci_async_validate_begin(s);
1119 uhci_process_frame(s);
1120 uhci_async_validate_end(s);
1121 /* The spec says frnum is the frame currently being processed, and
1122 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1123 s->frnum = (s->frnum + 1) & 0x7ff;
1124 s->expire_time += frame_t;
1125 }
1126
1127 /* Complete the previous frame(s) */
1128 if (s->pending_int_mask) {
1129 s->status2 |= s->pending_int_mask;
1130 s->status |= UHCI_STS_USBINT;
1131 uhci_update_irq(s);
1132 }
1133 s->pending_int_mask = 0;
1134
1135 timer_mod(s->frame_timer, t_now + frame_t);
1136 }
1137
1138 static const MemoryRegionOps uhci_ioport_ops = {
1139 .read = uhci_port_read,
1140 .write = uhci_port_write,
1141 .valid.min_access_size = 1,
1142 .valid.max_access_size = 4,
1143 .impl.min_access_size = 2,
1144 .impl.max_access_size = 2,
1145 .endianness = DEVICE_LITTLE_ENDIAN,
1146 };
1147
1148 static USBPortOps uhci_port_ops = {
1149 .attach = uhci_attach,
1150 .detach = uhci_detach,
1151 .child_detach = uhci_child_detach,
1152 .wakeup = uhci_wakeup,
1153 .complete = uhci_async_complete,
1154 };
1155
1156 static USBBusOps uhci_bus_ops = {
1157 };
1158
1159 void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
1160 {
1161 Error *err = NULL;
1162 UHCIPCIDeviceClass *u = UHCI_GET_CLASS(dev);
1163 UHCIState *s = UHCI(dev);
1164 uint8_t *pci_conf = s->dev.config;
1165 int i;
1166
1167 pci_conf[PCI_CLASS_PROG] = 0x00;
1168 /* TODO: reset value should be 0. */
1169 pci_conf[USB_SBRN] = USB_RELEASE_1; /* release number */
1170 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
1171 s->irq = pci_allocate_irq(dev);
1172
1173 if (s->masterbus) {
1174 USBPort *ports[NB_PORTS];
1175 for(i = 0; i < NB_PORTS; i++) {
1176 ports[i] = &s->ports[i].port;
1177 }
1178 usb_register_companion(s->masterbus, ports, NB_PORTS,
1179 s->firstport, s, &uhci_port_ops,
1180 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1181 &err);
1182 if (err) {
1183 error_propagate(errp, err);
1184 return;
1185 }
1186 } else {
1187 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
1188 for (i = 0; i < NB_PORTS; i++) {
1189 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1190 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1191 }
1192 }
1193 s->bh = qemu_bh_new_guarded(uhci_bh, s, &DEVICE(dev)->mem_reentrancy_guard);
1194 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
1195 s->num_ports_vmstate = NB_PORTS;
1196 QTAILQ_INIT(&s->queues);
1197
1198 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
1199 "uhci", 0x20);
1200
1201 /* Use region 4 for consistency with real hardware. BSD guests seem
1202 to rely on this. */
1203 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1204 }
1205
1206 static void usb_uhci_exit(PCIDevice *dev)
1207 {
1208 UHCIState *s = UHCI(dev);
1209
1210 trace_usb_uhci_exit();
1211
1212 if (s->frame_timer) {
1213 timer_free(s->frame_timer);
1214 s->frame_timer = NULL;
1215 }
1216
1217 if (s->bh) {
1218 qemu_bh_delete(s->bh);
1219 }
1220
1221 uhci_async_cancel_all(s);
1222
1223 if (!s->masterbus) {
1224 usb_bus_release(&s->bus);
1225 }
1226 }
1227
1228 static Property uhci_properties_companion[] = {
1229 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1230 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1231 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1232 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1233 DEFINE_PROP_END_OF_LIST(),
1234 };
1235 static Property uhci_properties_standalone[] = {
1236 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1237 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1238 DEFINE_PROP_END_OF_LIST(),
1239 };
1240
1241 static void uhci_class_init(ObjectClass *klass, void *data)
1242 {
1243 DeviceClass *dc = DEVICE_CLASS(klass);
1244 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1245
1246 k->class_id = PCI_CLASS_SERIAL_USB;
1247 dc->vmsd = &vmstate_uhci;
1248 dc->reset = uhci_reset;
1249 set_bit(DEVICE_CATEGORY_USB, dc->categories);
1250 }
1251
1252 static const TypeInfo uhci_pci_type_info = {
1253 .name = TYPE_UHCI,
1254 .parent = TYPE_PCI_DEVICE,
1255 .instance_size = sizeof(UHCIState),
1256 .class_size = sizeof(UHCIPCIDeviceClass),
1257 .abstract = true,
1258 .class_init = uhci_class_init,
1259 .interfaces = (InterfaceInfo[]) {
1260 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1261 { },
1262 },
1263 };
1264
1265 void uhci_data_class_init(ObjectClass *klass, void *data)
1266 {
1267 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1268 DeviceClass *dc = DEVICE_CLASS(klass);
1269 UHCIPCIDeviceClass *u = UHCI_CLASS(klass);
1270 UHCIInfo *info = data;
1271
1272 k->realize = info->realize ? info->realize : usb_uhci_common_realize;
1273 k->exit = info->unplug ? usb_uhci_exit : NULL;
1274 k->vendor_id = info->vendor_id;
1275 k->device_id = info->device_id;
1276 k->revision = info->revision;
1277 if (!info->unplug) {
1278 /* uhci controllers in companion setups can't be hotplugged */
1279 dc->hotpluggable = false;
1280 device_class_set_props(dc, uhci_properties_companion);
1281 } else {
1282 device_class_set_props(dc, uhci_properties_standalone);
1283 }
1284 if (info->notuser) {
1285 dc->user_creatable = false;
1286 }
1287 u->info = *info;
1288 }
1289
1290 static UHCIInfo uhci_info[] = {
1291 {
1292 .name = TYPE_PIIX3_USB_UHCI,
1293 .vendor_id = PCI_VENDOR_ID_INTEL,
1294 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
1295 .revision = 0x01,
1296 .irq_pin = 3,
1297 .unplug = true,
1298 },{
1299 .name = TYPE_PIIX4_USB_UHCI,
1300 .vendor_id = PCI_VENDOR_ID_INTEL,
1301 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
1302 .revision = 0x01,
1303 .irq_pin = 3,
1304 .unplug = true,
1305 },{
1306 .name = TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */
1307 .vendor_id = PCI_VENDOR_ID_INTEL,
1308 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
1309 .revision = 0x03,
1310 .irq_pin = 0,
1311 .unplug = false,
1312 },{
1313 .name = TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */
1314 .vendor_id = PCI_VENDOR_ID_INTEL,
1315 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
1316 .revision = 0x03,
1317 .irq_pin = 1,
1318 .unplug = false,
1319 },{
1320 .name = TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */
1321 .vendor_id = PCI_VENDOR_ID_INTEL,
1322 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
1323 .revision = 0x03,
1324 .irq_pin = 2,
1325 .unplug = false,
1326 },{
1327 .name = TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */
1328 .vendor_id = PCI_VENDOR_ID_INTEL,
1329 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
1330 .revision = 0x03,
1331 .irq_pin = 0,
1332 .unplug = false,
1333 },{
1334 .name = TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */
1335 .vendor_id = PCI_VENDOR_ID_INTEL,
1336 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
1337 .revision = 0x03,
1338 .irq_pin = 1,
1339 .unplug = false,
1340 },{
1341 .name = TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */
1342 .vendor_id = PCI_VENDOR_ID_INTEL,
1343 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
1344 .revision = 0x03,
1345 .irq_pin = 2,
1346 .unplug = false,
1347 }
1348 };
1349
1350 static void uhci_register_types(void)
1351 {
1352 TypeInfo uhci_type_info = {
1353 .parent = TYPE_UHCI,
1354 .class_init = uhci_data_class_init,
1355 };
1356 int i;
1357
1358 type_register_static(&uhci_pci_type_info);
1359
1360 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
1361 uhci_type_info.name = uhci_info[i].name;
1362 uhci_type_info.class_data = uhci_info + i;
1363 type_register(&uhci_type_info);
1364 }
1365 }
1366
1367 type_init(uhci_register_types)
AR7 emulation for QEMU