4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
121 case ARMMMUIdx_SE20_2
:
122 case ARMMMUIdx_SE20_2_PAN
:
123 useridx
= ARMMMUIdx_SE20_0
;
126 g_assert_not_reached();
129 return arm_to_core_mmu_idx(useridx
);
132 static void reset_btype(DisasContext
*s
)
135 TCGv_i32 zero
= tcg_const_i32(0);
136 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
137 tcg_temp_free_i32(zero
);
142 static void set_btype(DisasContext
*s
, int val
)
146 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
147 tcg_debug_assert(val
>= 1 && val
<= 3);
149 tcg_val
= tcg_const_i32(val
);
150 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
151 tcg_temp_free_i32(tcg_val
);
155 void gen_a64_set_pc_im(uint64_t val
)
157 tcg_gen_movi_i64(cpu_pc
, val
);
161 * Handle Top Byte Ignore (TBI) bits.
163 * If address tagging is enabled via the TCR TBI bits:
164 * + for EL2 and EL3 there is only one TBI bit, and if it is set
165 * then the address is zero-extended, clearing bits [63:56]
166 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
167 * and TBI1 controls addressses with bit 55 == 1.
168 * If the appropriate TBI bit is set for the address then
169 * the address is sign-extended from bit 55 into bits [63:56]
171 * Here We have concatenated TBI{1,0} into tbi.
173 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
174 TCGv_i64 src
, int tbi
)
177 /* Load unmodified address */
178 tcg_gen_mov_i64(dst
, src
);
179 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
180 /* Force tag byte to all zero */
181 tcg_gen_extract_i64(dst
, src
, 0, 56);
183 /* Sign-extend from bit 55. */
184 tcg_gen_sextract_i64(dst
, src
, 0, 56);
188 /* tbi0 but !tbi1: only use the extension if positive */
189 tcg_gen_and_i64(dst
, dst
, src
);
192 /* !tbi0 but tbi1: only use the extension if negative */
193 tcg_gen_or_i64(dst
, dst
, src
);
196 /* tbi0 and tbi1: always use the extension */
199 g_assert_not_reached();
204 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
207 * If address tagging is enabled for instructions via the TCR TBI bits,
208 * then loading an address into the PC will clear out any tag.
210 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
214 * Handle MTE and/or TBI.
216 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
217 * for the tag to be present in the FAR_ELx register. But for user-only
218 * mode we do not have a TLB with which to implement this, so we must
219 * remove the top byte now.
221 * Always return a fresh temporary that we can increment independently
222 * of the write-back address.
225 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
227 TCGv_i64 clean
= new_tmp_a64(s
);
228 #ifdef CONFIG_USER_ONLY
229 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
231 tcg_gen_mov_i64(clean
, addr
);
236 /* Insert a zero tag into src, with the result at dst. */
237 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
239 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
242 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
243 MMUAccessType acc
, int log2_size
)
245 TCGv_i32 t_acc
= tcg_const_i32(acc
);
246 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
247 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
249 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
250 tcg_temp_free_i32(t_acc
);
251 tcg_temp_free_i32(t_idx
);
252 tcg_temp_free_i32(t_size
);
256 * For MTE, check a single logical or atomic access. This probes a single
257 * address, the exact one specified. The size and alignment of the access
258 * is not relevant to MTE, per se, but watchpoints do require the size,
259 * and we want to recognize those before making any other changes to state.
261 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
262 bool is_write
, bool tag_checked
,
263 int log2_size
, bool is_unpriv
,
266 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
271 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
272 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
273 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
274 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
275 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
276 tcg_desc
= tcg_const_i32(desc
);
278 ret
= new_tmp_a64(s
);
279 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
280 tcg_temp_free_i32(tcg_desc
);
284 return clean_data_tbi(s
, addr
);
287 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
288 bool tag_checked
, int log2_size
)
290 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
291 false, get_mem_index(s
));
295 * For MTE, check multiple logical sequential accesses.
297 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
298 bool tag_checked
, int size
)
300 if (tag_checked
&& s
->mte_active
[0]) {
305 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
306 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
307 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
308 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
309 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
310 tcg_desc
= tcg_const_i32(desc
);
312 ret
= new_tmp_a64(s
);
313 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
314 tcg_temp_free_i32(tcg_desc
);
318 return clean_data_tbi(s
, addr
);
321 typedef struct DisasCompare64
{
326 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
330 arm_test_cc(&c32
, cc
);
332 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
333 * properly. The NE/EQ comparisons are also fine with this choice. */
334 c64
->cond
= c32
.cond
;
335 c64
->value
= tcg_temp_new_i64();
336 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
341 static void a64_free_cc(DisasCompare64
*c64
)
343 tcg_temp_free_i64(c64
->value
);
346 static void gen_exception_internal(int excp
)
348 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
350 assert(excp_is_internal(excp
));
351 gen_helper_exception_internal(cpu_env
, tcg_excp
);
352 tcg_temp_free_i32(tcg_excp
);
355 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
357 gen_a64_set_pc_im(pc
);
358 gen_exception_internal(excp
);
359 s
->base
.is_jmp
= DISAS_NORETURN
;
362 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
366 gen_a64_set_pc_im(s
->pc_curr
);
367 tcg_syn
= tcg_const_i32(syndrome
);
368 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
369 tcg_temp_free_i32(tcg_syn
);
370 s
->base
.is_jmp
= DISAS_NORETURN
;
373 static void gen_step_complete_exception(DisasContext
*s
)
375 /* We just completed step of an insn. Move from Active-not-pending
376 * to Active-pending, and then also take the swstep exception.
377 * This corresponds to making the (IMPDEF) choice to prioritize
378 * swstep exceptions over asynchronous exceptions taken to an exception
379 * level where debug is disabled. This choice has the advantage that
380 * we do not need to maintain internal state corresponding to the
381 * ISV/EX syndrome bits between completion of the step and generation
382 * of the exception, and our syndrome information is always correct.
385 gen_swstep_exception(s
, 1, s
->is_ldex
);
386 s
->base
.is_jmp
= DISAS_NORETURN
;
389 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
391 /* No direct tb linking with singlestep (either QEMU's or the ARM
392 * debug architecture kind) or deterministic io
394 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
395 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
399 #ifndef CONFIG_USER_ONLY
400 /* Only link tbs from inside the same guest page */
401 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
409 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
411 const TranslationBlock
*tb
;
414 if (use_goto_tb(s
, n
, dest
)) {
416 gen_a64_set_pc_im(dest
);
417 tcg_gen_exit_tb(tb
, n
);
418 s
->base
.is_jmp
= DISAS_NORETURN
;
420 gen_a64_set_pc_im(dest
);
422 gen_step_complete_exception(s
);
423 } else if (s
->base
.singlestep_enabled
) {
424 gen_exception_internal(EXCP_DEBUG
);
426 tcg_gen_lookup_and_goto_ptr();
427 s
->base
.is_jmp
= DISAS_NORETURN
;
432 static void init_tmp_a64_array(DisasContext
*s
)
434 #ifdef CONFIG_DEBUG_TCG
435 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
437 s
->tmp_a64_count
= 0;
440 static void free_tmp_a64(DisasContext
*s
)
443 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
444 tcg_temp_free_i64(s
->tmp_a64
[i
]);
446 init_tmp_a64_array(s
);
449 TCGv_i64
new_tmp_a64(DisasContext
*s
)
451 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
452 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
455 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
457 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
458 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
461 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
463 TCGv_i64 t
= new_tmp_a64(s
);
464 tcg_gen_movi_i64(t
, 0);
469 * Register access functions
471 * These functions are used for directly accessing a register in where
472 * changes to the final register value are likely to be made. If you
473 * need to use a register for temporary calculation (e.g. index type
474 * operations) use the read_* form.
476 * B1.2.1 Register mappings
478 * In instruction register encoding 31 can refer to ZR (zero register) or
479 * the SP (stack pointer) depending on context. In QEMU's case we map SP
480 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
481 * This is the point of the _sp forms.
483 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
486 return new_tmp_a64_zero(s
);
492 /* register access for when 31 == SP */
493 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
498 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
499 * representing the register contents. This TCGv is an auto-freed
500 * temporary so it need not be explicitly freed, and may be modified.
502 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
504 TCGv_i64 v
= new_tmp_a64(s
);
507 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
509 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
512 tcg_gen_movi_i64(v
, 0);
517 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
519 TCGv_i64 v
= new_tmp_a64(s
);
521 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
523 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
528 /* Return the offset into CPUARMState of a slice (from
529 * the least significant end) of FP register Qn (ie
531 * (Note that this is not the same mapping as for A32; see cpu.h)
533 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
535 return vec_reg_offset(s
, regno
, 0, size
);
538 /* Offset of the high half of the 128 bit vector Qn */
539 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
541 return vec_reg_offset(s
, regno
, 1, MO_64
);
544 /* Convenience accessors for reading and writing single and double
545 * FP registers. Writing clears the upper parts of the associated
546 * 128 bit vector register, as required by the architecture.
547 * Note that unlike the GP register accessors, the values returned
548 * by the read functions must be manually freed.
550 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
552 TCGv_i64 v
= tcg_temp_new_i64();
554 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
558 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
560 TCGv_i32 v
= tcg_temp_new_i32();
562 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
566 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
568 TCGv_i32 v
= tcg_temp_new_i32();
570 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
574 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
575 * If SVE is not enabled, then there are only 128 bits in the vector.
577 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
579 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
580 unsigned vsz
= vec_full_reg_size(s
);
582 /* Nop move, with side effect of clearing the tail. */
583 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
586 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
588 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
590 tcg_gen_st_i64(v
, cpu_env
, ofs
);
591 clear_vec_high(s
, false, reg
);
594 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
596 TCGv_i64 tmp
= tcg_temp_new_i64();
598 tcg_gen_extu_i32_i64(tmp
, v
);
599 write_fp_dreg(s
, reg
, tmp
);
600 tcg_temp_free_i64(tmp
);
603 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
604 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
605 GVecGen2Fn
*gvec_fn
, int vece
)
607 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
608 is_q
? 16 : 8, vec_full_reg_size(s
));
611 /* Expand a 2-operand + immediate AdvSIMD vector operation using
612 * an expander function.
614 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
615 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
617 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
618 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
621 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
622 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
623 GVecGen3Fn
*gvec_fn
, int vece
)
625 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
626 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
629 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
630 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
631 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
633 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
634 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
635 is_q
? 16 : 8, vec_full_reg_size(s
));
638 /* Expand a 2-operand operation using an out-of-line helper. */
639 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
640 int rn
, int data
, gen_helper_gvec_2
*fn
)
642 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
643 vec_full_reg_offset(s
, rn
),
644 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
647 /* Expand a 3-operand operation using an out-of-line helper. */
648 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
649 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
651 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
652 vec_full_reg_offset(s
, rn
),
653 vec_full_reg_offset(s
, rm
),
654 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
657 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
658 * an out-of-line helper.
660 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
661 int rm
, bool is_fp16
, int data
,
662 gen_helper_gvec_3_ptr
*fn
)
664 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
665 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
666 vec_full_reg_offset(s
, rn
),
667 vec_full_reg_offset(s
, rm
), fpst
,
668 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
669 tcg_temp_free_ptr(fpst
);
672 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
673 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
674 int rm
, gen_helper_gvec_3_ptr
*fn
)
676 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
678 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
679 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
680 vec_full_reg_offset(s
, rn
),
681 vec_full_reg_offset(s
, rm
), qc_ptr
,
682 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
683 tcg_temp_free_ptr(qc_ptr
);
686 /* Expand a 4-operand operation using an out-of-line helper. */
687 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
688 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
690 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
691 vec_full_reg_offset(s
, rn
),
692 vec_full_reg_offset(s
, rm
),
693 vec_full_reg_offset(s
, ra
),
694 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
698 * Expand a 4-operand + fpstatus pointer + simd data value operation using
699 * an out-of-line helper.
701 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
702 int rm
, int ra
, bool is_fp16
, int data
,
703 gen_helper_gvec_4_ptr
*fn
)
705 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
706 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
707 vec_full_reg_offset(s
, rn
),
708 vec_full_reg_offset(s
, rm
),
709 vec_full_reg_offset(s
, ra
), fpst
,
710 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
711 tcg_temp_free_ptr(fpst
);
714 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
715 * than the 32 bit equivalent.
717 static inline void gen_set_NZ64(TCGv_i64 result
)
719 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
720 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
723 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
724 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
727 gen_set_NZ64(result
);
729 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
730 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
732 tcg_gen_movi_i32(cpu_CF
, 0);
733 tcg_gen_movi_i32(cpu_VF
, 0);
736 /* dest = T0 + T1; compute C, N, V and Z flags */
737 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
740 TCGv_i64 result
, flag
, tmp
;
741 result
= tcg_temp_new_i64();
742 flag
= tcg_temp_new_i64();
743 tmp
= tcg_temp_new_i64();
745 tcg_gen_movi_i64(tmp
, 0);
746 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
748 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
750 gen_set_NZ64(result
);
752 tcg_gen_xor_i64(flag
, result
, t0
);
753 tcg_gen_xor_i64(tmp
, t0
, t1
);
754 tcg_gen_andc_i64(flag
, flag
, tmp
);
755 tcg_temp_free_i64(tmp
);
756 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
758 tcg_gen_mov_i64(dest
, result
);
759 tcg_temp_free_i64(result
);
760 tcg_temp_free_i64(flag
);
762 /* 32 bit arithmetic */
763 TCGv_i32 t0_32
= tcg_temp_new_i32();
764 TCGv_i32 t1_32
= tcg_temp_new_i32();
765 TCGv_i32 tmp
= tcg_temp_new_i32();
767 tcg_gen_movi_i32(tmp
, 0);
768 tcg_gen_extrl_i64_i32(t0_32
, t0
);
769 tcg_gen_extrl_i64_i32(t1_32
, t1
);
770 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
771 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
772 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
773 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
774 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
775 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
777 tcg_temp_free_i32(tmp
);
778 tcg_temp_free_i32(t0_32
);
779 tcg_temp_free_i32(t1_32
);
783 /* dest = T0 - T1; compute C, N, V and Z flags */
784 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
787 /* 64 bit arithmetic */
788 TCGv_i64 result
, flag
, tmp
;
790 result
= tcg_temp_new_i64();
791 flag
= tcg_temp_new_i64();
792 tcg_gen_sub_i64(result
, t0
, t1
);
794 gen_set_NZ64(result
);
796 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
797 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
799 tcg_gen_xor_i64(flag
, result
, t0
);
800 tmp
= tcg_temp_new_i64();
801 tcg_gen_xor_i64(tmp
, t0
, t1
);
802 tcg_gen_and_i64(flag
, flag
, tmp
);
803 tcg_temp_free_i64(tmp
);
804 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
805 tcg_gen_mov_i64(dest
, result
);
806 tcg_temp_free_i64(flag
);
807 tcg_temp_free_i64(result
);
809 /* 32 bit arithmetic */
810 TCGv_i32 t0_32
= tcg_temp_new_i32();
811 TCGv_i32 t1_32
= tcg_temp_new_i32();
814 tcg_gen_extrl_i64_i32(t0_32
, t0
);
815 tcg_gen_extrl_i64_i32(t1_32
, t1
);
816 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
817 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
818 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
819 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
820 tmp
= tcg_temp_new_i32();
821 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
822 tcg_temp_free_i32(t0_32
);
823 tcg_temp_free_i32(t1_32
);
824 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
825 tcg_temp_free_i32(tmp
);
826 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
830 /* dest = T0 + T1 + CF; do not compute flags. */
831 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
833 TCGv_i64 flag
= tcg_temp_new_i64();
834 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
835 tcg_gen_add_i64(dest
, t0
, t1
);
836 tcg_gen_add_i64(dest
, dest
, flag
);
837 tcg_temp_free_i64(flag
);
840 tcg_gen_ext32u_i64(dest
, dest
);
844 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
845 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
848 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
849 result
= tcg_temp_new_i64();
850 cf_64
= tcg_temp_new_i64();
851 vf_64
= tcg_temp_new_i64();
852 tmp
= tcg_const_i64(0);
854 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
855 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
856 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
857 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
858 gen_set_NZ64(result
);
860 tcg_gen_xor_i64(vf_64
, result
, t0
);
861 tcg_gen_xor_i64(tmp
, t0
, t1
);
862 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
863 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
865 tcg_gen_mov_i64(dest
, result
);
867 tcg_temp_free_i64(tmp
);
868 tcg_temp_free_i64(vf_64
);
869 tcg_temp_free_i64(cf_64
);
870 tcg_temp_free_i64(result
);
872 TCGv_i32 t0_32
, t1_32
, tmp
;
873 t0_32
= tcg_temp_new_i32();
874 t1_32
= tcg_temp_new_i32();
875 tmp
= tcg_const_i32(0);
877 tcg_gen_extrl_i64_i32(t0_32
, t0
);
878 tcg_gen_extrl_i64_i32(t1_32
, t1
);
879 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
880 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
882 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
883 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
884 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
885 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
886 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
888 tcg_temp_free_i32(tmp
);
889 tcg_temp_free_i32(t1_32
);
890 tcg_temp_free_i32(t0_32
);
895 * Load/Store generators
899 * Store from GPR register to memory.
901 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
902 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
904 unsigned int iss_srt
,
905 bool iss_sf
, bool iss_ar
)
907 memop
= finalize_memop(s
, memop
);
908 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
913 syn
= syn_data_abort_with_iss(0,
919 0, 0, 0, 0, 0, false);
920 disas_set_insn_syndrome(s
, syn
);
924 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
925 TCGv_i64 tcg_addr
, MemOp memop
,
927 unsigned int iss_srt
,
928 bool iss_sf
, bool iss_ar
)
930 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
931 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
935 * Load from memory to GPR register
937 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
938 MemOp memop
, bool extend
, int memidx
,
939 bool iss_valid
, unsigned int iss_srt
,
940 bool iss_sf
, bool iss_ar
)
942 memop
= finalize_memop(s
, memop
);
943 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
945 if (extend
&& (memop
& MO_SIGN
)) {
946 g_assert((memop
& MO_SIZE
) <= MO_32
);
947 tcg_gen_ext32u_i64(dest
, dest
);
953 syn
= syn_data_abort_with_iss(0,
955 (memop
& MO_SIGN
) != 0,
959 0, 0, 0, 0, 0, false);
960 disas_set_insn_syndrome(s
, syn
);
964 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
965 MemOp memop
, bool extend
,
966 bool iss_valid
, unsigned int iss_srt
,
967 bool iss_sf
, bool iss_ar
)
969 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
970 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
974 * Store from FP register to memory
976 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
978 /* This writes the bottom N bits of a 128 bit wide vector to memory */
979 TCGv_i64 tmplo
= tcg_temp_new_i64();
982 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
985 mop
= finalize_memop(s
, size
);
986 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
988 bool be
= s
->be_data
== MO_BE
;
989 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
990 TCGv_i64 tmphi
= tcg_temp_new_i64();
992 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
994 mop
= s
->be_data
| MO_Q
;
995 tcg_gen_qemu_st_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
996 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
997 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
998 tcg_gen_qemu_st_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
999 get_mem_index(s
), mop
);
1001 tcg_temp_free_i64(tcg_hiaddr
);
1002 tcg_temp_free_i64(tmphi
);
1005 tcg_temp_free_i64(tmplo
);
1009 * Load from memory to FP register
1011 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1013 /* This always zero-extends and writes to a full 128 bit wide vector */
1014 TCGv_i64 tmplo
= tcg_temp_new_i64();
1015 TCGv_i64 tmphi
= NULL
;
1019 mop
= finalize_memop(s
, size
);
1020 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
1022 bool be
= s
->be_data
== MO_BE
;
1023 TCGv_i64 tcg_hiaddr
;
1025 tmphi
= tcg_temp_new_i64();
1026 tcg_hiaddr
= tcg_temp_new_i64();
1028 mop
= s
->be_data
| MO_Q
;
1029 tcg_gen_qemu_ld_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
1030 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
1031 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1032 tcg_gen_qemu_ld_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
1033 get_mem_index(s
), mop
);
1034 tcg_temp_free_i64(tcg_hiaddr
);
1037 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1038 tcg_temp_free_i64(tmplo
);
1041 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1042 tcg_temp_free_i64(tmphi
);
1044 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1048 * Vector load/store helpers.
1050 * The principal difference between this and a FP load is that we don't
1051 * zero extend as we are filling a partial chunk of the vector register.
1052 * These functions don't support 128 bit loads/stores, which would be
1053 * normal load/store operations.
1055 * The _i32 versions are useful when operating on 32 bit quantities
1056 * (eg for floating point single or using Neon helper functions).
1059 /* Get value of an element within a vector register */
1060 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1061 int element
, MemOp memop
)
1063 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1066 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1069 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1072 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1075 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1078 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1081 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1085 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1088 g_assert_not_reached();
1092 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1093 int element
, MemOp memop
)
1095 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1098 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1101 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1104 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1107 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1114 g_assert_not_reached();
1118 /* Set value of an element within a vector register */
1119 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1120 int element
, MemOp memop
)
1122 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1125 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1128 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1131 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1134 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1137 g_assert_not_reached();
1141 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1142 int destidx
, int element
, MemOp memop
)
1144 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1147 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1150 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1153 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1156 g_assert_not_reached();
1160 /* Store from vector register to memory */
1161 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1162 TCGv_i64 tcg_addr
, MemOp mop
)
1164 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1166 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1167 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1169 tcg_temp_free_i64(tcg_tmp
);
1172 /* Load from memory to vector register */
1173 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1174 TCGv_i64 tcg_addr
, MemOp mop
)
1176 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1178 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1179 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1181 tcg_temp_free_i64(tcg_tmp
);
1184 /* Check that FP/Neon access is enabled. If it is, return
1185 * true. If not, emit code to generate an appropriate exception,
1186 * and return false; the caller should not emit any code for
1187 * the instruction. Note that this check must happen after all
1188 * unallocated-encoding checks (otherwise the syndrome information
1189 * for the resulting exception will be incorrect).
1191 static bool fp_access_check(DisasContext
*s
)
1193 if (s
->fp_excp_el
) {
1194 assert(!s
->fp_access_checked
);
1195 s
->fp_access_checked
= true;
1197 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1198 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1201 s
->fp_access_checked
= true;
1205 /* Check that SVE access is enabled. If it is, return true.
1206 * If not, emit code to generate an appropriate exception and return false.
1208 bool sve_access_check(DisasContext
*s
)
1210 if (s
->sve_excp_el
) {
1211 assert(!s
->sve_access_checked
);
1212 s
->sve_access_checked
= true;
1214 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1215 syn_sve_access_trap(), s
->sve_excp_el
);
1218 s
->sve_access_checked
= true;
1219 return fp_access_check(s
);
1223 * This utility function is for doing register extension with an
1224 * optional shift. You will likely want to pass a temporary for the
1225 * destination register. See DecodeRegExtend() in the ARM ARM.
1227 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1228 int option
, unsigned int shift
)
1230 int extsize
= extract32(option
, 0, 2);
1231 bool is_signed
= extract32(option
, 2, 1);
1236 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1239 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1242 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1245 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1251 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1254 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1257 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1260 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1266 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1270 static inline void gen_check_sp_alignment(DisasContext
*s
)
1272 /* The AArch64 architecture mandates that (if enabled via PSTATE
1273 * or SCTLR bits) there is a check that SP is 16-aligned on every
1274 * SP-relative load or store (with an exception generated if it is not).
1275 * In line with general QEMU practice regarding misaligned accesses,
1276 * we omit these checks for the sake of guest program performance.
1277 * This function is provided as a hook so we can more easily add these
1278 * checks in future (possibly as a "favour catching guest program bugs
1279 * over speed" user selectable option).
1284 * This provides a simple table based table lookup decoder. It is
1285 * intended to be used when the relevant bits for decode are too
1286 * awkwardly placed and switch/if based logic would be confusing and
1287 * deeply nested. Since it's a linear search through the table, tables
1288 * should be kept small.
1290 * It returns the first handler where insn & mask == pattern, or
1291 * NULL if there is no match.
1292 * The table is terminated by an empty mask (i.e. 0)
1294 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1297 const AArch64DecodeTable
*tptr
= table
;
1299 while (tptr
->mask
) {
1300 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1301 return tptr
->disas_fn
;
1309 * The instruction disassembly implemented here matches
1310 * the instruction encoding classifications in chapter C4
1311 * of the ARM Architecture Reference Manual (DDI0487B_a);
1312 * classification names and decode diagrams here should generally
1313 * match up with those in the manual.
1316 /* Unconditional branch (immediate)
1318 * +----+-----------+-------------------------------------+
1319 * | op | 0 0 1 0 1 | imm26 |
1320 * +----+-----------+-------------------------------------+
1322 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1324 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1326 if (insn
& (1U << 31)) {
1327 /* BL Branch with link */
1328 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1331 /* B Branch / BL Branch with link */
1333 gen_goto_tb(s
, 0, addr
);
1336 /* Compare and branch (immediate)
1337 * 31 30 25 24 23 5 4 0
1338 * +----+-------------+----+---------------------+--------+
1339 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1340 * +----+-------------+----+---------------------+--------+
1342 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1344 unsigned int sf
, op
, rt
;
1346 TCGLabel
*label_match
;
1349 sf
= extract32(insn
, 31, 1);
1350 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1351 rt
= extract32(insn
, 0, 5);
1352 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1354 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1355 label_match
= gen_new_label();
1358 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1359 tcg_cmp
, 0, label_match
);
1361 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1362 gen_set_label(label_match
);
1363 gen_goto_tb(s
, 1, addr
);
1366 /* Test and branch (immediate)
1367 * 31 30 25 24 23 19 18 5 4 0
1368 * +----+-------------+----+-------+-------------+------+
1369 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1370 * +----+-------------+----+-------+-------------+------+
1372 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1374 unsigned int bit_pos
, op
, rt
;
1376 TCGLabel
*label_match
;
1379 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1380 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1381 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1382 rt
= extract32(insn
, 0, 5);
1384 tcg_cmp
= tcg_temp_new_i64();
1385 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1386 label_match
= gen_new_label();
1389 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1390 tcg_cmp
, 0, label_match
);
1391 tcg_temp_free_i64(tcg_cmp
);
1392 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1393 gen_set_label(label_match
);
1394 gen_goto_tb(s
, 1, addr
);
1397 /* Conditional branch (immediate)
1398 * 31 25 24 23 5 4 3 0
1399 * +---------------+----+---------------------+----+------+
1400 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1401 * +---------------+----+---------------------+----+------+
1403 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1408 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1409 unallocated_encoding(s
);
1412 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1413 cond
= extract32(insn
, 0, 4);
1417 /* genuinely conditional branches */
1418 TCGLabel
*label_match
= gen_new_label();
1419 arm_gen_test_cc(cond
, label_match
);
1420 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1421 gen_set_label(label_match
);
1422 gen_goto_tb(s
, 1, addr
);
1424 /* 0xe and 0xf are both "always" conditions */
1425 gen_goto_tb(s
, 0, addr
);
1429 /* HINT instruction group, including various allocated HINTs */
1430 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1431 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1433 unsigned int selector
= crm
<< 3 | op2
;
1436 unallocated_encoding(s
);
1441 case 0b00000: /* NOP */
1443 case 0b00011: /* WFI */
1444 s
->base
.is_jmp
= DISAS_WFI
;
1446 case 0b00001: /* YIELD */
1447 /* When running in MTTCG we don't generate jumps to the yield and
1448 * WFE helpers as it won't affect the scheduling of other vCPUs.
1449 * If we wanted to more completely model WFE/SEV so we don't busy
1450 * spin unnecessarily we would need to do something more involved.
1452 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1453 s
->base
.is_jmp
= DISAS_YIELD
;
1456 case 0b00010: /* WFE */
1457 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1458 s
->base
.is_jmp
= DISAS_WFE
;
1461 case 0b00100: /* SEV */
1462 case 0b00101: /* SEVL */
1463 /* we treat all as NOP at least for now */
1465 case 0b00111: /* XPACLRI */
1466 if (s
->pauth_active
) {
1467 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1470 case 0b01000: /* PACIA1716 */
1471 if (s
->pauth_active
) {
1472 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1475 case 0b01010: /* PACIB1716 */
1476 if (s
->pauth_active
) {
1477 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1480 case 0b01100: /* AUTIA1716 */
1481 if (s
->pauth_active
) {
1482 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1485 case 0b01110: /* AUTIB1716 */
1486 if (s
->pauth_active
) {
1487 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1490 case 0b11000: /* PACIAZ */
1491 if (s
->pauth_active
) {
1492 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1493 new_tmp_a64_zero(s
));
1496 case 0b11001: /* PACIASP */
1497 if (s
->pauth_active
) {
1498 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1501 case 0b11010: /* PACIBZ */
1502 if (s
->pauth_active
) {
1503 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1504 new_tmp_a64_zero(s
));
1507 case 0b11011: /* PACIBSP */
1508 if (s
->pauth_active
) {
1509 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1512 case 0b11100: /* AUTIAZ */
1513 if (s
->pauth_active
) {
1514 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1515 new_tmp_a64_zero(s
));
1518 case 0b11101: /* AUTIASP */
1519 if (s
->pauth_active
) {
1520 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1523 case 0b11110: /* AUTIBZ */
1524 if (s
->pauth_active
) {
1525 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1526 new_tmp_a64_zero(s
));
1529 case 0b11111: /* AUTIBSP */
1530 if (s
->pauth_active
) {
1531 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1535 /* default specified as NOP equivalent */
1540 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1542 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1545 /* CLREX, DSB, DMB, ISB */
1546 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1547 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1552 unallocated_encoding(s
);
1563 case 1: /* MBReqTypes_Reads */
1564 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1566 case 2: /* MBReqTypes_Writes */
1567 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1569 default: /* MBReqTypes_All */
1570 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1576 /* We need to break the TB after this insn to execute
1577 * a self-modified code correctly and also to take
1578 * any pending interrupts immediately.
1581 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1585 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1586 goto do_unallocated
;
1589 * TODO: There is no speculation barrier opcode for TCG;
1590 * MB and end the TB instead.
1592 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1593 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1598 unallocated_encoding(s
);
1603 static void gen_xaflag(void)
1605 TCGv_i32 z
= tcg_temp_new_i32();
1607 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1616 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1617 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1620 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1621 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1623 /* (!C & Z) << 31 -> -(Z & ~C) */
1624 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1625 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1628 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1630 tcg_temp_free_i32(z
);
1633 static void gen_axflag(void)
1635 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1636 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1638 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1639 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1641 tcg_gen_movi_i32(cpu_NF
, 0);
1642 tcg_gen_movi_i32(cpu_VF
, 0);
1645 /* MSR (immediate) - move immediate to processor state field */
1646 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1647 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1650 int op
= op1
<< 3 | op2
;
1652 /* End the TB by default, chaining is ok. */
1653 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1656 case 0x00: /* CFINV */
1657 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1658 goto do_unallocated
;
1660 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1661 s
->base
.is_jmp
= DISAS_NEXT
;
1664 case 0x01: /* XAFlag */
1665 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1666 goto do_unallocated
;
1669 s
->base
.is_jmp
= DISAS_NEXT
;
1672 case 0x02: /* AXFlag */
1673 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1674 goto do_unallocated
;
1677 s
->base
.is_jmp
= DISAS_NEXT
;
1680 case 0x03: /* UAO */
1681 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1682 goto do_unallocated
;
1685 set_pstate_bits(PSTATE_UAO
);
1687 clear_pstate_bits(PSTATE_UAO
);
1689 t1
= tcg_const_i32(s
->current_el
);
1690 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1691 tcg_temp_free_i32(t1
);
1694 case 0x04: /* PAN */
1695 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1696 goto do_unallocated
;
1699 set_pstate_bits(PSTATE_PAN
);
1701 clear_pstate_bits(PSTATE_PAN
);
1703 t1
= tcg_const_i32(s
->current_el
);
1704 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1705 tcg_temp_free_i32(t1
);
1708 case 0x05: /* SPSel */
1709 if (s
->current_el
== 0) {
1710 goto do_unallocated
;
1712 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1713 gen_helper_msr_i_spsel(cpu_env
, t1
);
1714 tcg_temp_free_i32(t1
);
1717 case 0x19: /* SSBS */
1718 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1719 goto do_unallocated
;
1722 set_pstate_bits(PSTATE_SSBS
);
1724 clear_pstate_bits(PSTATE_SSBS
);
1726 /* Don't need to rebuild hflags since SSBS is a nop */
1729 case 0x1a: /* DIT */
1730 if (!dc_isar_feature(aa64_dit
, s
)) {
1731 goto do_unallocated
;
1734 set_pstate_bits(PSTATE_DIT
);
1736 clear_pstate_bits(PSTATE_DIT
);
1738 /* There's no need to rebuild hflags because DIT is a nop */
1741 case 0x1e: /* DAIFSet */
1742 t1
= tcg_const_i32(crm
);
1743 gen_helper_msr_i_daifset(cpu_env
, t1
);
1744 tcg_temp_free_i32(t1
);
1747 case 0x1f: /* DAIFClear */
1748 t1
= tcg_const_i32(crm
);
1749 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1750 tcg_temp_free_i32(t1
);
1751 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1752 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1755 case 0x1c: /* TCO */
1756 if (dc_isar_feature(aa64_mte
, s
)) {
1757 /* Full MTE is enabled -- set the TCO bit as directed. */
1759 set_pstate_bits(PSTATE_TCO
);
1761 clear_pstate_bits(PSTATE_TCO
);
1763 t1
= tcg_const_i32(s
->current_el
);
1764 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1765 tcg_temp_free_i32(t1
);
1766 /* Many factors, including TCO, go into MTE_ACTIVE. */
1767 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1768 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1769 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1770 s
->base
.is_jmp
= DISAS_NEXT
;
1772 goto do_unallocated
;
1778 unallocated_encoding(s
);
1783 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1785 TCGv_i32 tmp
= tcg_temp_new_i32();
1786 TCGv_i32 nzcv
= tcg_temp_new_i32();
1788 /* build bit 31, N */
1789 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1790 /* build bit 30, Z */
1791 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1792 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1793 /* build bit 29, C */
1794 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1795 /* build bit 28, V */
1796 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1797 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1798 /* generate result */
1799 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1801 tcg_temp_free_i32(nzcv
);
1802 tcg_temp_free_i32(tmp
);
1805 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1807 TCGv_i32 nzcv
= tcg_temp_new_i32();
1809 /* take NZCV from R[t] */
1810 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1813 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1815 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1816 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1818 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1819 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1821 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1822 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1823 tcg_temp_free_i32(nzcv
);
1826 /* MRS - move from system register
1827 * MSR (register) - move to system register
1830 * These are all essentially the same insn in 'read' and 'write'
1831 * versions, with varying op0 fields.
1833 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1834 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1835 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1837 const ARMCPRegInfo
*ri
;
1840 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1841 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1842 crn
, crm
, op0
, op1
, op2
));
1845 /* Unknown register; this might be a guest error or a QEMU
1846 * unimplemented feature.
1848 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1849 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1850 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1851 unallocated_encoding(s
);
1855 /* Check access permissions */
1856 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1857 unallocated_encoding(s
);
1862 /* Emit code to perform further access permissions checks at
1863 * runtime; this may result in an exception.
1866 TCGv_i32 tcg_syn
, tcg_isread
;
1869 gen_a64_set_pc_im(s
->pc_curr
);
1870 tmpptr
= tcg_const_ptr(ri
);
1871 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1872 tcg_syn
= tcg_const_i32(syndrome
);
1873 tcg_isread
= tcg_const_i32(isread
);
1874 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1875 tcg_temp_free_ptr(tmpptr
);
1876 tcg_temp_free_i32(tcg_syn
);
1877 tcg_temp_free_i32(tcg_isread
);
1878 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1880 * The readfn or writefn might raise an exception;
1881 * synchronize the CPU state in case it does.
1883 gen_a64_set_pc_im(s
->pc_curr
);
1886 /* Handle special cases first */
1887 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1891 tcg_rt
= cpu_reg(s
, rt
);
1893 gen_get_nzcv(tcg_rt
);
1895 gen_set_nzcv(tcg_rt
);
1898 case ARM_CP_CURRENTEL
:
1899 /* Reads as current EL value from pstate, which is
1900 * guaranteed to be constant by the tb flags.
1902 tcg_rt
= cpu_reg(s
, rt
);
1903 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1906 /* Writes clear the aligned block of memory which rt points into. */
1907 if (s
->mte_active
[0]) {
1911 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1912 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1913 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1914 t_desc
= tcg_const_i32(desc
);
1916 tcg_rt
= new_tmp_a64(s
);
1917 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1918 tcg_temp_free_i32(t_desc
);
1920 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1922 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1926 TCGv_i64 clean_addr
, tag
;
1929 * DC_GVA, like DC_ZVA, requires that we supply the original
1930 * pointer for an invalid page. Probe that address first.
1932 tcg_rt
= cpu_reg(s
, rt
);
1933 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1934 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1937 /* Extract the tag from the register to match STZGM. */
1938 tag
= tcg_temp_new_i64();
1939 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1940 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1941 tcg_temp_free_i64(tag
);
1945 case ARM_CP_DC_GZVA
:
1947 TCGv_i64 clean_addr
, tag
;
1949 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1950 tcg_rt
= cpu_reg(s
, rt
);
1951 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1952 gen_helper_dc_zva(cpu_env
, clean_addr
);
1955 /* Extract the tag from the register to match STZGM. */
1956 tag
= tcg_temp_new_i64();
1957 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1958 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1959 tcg_temp_free_i64(tag
);
1966 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1968 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1972 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1976 tcg_rt
= cpu_reg(s
, rt
);
1979 if (ri
->type
& ARM_CP_CONST
) {
1980 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1981 } else if (ri
->readfn
) {
1983 tmpptr
= tcg_const_ptr(ri
);
1984 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1985 tcg_temp_free_ptr(tmpptr
);
1987 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1990 if (ri
->type
& ARM_CP_CONST
) {
1991 /* If not forbidden by access permissions, treat as WI */
1993 } else if (ri
->writefn
) {
1995 tmpptr
= tcg_const_ptr(ri
);
1996 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1997 tcg_temp_free_ptr(tmpptr
);
1999 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2003 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
2004 /* I/O operations must end the TB here (whether read or write) */
2005 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2007 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
2009 * A write to any coprocessor regiser that ends a TB
2010 * must rebuild the hflags for the next TB.
2012 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
2013 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
2014 tcg_temp_free_i32(tcg_el
);
2016 * We default to ending the TB on a coprocessor register write,
2017 * but allow this to be suppressed by the register definition
2018 * (usually only necessary to work around guest bugs).
2020 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2025 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2026 * +---------------------+---+-----+-----+-------+-------+-----+------+
2027 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2028 * +---------------------+---+-----+-----+-------+-------+-----+------+
2030 static void disas_system(DisasContext
*s
, uint32_t insn
)
2032 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2033 l
= extract32(insn
, 21, 1);
2034 op0
= extract32(insn
, 19, 2);
2035 op1
= extract32(insn
, 16, 3);
2036 crn
= extract32(insn
, 12, 4);
2037 crm
= extract32(insn
, 8, 4);
2038 op2
= extract32(insn
, 5, 3);
2039 rt
= extract32(insn
, 0, 5);
2042 if (l
|| rt
!= 31) {
2043 unallocated_encoding(s
);
2047 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2048 handle_hint(s
, insn
, op1
, op2
, crm
);
2050 case 3: /* CLREX, DSB, DMB, ISB */
2051 handle_sync(s
, insn
, op1
, op2
, crm
);
2053 case 4: /* MSR (immediate) */
2054 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2057 unallocated_encoding(s
);
2062 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2065 /* Exception generation
2067 * 31 24 23 21 20 5 4 2 1 0
2068 * +-----------------+-----+------------------------+-----+----+
2069 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2070 * +-----------------------+------------------------+----------+
2072 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2074 int opc
= extract32(insn
, 21, 3);
2075 int op2_ll
= extract32(insn
, 0, 5);
2076 int imm16
= extract32(insn
, 5, 16);
2081 /* For SVC, HVC and SMC we advance the single-step state
2082 * machine before taking the exception. This is architecturally
2083 * mandated, to ensure that single-stepping a system call
2084 * instruction works properly.
2089 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2090 syn_aa64_svc(imm16
), default_exception_el(s
));
2093 if (s
->current_el
== 0) {
2094 unallocated_encoding(s
);
2097 /* The pre HVC helper handles cases when HVC gets trapped
2098 * as an undefined insn by runtime configuration.
2100 gen_a64_set_pc_im(s
->pc_curr
);
2101 gen_helper_pre_hvc(cpu_env
);
2103 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2104 syn_aa64_hvc(imm16
), 2);
2107 if (s
->current_el
== 0) {
2108 unallocated_encoding(s
);
2111 gen_a64_set_pc_im(s
->pc_curr
);
2112 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2113 gen_helper_pre_smc(cpu_env
, tmp
);
2114 tcg_temp_free_i32(tmp
);
2116 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2117 syn_aa64_smc(imm16
), 3);
2120 unallocated_encoding(s
);
2126 unallocated_encoding(s
);
2130 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2134 unallocated_encoding(s
);
2137 /* HLT. This has two purposes.
2138 * Architecturally, it is an external halting debug instruction.
2139 * Since QEMU doesn't implement external debug, we treat this as
2140 * it is required for halting debug disabled: it will UNDEF.
2141 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2143 if (semihosting_enabled() && imm16
== 0xf000) {
2144 #ifndef CONFIG_USER_ONLY
2145 /* In system mode, don't allow userspace access to semihosting,
2146 * to provide some semblance of security (and for consistency
2147 * with our 32-bit semihosting).
2149 if (s
->current_el
== 0) {
2150 unsupported_encoding(s
, insn
);
2154 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2156 unsupported_encoding(s
, insn
);
2160 if (op2_ll
< 1 || op2_ll
> 3) {
2161 unallocated_encoding(s
);
2164 /* DCPS1, DCPS2, DCPS3 */
2165 unsupported_encoding(s
, insn
);
2168 unallocated_encoding(s
);
2173 /* Unconditional branch (register)
2174 * 31 25 24 21 20 16 15 10 9 5 4 0
2175 * +---------------+-------+-------+-------+------+-------+
2176 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2177 * +---------------+-------+-------+-------+------+-------+
2179 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2181 unsigned int opc
, op2
, op3
, rn
, op4
;
2182 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2186 opc
= extract32(insn
, 21, 4);
2187 op2
= extract32(insn
, 16, 5);
2188 op3
= extract32(insn
, 10, 6);
2189 rn
= extract32(insn
, 5, 5);
2190 op4
= extract32(insn
, 0, 5);
2193 goto do_unallocated
;
2205 goto do_unallocated
;
2207 dst
= cpu_reg(s
, rn
);
2212 if (!dc_isar_feature(aa64_pauth
, s
)) {
2213 goto do_unallocated
;
2217 if (rn
!= 0x1f || op4
!= 0x1f) {
2218 goto do_unallocated
;
2221 modifier
= cpu_X
[31];
2223 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2225 goto do_unallocated
;
2227 modifier
= new_tmp_a64_zero(s
);
2229 if (s
->pauth_active
) {
2230 dst
= new_tmp_a64(s
);
2232 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2234 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2237 dst
= cpu_reg(s
, rn
);
2242 goto do_unallocated
;
2244 gen_a64_set_pc(s
, dst
);
2245 /* BLR also needs to load return address */
2247 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2253 if (!dc_isar_feature(aa64_pauth
, s
)) {
2254 goto do_unallocated
;
2256 if ((op3
& ~1) != 2) {
2257 goto do_unallocated
;
2259 btype_mod
= opc
& 1;
2260 if (s
->pauth_active
) {
2261 dst
= new_tmp_a64(s
);
2262 modifier
= cpu_reg_sp(s
, op4
);
2264 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2266 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2269 dst
= cpu_reg(s
, rn
);
2271 gen_a64_set_pc(s
, dst
);
2272 /* BLRAA also needs to load return address */
2274 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2279 if (s
->current_el
== 0) {
2280 goto do_unallocated
;
2285 goto do_unallocated
;
2287 dst
= tcg_temp_new_i64();
2288 tcg_gen_ld_i64(dst
, cpu_env
,
2289 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2292 case 2: /* ERETAA */
2293 case 3: /* ERETAB */
2294 if (!dc_isar_feature(aa64_pauth
, s
)) {
2295 goto do_unallocated
;
2297 if (rn
!= 0x1f || op4
!= 0x1f) {
2298 goto do_unallocated
;
2300 dst
= tcg_temp_new_i64();
2301 tcg_gen_ld_i64(dst
, cpu_env
,
2302 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2303 if (s
->pauth_active
) {
2304 modifier
= cpu_X
[31];
2306 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2308 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2314 goto do_unallocated
;
2316 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2320 gen_helper_exception_return(cpu_env
, dst
);
2321 tcg_temp_free_i64(dst
);
2322 /* Must exit loop to check un-masked IRQs */
2323 s
->base
.is_jmp
= DISAS_EXIT
;
2327 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2328 goto do_unallocated
;
2330 unsupported_encoding(s
, insn
);
2336 unallocated_encoding(s
);
2340 switch (btype_mod
) {
2342 if (dc_isar_feature(aa64_bti
, s
)) {
2343 /* BR to {x16,x17} or !guard -> 1, else 3. */
2344 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2349 if (dc_isar_feature(aa64_bti
, s
)) {
2350 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2355 default: /* RET or none of the above. */
2356 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2360 s
->base
.is_jmp
= DISAS_JUMP
;
2363 /* Branches, exception generating and system instructions */
2364 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2366 switch (extract32(insn
, 25, 7)) {
2367 case 0x0a: case 0x0b:
2368 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2369 disas_uncond_b_imm(s
, insn
);
2371 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2372 disas_comp_b_imm(s
, insn
);
2374 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2375 disas_test_b_imm(s
, insn
);
2377 case 0x2a: /* Conditional branch (immediate) */
2378 disas_cond_b_imm(s
, insn
);
2380 case 0x6a: /* Exception generation / System */
2381 if (insn
& (1 << 24)) {
2382 if (extract32(insn
, 22, 2) == 0) {
2383 disas_system(s
, insn
);
2385 unallocated_encoding(s
);
2391 case 0x6b: /* Unconditional branch (register) */
2392 disas_uncond_b_reg(s
, insn
);
2395 unallocated_encoding(s
);
2401 * Load/Store exclusive instructions are implemented by remembering
2402 * the value/address loaded, and seeing if these are the same
2403 * when the store is performed. This is not actually the architecturally
2404 * mandated semantics, but it works for typical guest code sequences
2405 * and avoids having to monitor regular stores.
2407 * The store exclusive uses the atomic cmpxchg primitives to avoid
2408 * races in multi-threaded linux-user and when MTTCG softmmu is
2411 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2412 TCGv_i64 addr
, int size
, bool is_pair
)
2414 int idx
= get_mem_index(s
);
2415 MemOp memop
= s
->be_data
;
2417 g_assert(size
<= 3);
2419 g_assert(size
>= 2);
2421 /* The pair must be single-copy atomic for the doubleword. */
2422 memop
|= MO_64
| MO_ALIGN
;
2423 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2424 if (s
->be_data
== MO_LE
) {
2425 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2426 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2428 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2429 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2432 /* The pair must be single-copy atomic for *each* doubleword, not
2433 the entire quadword, however it must be quadword aligned. */
2435 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2436 memop
| MO_ALIGN_16
);
2438 TCGv_i64 addr2
= tcg_temp_new_i64();
2439 tcg_gen_addi_i64(addr2
, addr
, 8);
2440 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2441 tcg_temp_free_i64(addr2
);
2443 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2444 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2447 memop
|= size
| MO_ALIGN
;
2448 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2449 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2451 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2454 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2455 TCGv_i64 addr
, int size
, int is_pair
)
2457 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2458 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2461 * [addr + datasize] = {Rt2};
2467 * env->exclusive_addr = -1;
2469 TCGLabel
*fail_label
= gen_new_label();
2470 TCGLabel
*done_label
= gen_new_label();
2473 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2475 tmp
= tcg_temp_new_i64();
2478 if (s
->be_data
== MO_LE
) {
2479 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2481 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2483 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2484 cpu_exclusive_val
, tmp
,
2486 MO_64
| MO_ALIGN
| s
->be_data
);
2487 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2488 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2489 if (!HAVE_CMPXCHG128
) {
2490 gen_helper_exit_atomic(cpu_env
);
2491 s
->base
.is_jmp
= DISAS_NORETURN
;
2492 } else if (s
->be_data
== MO_LE
) {
2493 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2498 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2503 } else if (s
->be_data
== MO_LE
) {
2504 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2505 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2507 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2508 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2511 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2512 cpu_reg(s
, rt
), get_mem_index(s
),
2513 size
| MO_ALIGN
| s
->be_data
);
2514 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2516 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2517 tcg_temp_free_i64(tmp
);
2518 tcg_gen_br(done_label
);
2520 gen_set_label(fail_label
);
2521 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2522 gen_set_label(done_label
);
2523 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2526 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2529 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2530 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2531 int memidx
= get_mem_index(s
);
2532 TCGv_i64 clean_addr
;
2535 gen_check_sp_alignment(s
);
2537 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2538 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2539 size
| MO_ALIGN
| s
->be_data
);
2542 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2545 TCGv_i64 s1
= cpu_reg(s
, rs
);
2546 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2547 TCGv_i64 t1
= cpu_reg(s
, rt
);
2548 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2549 TCGv_i64 clean_addr
;
2550 int memidx
= get_mem_index(s
);
2553 gen_check_sp_alignment(s
);
2556 /* This is a single atomic access, despite the "pair". */
2557 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2560 TCGv_i64 cmp
= tcg_temp_new_i64();
2561 TCGv_i64 val
= tcg_temp_new_i64();
2563 if (s
->be_data
== MO_LE
) {
2564 tcg_gen_concat32_i64(val
, t1
, t2
);
2565 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2567 tcg_gen_concat32_i64(val
, t2
, t1
);
2568 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2571 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2572 MO_64
| MO_ALIGN
| s
->be_data
);
2573 tcg_temp_free_i64(val
);
2575 if (s
->be_data
== MO_LE
) {
2576 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2578 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2580 tcg_temp_free_i64(cmp
);
2581 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2582 if (HAVE_CMPXCHG128
) {
2583 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2584 if (s
->be_data
== MO_LE
) {
2585 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2586 clean_addr
, t1
, t2
);
2588 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2589 clean_addr
, t1
, t2
);
2591 tcg_temp_free_i32(tcg_rs
);
2593 gen_helper_exit_atomic(cpu_env
);
2594 s
->base
.is_jmp
= DISAS_NORETURN
;
2597 TCGv_i64 d1
= tcg_temp_new_i64();
2598 TCGv_i64 d2
= tcg_temp_new_i64();
2599 TCGv_i64 a2
= tcg_temp_new_i64();
2600 TCGv_i64 c1
= tcg_temp_new_i64();
2601 TCGv_i64 c2
= tcg_temp_new_i64();
2602 TCGv_i64 zero
= tcg_const_i64(0);
2604 /* Load the two words, in memory order. */
2605 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2606 MO_64
| MO_ALIGN_16
| s
->be_data
);
2607 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2608 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2610 /* Compare the two words, also in memory order. */
2611 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2612 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2613 tcg_gen_and_i64(c2
, c2
, c1
);
2615 /* If compare equal, write back new data, else write back old data. */
2616 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2617 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2618 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2619 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2620 tcg_temp_free_i64(a2
);
2621 tcg_temp_free_i64(c1
);
2622 tcg_temp_free_i64(c2
);
2623 tcg_temp_free_i64(zero
);
2625 /* Write back the data from memory to Rs. */
2626 tcg_gen_mov_i64(s1
, d1
);
2627 tcg_gen_mov_i64(s2
, d2
);
2628 tcg_temp_free_i64(d1
);
2629 tcg_temp_free_i64(d2
);
2633 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2634 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2636 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2638 int opc0
= extract32(opc
, 0, 1);
2642 regsize
= opc0
? 32 : 64;
2644 regsize
= size
== 3 ? 64 : 32;
2646 return regsize
== 64;
2649 /* Load/store exclusive
2651 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2652 * +-----+-------------+----+---+----+------+----+-------+------+------+
2653 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2654 * +-----+-------------+----+---+----+------+----+-------+------+------+
2656 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2657 * L: 0 -> store, 1 -> load
2658 * o2: 0 -> exclusive, 1 -> not
2659 * o1: 0 -> single register, 1 -> register pair
2660 * o0: 1 -> load-acquire/store-release, 0 -> not
2662 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2664 int rt
= extract32(insn
, 0, 5);
2665 int rn
= extract32(insn
, 5, 5);
2666 int rt2
= extract32(insn
, 10, 5);
2667 int rs
= extract32(insn
, 16, 5);
2668 int is_lasr
= extract32(insn
, 15, 1);
2669 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2670 int size
= extract32(insn
, 30, 2);
2671 TCGv_i64 clean_addr
;
2673 switch (o2_L_o1_o0
) {
2674 case 0x0: /* STXR */
2675 case 0x1: /* STLXR */
2677 gen_check_sp_alignment(s
);
2680 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2682 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2683 true, rn
!= 31, size
);
2684 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2687 case 0x4: /* LDXR */
2688 case 0x5: /* LDAXR */
2690 gen_check_sp_alignment(s
);
2692 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2693 false, rn
!= 31, size
);
2695 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2697 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2701 case 0x8: /* STLLR */
2702 if (!dc_isar_feature(aa64_lor
, s
)) {
2705 /* StoreLORelease is the same as Store-Release for QEMU. */
2707 case 0x9: /* STLR */
2708 /* Generate ISS for non-exclusive accesses including LASR. */
2710 gen_check_sp_alignment(s
);
2712 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2713 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2714 true, rn
!= 31, size
);
2715 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2716 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2717 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2720 case 0xc: /* LDLAR */
2721 if (!dc_isar_feature(aa64_lor
, s
)) {
2724 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2726 case 0xd: /* LDAR */
2727 /* Generate ISS for non-exclusive accesses including LASR. */
2729 gen_check_sp_alignment(s
);
2731 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2732 false, rn
!= 31, size
);
2733 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2734 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2735 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2736 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2739 case 0x2: case 0x3: /* CASP / STXP */
2740 if (size
& 2) { /* STXP / STLXP */
2742 gen_check_sp_alignment(s
);
2745 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2747 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2748 true, rn
!= 31, size
);
2749 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2753 && ((rt
| rs
) & 1) == 0
2754 && dc_isar_feature(aa64_atomics
, s
)) {
2756 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2761 case 0x6: case 0x7: /* CASPA / LDXP */
2762 if (size
& 2) { /* LDXP / LDAXP */
2764 gen_check_sp_alignment(s
);
2766 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2767 false, rn
!= 31, size
);
2769 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2771 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2776 && ((rt
| rs
) & 1) == 0
2777 && dc_isar_feature(aa64_atomics
, s
)) {
2778 /* CASPA / CASPAL */
2779 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2785 case 0xb: /* CASL */
2786 case 0xe: /* CASA */
2787 case 0xf: /* CASAL */
2788 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2789 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2794 unallocated_encoding(s
);
2798 * Load register (literal)
2800 * 31 30 29 27 26 25 24 23 5 4 0
2801 * +-----+-------+---+-----+-------------------+-------+
2802 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2803 * +-----+-------+---+-----+-------------------+-------+
2805 * V: 1 -> vector (simd/fp)
2806 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2807 * 10-> 32 bit signed, 11 -> prefetch
2808 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2810 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2812 int rt
= extract32(insn
, 0, 5);
2813 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2814 bool is_vector
= extract32(insn
, 26, 1);
2815 int opc
= extract32(insn
, 30, 2);
2816 bool is_signed
= false;
2818 TCGv_i64 tcg_rt
, clean_addr
;
2822 unallocated_encoding(s
);
2826 if (!fp_access_check(s
)) {
2831 /* PRFM (literal) : prefetch */
2834 size
= 2 + extract32(opc
, 0, 1);
2835 is_signed
= extract32(opc
, 1, 1);
2838 tcg_rt
= cpu_reg(s
, rt
);
2840 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2842 do_fp_ld(s
, rt
, clean_addr
, size
);
2844 /* Only unsigned 32bit loads target 32bit registers. */
2845 bool iss_sf
= opc
!= 0;
2847 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2848 false, true, rt
, iss_sf
, false);
2850 tcg_temp_free_i64(clean_addr
);
2854 * LDNP (Load Pair - non-temporal hint)
2855 * LDP (Load Pair - non vector)
2856 * LDPSW (Load Pair Signed Word - non vector)
2857 * STNP (Store Pair - non-temporal hint)
2858 * STP (Store Pair - non vector)
2859 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2860 * LDP (Load Pair of SIMD&FP)
2861 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2862 * STP (Store Pair of SIMD&FP)
2864 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2865 * +-----+-------+---+---+-------+---+-----------------------------+
2866 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2867 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2869 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2871 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2872 * V: 0 -> GPR, 1 -> Vector
2873 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2874 * 10 -> signed offset, 11 -> pre-index
2875 * L: 0 -> Store 1 -> Load
2877 * Rt, Rt2 = GPR or SIMD registers to be stored
2878 * Rn = general purpose register containing address
2879 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2881 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2883 int rt
= extract32(insn
, 0, 5);
2884 int rn
= extract32(insn
, 5, 5);
2885 int rt2
= extract32(insn
, 10, 5);
2886 uint64_t offset
= sextract64(insn
, 15, 7);
2887 int index
= extract32(insn
, 23, 2);
2888 bool is_vector
= extract32(insn
, 26, 1);
2889 bool is_load
= extract32(insn
, 22, 1);
2890 int opc
= extract32(insn
, 30, 2);
2892 bool is_signed
= false;
2893 bool postindex
= false;
2895 bool set_tag
= false;
2897 TCGv_i64 clean_addr
, dirty_addr
;
2902 unallocated_encoding(s
);
2908 } else if (opc
== 1 && !is_load
) {
2910 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2911 unallocated_encoding(s
);
2917 size
= 2 + extract32(opc
, 1, 1);
2918 is_signed
= extract32(opc
, 0, 1);
2919 if (!is_load
&& is_signed
) {
2920 unallocated_encoding(s
);
2926 case 1: /* post-index */
2931 /* signed offset with "non-temporal" hint. Since we don't emulate
2932 * caches we don't care about hints to the cache system about
2933 * data access patterns, and handle this identically to plain
2937 /* There is no non-temporal-hint version of LDPSW */
2938 unallocated_encoding(s
);
2943 case 2: /* signed offset, rn not updated */
2946 case 3: /* pre-index */
2952 if (is_vector
&& !fp_access_check(s
)) {
2956 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2959 gen_check_sp_alignment(s
);
2962 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2964 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2970 * TODO: We could rely on the stores below, at least for
2971 * system mode, if we arrange to add MO_ALIGN_16.
2973 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2974 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2975 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2977 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2981 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2982 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
2986 do_fp_ld(s
, rt
, clean_addr
, size
);
2988 do_fp_st(s
, rt
, clean_addr
, size
);
2990 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2992 do_fp_ld(s
, rt2
, clean_addr
, size
);
2994 do_fp_st(s
, rt2
, clean_addr
, size
);
2997 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2998 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
3001 TCGv_i64 tmp
= tcg_temp_new_i64();
3003 /* Do not modify tcg_rt before recognizing any exception
3004 * from the second load.
3006 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3007 false, false, 0, false, false);
3008 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3009 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3010 false, false, 0, false, false);
3012 tcg_gen_mov_i64(tcg_rt
, tmp
);
3013 tcg_temp_free_i64(tmp
);
3015 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3016 false, 0, false, false);
3017 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3018 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3019 false, 0, false, false);
3025 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3027 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3032 * Load/store (immediate post-indexed)
3033 * Load/store (immediate pre-indexed)
3034 * Load/store (unscaled immediate)
3036 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3037 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3038 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3039 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3041 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3043 * V = 0 -> non-vector
3044 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3045 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3047 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3053 int rn
= extract32(insn
, 5, 5);
3054 int imm9
= sextract32(insn
, 12, 9);
3055 int idx
= extract32(insn
, 10, 2);
3056 bool is_signed
= false;
3057 bool is_store
= false;
3058 bool is_extended
= false;
3059 bool is_unpriv
= (idx
== 2);
3060 bool iss_valid
= !is_vector
;
3065 TCGv_i64 clean_addr
, dirty_addr
;
3068 size
|= (opc
& 2) << 1;
3069 if (size
> 4 || is_unpriv
) {
3070 unallocated_encoding(s
);
3073 is_store
= ((opc
& 1) == 0);
3074 if (!fp_access_check(s
)) {
3078 if (size
== 3 && opc
== 2) {
3079 /* PRFM - prefetch */
3081 unallocated_encoding(s
);
3086 if (opc
== 3 && size
> 1) {
3087 unallocated_encoding(s
);
3090 is_store
= (opc
== 0);
3091 is_signed
= extract32(opc
, 1, 1);
3092 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3110 g_assert_not_reached();
3114 gen_check_sp_alignment(s
);
3117 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3119 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3122 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3123 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3124 writeback
|| rn
!= 31,
3125 size
, is_unpriv
, memidx
);
3129 do_fp_st(s
, rt
, clean_addr
, size
);
3131 do_fp_ld(s
, rt
, clean_addr
, size
);
3134 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3135 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3138 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3139 iss_valid
, rt
, iss_sf
, false);
3141 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3142 is_extended
, memidx
,
3143 iss_valid
, rt
, iss_sf
, false);
3148 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3150 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3152 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3157 * Load/store (register offset)
3159 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3160 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3161 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3162 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3165 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3166 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3168 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3169 * opc<0>: 0 -> store, 1 -> load
3170 * V: 1 -> vector/simd
3171 * opt: extend encoding (see DecodeRegExtend)
3172 * S: if S=1 then scale (essentially index by sizeof(size))
3173 * Rt: register to transfer into/out of
3174 * Rn: address register or SP for base
3175 * Rm: offset register or ZR for offset
3177 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3183 int rn
= extract32(insn
, 5, 5);
3184 int shift
= extract32(insn
, 12, 1);
3185 int rm
= extract32(insn
, 16, 5);
3186 int opt
= extract32(insn
, 13, 3);
3187 bool is_signed
= false;
3188 bool is_store
= false;
3189 bool is_extended
= false;
3191 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3193 if (extract32(opt
, 1, 1) == 0) {
3194 unallocated_encoding(s
);
3199 size
|= (opc
& 2) << 1;
3201 unallocated_encoding(s
);
3204 is_store
= !extract32(opc
, 0, 1);
3205 if (!fp_access_check(s
)) {
3209 if (size
== 3 && opc
== 2) {
3210 /* PRFM - prefetch */
3213 if (opc
== 3 && size
> 1) {
3214 unallocated_encoding(s
);
3217 is_store
= (opc
== 0);
3218 is_signed
= extract32(opc
, 1, 1);
3219 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3223 gen_check_sp_alignment(s
);
3225 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3227 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3228 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3230 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3231 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3235 do_fp_st(s
, rt
, clean_addr
, size
);
3237 do_fp_ld(s
, rt
, clean_addr
, size
);
3240 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3241 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3243 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3244 true, rt
, iss_sf
, false);
3246 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3247 is_extended
, true, rt
, iss_sf
, false);
3253 * Load/store (unsigned immediate)
3255 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3256 * +----+-------+---+-----+-----+------------+-------+------+
3257 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3258 * +----+-------+---+-----+-----+------------+-------+------+
3261 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3262 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3264 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3265 * opc<0>: 0 -> store, 1 -> load
3266 * Rn: base address register (inc SP)
3267 * Rt: target register
3269 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3275 int rn
= extract32(insn
, 5, 5);
3276 unsigned int imm12
= extract32(insn
, 10, 12);
3277 unsigned int offset
;
3279 TCGv_i64 clean_addr
, dirty_addr
;
3282 bool is_signed
= false;
3283 bool is_extended
= false;
3286 size
|= (opc
& 2) << 1;
3288 unallocated_encoding(s
);
3291 is_store
= !extract32(opc
, 0, 1);
3292 if (!fp_access_check(s
)) {
3296 if (size
== 3 && opc
== 2) {
3297 /* PRFM - prefetch */
3300 if (opc
== 3 && size
> 1) {
3301 unallocated_encoding(s
);
3304 is_store
= (opc
== 0);
3305 is_signed
= extract32(opc
, 1, 1);
3306 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3310 gen_check_sp_alignment(s
);
3312 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3313 offset
= imm12
<< size
;
3314 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3315 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3319 do_fp_st(s
, rt
, clean_addr
, size
);
3321 do_fp_ld(s
, rt
, clean_addr
, size
);
3324 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3325 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3327 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3328 true, rt
, iss_sf
, false);
3330 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3331 is_extended
, true, rt
, iss_sf
, false);
3336 /* Atomic memory operations
3338 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3339 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3340 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3341 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3343 * Rt: the result register
3344 * Rn: base address or SP
3345 * Rs: the source register for the operation
3346 * V: vector flag (always 0 as of v8.3)
3350 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3351 int size
, int rt
, bool is_vector
)
3353 int rs
= extract32(insn
, 16, 5);
3354 int rn
= extract32(insn
, 5, 5);
3355 int o3_opc
= extract32(insn
, 12, 4);
3356 bool r
= extract32(insn
, 22, 1);
3357 bool a
= extract32(insn
, 23, 1);
3358 TCGv_i64 tcg_rs
, tcg_rt
, clean_addr
;
3359 AtomicThreeOpFn
*fn
= NULL
;
3360 MemOp mop
= s
->be_data
| size
| MO_ALIGN
;
3362 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3363 unallocated_encoding(s
);
3367 case 000: /* LDADD */
3368 fn
= tcg_gen_atomic_fetch_add_i64
;
3370 case 001: /* LDCLR */
3371 fn
= tcg_gen_atomic_fetch_and_i64
;
3373 case 002: /* LDEOR */
3374 fn
= tcg_gen_atomic_fetch_xor_i64
;
3376 case 003: /* LDSET */
3377 fn
= tcg_gen_atomic_fetch_or_i64
;
3379 case 004: /* LDSMAX */
3380 fn
= tcg_gen_atomic_fetch_smax_i64
;
3383 case 005: /* LDSMIN */
3384 fn
= tcg_gen_atomic_fetch_smin_i64
;
3387 case 006: /* LDUMAX */
3388 fn
= tcg_gen_atomic_fetch_umax_i64
;
3390 case 007: /* LDUMIN */
3391 fn
= tcg_gen_atomic_fetch_umin_i64
;
3394 fn
= tcg_gen_atomic_xchg_i64
;
3396 case 014: /* LDAPR, LDAPRH, LDAPRB */
3397 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3398 rs
!= 31 || a
!= 1 || r
!= 0) {
3399 unallocated_encoding(s
);
3404 unallocated_encoding(s
);
3409 gen_check_sp_alignment(s
);
3411 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3413 if (o3_opc
== 014) {
3415 * LDAPR* are a special case because they are a simple load, not a
3416 * fetch-and-do-something op.
3417 * The architectural consistency requirements here are weaker than
3418 * full load-acquire (we only need "load-acquire processor consistent"),
3419 * but we choose to implement them as full LDAQ.
3421 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3422 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3423 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3427 tcg_rs
= read_cpu_reg(s
, rs
, true);
3428 tcg_rt
= cpu_reg(s
, rt
);
3430 if (o3_opc
== 1) { /* LDCLR */
3431 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3434 /* The tcg atomic primitives are all full barriers. Therefore we
3435 * can ignore the Acquire and Release bits of this instruction.
3437 fn(tcg_rt
, clean_addr
, tcg_rs
, get_mem_index(s
), mop
);
3439 if ((mop
& MO_SIGN
) && size
!= MO_64
) {
3440 tcg_gen_ext32u_i64(tcg_rt
, tcg_rt
);
3445 * PAC memory operations
3447 * 31 30 27 26 24 22 21 12 11 10 5 0
3448 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3449 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3450 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3452 * Rt: the result register
3453 * Rn: base address or SP
3454 * V: vector flag (always 0 as of v8.3)
3455 * M: clear for key DA, set for key DB
3456 * W: pre-indexing flag
3459 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3460 int size
, int rt
, bool is_vector
)
3462 int rn
= extract32(insn
, 5, 5);
3463 bool is_wback
= extract32(insn
, 11, 1);
3464 bool use_key_a
= !extract32(insn
, 23, 1);
3466 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3468 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3469 unallocated_encoding(s
);
3474 gen_check_sp_alignment(s
);
3476 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3478 if (s
->pauth_active
) {
3480 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3481 new_tmp_a64_zero(s
));
3483 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3484 new_tmp_a64_zero(s
));
3488 /* Form the 10-bit signed, scaled offset. */
3489 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3490 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3491 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3493 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3494 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3495 is_wback
|| rn
!= 31, size
);
3497 tcg_rt
= cpu_reg(s
, rt
);
3498 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3499 /* extend */ false, /* iss_valid */ !is_wback
,
3500 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3503 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3508 * LDAPR/STLR (unscaled immediate)
3510 * 31 30 24 22 21 12 10 5 0
3511 * +------+-------------+-----+---+--------+-----+----+-----+
3512 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3513 * +------+-------------+-----+---+--------+-----+----+-----+
3515 * Rt: source or destination register
3517 * imm9: unscaled immediate offset
3518 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3519 * size: size of load/store
3521 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3523 int rt
= extract32(insn
, 0, 5);
3524 int rn
= extract32(insn
, 5, 5);
3525 int offset
= sextract32(insn
, 12, 9);
3526 int opc
= extract32(insn
, 22, 2);
3527 int size
= extract32(insn
, 30, 2);
3528 TCGv_i64 clean_addr
, dirty_addr
;
3529 bool is_store
= false;
3530 bool extend
= false;
3534 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3535 unallocated_encoding(s
);
3539 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3540 mop
= size
| MO_ALIGN
;
3543 case 0: /* STLURB */
3546 case 1: /* LDAPUR* */
3548 case 2: /* LDAPURS* 64-bit variant */
3550 unallocated_encoding(s
);
3555 case 3: /* LDAPURS* 32-bit variant */
3557 unallocated_encoding(s
);
3561 extend
= true; /* zero-extend 32->64 after signed load */
3564 g_assert_not_reached();
3567 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3570 gen_check_sp_alignment(s
);
3573 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3574 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3575 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3578 /* Store-Release semantics */
3579 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3580 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3583 * Load-AcquirePC semantics; we implement as the slightly more
3584 * restrictive Load-Acquire.
3586 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3587 extend
, true, rt
, iss_sf
, true);
3588 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3592 /* Load/store register (all forms) */
3593 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3595 int rt
= extract32(insn
, 0, 5);
3596 int opc
= extract32(insn
, 22, 2);
3597 bool is_vector
= extract32(insn
, 26, 1);
3598 int size
= extract32(insn
, 30, 2);
3600 switch (extract32(insn
, 24, 2)) {
3602 if (extract32(insn
, 21, 1) == 0) {
3603 /* Load/store register (unscaled immediate)
3604 * Load/store immediate pre/post-indexed
3605 * Load/store register unprivileged
3607 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3610 switch (extract32(insn
, 10, 2)) {
3612 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3615 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3618 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3623 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3626 unallocated_encoding(s
);
3629 /* AdvSIMD load/store multiple structures
3631 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3632 * +---+---+---------------+---+-------------+--------+------+------+------+
3633 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3634 * +---+---+---------------+---+-------------+--------+------+------+------+
3636 * AdvSIMD load/store multiple structures (post-indexed)
3638 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3639 * +---+---+---------------+---+---+---------+--------+------+------+------+
3640 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3641 * +---+---+---------------+---+---+---------+--------+------+------+------+
3643 * Rt: first (or only) SIMD&FP register to be transferred
3644 * Rn: base address or SP
3645 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3647 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3649 int rt
= extract32(insn
, 0, 5);
3650 int rn
= extract32(insn
, 5, 5);
3651 int rm
= extract32(insn
, 16, 5);
3652 int size
= extract32(insn
, 10, 2);
3653 int opcode
= extract32(insn
, 12, 4);
3654 bool is_store
= !extract32(insn
, 22, 1);
3655 bool is_postidx
= extract32(insn
, 23, 1);
3656 bool is_q
= extract32(insn
, 30, 1);
3657 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3658 MemOp endian
, align
, mop
;
3660 int total
; /* total bytes */
3661 int elements
; /* elements per vector */
3662 int rpt
; /* num iterations */
3663 int selem
; /* structure elements */
3666 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3667 unallocated_encoding(s
);
3671 if (!is_postidx
&& rm
!= 0) {
3672 unallocated_encoding(s
);
3676 /* From the shared decode logic */
3707 unallocated_encoding(s
);
3711 if (size
== 3 && !is_q
&& selem
!= 1) {
3713 unallocated_encoding(s
);
3717 if (!fp_access_check(s
)) {
3722 gen_check_sp_alignment(s
);
3725 /* For our purposes, bytes are always little-endian. */
3726 endian
= s
->be_data
;
3731 total
= rpt
* selem
* (is_q
? 16 : 8);
3732 tcg_rn
= cpu_reg_sp(s
, rn
);
3735 * Issue the MTE check vs the logical repeat count, before we
3736 * promote consecutive little-endian elements below.
3738 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3742 * Consecutive little-endian elements from a single register
3743 * can be promoted to a larger little-endian operation.
3746 if (selem
== 1 && endian
== MO_LE
) {
3747 align
= pow2_align(size
);
3750 if (!s
->align_mem
) {
3753 mop
= endian
| size
| align
;
3755 elements
= (is_q
? 16 : 8) >> size
;
3756 tcg_ebytes
= tcg_const_i64(1 << size
);
3757 for (r
= 0; r
< rpt
; r
++) {
3759 for (e
= 0; e
< elements
; e
++) {
3761 for (xs
= 0; xs
< selem
; xs
++) {
3762 int tt
= (rt
+ r
+ xs
) % 32;
3764 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3766 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3768 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3772 tcg_temp_free_i64(tcg_ebytes
);
3775 /* For non-quad operations, setting a slice of the low
3776 * 64 bits of the register clears the high 64 bits (in
3777 * the ARM ARM pseudocode this is implicit in the fact
3778 * that 'rval' is a 64 bit wide variable).
3779 * For quad operations, we might still need to zero the
3782 for (r
= 0; r
< rpt
* selem
; r
++) {
3783 int tt
= (rt
+ r
) % 32;
3784 clear_vec_high(s
, is_q
, tt
);
3790 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3792 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3797 /* AdvSIMD load/store single structure
3799 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3800 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3801 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3802 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3804 * AdvSIMD load/store single structure (post-indexed)
3806 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3807 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3808 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3809 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3811 * Rt: first (or only) SIMD&FP register to be transferred
3812 * Rn: base address or SP
3813 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3814 * index = encoded in Q:S:size dependent on size
3816 * lane_size = encoded in R, opc
3817 * transfer width = encoded in opc, S, size
3819 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3821 int rt
= extract32(insn
, 0, 5);
3822 int rn
= extract32(insn
, 5, 5);
3823 int rm
= extract32(insn
, 16, 5);
3824 int size
= extract32(insn
, 10, 2);
3825 int S
= extract32(insn
, 12, 1);
3826 int opc
= extract32(insn
, 13, 3);
3827 int R
= extract32(insn
, 21, 1);
3828 int is_load
= extract32(insn
, 22, 1);
3829 int is_postidx
= extract32(insn
, 23, 1);
3830 int is_q
= extract32(insn
, 30, 1);
3832 int scale
= extract32(opc
, 1, 2);
3833 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3834 bool replicate
= false;
3835 int index
= is_q
<< 3 | S
<< 2 | size
;
3837 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3840 if (extract32(insn
, 31, 1)) {
3841 unallocated_encoding(s
);
3844 if (!is_postidx
&& rm
!= 0) {
3845 unallocated_encoding(s
);
3851 if (!is_load
|| S
) {
3852 unallocated_encoding(s
);
3861 if (extract32(size
, 0, 1)) {
3862 unallocated_encoding(s
);
3868 if (extract32(size
, 1, 1)) {
3869 unallocated_encoding(s
);
3872 if (!extract32(size
, 0, 1)) {
3876 unallocated_encoding(s
);
3884 g_assert_not_reached();
3887 if (!fp_access_check(s
)) {
3892 gen_check_sp_alignment(s
);
3895 total
= selem
<< scale
;
3896 tcg_rn
= cpu_reg_sp(s
, rn
);
3898 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3900 mop
= finalize_memop(s
, scale
);
3902 tcg_ebytes
= tcg_const_i64(1 << scale
);
3903 for (xs
= 0; xs
< selem
; xs
++) {
3905 /* Load and replicate to all elements */
3906 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3908 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3909 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3910 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3912 tcg_temp_free_i64(tcg_tmp
);
3914 /* Load/store one element per register */
3916 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3918 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3921 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3924 tcg_temp_free_i64(tcg_ebytes
);
3928 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3930 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3936 * Load/Store memory tags
3938 * 31 30 29 24 22 21 12 10 5 0
3939 * +-----+-------------+-----+---+------+-----+------+------+
3940 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3941 * +-----+-------------+-----+---+------+-----+------+------+
3943 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3945 int rt
= extract32(insn
, 0, 5);
3946 int rn
= extract32(insn
, 5, 5);
3947 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3948 int op2
= extract32(insn
, 10, 2);
3949 int op1
= extract32(insn
, 22, 2);
3950 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3952 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3954 /* We checked insn bits [29:24,21] in the caller. */
3955 if (extract32(insn
, 30, 2) != 3) {
3956 goto do_unallocated
;
3960 * @index is a tri-state variable which has 3 states:
3961 * < 0 : post-index, writeback
3962 * = 0 : signed offset
3963 * > 0 : pre-index, writeback
3972 if (s
->current_el
== 0 || offset
!= 0) {
3973 goto do_unallocated
;
3975 is_mult
= is_zero
= true;
3995 if (s
->current_el
== 0 || offset
!= 0) {
3996 goto do_unallocated
;
4004 is_pair
= is_zero
= true;
4008 if (s
->current_el
== 0 || offset
!= 0) {
4009 goto do_unallocated
;
4011 is_mult
= is_load
= true;
4017 unallocated_encoding(s
);
4022 ? !dc_isar_feature(aa64_mte
, s
)
4023 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4024 goto do_unallocated
;
4028 gen_check_sp_alignment(s
);
4031 addr
= read_cpu_reg_sp(s
, rn
, true);
4033 /* pre-index or signed offset */
4034 tcg_gen_addi_i64(addr
, addr
, offset
);
4038 tcg_rt
= cpu_reg(s
, rt
);
4041 int size
= 4 << s
->dcz_blocksize
;
4044 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4047 * The non-tags portion of STZGM is mostly like DC_ZVA,
4048 * except the alignment happens before the access.
4050 clean_addr
= clean_data_tbi(s
, addr
);
4051 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4052 gen_helper_dc_zva(cpu_env
, clean_addr
);
4053 } else if (s
->ata
) {
4055 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4057 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4060 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4061 int size
= 4 << GMID_EL1_BS
;
4063 clean_addr
= clean_data_tbi(s
, addr
);
4064 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4065 gen_probe_access(s
, clean_addr
, acc
, size
);
4068 /* The result tags are zeros. */
4069 tcg_gen_movi_i64(tcg_rt
, 0);
4076 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4077 tcg_rt
= cpu_reg(s
, rt
);
4079 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4081 clean_addr
= clean_data_tbi(s
, addr
);
4082 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4083 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4086 tcg_rt
= cpu_reg_sp(s
, rt
);
4089 * For STG and ST2G, we need to check alignment and probe memory.
4090 * TODO: For STZG and STZ2G, we could rely on the stores below,
4091 * at least for system mode; user-only won't enforce alignment.
4094 gen_helper_st2g_stub(cpu_env
, addr
);
4096 gen_helper_stg_stub(cpu_env
, addr
);
4098 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4100 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4102 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4106 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4108 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4114 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4115 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4116 int mem_index
= get_mem_index(s
);
4117 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4119 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4120 MO_Q
| MO_ALIGN_16
);
4121 for (i
= 8; i
< n
; i
+= 8) {
4122 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4123 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4125 tcg_temp_free_i64(tcg_zero
);
4129 /* pre-index or post-index */
4132 tcg_gen_addi_i64(addr
, addr
, offset
);
4134 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4138 /* Loads and stores */
4139 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4141 switch (extract32(insn
, 24, 6)) {
4142 case 0x08: /* Load/store exclusive */
4143 disas_ldst_excl(s
, insn
);
4145 case 0x18: case 0x1c: /* Load register (literal) */
4146 disas_ld_lit(s
, insn
);
4148 case 0x28: case 0x29:
4149 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4150 disas_ldst_pair(s
, insn
);
4152 case 0x38: case 0x39:
4153 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4154 disas_ldst_reg(s
, insn
);
4156 case 0x0c: /* AdvSIMD load/store multiple structures */
4157 disas_ldst_multiple_struct(s
, insn
);
4159 case 0x0d: /* AdvSIMD load/store single structure */
4160 disas_ldst_single_struct(s
, insn
);
4163 if (extract32(insn
, 21, 1) != 0) {
4164 disas_ldst_tag(s
, insn
);
4165 } else if (extract32(insn
, 10, 2) == 0) {
4166 disas_ldst_ldapr_stlr(s
, insn
);
4168 unallocated_encoding(s
);
4172 unallocated_encoding(s
);
4177 /* PC-rel. addressing
4178 * 31 30 29 28 24 23 5 4 0
4179 * +----+-------+-----------+-------------------+------+
4180 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4181 * +----+-------+-----------+-------------------+------+
4183 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4185 unsigned int page
, rd
;
4189 page
= extract32(insn
, 31, 1);
4190 /* SignExtend(immhi:immlo) -> offset */
4191 offset
= sextract64(insn
, 5, 19);
4192 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4193 rd
= extract32(insn
, 0, 5);
4197 /* ADRP (page based) */
4202 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4206 * Add/subtract (immediate)
4208 * 31 30 29 28 23 22 21 10 9 5 4 0
4209 * +--+--+--+-------------+--+-------------+-----+-----+
4210 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4211 * +--+--+--+-------------+--+-------------+-----+-----+
4213 * sf: 0 -> 32bit, 1 -> 64bit
4214 * op: 0 -> add , 1 -> sub
4216 * sh: 1 -> LSL imm by 12
4218 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4220 int rd
= extract32(insn
, 0, 5);
4221 int rn
= extract32(insn
, 5, 5);
4222 uint64_t imm
= extract32(insn
, 10, 12);
4223 bool shift
= extract32(insn
, 22, 1);
4224 bool setflags
= extract32(insn
, 29, 1);
4225 bool sub_op
= extract32(insn
, 30, 1);
4226 bool is_64bit
= extract32(insn
, 31, 1);
4228 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4229 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4230 TCGv_i64 tcg_result
;
4236 tcg_result
= tcg_temp_new_i64();
4239 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4241 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4244 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4246 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4248 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4250 tcg_temp_free_i64(tcg_imm
);
4254 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4256 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4259 tcg_temp_free_i64(tcg_result
);
4263 * Add/subtract (immediate, with tags)
4265 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4266 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4267 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4268 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4270 * op: 0 -> add, 1 -> sub
4272 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4274 int rd
= extract32(insn
, 0, 5);
4275 int rn
= extract32(insn
, 5, 5);
4276 int uimm4
= extract32(insn
, 10, 4);
4277 int uimm6
= extract32(insn
, 16, 6);
4278 bool sub_op
= extract32(insn
, 30, 1);
4279 TCGv_i64 tcg_rn
, tcg_rd
;
4282 /* Test all of sf=1, S=0, o2=0, o3=0. */
4283 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4284 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4285 unallocated_encoding(s
);
4289 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4294 tcg_rn
= cpu_reg_sp(s
, rn
);
4295 tcg_rd
= cpu_reg_sp(s
, rd
);
4298 TCGv_i32 offset
= tcg_const_i32(imm
);
4299 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4301 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4302 tcg_temp_free_i32(tag_offset
);
4303 tcg_temp_free_i32(offset
);
4305 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4306 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4310 /* The input should be a value in the bottom e bits (with higher
4311 * bits zero); returns that value replicated into every element
4312 * of size e in a 64 bit integer.
4314 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4324 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4325 static inline uint64_t bitmask64(unsigned int length
)
4327 assert(length
> 0 && length
<= 64);
4328 return ~0ULL >> (64 - length
);
4331 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4332 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4333 * value (ie should cause a guest UNDEF exception), and true if they are
4334 * valid, in which case the decoded bit pattern is written to result.
4336 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4337 unsigned int imms
, unsigned int immr
)
4340 unsigned e
, levels
, s
, r
;
4343 assert(immn
< 2 && imms
< 64 && immr
< 64);
4345 /* The bit patterns we create here are 64 bit patterns which
4346 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4347 * 64 bits each. Each element contains the same value: a run
4348 * of between 1 and e-1 non-zero bits, rotated within the
4349 * element by between 0 and e-1 bits.
4351 * The element size and run length are encoded into immn (1 bit)
4352 * and imms (6 bits) as follows:
4353 * 64 bit elements: immn = 1, imms = <length of run - 1>
4354 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4355 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4356 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4357 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4358 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4359 * Notice that immn = 0, imms = 11111x is the only combination
4360 * not covered by one of the above options; this is reserved.
4361 * Further, <length of run - 1> all-ones is a reserved pattern.
4363 * In all cases the rotation is by immr % e (and immr is 6 bits).
4366 /* First determine the element size */
4367 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4369 /* This is the immn == 0, imms == 0x11111x case */
4379 /* <length of run - 1> mustn't be all-ones. */
4383 /* Create the value of one element: s+1 set bits rotated
4384 * by r within the element (which is e bits wide)...
4386 mask
= bitmask64(s
+ 1);
4388 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4389 mask
&= bitmask64(e
);
4391 /* ...then replicate the element over the whole 64 bit value */
4392 mask
= bitfield_replicate(mask
, e
);
4397 /* Logical (immediate)
4398 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4399 * +----+-----+-------------+---+------+------+------+------+
4400 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4401 * +----+-----+-------------+---+------+------+------+------+
4403 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4405 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4406 TCGv_i64 tcg_rd
, tcg_rn
;
4408 bool is_and
= false;
4410 sf
= extract32(insn
, 31, 1);
4411 opc
= extract32(insn
, 29, 2);
4412 is_n
= extract32(insn
, 22, 1);
4413 immr
= extract32(insn
, 16, 6);
4414 imms
= extract32(insn
, 10, 6);
4415 rn
= extract32(insn
, 5, 5);
4416 rd
= extract32(insn
, 0, 5);
4419 unallocated_encoding(s
);
4423 if (opc
== 0x3) { /* ANDS */
4424 tcg_rd
= cpu_reg(s
, rd
);
4426 tcg_rd
= cpu_reg_sp(s
, rd
);
4428 tcg_rn
= cpu_reg(s
, rn
);
4430 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4431 /* some immediate field values are reserved */
4432 unallocated_encoding(s
);
4437 wmask
&= 0xffffffff;
4441 case 0x3: /* ANDS */
4443 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4447 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4450 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4453 assert(FALSE
); /* must handle all above */
4457 if (!sf
&& !is_and
) {
4458 /* zero extend final result; we know we can skip this for AND
4459 * since the immediate had the high 32 bits clear.
4461 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4464 if (opc
== 3) { /* ANDS */
4465 gen_logic_CC(sf
, tcg_rd
);
4470 * Move wide (immediate)
4472 * 31 30 29 28 23 22 21 20 5 4 0
4473 * +--+-----+-------------+-----+----------------+------+
4474 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4475 * +--+-----+-------------+-----+----------------+------+
4477 * sf: 0 -> 32 bit, 1 -> 64 bit
4478 * opc: 00 -> N, 10 -> Z, 11 -> K
4479 * hw: shift/16 (0,16, and sf only 32, 48)
4481 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4483 int rd
= extract32(insn
, 0, 5);
4484 uint64_t imm
= extract32(insn
, 5, 16);
4485 int sf
= extract32(insn
, 31, 1);
4486 int opc
= extract32(insn
, 29, 2);
4487 int pos
= extract32(insn
, 21, 2) << 4;
4488 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4491 if (!sf
&& (pos
>= 32)) {
4492 unallocated_encoding(s
);
4506 tcg_gen_movi_i64(tcg_rd
, imm
);
4509 tcg_imm
= tcg_const_i64(imm
);
4510 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4511 tcg_temp_free_i64(tcg_imm
);
4513 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4517 unallocated_encoding(s
);
4523 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4524 * +----+-----+-------------+---+------+------+------+------+
4525 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4526 * +----+-----+-------------+---+------+------+------+------+
4528 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4530 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4531 TCGv_i64 tcg_rd
, tcg_tmp
;
4533 sf
= extract32(insn
, 31, 1);
4534 opc
= extract32(insn
, 29, 2);
4535 n
= extract32(insn
, 22, 1);
4536 ri
= extract32(insn
, 16, 6);
4537 si
= extract32(insn
, 10, 6);
4538 rn
= extract32(insn
, 5, 5);
4539 rd
= extract32(insn
, 0, 5);
4540 bitsize
= sf
? 64 : 32;
4542 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4543 unallocated_encoding(s
);
4547 tcg_rd
= cpu_reg(s
, rd
);
4549 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4550 to be smaller than bitsize, we'll never reference data outside the
4551 low 32-bits anyway. */
4552 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4554 /* Recognize simple(r) extractions. */
4556 /* Wd<s-r:0> = Wn<s:r> */
4557 len
= (si
- ri
) + 1;
4558 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4559 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4561 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4562 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4565 /* opc == 1, BFXIL fall through to deposit */
4566 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4569 /* Handle the ri > si case with a deposit
4570 * Wd<32+s-r,32-r> = Wn<s:0>
4573 pos
= (bitsize
- ri
) & (bitsize
- 1);
4576 if (opc
== 0 && len
< ri
) {
4577 /* SBFM: sign extend the destination field from len to fill
4578 the balance of the word. Let the deposit below insert all
4579 of those sign bits. */
4580 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4584 if (opc
== 1) { /* BFM, BFXIL */
4585 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4587 /* SBFM or UBFM: We start with zero, and we haven't modified
4588 any bits outside bitsize, therefore the zero-extension
4589 below is unneeded. */
4590 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4595 if (!sf
) { /* zero extend final result */
4596 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4601 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4602 * +----+------+-------------+---+----+------+--------+------+------+
4603 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4604 * +----+------+-------------+---+----+------+--------+------+------+
4606 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4608 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4610 sf
= extract32(insn
, 31, 1);
4611 n
= extract32(insn
, 22, 1);
4612 rm
= extract32(insn
, 16, 5);
4613 imm
= extract32(insn
, 10, 6);
4614 rn
= extract32(insn
, 5, 5);
4615 rd
= extract32(insn
, 0, 5);
4616 op21
= extract32(insn
, 29, 2);
4617 op0
= extract32(insn
, 21, 1);
4618 bitsize
= sf
? 64 : 32;
4620 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4621 unallocated_encoding(s
);
4623 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4625 tcg_rd
= cpu_reg(s
, rd
);
4627 if (unlikely(imm
== 0)) {
4628 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4629 * so an extract from bit 0 is a special case.
4632 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4634 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4637 tcg_rm
= cpu_reg(s
, rm
);
4638 tcg_rn
= cpu_reg(s
, rn
);
4641 /* Specialization to ROR happens in EXTRACT2. */
4642 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4644 TCGv_i32 t0
= tcg_temp_new_i32();
4646 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4648 tcg_gen_rotri_i32(t0
, t0
, imm
);
4650 TCGv_i32 t1
= tcg_temp_new_i32();
4651 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4652 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4653 tcg_temp_free_i32(t1
);
4655 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4656 tcg_temp_free_i32(t0
);
4662 /* Data processing - immediate */
4663 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4665 switch (extract32(insn
, 23, 6)) {
4666 case 0x20: case 0x21: /* PC-rel. addressing */
4667 disas_pc_rel_adr(s
, insn
);
4669 case 0x22: /* Add/subtract (immediate) */
4670 disas_add_sub_imm(s
, insn
);
4672 case 0x23: /* Add/subtract (immediate, with tags) */
4673 disas_add_sub_imm_with_tags(s
, insn
);
4675 case 0x24: /* Logical (immediate) */
4676 disas_logic_imm(s
, insn
);
4678 case 0x25: /* Move wide (immediate) */
4679 disas_movw_imm(s
, insn
);
4681 case 0x26: /* Bitfield */
4682 disas_bitfield(s
, insn
);
4684 case 0x27: /* Extract */
4685 disas_extract(s
, insn
);
4688 unallocated_encoding(s
);
4693 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4694 * Note that it is the caller's responsibility to ensure that the
4695 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4696 * mandated semantics for out of range shifts.
4698 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4699 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4701 switch (shift_type
) {
4702 case A64_SHIFT_TYPE_LSL
:
4703 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4705 case A64_SHIFT_TYPE_LSR
:
4706 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4708 case A64_SHIFT_TYPE_ASR
:
4710 tcg_gen_ext32s_i64(dst
, src
);
4712 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4714 case A64_SHIFT_TYPE_ROR
:
4716 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4719 t0
= tcg_temp_new_i32();
4720 t1
= tcg_temp_new_i32();
4721 tcg_gen_extrl_i64_i32(t0
, src
);
4722 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4723 tcg_gen_rotr_i32(t0
, t0
, t1
);
4724 tcg_gen_extu_i32_i64(dst
, t0
);
4725 tcg_temp_free_i32(t0
);
4726 tcg_temp_free_i32(t1
);
4730 assert(FALSE
); /* all shift types should be handled */
4734 if (!sf
) { /* zero extend final result */
4735 tcg_gen_ext32u_i64(dst
, dst
);
4739 /* Shift a TCGv src by immediate, put result in dst.
4740 * The shift amount must be in range (this should always be true as the
4741 * relevant instructions will UNDEF on bad shift immediates).
4743 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4744 enum a64_shift_type shift_type
, unsigned int shift_i
)
4746 assert(shift_i
< (sf
? 64 : 32));
4749 tcg_gen_mov_i64(dst
, src
);
4751 TCGv_i64 shift_const
;
4753 shift_const
= tcg_const_i64(shift_i
);
4754 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4755 tcg_temp_free_i64(shift_const
);
4759 /* Logical (shifted register)
4760 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4761 * +----+-----+-----------+-------+---+------+--------+------+------+
4762 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4763 * +----+-----+-----------+-------+---+------+--------+------+------+
4765 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4767 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4768 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4770 sf
= extract32(insn
, 31, 1);
4771 opc
= extract32(insn
, 29, 2);
4772 shift_type
= extract32(insn
, 22, 2);
4773 invert
= extract32(insn
, 21, 1);
4774 rm
= extract32(insn
, 16, 5);
4775 shift_amount
= extract32(insn
, 10, 6);
4776 rn
= extract32(insn
, 5, 5);
4777 rd
= extract32(insn
, 0, 5);
4779 if (!sf
&& (shift_amount
& (1 << 5))) {
4780 unallocated_encoding(s
);
4784 tcg_rd
= cpu_reg(s
, rd
);
4786 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4787 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4788 * register-register MOV and MVN, so it is worth special casing.
4790 tcg_rm
= cpu_reg(s
, rm
);
4792 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4794 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4798 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4800 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4806 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4809 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4812 tcg_rn
= cpu_reg(s
, rn
);
4814 switch (opc
| (invert
<< 2)) {
4817 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4820 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4823 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4827 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4830 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4833 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4841 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4845 gen_logic_CC(sf
, tcg_rd
);
4850 * Add/subtract (extended register)
4852 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4853 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4854 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4855 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4857 * sf: 0 -> 32bit, 1 -> 64bit
4858 * op: 0 -> add , 1 -> sub
4861 * option: extension type (see DecodeRegExtend)
4862 * imm3: optional shift to Rm
4864 * Rd = Rn + LSL(extend(Rm), amount)
4866 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4868 int rd
= extract32(insn
, 0, 5);
4869 int rn
= extract32(insn
, 5, 5);
4870 int imm3
= extract32(insn
, 10, 3);
4871 int option
= extract32(insn
, 13, 3);
4872 int rm
= extract32(insn
, 16, 5);
4873 int opt
= extract32(insn
, 22, 2);
4874 bool setflags
= extract32(insn
, 29, 1);
4875 bool sub_op
= extract32(insn
, 30, 1);
4876 bool sf
= extract32(insn
, 31, 1);
4878 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4880 TCGv_i64 tcg_result
;
4882 if (imm3
> 4 || opt
!= 0) {
4883 unallocated_encoding(s
);
4887 /* non-flag setting ops may use SP */
4889 tcg_rd
= cpu_reg_sp(s
, rd
);
4891 tcg_rd
= cpu_reg(s
, rd
);
4893 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4895 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4896 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4898 tcg_result
= tcg_temp_new_i64();
4902 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4904 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4908 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4910 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4915 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4917 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4920 tcg_temp_free_i64(tcg_result
);
4924 * Add/subtract (shifted register)
4926 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4927 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4928 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4929 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4931 * sf: 0 -> 32bit, 1 -> 64bit
4932 * op: 0 -> add , 1 -> sub
4934 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4935 * imm6: Shift amount to apply to Rm before the add/sub
4937 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4939 int rd
= extract32(insn
, 0, 5);
4940 int rn
= extract32(insn
, 5, 5);
4941 int imm6
= extract32(insn
, 10, 6);
4942 int rm
= extract32(insn
, 16, 5);
4943 int shift_type
= extract32(insn
, 22, 2);
4944 bool setflags
= extract32(insn
, 29, 1);
4945 bool sub_op
= extract32(insn
, 30, 1);
4946 bool sf
= extract32(insn
, 31, 1);
4948 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4949 TCGv_i64 tcg_rn
, tcg_rm
;
4950 TCGv_i64 tcg_result
;
4952 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4953 unallocated_encoding(s
);
4957 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4958 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4960 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4962 tcg_result
= tcg_temp_new_i64();
4966 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4968 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4972 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4974 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4979 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4981 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4984 tcg_temp_free_i64(tcg_result
);
4987 /* Data-processing (3 source)
4989 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4990 * +--+------+-----------+------+------+----+------+------+------+
4991 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4992 * +--+------+-----------+------+------+----+------+------+------+
4994 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4996 int rd
= extract32(insn
, 0, 5);
4997 int rn
= extract32(insn
, 5, 5);
4998 int ra
= extract32(insn
, 10, 5);
4999 int rm
= extract32(insn
, 16, 5);
5000 int op_id
= (extract32(insn
, 29, 3) << 4) |
5001 (extract32(insn
, 21, 3) << 1) |
5002 extract32(insn
, 15, 1);
5003 bool sf
= extract32(insn
, 31, 1);
5004 bool is_sub
= extract32(op_id
, 0, 1);
5005 bool is_high
= extract32(op_id
, 2, 1);
5006 bool is_signed
= false;
5011 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
5013 case 0x42: /* SMADDL */
5014 case 0x43: /* SMSUBL */
5015 case 0x44: /* SMULH */
5018 case 0x0: /* MADD (32bit) */
5019 case 0x1: /* MSUB (32bit) */
5020 case 0x40: /* MADD (64bit) */
5021 case 0x41: /* MSUB (64bit) */
5022 case 0x4a: /* UMADDL */
5023 case 0x4b: /* UMSUBL */
5024 case 0x4c: /* UMULH */
5027 unallocated_encoding(s
);
5032 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5033 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5034 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5035 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5038 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5040 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5043 tcg_temp_free_i64(low_bits
);
5047 tcg_op1
= tcg_temp_new_i64();
5048 tcg_op2
= tcg_temp_new_i64();
5049 tcg_tmp
= tcg_temp_new_i64();
5052 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5053 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5056 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5057 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5059 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5060 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5064 if (ra
== 31 && !is_sub
) {
5065 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5066 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5068 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5070 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5072 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5077 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5080 tcg_temp_free_i64(tcg_op1
);
5081 tcg_temp_free_i64(tcg_op2
);
5082 tcg_temp_free_i64(tcg_tmp
);
5085 /* Add/subtract (with carry)
5086 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5087 * +--+--+--+------------------------+------+-------------+------+-----+
5088 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5089 * +--+--+--+------------------------+------+-------------+------+-----+
5092 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5094 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5095 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5097 sf
= extract32(insn
, 31, 1);
5098 op
= extract32(insn
, 30, 1);
5099 setflags
= extract32(insn
, 29, 1);
5100 rm
= extract32(insn
, 16, 5);
5101 rn
= extract32(insn
, 5, 5);
5102 rd
= extract32(insn
, 0, 5);
5104 tcg_rd
= cpu_reg(s
, rd
);
5105 tcg_rn
= cpu_reg(s
, rn
);
5108 tcg_y
= new_tmp_a64(s
);
5109 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5111 tcg_y
= cpu_reg(s
, rm
);
5115 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5117 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5122 * Rotate right into flags
5123 * 31 30 29 21 15 10 5 4 0
5124 * +--+--+--+-----------------+--------+-----------+------+--+------+
5125 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5126 * +--+--+--+-----------------+--------+-----------+------+--+------+
5128 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5130 int mask
= extract32(insn
, 0, 4);
5131 int o2
= extract32(insn
, 4, 1);
5132 int rn
= extract32(insn
, 5, 5);
5133 int imm6
= extract32(insn
, 15, 6);
5134 int sf_op_s
= extract32(insn
, 29, 3);
5138 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5139 unallocated_encoding(s
);
5143 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5144 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5146 nzcv
= tcg_temp_new_i32();
5147 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5149 if (mask
& 8) { /* N */
5150 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5152 if (mask
& 4) { /* Z */
5153 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5154 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5156 if (mask
& 2) { /* C */
5157 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5159 if (mask
& 1) { /* V */
5160 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5163 tcg_temp_free_i32(nzcv
);
5167 * Evaluate into flags
5168 * 31 30 29 21 15 14 10 5 4 0
5169 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5170 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5171 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5173 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5175 int o3_mask
= extract32(insn
, 0, 5);
5176 int rn
= extract32(insn
, 5, 5);
5177 int o2
= extract32(insn
, 15, 6);
5178 int sz
= extract32(insn
, 14, 1);
5179 int sf_op_s
= extract32(insn
, 29, 3);
5183 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5184 !dc_isar_feature(aa64_condm_4
, s
)) {
5185 unallocated_encoding(s
);
5188 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5190 tmp
= tcg_temp_new_i32();
5191 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5192 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5193 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5194 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5195 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5196 tcg_temp_free_i32(tmp
);
5199 /* Conditional compare (immediate / register)
5200 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5201 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5202 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5203 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5206 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5208 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5209 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5210 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5213 if (!extract32(insn
, 29, 1)) {
5214 unallocated_encoding(s
);
5217 if (insn
& (1 << 10 | 1 << 4)) {
5218 unallocated_encoding(s
);
5221 sf
= extract32(insn
, 31, 1);
5222 op
= extract32(insn
, 30, 1);
5223 is_imm
= extract32(insn
, 11, 1);
5224 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5225 cond
= extract32(insn
, 12, 4);
5226 rn
= extract32(insn
, 5, 5);
5227 nzcv
= extract32(insn
, 0, 4);
5229 /* Set T0 = !COND. */
5230 tcg_t0
= tcg_temp_new_i32();
5231 arm_test_cc(&c
, cond
);
5232 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5235 /* Load the arguments for the new comparison. */
5237 tcg_y
= new_tmp_a64(s
);
5238 tcg_gen_movi_i64(tcg_y
, y
);
5240 tcg_y
= cpu_reg(s
, y
);
5242 tcg_rn
= cpu_reg(s
, rn
);
5244 /* Set the flags for the new comparison. */
5245 tcg_tmp
= tcg_temp_new_i64();
5247 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5249 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5251 tcg_temp_free_i64(tcg_tmp
);
5253 /* If COND was false, force the flags to #nzcv. Compute two masks
5254 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5255 * For tcg hosts that support ANDC, we can make do with just T1.
5256 * In either case, allow the tcg optimizer to delete any unused mask.
5258 tcg_t1
= tcg_temp_new_i32();
5259 tcg_t2
= tcg_temp_new_i32();
5260 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5261 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5263 if (nzcv
& 8) { /* N */
5264 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5266 if (TCG_TARGET_HAS_andc_i32
) {
5267 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5269 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5272 if (nzcv
& 4) { /* Z */
5273 if (TCG_TARGET_HAS_andc_i32
) {
5274 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5276 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5279 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5281 if (nzcv
& 2) { /* C */
5282 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5284 if (TCG_TARGET_HAS_andc_i32
) {
5285 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5287 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5290 if (nzcv
& 1) { /* V */
5291 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5293 if (TCG_TARGET_HAS_andc_i32
) {
5294 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5296 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5299 tcg_temp_free_i32(tcg_t0
);
5300 tcg_temp_free_i32(tcg_t1
);
5301 tcg_temp_free_i32(tcg_t2
);
5304 /* Conditional select
5305 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5306 * +----+----+---+-----------------+------+------+-----+------+------+
5307 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5308 * +----+----+---+-----------------+------+------+-----+------+------+
5310 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5312 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5313 TCGv_i64 tcg_rd
, zero
;
5316 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5317 /* S == 1 or op2<1> == 1 */
5318 unallocated_encoding(s
);
5321 sf
= extract32(insn
, 31, 1);
5322 else_inv
= extract32(insn
, 30, 1);
5323 rm
= extract32(insn
, 16, 5);
5324 cond
= extract32(insn
, 12, 4);
5325 else_inc
= extract32(insn
, 10, 1);
5326 rn
= extract32(insn
, 5, 5);
5327 rd
= extract32(insn
, 0, 5);
5329 tcg_rd
= cpu_reg(s
, rd
);
5331 a64_test_cc(&c
, cond
);
5332 zero
= tcg_const_i64(0);
5334 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5336 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5338 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5341 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5342 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5343 if (else_inv
&& else_inc
) {
5344 tcg_gen_neg_i64(t_false
, t_false
);
5345 } else if (else_inv
) {
5346 tcg_gen_not_i64(t_false
, t_false
);
5347 } else if (else_inc
) {
5348 tcg_gen_addi_i64(t_false
, t_false
, 1);
5350 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5353 tcg_temp_free_i64(zero
);
5357 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5361 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5362 unsigned int rn
, unsigned int rd
)
5364 TCGv_i64 tcg_rd
, tcg_rn
;
5365 tcg_rd
= cpu_reg(s
, rd
);
5366 tcg_rn
= cpu_reg(s
, rn
);
5369 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5371 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5372 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5373 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5374 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5375 tcg_temp_free_i32(tcg_tmp32
);
5379 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5380 unsigned int rn
, unsigned int rd
)
5382 TCGv_i64 tcg_rd
, tcg_rn
;
5383 tcg_rd
= cpu_reg(s
, rd
);
5384 tcg_rn
= cpu_reg(s
, rn
);
5387 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5389 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5390 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5391 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5392 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5393 tcg_temp_free_i32(tcg_tmp32
);
5397 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5398 unsigned int rn
, unsigned int rd
)
5400 TCGv_i64 tcg_rd
, tcg_rn
;
5401 tcg_rd
= cpu_reg(s
, rd
);
5402 tcg_rn
= cpu_reg(s
, rn
);
5405 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5407 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5408 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5409 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5410 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5411 tcg_temp_free_i32(tcg_tmp32
);
5415 /* REV with sf==1, opcode==3 ("REV64") */
5416 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5417 unsigned int rn
, unsigned int rd
)
5420 unallocated_encoding(s
);
5423 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5426 /* REV with sf==0, opcode==2
5427 * REV32 (sf==1, opcode==2)
5429 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5430 unsigned int rn
, unsigned int rd
)
5432 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5435 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5436 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5438 /* bswap32_i64 requires zero high word */
5439 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
5440 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
5441 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
5442 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
5443 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5445 tcg_temp_free_i64(tcg_tmp
);
5447 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
5448 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5452 /* REV16 (opcode==1) */
5453 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5454 unsigned int rn
, unsigned int rd
)
5456 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5457 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5458 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5459 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5461 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5462 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5463 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5464 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5465 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5467 tcg_temp_free_i64(mask
);
5468 tcg_temp_free_i64(tcg_tmp
);
5471 /* Data-processing (1 source)
5472 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5473 * +----+---+---+-----------------+---------+--------+------+------+
5474 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5475 * +----+---+---+-----------------+---------+--------+------+------+
5477 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5479 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5482 if (extract32(insn
, 29, 1)) {
5483 unallocated_encoding(s
);
5487 sf
= extract32(insn
, 31, 1);
5488 opcode
= extract32(insn
, 10, 6);
5489 opcode2
= extract32(insn
, 16, 5);
5490 rn
= extract32(insn
, 5, 5);
5491 rd
= extract32(insn
, 0, 5);
5493 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5495 switch (MAP(sf
, opcode2
, opcode
)) {
5496 case MAP(0, 0x00, 0x00): /* RBIT */
5497 case MAP(1, 0x00, 0x00):
5498 handle_rbit(s
, sf
, rn
, rd
);
5500 case MAP(0, 0x00, 0x01): /* REV16 */
5501 case MAP(1, 0x00, 0x01):
5502 handle_rev16(s
, sf
, rn
, rd
);
5504 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5505 case MAP(1, 0x00, 0x02):
5506 handle_rev32(s
, sf
, rn
, rd
);
5508 case MAP(1, 0x00, 0x03): /* REV64 */
5509 handle_rev64(s
, sf
, rn
, rd
);
5511 case MAP(0, 0x00, 0x04): /* CLZ */
5512 case MAP(1, 0x00, 0x04):
5513 handle_clz(s
, sf
, rn
, rd
);
5515 case MAP(0, 0x00, 0x05): /* CLS */
5516 case MAP(1, 0x00, 0x05):
5517 handle_cls(s
, sf
, rn
, rd
);
5519 case MAP(1, 0x01, 0x00): /* PACIA */
5520 if (s
->pauth_active
) {
5521 tcg_rd
= cpu_reg(s
, rd
);
5522 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5523 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5524 goto do_unallocated
;
5527 case MAP(1, 0x01, 0x01): /* PACIB */
5528 if (s
->pauth_active
) {
5529 tcg_rd
= cpu_reg(s
, rd
);
5530 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5531 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5532 goto do_unallocated
;
5535 case MAP(1, 0x01, 0x02): /* PACDA */
5536 if (s
->pauth_active
) {
5537 tcg_rd
= cpu_reg(s
, rd
);
5538 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5539 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5540 goto do_unallocated
;
5543 case MAP(1, 0x01, 0x03): /* PACDB */
5544 if (s
->pauth_active
) {
5545 tcg_rd
= cpu_reg(s
, rd
);
5546 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5547 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5548 goto do_unallocated
;
5551 case MAP(1, 0x01, 0x04): /* AUTIA */
5552 if (s
->pauth_active
) {
5553 tcg_rd
= cpu_reg(s
, rd
);
5554 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5555 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5556 goto do_unallocated
;
5559 case MAP(1, 0x01, 0x05): /* AUTIB */
5560 if (s
->pauth_active
) {
5561 tcg_rd
= cpu_reg(s
, rd
);
5562 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5563 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5564 goto do_unallocated
;
5567 case MAP(1, 0x01, 0x06): /* AUTDA */
5568 if (s
->pauth_active
) {
5569 tcg_rd
= cpu_reg(s
, rd
);
5570 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5571 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5572 goto do_unallocated
;
5575 case MAP(1, 0x01, 0x07): /* AUTDB */
5576 if (s
->pauth_active
) {
5577 tcg_rd
= cpu_reg(s
, rd
);
5578 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5579 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5580 goto do_unallocated
;
5583 case MAP(1, 0x01, 0x08): /* PACIZA */
5584 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5585 goto do_unallocated
;
5586 } else if (s
->pauth_active
) {
5587 tcg_rd
= cpu_reg(s
, rd
);
5588 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5591 case MAP(1, 0x01, 0x09): /* PACIZB */
5592 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5593 goto do_unallocated
;
5594 } else if (s
->pauth_active
) {
5595 tcg_rd
= cpu_reg(s
, rd
);
5596 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5599 case MAP(1, 0x01, 0x0a): /* PACDZA */
5600 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5601 goto do_unallocated
;
5602 } else if (s
->pauth_active
) {
5603 tcg_rd
= cpu_reg(s
, rd
);
5604 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5607 case MAP(1, 0x01, 0x0b): /* PACDZB */
5608 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5609 goto do_unallocated
;
5610 } else if (s
->pauth_active
) {
5611 tcg_rd
= cpu_reg(s
, rd
);
5612 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5615 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5616 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5617 goto do_unallocated
;
5618 } else if (s
->pauth_active
) {
5619 tcg_rd
= cpu_reg(s
, rd
);
5620 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5623 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5624 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5625 goto do_unallocated
;
5626 } else if (s
->pauth_active
) {
5627 tcg_rd
= cpu_reg(s
, rd
);
5628 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5631 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5632 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5633 goto do_unallocated
;
5634 } else if (s
->pauth_active
) {
5635 tcg_rd
= cpu_reg(s
, rd
);
5636 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5639 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5640 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5641 goto do_unallocated
;
5642 } else if (s
->pauth_active
) {
5643 tcg_rd
= cpu_reg(s
, rd
);
5644 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5647 case MAP(1, 0x01, 0x10): /* XPACI */
5648 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5649 goto do_unallocated
;
5650 } else if (s
->pauth_active
) {
5651 tcg_rd
= cpu_reg(s
, rd
);
5652 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5655 case MAP(1, 0x01, 0x11): /* XPACD */
5656 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5657 goto do_unallocated
;
5658 } else if (s
->pauth_active
) {
5659 tcg_rd
= cpu_reg(s
, rd
);
5660 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5665 unallocated_encoding(s
);
5672 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5673 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5675 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5676 tcg_rd
= cpu_reg(s
, rd
);
5678 if (!sf
&& is_signed
) {
5679 tcg_n
= new_tmp_a64(s
);
5680 tcg_m
= new_tmp_a64(s
);
5681 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5682 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5684 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5685 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5689 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5691 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5694 if (!sf
) { /* zero extend final result */
5695 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5699 /* LSLV, LSRV, ASRV, RORV */
5700 static void handle_shift_reg(DisasContext
*s
,
5701 enum a64_shift_type shift_type
, unsigned int sf
,
5702 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5704 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5705 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5706 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5708 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5709 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5710 tcg_temp_free_i64(tcg_shift
);
5713 /* CRC32[BHWX], CRC32C[BHWX] */
5714 static void handle_crc32(DisasContext
*s
,
5715 unsigned int sf
, unsigned int sz
, bool crc32c
,
5716 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5718 TCGv_i64 tcg_acc
, tcg_val
;
5721 if (!dc_isar_feature(aa64_crc32
, s
)
5722 || (sf
== 1 && sz
!= 3)
5723 || (sf
== 0 && sz
== 3)) {
5724 unallocated_encoding(s
);
5729 tcg_val
= cpu_reg(s
, rm
);
5743 g_assert_not_reached();
5745 tcg_val
= new_tmp_a64(s
);
5746 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5749 tcg_acc
= cpu_reg(s
, rn
);
5750 tcg_bytes
= tcg_const_i32(1 << sz
);
5753 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5755 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5758 tcg_temp_free_i32(tcg_bytes
);
5761 /* Data-processing (2 source)
5762 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5763 * +----+---+---+-----------------+------+--------+------+------+
5764 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5765 * +----+---+---+-----------------+------+--------+------+------+
5767 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5769 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5770 sf
= extract32(insn
, 31, 1);
5771 setflag
= extract32(insn
, 29, 1);
5772 rm
= extract32(insn
, 16, 5);
5773 opcode
= extract32(insn
, 10, 6);
5774 rn
= extract32(insn
, 5, 5);
5775 rd
= extract32(insn
, 0, 5);
5777 if (setflag
&& opcode
!= 0) {
5778 unallocated_encoding(s
);
5783 case 0: /* SUBP(S) */
5784 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5785 goto do_unallocated
;
5787 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5789 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5790 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5791 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5792 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5793 tcg_d
= cpu_reg(s
, rd
);
5796 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5798 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5803 handle_div(s
, false, sf
, rm
, rn
, rd
);
5806 handle_div(s
, true, sf
, rm
, rn
, rd
);
5809 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5810 goto do_unallocated
;
5813 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5814 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5816 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5821 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5822 goto do_unallocated
;
5824 TCGv_i64 t1
= tcg_const_i64(1);
5825 TCGv_i64 t2
= tcg_temp_new_i64();
5827 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5828 tcg_gen_shl_i64(t1
, t1
, t2
);
5829 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5831 tcg_temp_free_i64(t1
);
5832 tcg_temp_free_i64(t2
);
5836 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5839 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5842 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5845 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5847 case 12: /* PACGA */
5848 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5849 goto do_unallocated
;
5851 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5852 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5861 case 23: /* CRC32 */
5863 int sz
= extract32(opcode
, 0, 2);
5864 bool crc32c
= extract32(opcode
, 2, 1);
5865 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5870 unallocated_encoding(s
);
5876 * Data processing - register
5877 * 31 30 29 28 25 21 20 16 10 0
5878 * +--+---+--+---+-------+-----+-------+-------+---------+
5879 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5880 * +--+---+--+---+-------+-----+-------+-------+---------+
5882 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5884 int op0
= extract32(insn
, 30, 1);
5885 int op1
= extract32(insn
, 28, 1);
5886 int op2
= extract32(insn
, 21, 4);
5887 int op3
= extract32(insn
, 10, 6);
5892 /* Add/sub (extended register) */
5893 disas_add_sub_ext_reg(s
, insn
);
5895 /* Add/sub (shifted register) */
5896 disas_add_sub_reg(s
, insn
);
5899 /* Logical (shifted register) */
5900 disas_logic_reg(s
, insn
);
5908 case 0x00: /* Add/subtract (with carry) */
5909 disas_adc_sbc(s
, insn
);
5912 case 0x01: /* Rotate right into flags */
5914 disas_rotate_right_into_flags(s
, insn
);
5917 case 0x02: /* Evaluate into flags */
5921 disas_evaluate_into_flags(s
, insn
);
5925 goto do_unallocated
;
5929 case 0x2: /* Conditional compare */
5930 disas_cc(s
, insn
); /* both imm and reg forms */
5933 case 0x4: /* Conditional select */
5934 disas_cond_select(s
, insn
);
5937 case 0x6: /* Data-processing */
5938 if (op0
) { /* (1 source) */
5939 disas_data_proc_1src(s
, insn
);
5940 } else { /* (2 source) */
5941 disas_data_proc_2src(s
, insn
);
5944 case 0x8 ... 0xf: /* (3 source) */
5945 disas_data_proc_3src(s
, insn
);
5950 unallocated_encoding(s
);
5955 static void handle_fp_compare(DisasContext
*s
, int size
,
5956 unsigned int rn
, unsigned int rm
,
5957 bool cmp_with_zero
, bool signal_all_nans
)
5959 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5960 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5962 if (size
== MO_64
) {
5963 TCGv_i64 tcg_vn
, tcg_vm
;
5965 tcg_vn
= read_fp_dreg(s
, rn
);
5966 if (cmp_with_zero
) {
5967 tcg_vm
= tcg_const_i64(0);
5969 tcg_vm
= read_fp_dreg(s
, rm
);
5971 if (signal_all_nans
) {
5972 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5974 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5976 tcg_temp_free_i64(tcg_vn
);
5977 tcg_temp_free_i64(tcg_vm
);
5979 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5980 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5982 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5983 if (cmp_with_zero
) {
5984 tcg_gen_movi_i32(tcg_vm
, 0);
5986 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5991 if (signal_all_nans
) {
5992 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5994 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5998 if (signal_all_nans
) {
5999 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6001 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6005 g_assert_not_reached();
6008 tcg_temp_free_i32(tcg_vn
);
6009 tcg_temp_free_i32(tcg_vm
);
6012 tcg_temp_free_ptr(fpst
);
6014 gen_set_nzcv(tcg_flags
);
6016 tcg_temp_free_i64(tcg_flags
);
6019 /* Floating point compare
6020 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
6021 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6022 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
6023 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6025 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
6027 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
6030 mos
= extract32(insn
, 29, 3);
6031 type
= extract32(insn
, 22, 2);
6032 rm
= extract32(insn
, 16, 5);
6033 op
= extract32(insn
, 14, 2);
6034 rn
= extract32(insn
, 5, 5);
6035 opc
= extract32(insn
, 3, 2);
6036 op2r
= extract32(insn
, 0, 3);
6038 if (mos
|| op
|| op2r
) {
6039 unallocated_encoding(s
);
6052 if (dc_isar_feature(aa64_fp16
, s
)) {
6057 unallocated_encoding(s
);
6061 if (!fp_access_check(s
)) {
6065 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6068 /* Floating point conditional compare
6069 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6070 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6071 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6072 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6074 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6076 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6078 TCGLabel
*label_continue
= NULL
;
6081 mos
= extract32(insn
, 29, 3);
6082 type
= extract32(insn
, 22, 2);
6083 rm
= extract32(insn
, 16, 5);
6084 cond
= extract32(insn
, 12, 4);
6085 rn
= extract32(insn
, 5, 5);
6086 op
= extract32(insn
, 4, 1);
6087 nzcv
= extract32(insn
, 0, 4);
6090 unallocated_encoding(s
);
6103 if (dc_isar_feature(aa64_fp16
, s
)) {
6108 unallocated_encoding(s
);
6112 if (!fp_access_check(s
)) {
6116 if (cond
< 0x0e) { /* not always */
6117 TCGLabel
*label_match
= gen_new_label();
6118 label_continue
= gen_new_label();
6119 arm_gen_test_cc(cond
, label_match
);
6121 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6122 gen_set_nzcv(tcg_flags
);
6123 tcg_temp_free_i64(tcg_flags
);
6124 tcg_gen_br(label_continue
);
6125 gen_set_label(label_match
);
6128 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6131 gen_set_label(label_continue
);
6135 /* Floating point conditional select
6136 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6137 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6138 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6139 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6141 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6143 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6144 TCGv_i64 t_true
, t_false
, t_zero
;
6148 mos
= extract32(insn
, 29, 3);
6149 type
= extract32(insn
, 22, 2);
6150 rm
= extract32(insn
, 16, 5);
6151 cond
= extract32(insn
, 12, 4);
6152 rn
= extract32(insn
, 5, 5);
6153 rd
= extract32(insn
, 0, 5);
6156 unallocated_encoding(s
);
6169 if (dc_isar_feature(aa64_fp16
, s
)) {
6174 unallocated_encoding(s
);
6178 if (!fp_access_check(s
)) {
6182 /* Zero extend sreg & hreg inputs to 64 bits now. */
6183 t_true
= tcg_temp_new_i64();
6184 t_false
= tcg_temp_new_i64();
6185 read_vec_element(s
, t_true
, rn
, 0, sz
);
6186 read_vec_element(s
, t_false
, rm
, 0, sz
);
6188 a64_test_cc(&c
, cond
);
6189 t_zero
= tcg_const_i64(0);
6190 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6191 tcg_temp_free_i64(t_zero
);
6192 tcg_temp_free_i64(t_false
);
6195 /* Note that sregs & hregs write back zeros to the high bits,
6196 and we've already done the zero-extension. */
6197 write_fp_dreg(s
, rd
, t_true
);
6198 tcg_temp_free_i64(t_true
);
6201 /* Floating-point data-processing (1 source) - half precision */
6202 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6204 TCGv_ptr fpst
= NULL
;
6205 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6206 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6209 case 0x0: /* FMOV */
6210 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6212 case 0x1: /* FABS */
6213 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6215 case 0x2: /* FNEG */
6216 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6218 case 0x3: /* FSQRT */
6219 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6220 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6222 case 0x8: /* FRINTN */
6223 case 0x9: /* FRINTP */
6224 case 0xa: /* FRINTM */
6225 case 0xb: /* FRINTZ */
6226 case 0xc: /* FRINTA */
6228 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6229 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6231 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6232 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6234 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6235 tcg_temp_free_i32(tcg_rmode
);
6238 case 0xe: /* FRINTX */
6239 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6240 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6242 case 0xf: /* FRINTI */
6243 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6244 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6250 write_fp_sreg(s
, rd
, tcg_res
);
6253 tcg_temp_free_ptr(fpst
);
6255 tcg_temp_free_i32(tcg_op
);
6256 tcg_temp_free_i32(tcg_res
);
6259 /* Floating-point data-processing (1 source) - single precision */
6260 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6262 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6263 TCGv_i32 tcg_op
, tcg_res
;
6267 tcg_op
= read_fp_sreg(s
, rn
);
6268 tcg_res
= tcg_temp_new_i32();
6271 case 0x0: /* FMOV */
6272 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6274 case 0x1: /* FABS */
6275 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6277 case 0x2: /* FNEG */
6278 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6280 case 0x3: /* FSQRT */
6281 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6283 case 0x6: /* BFCVT */
6284 gen_fpst
= gen_helper_bfcvt
;
6286 case 0x8: /* FRINTN */
6287 case 0x9: /* FRINTP */
6288 case 0xa: /* FRINTM */
6289 case 0xb: /* FRINTZ */
6290 case 0xc: /* FRINTA */
6291 rmode
= arm_rmode_to_sf(opcode
& 7);
6292 gen_fpst
= gen_helper_rints
;
6294 case 0xe: /* FRINTX */
6295 gen_fpst
= gen_helper_rints_exact
;
6297 case 0xf: /* FRINTI */
6298 gen_fpst
= gen_helper_rints
;
6300 case 0x10: /* FRINT32Z */
6301 rmode
= float_round_to_zero
;
6302 gen_fpst
= gen_helper_frint32_s
;
6304 case 0x11: /* FRINT32X */
6305 gen_fpst
= gen_helper_frint32_s
;
6307 case 0x12: /* FRINT64Z */
6308 rmode
= float_round_to_zero
;
6309 gen_fpst
= gen_helper_frint64_s
;
6311 case 0x13: /* FRINT64X */
6312 gen_fpst
= gen_helper_frint64_s
;
6315 g_assert_not_reached();
6318 fpst
= fpstatus_ptr(FPST_FPCR
);
6320 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6321 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6322 gen_fpst(tcg_res
, tcg_op
, fpst
);
6323 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6324 tcg_temp_free_i32(tcg_rmode
);
6326 gen_fpst(tcg_res
, tcg_op
, fpst
);
6328 tcg_temp_free_ptr(fpst
);
6331 write_fp_sreg(s
, rd
, tcg_res
);
6332 tcg_temp_free_i32(tcg_op
);
6333 tcg_temp_free_i32(tcg_res
);
6336 /* Floating-point data-processing (1 source) - double precision */
6337 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6339 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6340 TCGv_i64 tcg_op
, tcg_res
;
6345 case 0x0: /* FMOV */
6346 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6350 tcg_op
= read_fp_dreg(s
, rn
);
6351 tcg_res
= tcg_temp_new_i64();
6354 case 0x1: /* FABS */
6355 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6357 case 0x2: /* FNEG */
6358 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6360 case 0x3: /* FSQRT */
6361 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6363 case 0x8: /* FRINTN */
6364 case 0x9: /* FRINTP */
6365 case 0xa: /* FRINTM */
6366 case 0xb: /* FRINTZ */
6367 case 0xc: /* FRINTA */
6368 rmode
= arm_rmode_to_sf(opcode
& 7);
6369 gen_fpst
= gen_helper_rintd
;
6371 case 0xe: /* FRINTX */
6372 gen_fpst
= gen_helper_rintd_exact
;
6374 case 0xf: /* FRINTI */
6375 gen_fpst
= gen_helper_rintd
;
6377 case 0x10: /* FRINT32Z */
6378 rmode
= float_round_to_zero
;
6379 gen_fpst
= gen_helper_frint32_d
;
6381 case 0x11: /* FRINT32X */
6382 gen_fpst
= gen_helper_frint32_d
;
6384 case 0x12: /* FRINT64Z */
6385 rmode
= float_round_to_zero
;
6386 gen_fpst
= gen_helper_frint64_d
;
6388 case 0x13: /* FRINT64X */
6389 gen_fpst
= gen_helper_frint64_d
;
6392 g_assert_not_reached();
6395 fpst
= fpstatus_ptr(FPST_FPCR
);
6397 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6398 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6399 gen_fpst(tcg_res
, tcg_op
, fpst
);
6400 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6401 tcg_temp_free_i32(tcg_rmode
);
6403 gen_fpst(tcg_res
, tcg_op
, fpst
);
6405 tcg_temp_free_ptr(fpst
);
6408 write_fp_dreg(s
, rd
, tcg_res
);
6409 tcg_temp_free_i64(tcg_op
);
6410 tcg_temp_free_i64(tcg_res
);
6413 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6414 int rd
, int rn
, int dtype
, int ntype
)
6419 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6421 /* Single to double */
6422 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6423 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6424 write_fp_dreg(s
, rd
, tcg_rd
);
6425 tcg_temp_free_i64(tcg_rd
);
6427 /* Single to half */
6428 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6429 TCGv_i32 ahp
= get_ahp_flag();
6430 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6432 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6433 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6434 write_fp_sreg(s
, rd
, tcg_rd
);
6435 tcg_temp_free_i32(tcg_rd
);
6436 tcg_temp_free_i32(ahp
);
6437 tcg_temp_free_ptr(fpst
);
6439 tcg_temp_free_i32(tcg_rn
);
6444 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6445 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6447 /* Double to single */
6448 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6450 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6451 TCGv_i32 ahp
= get_ahp_flag();
6452 /* Double to half */
6453 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6454 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6455 tcg_temp_free_ptr(fpst
);
6456 tcg_temp_free_i32(ahp
);
6458 write_fp_sreg(s
, rd
, tcg_rd
);
6459 tcg_temp_free_i32(tcg_rd
);
6460 tcg_temp_free_i64(tcg_rn
);
6465 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6466 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6467 TCGv_i32 tcg_ahp
= get_ahp_flag();
6468 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6470 /* Half to single */
6471 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6472 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6473 write_fp_sreg(s
, rd
, tcg_rd
);
6474 tcg_temp_free_i32(tcg_rd
);
6476 /* Half to double */
6477 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6478 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6479 write_fp_dreg(s
, rd
, tcg_rd
);
6480 tcg_temp_free_i64(tcg_rd
);
6482 tcg_temp_free_i32(tcg_rn
);
6483 tcg_temp_free_ptr(tcg_fpst
);
6484 tcg_temp_free_i32(tcg_ahp
);
6492 /* Floating point data-processing (1 source)
6493 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6494 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6495 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6496 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6498 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6500 int mos
= extract32(insn
, 29, 3);
6501 int type
= extract32(insn
, 22, 2);
6502 int opcode
= extract32(insn
, 15, 6);
6503 int rn
= extract32(insn
, 5, 5);
6504 int rd
= extract32(insn
, 0, 5);
6507 goto do_unallocated
;
6511 case 0x4: case 0x5: case 0x7:
6513 /* FCVT between half, single and double precision */
6514 int dtype
= extract32(opcode
, 0, 2);
6515 if (type
== 2 || dtype
== type
) {
6516 goto do_unallocated
;
6518 if (!fp_access_check(s
)) {
6522 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6526 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6527 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6528 goto do_unallocated
;
6534 /* 32-to-32 and 64-to-64 ops */
6537 if (!fp_access_check(s
)) {
6540 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6543 if (!fp_access_check(s
)) {
6546 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6549 if (!dc_isar_feature(aa64_fp16
, s
)) {
6550 goto do_unallocated
;
6553 if (!fp_access_check(s
)) {
6556 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6559 goto do_unallocated
;
6566 if (!dc_isar_feature(aa64_bf16
, s
)) {
6567 goto do_unallocated
;
6569 if (!fp_access_check(s
)) {
6572 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6575 goto do_unallocated
;
6581 unallocated_encoding(s
);
6586 /* Floating-point data-processing (2 source) - single precision */
6587 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6588 int rd
, int rn
, int rm
)
6595 tcg_res
= tcg_temp_new_i32();
6596 fpst
= fpstatus_ptr(FPST_FPCR
);
6597 tcg_op1
= read_fp_sreg(s
, rn
);
6598 tcg_op2
= read_fp_sreg(s
, rm
);
6601 case 0x0: /* FMUL */
6602 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6604 case 0x1: /* FDIV */
6605 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6607 case 0x2: /* FADD */
6608 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6610 case 0x3: /* FSUB */
6611 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6613 case 0x4: /* FMAX */
6614 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6616 case 0x5: /* FMIN */
6617 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6619 case 0x6: /* FMAXNM */
6620 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6622 case 0x7: /* FMINNM */
6623 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6625 case 0x8: /* FNMUL */
6626 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6627 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6631 write_fp_sreg(s
, rd
, tcg_res
);
6633 tcg_temp_free_ptr(fpst
);
6634 tcg_temp_free_i32(tcg_op1
);
6635 tcg_temp_free_i32(tcg_op2
);
6636 tcg_temp_free_i32(tcg_res
);
6639 /* Floating-point data-processing (2 source) - double precision */
6640 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6641 int rd
, int rn
, int rm
)
6648 tcg_res
= tcg_temp_new_i64();
6649 fpst
= fpstatus_ptr(FPST_FPCR
);
6650 tcg_op1
= read_fp_dreg(s
, rn
);
6651 tcg_op2
= read_fp_dreg(s
, rm
);
6654 case 0x0: /* FMUL */
6655 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6657 case 0x1: /* FDIV */
6658 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6660 case 0x2: /* FADD */
6661 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6663 case 0x3: /* FSUB */
6664 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6666 case 0x4: /* FMAX */
6667 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6669 case 0x5: /* FMIN */
6670 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6672 case 0x6: /* FMAXNM */
6673 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6675 case 0x7: /* FMINNM */
6676 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6678 case 0x8: /* FNMUL */
6679 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6680 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6684 write_fp_dreg(s
, rd
, tcg_res
);
6686 tcg_temp_free_ptr(fpst
);
6687 tcg_temp_free_i64(tcg_op1
);
6688 tcg_temp_free_i64(tcg_op2
);
6689 tcg_temp_free_i64(tcg_res
);
6692 /* Floating-point data-processing (2 source) - half precision */
6693 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6694 int rd
, int rn
, int rm
)
6701 tcg_res
= tcg_temp_new_i32();
6702 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6703 tcg_op1
= read_fp_hreg(s
, rn
);
6704 tcg_op2
= read_fp_hreg(s
, rm
);
6707 case 0x0: /* FMUL */
6708 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6710 case 0x1: /* FDIV */
6711 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6713 case 0x2: /* FADD */
6714 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6716 case 0x3: /* FSUB */
6717 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6719 case 0x4: /* FMAX */
6720 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6722 case 0x5: /* FMIN */
6723 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6725 case 0x6: /* FMAXNM */
6726 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6728 case 0x7: /* FMINNM */
6729 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6731 case 0x8: /* FNMUL */
6732 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6733 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6736 g_assert_not_reached();
6739 write_fp_sreg(s
, rd
, tcg_res
);
6741 tcg_temp_free_ptr(fpst
);
6742 tcg_temp_free_i32(tcg_op1
);
6743 tcg_temp_free_i32(tcg_op2
);
6744 tcg_temp_free_i32(tcg_res
);
6747 /* Floating point data-processing (2 source)
6748 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6749 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6750 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6751 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6753 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6755 int mos
= extract32(insn
, 29, 3);
6756 int type
= extract32(insn
, 22, 2);
6757 int rd
= extract32(insn
, 0, 5);
6758 int rn
= extract32(insn
, 5, 5);
6759 int rm
= extract32(insn
, 16, 5);
6760 int opcode
= extract32(insn
, 12, 4);
6762 if (opcode
> 8 || mos
) {
6763 unallocated_encoding(s
);
6769 if (!fp_access_check(s
)) {
6772 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6775 if (!fp_access_check(s
)) {
6778 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6781 if (!dc_isar_feature(aa64_fp16
, s
)) {
6782 unallocated_encoding(s
);
6785 if (!fp_access_check(s
)) {
6788 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6791 unallocated_encoding(s
);
6795 /* Floating-point data-processing (3 source) - single precision */
6796 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6797 int rd
, int rn
, int rm
, int ra
)
6799 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6800 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6801 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6803 tcg_op1
= read_fp_sreg(s
, rn
);
6804 tcg_op2
= read_fp_sreg(s
, rm
);
6805 tcg_op3
= read_fp_sreg(s
, ra
);
6807 /* These are fused multiply-add, and must be done as one
6808 * floating point operation with no rounding between the
6809 * multiplication and addition steps.
6810 * NB that doing the negations here as separate steps is
6811 * correct : an input NaN should come out with its sign bit
6812 * flipped if it is a negated-input.
6815 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6819 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6822 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6824 write_fp_sreg(s
, rd
, tcg_res
);
6826 tcg_temp_free_ptr(fpst
);
6827 tcg_temp_free_i32(tcg_op1
);
6828 tcg_temp_free_i32(tcg_op2
);
6829 tcg_temp_free_i32(tcg_op3
);
6830 tcg_temp_free_i32(tcg_res
);
6833 /* Floating-point data-processing (3 source) - double precision */
6834 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6835 int rd
, int rn
, int rm
, int ra
)
6837 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6838 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6839 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6841 tcg_op1
= read_fp_dreg(s
, rn
);
6842 tcg_op2
= read_fp_dreg(s
, rm
);
6843 tcg_op3
= read_fp_dreg(s
, ra
);
6845 /* These are fused multiply-add, and must be done as one
6846 * floating point operation with no rounding between the
6847 * multiplication and addition steps.
6848 * NB that doing the negations here as separate steps is
6849 * correct : an input NaN should come out with its sign bit
6850 * flipped if it is a negated-input.
6853 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6857 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6860 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6862 write_fp_dreg(s
, rd
, tcg_res
);
6864 tcg_temp_free_ptr(fpst
);
6865 tcg_temp_free_i64(tcg_op1
);
6866 tcg_temp_free_i64(tcg_op2
);
6867 tcg_temp_free_i64(tcg_op3
);
6868 tcg_temp_free_i64(tcg_res
);
6871 /* Floating-point data-processing (3 source) - half precision */
6872 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6873 int rd
, int rn
, int rm
, int ra
)
6875 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6876 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6877 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6879 tcg_op1
= read_fp_hreg(s
, rn
);
6880 tcg_op2
= read_fp_hreg(s
, rm
);
6881 tcg_op3
= read_fp_hreg(s
, ra
);
6883 /* These are fused multiply-add, and must be done as one
6884 * floating point operation with no rounding between the
6885 * multiplication and addition steps.
6886 * NB that doing the negations here as separate steps is
6887 * correct : an input NaN should come out with its sign bit
6888 * flipped if it is a negated-input.
6891 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6895 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6898 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6900 write_fp_sreg(s
, rd
, tcg_res
);
6902 tcg_temp_free_ptr(fpst
);
6903 tcg_temp_free_i32(tcg_op1
);
6904 tcg_temp_free_i32(tcg_op2
);
6905 tcg_temp_free_i32(tcg_op3
);
6906 tcg_temp_free_i32(tcg_res
);
6909 /* Floating point data-processing (3 source)
6910 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6911 * +---+---+---+-----------+------+----+------+----+------+------+------+
6912 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6913 * +---+---+---+-----------+------+----+------+----+------+------+------+
6915 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6917 int mos
= extract32(insn
, 29, 3);
6918 int type
= extract32(insn
, 22, 2);
6919 int rd
= extract32(insn
, 0, 5);
6920 int rn
= extract32(insn
, 5, 5);
6921 int ra
= extract32(insn
, 10, 5);
6922 int rm
= extract32(insn
, 16, 5);
6923 bool o0
= extract32(insn
, 15, 1);
6924 bool o1
= extract32(insn
, 21, 1);
6927 unallocated_encoding(s
);
6933 if (!fp_access_check(s
)) {
6936 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6939 if (!fp_access_check(s
)) {
6942 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6945 if (!dc_isar_feature(aa64_fp16
, s
)) {
6946 unallocated_encoding(s
);
6949 if (!fp_access_check(s
)) {
6952 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6955 unallocated_encoding(s
);
6959 /* Floating point immediate
6960 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6961 * +---+---+---+-----------+------+---+------------+-------+------+------+
6962 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6963 * +---+---+---+-----------+------+---+------------+-------+------+------+
6965 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6967 int rd
= extract32(insn
, 0, 5);
6968 int imm5
= extract32(insn
, 5, 5);
6969 int imm8
= extract32(insn
, 13, 8);
6970 int type
= extract32(insn
, 22, 2);
6971 int mos
= extract32(insn
, 29, 3);
6977 unallocated_encoding(s
);
6990 if (dc_isar_feature(aa64_fp16
, s
)) {
6995 unallocated_encoding(s
);
6999 if (!fp_access_check(s
)) {
7003 imm
= vfp_expand_imm(sz
, imm8
);
7005 tcg_res
= tcg_const_i64(imm
);
7006 write_fp_dreg(s
, rd
, tcg_res
);
7007 tcg_temp_free_i64(tcg_res
);
7010 /* Handle floating point <=> fixed point conversions. Note that we can
7011 * also deal with fp <=> integer conversions as a special case (scale == 64)
7012 * OPTME: consider handling that special case specially or at least skipping
7013 * the call to scalbn in the helpers for zero shifts.
7015 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
7016 bool itof
, int rmode
, int scale
, int sf
, int type
)
7018 bool is_signed
= !(opcode
& 1);
7019 TCGv_ptr tcg_fpstatus
;
7020 TCGv_i32 tcg_shift
, tcg_single
;
7021 TCGv_i64 tcg_double
;
7023 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
7025 tcg_shift
= tcg_const_i32(64 - scale
);
7028 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
7030 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
7033 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
7035 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
7038 tcg_int
= tcg_extend
;
7042 case 1: /* float64 */
7043 tcg_double
= tcg_temp_new_i64();
7045 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
7046 tcg_shift
, tcg_fpstatus
);
7048 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
7049 tcg_shift
, tcg_fpstatus
);
7051 write_fp_dreg(s
, rd
, tcg_double
);
7052 tcg_temp_free_i64(tcg_double
);
7055 case 0: /* float32 */
7056 tcg_single
= tcg_temp_new_i32();
7058 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
7059 tcg_shift
, tcg_fpstatus
);
7061 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
7062 tcg_shift
, tcg_fpstatus
);
7064 write_fp_sreg(s
, rd
, tcg_single
);
7065 tcg_temp_free_i32(tcg_single
);
7068 case 3: /* float16 */
7069 tcg_single
= tcg_temp_new_i32();
7071 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7072 tcg_shift
, tcg_fpstatus
);
7074 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7075 tcg_shift
, tcg_fpstatus
);
7077 write_fp_sreg(s
, rd
, tcg_single
);
7078 tcg_temp_free_i32(tcg_single
);
7082 g_assert_not_reached();
7085 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7088 if (extract32(opcode
, 2, 1)) {
7089 /* There are too many rounding modes to all fit into rmode,
7090 * so FCVTA[US] is a special case.
7092 rmode
= FPROUNDING_TIEAWAY
;
7095 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7097 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7100 case 1: /* float64 */
7101 tcg_double
= read_fp_dreg(s
, rn
);
7104 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7105 tcg_shift
, tcg_fpstatus
);
7107 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7108 tcg_shift
, tcg_fpstatus
);
7112 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7113 tcg_shift
, tcg_fpstatus
);
7115 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7116 tcg_shift
, tcg_fpstatus
);
7120 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7122 tcg_temp_free_i64(tcg_double
);
7125 case 0: /* float32 */
7126 tcg_single
= read_fp_sreg(s
, rn
);
7129 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7130 tcg_shift
, tcg_fpstatus
);
7132 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7133 tcg_shift
, tcg_fpstatus
);
7136 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7138 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7139 tcg_shift
, tcg_fpstatus
);
7141 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7142 tcg_shift
, tcg_fpstatus
);
7144 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7145 tcg_temp_free_i32(tcg_dest
);
7147 tcg_temp_free_i32(tcg_single
);
7150 case 3: /* float16 */
7151 tcg_single
= read_fp_sreg(s
, rn
);
7154 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7155 tcg_shift
, tcg_fpstatus
);
7157 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7158 tcg_shift
, tcg_fpstatus
);
7161 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7163 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7164 tcg_shift
, tcg_fpstatus
);
7166 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7167 tcg_shift
, tcg_fpstatus
);
7169 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7170 tcg_temp_free_i32(tcg_dest
);
7172 tcg_temp_free_i32(tcg_single
);
7176 g_assert_not_reached();
7179 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7180 tcg_temp_free_i32(tcg_rmode
);
7183 tcg_temp_free_ptr(tcg_fpstatus
);
7184 tcg_temp_free_i32(tcg_shift
);
7187 /* Floating point <-> fixed point conversions
7188 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7189 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7190 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7191 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7193 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7195 int rd
= extract32(insn
, 0, 5);
7196 int rn
= extract32(insn
, 5, 5);
7197 int scale
= extract32(insn
, 10, 6);
7198 int opcode
= extract32(insn
, 16, 3);
7199 int rmode
= extract32(insn
, 19, 2);
7200 int type
= extract32(insn
, 22, 2);
7201 bool sbit
= extract32(insn
, 29, 1);
7202 bool sf
= extract32(insn
, 31, 1);
7205 if (sbit
|| (!sf
&& scale
< 32)) {
7206 unallocated_encoding(s
);
7211 case 0: /* float32 */
7212 case 1: /* float64 */
7214 case 3: /* float16 */
7215 if (dc_isar_feature(aa64_fp16
, s
)) {
7220 unallocated_encoding(s
);
7224 switch ((rmode
<< 3) | opcode
) {
7225 case 0x2: /* SCVTF */
7226 case 0x3: /* UCVTF */
7229 case 0x18: /* FCVTZS */
7230 case 0x19: /* FCVTZU */
7234 unallocated_encoding(s
);
7238 if (!fp_access_check(s
)) {
7242 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7245 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7247 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7248 * without conversion.
7252 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7258 tmp
= tcg_temp_new_i64();
7259 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7260 write_fp_dreg(s
, rd
, tmp
);
7261 tcg_temp_free_i64(tmp
);
7265 write_fp_dreg(s
, rd
, tcg_rn
);
7268 /* 64 bit to top half. */
7269 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7270 clear_vec_high(s
, true, rd
);
7274 tmp
= tcg_temp_new_i64();
7275 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7276 write_fp_dreg(s
, rd
, tmp
);
7277 tcg_temp_free_i64(tmp
);
7280 g_assert_not_reached();
7283 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7288 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7292 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7295 /* 64 bits from top half */
7296 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7300 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7303 g_assert_not_reached();
7308 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7310 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7311 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7313 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7315 tcg_temp_free_ptr(fpstatus
);
7317 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7318 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7319 tcg_gen_movi_i32(cpu_CF
, 0);
7320 tcg_gen_movi_i32(cpu_NF
, 0);
7321 tcg_gen_movi_i32(cpu_VF
, 0);
7323 tcg_temp_free_i64(t
);
7326 /* Floating point <-> integer conversions
7327 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7328 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7329 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7330 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7332 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7334 int rd
= extract32(insn
, 0, 5);
7335 int rn
= extract32(insn
, 5, 5);
7336 int opcode
= extract32(insn
, 16, 3);
7337 int rmode
= extract32(insn
, 19, 2);
7338 int type
= extract32(insn
, 22, 2);
7339 bool sbit
= extract32(insn
, 29, 1);
7340 bool sf
= extract32(insn
, 31, 1);
7344 goto do_unallocated
;
7352 case 4: /* FCVTAS */
7353 case 5: /* FCVTAU */
7355 goto do_unallocated
;
7358 case 0: /* FCVT[NPMZ]S */
7359 case 1: /* FCVT[NPMZ]U */
7361 case 0: /* float32 */
7362 case 1: /* float64 */
7364 case 3: /* float16 */
7365 if (!dc_isar_feature(aa64_fp16
, s
)) {
7366 goto do_unallocated
;
7370 goto do_unallocated
;
7372 if (!fp_access_check(s
)) {
7375 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7379 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7380 case 0b01100110: /* FMOV half <-> 32-bit int */
7382 case 0b11100110: /* FMOV half <-> 64-bit int */
7384 if (!dc_isar_feature(aa64_fp16
, s
)) {
7385 goto do_unallocated
;
7388 case 0b00000110: /* FMOV 32-bit */
7390 case 0b10100110: /* FMOV 64-bit */
7392 case 0b11001110: /* FMOV top half of 128-bit */
7394 if (!fp_access_check(s
)) {
7398 handle_fmov(s
, rd
, rn
, type
, itof
);
7401 case 0b00111110: /* FJCVTZS */
7402 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7403 goto do_unallocated
;
7404 } else if (fp_access_check(s
)) {
7405 handle_fjcvtzs(s
, rd
, rn
);
7411 unallocated_encoding(s
);
7418 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7419 * 31 30 29 28 25 24 0
7420 * +---+---+---+---------+-----------------------------+
7421 * | | 0 | | 1 1 1 1 | |
7422 * +---+---+---+---------+-----------------------------+
7424 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7426 if (extract32(insn
, 24, 1)) {
7427 /* Floating point data-processing (3 source) */
7428 disas_fp_3src(s
, insn
);
7429 } else if (extract32(insn
, 21, 1) == 0) {
7430 /* Floating point to fixed point conversions */
7431 disas_fp_fixed_conv(s
, insn
);
7433 switch (extract32(insn
, 10, 2)) {
7435 /* Floating point conditional compare */
7436 disas_fp_ccomp(s
, insn
);
7439 /* Floating point data-processing (2 source) */
7440 disas_fp_2src(s
, insn
);
7443 /* Floating point conditional select */
7444 disas_fp_csel(s
, insn
);
7447 switch (ctz32(extract32(insn
, 12, 4))) {
7448 case 0: /* [15:12] == xxx1 */
7449 /* Floating point immediate */
7450 disas_fp_imm(s
, insn
);
7452 case 1: /* [15:12] == xx10 */
7453 /* Floating point compare */
7454 disas_fp_compare(s
, insn
);
7456 case 2: /* [15:12] == x100 */
7457 /* Floating point data-processing (1 source) */
7458 disas_fp_1src(s
, insn
);
7460 case 3: /* [15:12] == 1000 */
7461 unallocated_encoding(s
);
7463 default: /* [15:12] == 0000 */
7464 /* Floating point <-> integer conversions */
7465 disas_fp_int_conv(s
, insn
);
7473 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7476 /* Extract 64 bits from the middle of two concatenated 64 bit
7477 * vector register slices left:right. The extracted bits start
7478 * at 'pos' bits into the right (least significant) side.
7479 * We return the result in tcg_right, and guarantee not to
7482 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7483 assert(pos
> 0 && pos
< 64);
7485 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7486 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7487 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7489 tcg_temp_free_i64(tcg_tmp
);
7493 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7494 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7495 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7496 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7498 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7500 int is_q
= extract32(insn
, 30, 1);
7501 int op2
= extract32(insn
, 22, 2);
7502 int imm4
= extract32(insn
, 11, 4);
7503 int rm
= extract32(insn
, 16, 5);
7504 int rn
= extract32(insn
, 5, 5);
7505 int rd
= extract32(insn
, 0, 5);
7506 int pos
= imm4
<< 3;
7507 TCGv_i64 tcg_resl
, tcg_resh
;
7509 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7510 unallocated_encoding(s
);
7514 if (!fp_access_check(s
)) {
7518 tcg_resh
= tcg_temp_new_i64();
7519 tcg_resl
= tcg_temp_new_i64();
7521 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7522 * either extracting 128 bits from a 128:128 concatenation, or
7523 * extracting 64 bits from a 64:64 concatenation.
7526 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7528 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7529 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7537 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7538 EltPosns
*elt
= eltposns
;
7545 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7547 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7550 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7551 tcg_hh
= tcg_temp_new_i64();
7552 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7553 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7554 tcg_temp_free_i64(tcg_hh
);
7558 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7559 tcg_temp_free_i64(tcg_resl
);
7561 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7563 tcg_temp_free_i64(tcg_resh
);
7564 clear_vec_high(s
, is_q
, rd
);
7568 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7569 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7570 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7571 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7573 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7575 int op2
= extract32(insn
, 22, 2);
7576 int is_q
= extract32(insn
, 30, 1);
7577 int rm
= extract32(insn
, 16, 5);
7578 int rn
= extract32(insn
, 5, 5);
7579 int rd
= extract32(insn
, 0, 5);
7580 int is_tbx
= extract32(insn
, 12, 1);
7581 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7584 unallocated_encoding(s
);
7588 if (!fp_access_check(s
)) {
7592 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7593 vec_full_reg_offset(s
, rm
), cpu_env
,
7594 is_q
? 16 : 8, vec_full_reg_size(s
),
7595 (len
<< 6) | (is_tbx
<< 5) | rn
,
7596 gen_helper_simd_tblx
);
7600 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7601 * +---+---+-------------+------+---+------+---+------------------+------+
7602 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7603 * +---+---+-------------+------+---+------+---+------------------+------+
7605 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7607 int rd
= extract32(insn
, 0, 5);
7608 int rn
= extract32(insn
, 5, 5);
7609 int rm
= extract32(insn
, 16, 5);
7610 int size
= extract32(insn
, 22, 2);
7611 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7612 * bit 2 indicates 1 vs 2 variant of the insn.
7614 int opcode
= extract32(insn
, 12, 2);
7615 bool part
= extract32(insn
, 14, 1);
7616 bool is_q
= extract32(insn
, 30, 1);
7617 int esize
= 8 << size
;
7619 int datasize
= is_q
? 128 : 64;
7620 int elements
= datasize
/ esize
;
7621 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7623 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7624 unallocated_encoding(s
);
7628 if (!fp_access_check(s
)) {
7632 tcg_resl
= tcg_const_i64(0);
7633 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7634 tcg_res
= tcg_temp_new_i64();
7636 for (i
= 0; i
< elements
; i
++) {
7638 case 1: /* UZP1/2 */
7640 int midpoint
= elements
/ 2;
7642 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7644 read_vec_element(s
, tcg_res
, rm
,
7645 2 * (i
- midpoint
) + part
, size
);
7649 case 2: /* TRN1/2 */
7651 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7653 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7656 case 3: /* ZIP1/2 */
7658 int base
= part
* elements
/ 2;
7660 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7662 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7667 g_assert_not_reached();
7672 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7673 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7675 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7676 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7680 tcg_temp_free_i64(tcg_res
);
7682 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7683 tcg_temp_free_i64(tcg_resl
);
7686 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7687 tcg_temp_free_i64(tcg_resh
);
7689 clear_vec_high(s
, is_q
, rd
);
7693 * do_reduction_op helper
7695 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7696 * important for correct NaN propagation that we do these
7697 * operations in exactly the order specified by the pseudocode.
7699 * This is a recursive function, TCG temps should be freed by the
7700 * calling function once it is done with the values.
7702 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7703 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7705 if (esize
== size
) {
7707 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7710 /* We should have one register left here */
7711 assert(ctpop8(vmap
) == 1);
7712 element
= ctz32(vmap
);
7713 assert(element
< 8);
7715 tcg_elem
= tcg_temp_new_i32();
7716 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7719 int bits
= size
/ 2;
7720 int shift
= ctpop8(vmap
) / 2;
7721 int vmap_lo
= (vmap
>> shift
) & vmap
;
7722 int vmap_hi
= (vmap
& ~vmap_lo
);
7723 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7725 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7726 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7727 tcg_res
= tcg_temp_new_i32();
7730 case 0x0c: /* fmaxnmv half-precision */
7731 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7733 case 0x0f: /* fmaxv half-precision */
7734 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7736 case 0x1c: /* fminnmv half-precision */
7737 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7739 case 0x1f: /* fminv half-precision */
7740 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7742 case 0x2c: /* fmaxnmv */
7743 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7745 case 0x2f: /* fmaxv */
7746 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7748 case 0x3c: /* fminnmv */
7749 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7751 case 0x3f: /* fminv */
7752 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7755 g_assert_not_reached();
7758 tcg_temp_free_i32(tcg_hi
);
7759 tcg_temp_free_i32(tcg_lo
);
7764 /* AdvSIMD across lanes
7765 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7766 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7767 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7768 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7770 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7772 int rd
= extract32(insn
, 0, 5);
7773 int rn
= extract32(insn
, 5, 5);
7774 int size
= extract32(insn
, 22, 2);
7775 int opcode
= extract32(insn
, 12, 5);
7776 bool is_q
= extract32(insn
, 30, 1);
7777 bool is_u
= extract32(insn
, 29, 1);
7779 bool is_min
= false;
7783 TCGv_i64 tcg_res
, tcg_elt
;
7786 case 0x1b: /* ADDV */
7788 unallocated_encoding(s
);
7792 case 0x3: /* SADDLV, UADDLV */
7793 case 0xa: /* SMAXV, UMAXV */
7794 case 0x1a: /* SMINV, UMINV */
7795 if (size
== 3 || (size
== 2 && !is_q
)) {
7796 unallocated_encoding(s
);
7800 case 0xc: /* FMAXNMV, FMINNMV */
7801 case 0xf: /* FMAXV, FMINV */
7802 /* Bit 1 of size field encodes min vs max and the actual size
7803 * depends on the encoding of the U bit. If not set (and FP16
7804 * enabled) then we do half-precision float instead of single
7807 is_min
= extract32(size
, 1, 1);
7809 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7811 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7812 unallocated_encoding(s
);
7819 unallocated_encoding(s
);
7823 if (!fp_access_check(s
)) {
7828 elements
= (is_q
? 128 : 64) / esize
;
7830 tcg_res
= tcg_temp_new_i64();
7831 tcg_elt
= tcg_temp_new_i64();
7833 /* These instructions operate across all lanes of a vector
7834 * to produce a single result. We can guarantee that a 64
7835 * bit intermediate is sufficient:
7836 * + for [US]ADDLV the maximum element size is 32 bits, and
7837 * the result type is 64 bits
7838 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7839 * same as the element size, which is 32 bits at most
7840 * For the integer operations we can choose to work at 64
7841 * or 32 bits and truncate at the end; for simplicity
7842 * we use 64 bits always. The floating point
7843 * ops do require 32 bit intermediates, though.
7846 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7848 for (i
= 1; i
< elements
; i
++) {
7849 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7852 case 0x03: /* SADDLV / UADDLV */
7853 case 0x1b: /* ADDV */
7854 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7856 case 0x0a: /* SMAXV / UMAXV */
7858 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7860 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7863 case 0x1a: /* SMINV / UMINV */
7865 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7867 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7871 g_assert_not_reached();
7876 /* Floating point vector reduction ops which work across 32
7877 * bit (single) or 16 bit (half-precision) intermediates.
7878 * Note that correct NaN propagation requires that we do these
7879 * operations in exactly the order specified by the pseudocode.
7881 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7882 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7883 int vmap
= (1 << elements
) - 1;
7884 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7885 (is_q
? 128 : 64), vmap
, fpst
);
7886 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7887 tcg_temp_free_i32(tcg_res32
);
7888 tcg_temp_free_ptr(fpst
);
7891 tcg_temp_free_i64(tcg_elt
);
7893 /* Now truncate the result to the width required for the final output */
7894 if (opcode
== 0x03) {
7895 /* SADDLV, UADDLV: result is 2*esize */
7901 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7904 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7907 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7912 g_assert_not_reached();
7915 write_fp_dreg(s
, rd
, tcg_res
);
7916 tcg_temp_free_i64(tcg_res
);
7919 /* DUP (Element, Vector)
7921 * 31 30 29 21 20 16 15 10 9 5 4 0
7922 * +---+---+-------------------+--------+-------------+------+------+
7923 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7924 * +---+---+-------------------+--------+-------------+------+------+
7926 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7928 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7931 int size
= ctz32(imm5
);
7934 if (size
> 3 || (size
== 3 && !is_q
)) {
7935 unallocated_encoding(s
);
7939 if (!fp_access_check(s
)) {
7943 index
= imm5
>> (size
+ 1);
7944 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7945 vec_reg_offset(s
, rn
, index
, size
),
7946 is_q
? 16 : 8, vec_full_reg_size(s
));
7949 /* DUP (element, scalar)
7950 * 31 21 20 16 15 10 9 5 4 0
7951 * +-----------------------+--------+-------------+------+------+
7952 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7953 * +-----------------------+--------+-------------+------+------+
7955 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7958 int size
= ctz32(imm5
);
7963 unallocated_encoding(s
);
7967 if (!fp_access_check(s
)) {
7971 index
= imm5
>> (size
+ 1);
7973 /* This instruction just extracts the specified element and
7974 * zero-extends it into the bottom of the destination register.
7976 tmp
= tcg_temp_new_i64();
7977 read_vec_element(s
, tmp
, rn
, index
, size
);
7978 write_fp_dreg(s
, rd
, tmp
);
7979 tcg_temp_free_i64(tmp
);
7984 * 31 30 29 21 20 16 15 10 9 5 4 0
7985 * +---+---+-------------------+--------+-------------+------+------+
7986 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7987 * +---+---+-------------------+--------+-------------+------+------+
7989 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7991 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7994 int size
= ctz32(imm5
);
7995 uint32_t dofs
, oprsz
, maxsz
;
7997 if (size
> 3 || ((size
== 3) && !is_q
)) {
7998 unallocated_encoding(s
);
8002 if (!fp_access_check(s
)) {
8006 dofs
= vec_full_reg_offset(s
, rd
);
8007 oprsz
= is_q
? 16 : 8;
8008 maxsz
= vec_full_reg_size(s
);
8010 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
8015 * 31 21 20 16 15 14 11 10 9 5 4 0
8016 * +-----------------------+--------+------------+---+------+------+
8017 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8018 * +-----------------------+--------+------------+---+------+------+
8020 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8021 * index: encoded in imm5<4:size+1>
8023 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
8026 int size
= ctz32(imm5
);
8027 int src_index
, dst_index
;
8031 unallocated_encoding(s
);
8035 if (!fp_access_check(s
)) {
8039 dst_index
= extract32(imm5
, 1+size
, 5);
8040 src_index
= extract32(imm4
, size
, 4);
8042 tmp
= tcg_temp_new_i64();
8044 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8045 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8047 tcg_temp_free_i64(tmp
);
8049 /* INS is considered a 128-bit write for SVE. */
8050 clear_vec_high(s
, true, rd
);
8056 * 31 21 20 16 15 10 9 5 4 0
8057 * +-----------------------+--------+-------------+------+------+
8058 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8059 * +-----------------------+--------+-------------+------+------+
8061 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8062 * index: encoded in imm5<4:size+1>
8064 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8066 int size
= ctz32(imm5
);
8070 unallocated_encoding(s
);
8074 if (!fp_access_check(s
)) {
8078 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8079 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8081 /* INS is considered a 128-bit write for SVE. */
8082 clear_vec_high(s
, true, rd
);
8089 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8090 * +---+---+-------------------+--------+-------------+------+------+
8091 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8092 * +---+---+-------------------+--------+-------------+------+------+
8094 * U: unsigned when set
8095 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8097 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8098 int rn
, int rd
, int imm5
)
8100 int size
= ctz32(imm5
);
8104 /* Check for UnallocatedEncodings */
8106 if (size
> 2 || (size
== 2 && !is_q
)) {
8107 unallocated_encoding(s
);
8112 || (size
< 3 && is_q
)
8113 || (size
== 3 && !is_q
)) {
8114 unallocated_encoding(s
);
8119 if (!fp_access_check(s
)) {
8123 element
= extract32(imm5
, 1+size
, 4);
8125 tcg_rd
= cpu_reg(s
, rd
);
8126 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8127 if (is_signed
&& !is_q
) {
8128 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8133 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8134 * +---+---+----+-----------------+------+---+------+---+------+------+
8135 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8136 * +---+---+----+-----------------+------+---+------+---+------+------+
8138 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8140 int rd
= extract32(insn
, 0, 5);
8141 int rn
= extract32(insn
, 5, 5);
8142 int imm4
= extract32(insn
, 11, 4);
8143 int op
= extract32(insn
, 29, 1);
8144 int is_q
= extract32(insn
, 30, 1);
8145 int imm5
= extract32(insn
, 16, 5);
8150 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8152 unallocated_encoding(s
);
8157 /* DUP (element - vector) */
8158 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8162 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8167 handle_simd_insg(s
, rd
, rn
, imm5
);
8169 unallocated_encoding(s
);
8174 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8175 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8178 unallocated_encoding(s
);
8184 /* AdvSIMD modified immediate
8185 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8186 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8187 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8188 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8190 * There are a number of operations that can be carried out here:
8191 * MOVI - move (shifted) imm into register
8192 * MVNI - move inverted (shifted) imm into register
8193 * ORR - bitwise OR of (shifted) imm with register
8194 * BIC - bitwise clear of (shifted) imm with register
8195 * With ARMv8.2 we also have:
8196 * FMOV half-precision
8198 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8200 int rd
= extract32(insn
, 0, 5);
8201 int cmode
= extract32(insn
, 12, 4);
8202 int cmode_3_1
= extract32(cmode
, 1, 3);
8203 int cmode_0
= extract32(cmode
, 0, 1);
8204 int o2
= extract32(insn
, 11, 1);
8205 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8206 bool is_neg
= extract32(insn
, 29, 1);
8207 bool is_q
= extract32(insn
, 30, 1);
8210 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8211 /* Check for FMOV (vector, immediate) - half-precision */
8212 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8213 unallocated_encoding(s
);
8218 if (!fp_access_check(s
)) {
8222 /* See AdvSIMDExpandImm() in ARM ARM */
8223 switch (cmode_3_1
) {
8224 case 0: /* Replicate(Zeros(24):imm8, 2) */
8225 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
8226 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
8227 case 3: /* Replicate(imm8:Zeros(24), 2) */
8229 int shift
= cmode_3_1
* 8;
8230 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
8233 case 4: /* Replicate(Zeros(8):imm8, 4) */
8234 case 5: /* Replicate(imm8:Zeros(8), 4) */
8236 int shift
= (cmode_3_1
& 0x1) * 8;
8237 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
8242 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
8243 imm
= (abcdefgh
<< 16) | 0xffff;
8245 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
8246 imm
= (abcdefgh
<< 8) | 0xff;
8248 imm
= bitfield_replicate(imm
, 32);
8251 if (!cmode_0
&& !is_neg
) {
8252 imm
= bitfield_replicate(abcdefgh
, 8);
8253 } else if (!cmode_0
&& is_neg
) {
8256 for (i
= 0; i
< 8; i
++) {
8257 if ((abcdefgh
) & (1 << i
)) {
8258 imm
|= 0xffULL
<< (i
* 8);
8261 } else if (cmode_0
) {
8263 imm
= (abcdefgh
& 0x3f) << 48;
8264 if (abcdefgh
& 0x80) {
8265 imm
|= 0x8000000000000000ULL
;
8267 if (abcdefgh
& 0x40) {
8268 imm
|= 0x3fc0000000000000ULL
;
8270 imm
|= 0x4000000000000000ULL
;
8274 /* FMOV (vector, immediate) - half-precision */
8275 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8276 /* now duplicate across the lanes */
8277 imm
= bitfield_replicate(imm
, 16);
8279 imm
= (abcdefgh
& 0x3f) << 19;
8280 if (abcdefgh
& 0x80) {
8283 if (abcdefgh
& 0x40) {
8294 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
8295 g_assert_not_reached();
8298 if (cmode_3_1
!= 7 && is_neg
) {
8302 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8303 /* MOVI or MVNI, with MVNI negation handled above. */
8304 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8305 vec_full_reg_size(s
), imm
);
8307 /* ORR or BIC, with BIC negation to AND handled above. */
8309 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8311 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8316 /* AdvSIMD scalar copy
8317 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8318 * +-----+----+-----------------+------+---+------+---+------+------+
8319 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8320 * +-----+----+-----------------+------+---+------+---+------+------+
8322 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8324 int rd
= extract32(insn
, 0, 5);
8325 int rn
= extract32(insn
, 5, 5);
8326 int imm4
= extract32(insn
, 11, 4);
8327 int imm5
= extract32(insn
, 16, 5);
8328 int op
= extract32(insn
, 29, 1);
8330 if (op
!= 0 || imm4
!= 0) {
8331 unallocated_encoding(s
);
8335 /* DUP (element, scalar) */
8336 handle_simd_dupes(s
, rd
, rn
, imm5
);
8339 /* AdvSIMD scalar pairwise
8340 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8341 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8342 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8343 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8345 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8347 int u
= extract32(insn
, 29, 1);
8348 int size
= extract32(insn
, 22, 2);
8349 int opcode
= extract32(insn
, 12, 5);
8350 int rn
= extract32(insn
, 5, 5);
8351 int rd
= extract32(insn
, 0, 5);
8354 /* For some ops (the FP ones), size[1] is part of the encoding.
8355 * For ADDP strictly it is not but size[1] is always 1 for valid
8358 opcode
|= (extract32(size
, 1, 1) << 5);
8361 case 0x3b: /* ADDP */
8362 if (u
|| size
!= 3) {
8363 unallocated_encoding(s
);
8366 if (!fp_access_check(s
)) {
8372 case 0xc: /* FMAXNMP */
8373 case 0xd: /* FADDP */
8374 case 0xf: /* FMAXP */
8375 case 0x2c: /* FMINNMP */
8376 case 0x2f: /* FMINP */
8377 /* FP op, size[0] is 32 or 64 bit*/
8379 if (!dc_isar_feature(aa64_fp16
, s
)) {
8380 unallocated_encoding(s
);
8386 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8389 if (!fp_access_check(s
)) {
8393 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8396 unallocated_encoding(s
);
8400 if (size
== MO_64
) {
8401 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8402 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8403 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8405 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8406 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8409 case 0x3b: /* ADDP */
8410 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8412 case 0xc: /* FMAXNMP */
8413 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8415 case 0xd: /* FADDP */
8416 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8418 case 0xf: /* FMAXP */
8419 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8421 case 0x2c: /* FMINNMP */
8422 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8424 case 0x2f: /* FMINP */
8425 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8428 g_assert_not_reached();
8431 write_fp_dreg(s
, rd
, tcg_res
);
8433 tcg_temp_free_i64(tcg_op1
);
8434 tcg_temp_free_i64(tcg_op2
);
8435 tcg_temp_free_i64(tcg_res
);
8437 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8438 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8439 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8441 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8442 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8444 if (size
== MO_16
) {
8446 case 0xc: /* FMAXNMP */
8447 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8449 case 0xd: /* FADDP */
8450 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8452 case 0xf: /* FMAXP */
8453 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8455 case 0x2c: /* FMINNMP */
8456 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8458 case 0x2f: /* FMINP */
8459 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8462 g_assert_not_reached();
8466 case 0xc: /* FMAXNMP */
8467 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8469 case 0xd: /* FADDP */
8470 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8472 case 0xf: /* FMAXP */
8473 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8475 case 0x2c: /* FMINNMP */
8476 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8478 case 0x2f: /* FMINP */
8479 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8482 g_assert_not_reached();
8486 write_fp_sreg(s
, rd
, tcg_res
);
8488 tcg_temp_free_i32(tcg_op1
);
8489 tcg_temp_free_i32(tcg_op2
);
8490 tcg_temp_free_i32(tcg_res
);
8494 tcg_temp_free_ptr(fpst
);
8499 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8501 * This code is handles the common shifting code and is used by both
8502 * the vector and scalar code.
8504 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8505 TCGv_i64 tcg_rnd
, bool accumulate
,
8506 bool is_u
, int size
, int shift
)
8508 bool extended_result
= false;
8509 bool round
= tcg_rnd
!= NULL
;
8511 TCGv_i64 tcg_src_hi
;
8513 if (round
&& size
== 3) {
8514 extended_result
= true;
8515 ext_lshift
= 64 - shift
;
8516 tcg_src_hi
= tcg_temp_new_i64();
8517 } else if (shift
== 64) {
8518 if (!accumulate
&& is_u
) {
8519 /* result is zero */
8520 tcg_gen_movi_i64(tcg_res
, 0);
8525 /* Deal with the rounding step */
8527 if (extended_result
) {
8528 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8530 /* take care of sign extending tcg_res */
8531 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8532 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8533 tcg_src
, tcg_src_hi
,
8536 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8540 tcg_temp_free_i64(tcg_zero
);
8542 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8546 /* Now do the shift right */
8547 if (round
&& extended_result
) {
8548 /* extended case, >64 bit precision required */
8549 if (ext_lshift
== 0) {
8550 /* special case, only high bits matter */
8551 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8553 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8554 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8555 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8560 /* essentially shifting in 64 zeros */
8561 tcg_gen_movi_i64(tcg_src
, 0);
8563 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8567 /* effectively extending the sign-bit */
8568 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8570 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8576 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8578 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8581 if (extended_result
) {
8582 tcg_temp_free_i64(tcg_src_hi
);
8586 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8587 static void handle_scalar_simd_shri(DisasContext
*s
,
8588 bool is_u
, int immh
, int immb
,
8589 int opcode
, int rn
, int rd
)
8592 int immhb
= immh
<< 3 | immb
;
8593 int shift
= 2 * (8 << size
) - immhb
;
8594 bool accumulate
= false;
8596 bool insert
= false;
8601 if (!extract32(immh
, 3, 1)) {
8602 unallocated_encoding(s
);
8606 if (!fp_access_check(s
)) {
8611 case 0x02: /* SSRA / USRA (accumulate) */
8614 case 0x04: /* SRSHR / URSHR (rounding) */
8617 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8618 accumulate
= round
= true;
8620 case 0x08: /* SRI */
8626 uint64_t round_const
= 1ULL << (shift
- 1);
8627 tcg_round
= tcg_const_i64(round_const
);
8632 tcg_rn
= read_fp_dreg(s
, rn
);
8633 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8636 /* shift count same as element size is valid but does nothing;
8637 * special case to avoid potential shift by 64.
8639 int esize
= 8 << size
;
8640 if (shift
!= esize
) {
8641 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8642 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8645 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8646 accumulate
, is_u
, size
, shift
);
8649 write_fp_dreg(s
, rd
, tcg_rd
);
8651 tcg_temp_free_i64(tcg_rn
);
8652 tcg_temp_free_i64(tcg_rd
);
8654 tcg_temp_free_i64(tcg_round
);
8658 /* SHL/SLI - Scalar shift left */
8659 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8660 int immh
, int immb
, int opcode
,
8663 int size
= 32 - clz32(immh
) - 1;
8664 int immhb
= immh
<< 3 | immb
;
8665 int shift
= immhb
- (8 << size
);
8669 if (!extract32(immh
, 3, 1)) {
8670 unallocated_encoding(s
);
8674 if (!fp_access_check(s
)) {
8678 tcg_rn
= read_fp_dreg(s
, rn
);
8679 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8682 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8684 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8687 write_fp_dreg(s
, rd
, tcg_rd
);
8689 tcg_temp_free_i64(tcg_rn
);
8690 tcg_temp_free_i64(tcg_rd
);
8693 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8694 * (signed/unsigned) narrowing */
8695 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8696 bool is_u_shift
, bool is_u_narrow
,
8697 int immh
, int immb
, int opcode
,
8700 int immhb
= immh
<< 3 | immb
;
8701 int size
= 32 - clz32(immh
) - 1;
8702 int esize
= 8 << size
;
8703 int shift
= (2 * esize
) - immhb
;
8704 int elements
= is_scalar
? 1 : (64 / esize
);
8705 bool round
= extract32(opcode
, 0, 1);
8706 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8707 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8708 TCGv_i32 tcg_rd_narrowed
;
8711 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8712 { gen_helper_neon_narrow_sat_s8
,
8713 gen_helper_neon_unarrow_sat8
},
8714 { gen_helper_neon_narrow_sat_s16
,
8715 gen_helper_neon_unarrow_sat16
},
8716 { gen_helper_neon_narrow_sat_s32
,
8717 gen_helper_neon_unarrow_sat32
},
8720 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8721 gen_helper_neon_narrow_sat_u8
,
8722 gen_helper_neon_narrow_sat_u16
,
8723 gen_helper_neon_narrow_sat_u32
,
8726 NeonGenNarrowEnvFn
*narrowfn
;
8732 if (extract32(immh
, 3, 1)) {
8733 unallocated_encoding(s
);
8737 if (!fp_access_check(s
)) {
8742 narrowfn
= unsigned_narrow_fns
[size
];
8744 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8747 tcg_rn
= tcg_temp_new_i64();
8748 tcg_rd
= tcg_temp_new_i64();
8749 tcg_rd_narrowed
= tcg_temp_new_i32();
8750 tcg_final
= tcg_const_i64(0);
8753 uint64_t round_const
= 1ULL << (shift
- 1);
8754 tcg_round
= tcg_const_i64(round_const
);
8759 for (i
= 0; i
< elements
; i
++) {
8760 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8761 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8762 false, is_u_shift
, size
+1, shift
);
8763 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8764 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8765 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8769 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8771 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8775 tcg_temp_free_i64(tcg_round
);
8777 tcg_temp_free_i64(tcg_rn
);
8778 tcg_temp_free_i64(tcg_rd
);
8779 tcg_temp_free_i32(tcg_rd_narrowed
);
8780 tcg_temp_free_i64(tcg_final
);
8782 clear_vec_high(s
, is_q
, rd
);
8785 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8786 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8787 bool src_unsigned
, bool dst_unsigned
,
8788 int immh
, int immb
, int rn
, int rd
)
8790 int immhb
= immh
<< 3 | immb
;
8791 int size
= 32 - clz32(immh
) - 1;
8792 int shift
= immhb
- (8 << size
);
8796 assert(!(scalar
&& is_q
));
8799 if (!is_q
&& extract32(immh
, 3, 1)) {
8800 unallocated_encoding(s
);
8804 /* Since we use the variable-shift helpers we must
8805 * replicate the shift count into each element of
8806 * the tcg_shift value.
8810 shift
|= shift
<< 8;
8813 shift
|= shift
<< 16;
8819 g_assert_not_reached();
8823 if (!fp_access_check(s
)) {
8828 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8829 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8830 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8831 { NULL
, gen_helper_neon_qshl_u64
},
8833 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8834 int maxpass
= is_q
? 2 : 1;
8836 for (pass
= 0; pass
< maxpass
; pass
++) {
8837 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8839 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8840 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8841 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8843 tcg_temp_free_i64(tcg_op
);
8845 tcg_temp_free_i64(tcg_shift
);
8846 clear_vec_high(s
, is_q
, rd
);
8848 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8849 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8851 { gen_helper_neon_qshl_s8
,
8852 gen_helper_neon_qshl_s16
,
8853 gen_helper_neon_qshl_s32
},
8854 { gen_helper_neon_qshlu_s8
,
8855 gen_helper_neon_qshlu_s16
,
8856 gen_helper_neon_qshlu_s32
}
8858 { NULL
, NULL
, NULL
},
8859 { gen_helper_neon_qshl_u8
,
8860 gen_helper_neon_qshl_u16
,
8861 gen_helper_neon_qshl_u32
}
8864 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8865 MemOp memop
= scalar
? size
: MO_32
;
8866 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8868 for (pass
= 0; pass
< maxpass
; pass
++) {
8869 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8871 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8872 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8876 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8879 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8884 g_assert_not_reached();
8886 write_fp_sreg(s
, rd
, tcg_op
);
8888 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8891 tcg_temp_free_i32(tcg_op
);
8893 tcg_temp_free_i32(tcg_shift
);
8896 clear_vec_high(s
, is_q
, rd
);
8901 /* Common vector code for handling integer to FP conversion */
8902 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8903 int elements
, int is_signed
,
8904 int fracbits
, int size
)
8906 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8907 TCGv_i32 tcg_shift
= NULL
;
8909 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8912 if (fracbits
|| size
== MO_64
) {
8913 tcg_shift
= tcg_const_i32(fracbits
);
8916 if (size
== MO_64
) {
8917 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8918 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8920 for (pass
= 0; pass
< elements
; pass
++) {
8921 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8924 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8925 tcg_shift
, tcg_fpst
);
8927 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8928 tcg_shift
, tcg_fpst
);
8930 if (elements
== 1) {
8931 write_fp_dreg(s
, rd
, tcg_double
);
8933 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8937 tcg_temp_free_i64(tcg_int64
);
8938 tcg_temp_free_i64(tcg_double
);
8941 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8942 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8944 for (pass
= 0; pass
< elements
; pass
++) {
8945 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8951 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8952 tcg_shift
, tcg_fpst
);
8954 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8955 tcg_shift
, tcg_fpst
);
8959 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8961 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8968 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8969 tcg_shift
, tcg_fpst
);
8971 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8972 tcg_shift
, tcg_fpst
);
8976 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8978 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8983 g_assert_not_reached();
8986 if (elements
== 1) {
8987 write_fp_sreg(s
, rd
, tcg_float
);
8989 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8993 tcg_temp_free_i32(tcg_int32
);
8994 tcg_temp_free_i32(tcg_float
);
8997 tcg_temp_free_ptr(tcg_fpst
);
8999 tcg_temp_free_i32(tcg_shift
);
9002 clear_vec_high(s
, elements
<< size
== 16, rd
);
9005 /* UCVTF/SCVTF - Integer to FP conversion */
9006 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
9007 bool is_q
, bool is_u
,
9008 int immh
, int immb
, int opcode
,
9011 int size
, elements
, fracbits
;
9012 int immhb
= immh
<< 3 | immb
;
9016 if (!is_scalar
&& !is_q
) {
9017 unallocated_encoding(s
);
9020 } else if (immh
& 4) {
9022 } else if (immh
& 2) {
9024 if (!dc_isar_feature(aa64_fp16
, s
)) {
9025 unallocated_encoding(s
);
9029 /* immh == 0 would be a failure of the decode logic */
9030 g_assert(immh
== 1);
9031 unallocated_encoding(s
);
9038 elements
= (8 << is_q
) >> size
;
9040 fracbits
= (16 << size
) - immhb
;
9042 if (!fp_access_check(s
)) {
9046 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
9049 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
9050 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
9051 bool is_q
, bool is_u
,
9052 int immh
, int immb
, int rn
, int rd
)
9054 int immhb
= immh
<< 3 | immb
;
9055 int pass
, size
, fracbits
;
9056 TCGv_ptr tcg_fpstatus
;
9057 TCGv_i32 tcg_rmode
, tcg_shift
;
9061 if (!is_scalar
&& !is_q
) {
9062 unallocated_encoding(s
);
9065 } else if (immh
& 0x4) {
9067 } else if (immh
& 0x2) {
9069 if (!dc_isar_feature(aa64_fp16
, s
)) {
9070 unallocated_encoding(s
);
9074 /* Should have split out AdvSIMD modified immediate earlier. */
9076 unallocated_encoding(s
);
9080 if (!fp_access_check(s
)) {
9084 assert(!(is_scalar
&& is_q
));
9086 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9087 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9088 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9089 fracbits
= (16 << size
) - immhb
;
9090 tcg_shift
= tcg_const_i32(fracbits
);
9092 if (size
== MO_64
) {
9093 int maxpass
= is_scalar
? 1 : 2;
9095 for (pass
= 0; pass
< maxpass
; pass
++) {
9096 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9098 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9100 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9102 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9104 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9105 tcg_temp_free_i64(tcg_op
);
9107 clear_vec_high(s
, is_q
, rd
);
9109 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9110 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9115 fn
= gen_helper_vfp_touhh
;
9117 fn
= gen_helper_vfp_toshh
;
9122 fn
= gen_helper_vfp_touls
;
9124 fn
= gen_helper_vfp_tosls
;
9128 g_assert_not_reached();
9131 for (pass
= 0; pass
< maxpass
; pass
++) {
9132 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9134 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9135 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9137 write_fp_sreg(s
, rd
, tcg_op
);
9139 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9141 tcg_temp_free_i32(tcg_op
);
9144 clear_vec_high(s
, is_q
, rd
);
9148 tcg_temp_free_ptr(tcg_fpstatus
);
9149 tcg_temp_free_i32(tcg_shift
);
9150 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9151 tcg_temp_free_i32(tcg_rmode
);
9154 /* AdvSIMD scalar shift by immediate
9155 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9156 * +-----+---+-------------+------+------+--------+---+------+------+
9157 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9158 * +-----+---+-------------+------+------+--------+---+------+------+
9160 * This is the scalar version so it works on a fixed sized registers
9162 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9164 int rd
= extract32(insn
, 0, 5);
9165 int rn
= extract32(insn
, 5, 5);
9166 int opcode
= extract32(insn
, 11, 5);
9167 int immb
= extract32(insn
, 16, 3);
9168 int immh
= extract32(insn
, 19, 4);
9169 bool is_u
= extract32(insn
, 29, 1);
9172 unallocated_encoding(s
);
9177 case 0x08: /* SRI */
9179 unallocated_encoding(s
);
9183 case 0x00: /* SSHR / USHR */
9184 case 0x02: /* SSRA / USRA */
9185 case 0x04: /* SRSHR / URSHR */
9186 case 0x06: /* SRSRA / URSRA */
9187 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9189 case 0x0a: /* SHL / SLI */
9190 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9192 case 0x1c: /* SCVTF, UCVTF */
9193 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9196 case 0x10: /* SQSHRUN, SQSHRUN2 */
9197 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9199 unallocated_encoding(s
);
9202 handle_vec_simd_sqshrn(s
, true, false, false, true,
9203 immh
, immb
, opcode
, rn
, rd
);
9205 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9206 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9207 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9208 immh
, immb
, opcode
, rn
, rd
);
9210 case 0xc: /* SQSHLU */
9212 unallocated_encoding(s
);
9215 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9217 case 0xe: /* SQSHL, UQSHL */
9218 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9220 case 0x1f: /* FCVTZS, FCVTZU */
9221 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9224 unallocated_encoding(s
);
9229 /* AdvSIMD scalar three different
9230 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9231 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9232 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9233 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9235 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9237 bool is_u
= extract32(insn
, 29, 1);
9238 int size
= extract32(insn
, 22, 2);
9239 int opcode
= extract32(insn
, 12, 4);
9240 int rm
= extract32(insn
, 16, 5);
9241 int rn
= extract32(insn
, 5, 5);
9242 int rd
= extract32(insn
, 0, 5);
9245 unallocated_encoding(s
);
9250 case 0x9: /* SQDMLAL, SQDMLAL2 */
9251 case 0xb: /* SQDMLSL, SQDMLSL2 */
9252 case 0xd: /* SQDMULL, SQDMULL2 */
9253 if (size
== 0 || size
== 3) {
9254 unallocated_encoding(s
);
9259 unallocated_encoding(s
);
9263 if (!fp_access_check(s
)) {
9268 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9269 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9270 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9272 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9273 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9275 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9276 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9279 case 0xd: /* SQDMULL, SQDMULL2 */
9281 case 0xb: /* SQDMLSL, SQDMLSL2 */
9282 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9284 case 0x9: /* SQDMLAL, SQDMLAL2 */
9285 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9286 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9290 g_assert_not_reached();
9293 write_fp_dreg(s
, rd
, tcg_res
);
9295 tcg_temp_free_i64(tcg_op1
);
9296 tcg_temp_free_i64(tcg_op2
);
9297 tcg_temp_free_i64(tcg_res
);
9299 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9300 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9301 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9303 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9304 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9307 case 0xd: /* SQDMULL, SQDMULL2 */
9309 case 0xb: /* SQDMLSL, SQDMLSL2 */
9310 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9312 case 0x9: /* SQDMLAL, SQDMLAL2 */
9314 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9315 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9316 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9318 tcg_temp_free_i64(tcg_op3
);
9322 g_assert_not_reached();
9325 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9326 write_fp_dreg(s
, rd
, tcg_res
);
9328 tcg_temp_free_i32(tcg_op1
);
9329 tcg_temp_free_i32(tcg_op2
);
9330 tcg_temp_free_i64(tcg_res
);
9334 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9335 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9337 /* Handle 64x64->64 opcodes which are shared between the scalar
9338 * and vector 3-same groups. We cover every opcode where size == 3
9339 * is valid in either the three-reg-same (integer, not pairwise)
9340 * or scalar-three-reg-same groups.
9345 case 0x1: /* SQADD */
9347 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9349 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9352 case 0x5: /* SQSUB */
9354 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9356 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9359 case 0x6: /* CMGT, CMHI */
9360 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9361 * We implement this using setcond (test) and then negating.
9363 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9365 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9366 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9368 case 0x7: /* CMGE, CMHS */
9369 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9371 case 0x11: /* CMTST, CMEQ */
9376 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9378 case 0x8: /* SSHL, USHL */
9380 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9382 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9385 case 0x9: /* SQSHL, UQSHL */
9387 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9389 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9392 case 0xa: /* SRSHL, URSHL */
9394 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9396 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9399 case 0xb: /* SQRSHL, UQRSHL */
9401 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9403 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9406 case 0x10: /* ADD, SUB */
9408 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9410 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9414 g_assert_not_reached();
9418 /* Handle the 3-same-operands float operations; shared by the scalar
9419 * and vector encodings. The caller must filter out any encodings
9420 * not allocated for the encoding it is dealing with.
9422 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9423 int fpopcode
, int rd
, int rn
, int rm
)
9426 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9428 for (pass
= 0; pass
< elements
; pass
++) {
9431 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9432 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9433 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9435 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9436 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9439 case 0x39: /* FMLS */
9440 /* As usual for ARM, separate negation for fused multiply-add */
9441 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9443 case 0x19: /* FMLA */
9444 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9445 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9448 case 0x18: /* FMAXNM */
9449 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9451 case 0x1a: /* FADD */
9452 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9454 case 0x1b: /* FMULX */
9455 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9457 case 0x1c: /* FCMEQ */
9458 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9460 case 0x1e: /* FMAX */
9461 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9463 case 0x1f: /* FRECPS */
9464 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9466 case 0x38: /* FMINNM */
9467 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9469 case 0x3a: /* FSUB */
9470 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9472 case 0x3e: /* FMIN */
9473 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9475 case 0x3f: /* FRSQRTS */
9476 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9478 case 0x5b: /* FMUL */
9479 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9481 case 0x5c: /* FCMGE */
9482 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9484 case 0x5d: /* FACGE */
9485 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9487 case 0x5f: /* FDIV */
9488 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9490 case 0x7a: /* FABD */
9491 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9492 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9494 case 0x7c: /* FCMGT */
9495 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9497 case 0x7d: /* FACGT */
9498 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9501 g_assert_not_reached();
9504 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9506 tcg_temp_free_i64(tcg_res
);
9507 tcg_temp_free_i64(tcg_op1
);
9508 tcg_temp_free_i64(tcg_op2
);
9511 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9512 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9513 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9515 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9516 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9519 case 0x39: /* FMLS */
9520 /* As usual for ARM, separate negation for fused multiply-add */
9521 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9523 case 0x19: /* FMLA */
9524 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9525 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9528 case 0x1a: /* FADD */
9529 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9531 case 0x1b: /* FMULX */
9532 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9534 case 0x1c: /* FCMEQ */
9535 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9537 case 0x1e: /* FMAX */
9538 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9540 case 0x1f: /* FRECPS */
9541 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9543 case 0x18: /* FMAXNM */
9544 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9546 case 0x38: /* FMINNM */
9547 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9549 case 0x3a: /* FSUB */
9550 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9552 case 0x3e: /* FMIN */
9553 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9555 case 0x3f: /* FRSQRTS */
9556 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9558 case 0x5b: /* FMUL */
9559 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9561 case 0x5c: /* FCMGE */
9562 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9564 case 0x5d: /* FACGE */
9565 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9567 case 0x5f: /* FDIV */
9568 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9570 case 0x7a: /* FABD */
9571 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9572 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9574 case 0x7c: /* FCMGT */
9575 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9577 case 0x7d: /* FACGT */
9578 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9581 g_assert_not_reached();
9584 if (elements
== 1) {
9585 /* scalar single so clear high part */
9586 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9588 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9589 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9590 tcg_temp_free_i64(tcg_tmp
);
9592 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9595 tcg_temp_free_i32(tcg_res
);
9596 tcg_temp_free_i32(tcg_op1
);
9597 tcg_temp_free_i32(tcg_op2
);
9601 tcg_temp_free_ptr(fpst
);
9603 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9606 /* AdvSIMD scalar three same
9607 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9608 * +-----+---+-----------+------+---+------+--------+---+------+------+
9609 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9610 * +-----+---+-----------+------+---+------+--------+---+------+------+
9612 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9614 int rd
= extract32(insn
, 0, 5);
9615 int rn
= extract32(insn
, 5, 5);
9616 int opcode
= extract32(insn
, 11, 5);
9617 int rm
= extract32(insn
, 16, 5);
9618 int size
= extract32(insn
, 22, 2);
9619 bool u
= extract32(insn
, 29, 1);
9622 if (opcode
>= 0x18) {
9623 /* Floating point: U, size[1] and opcode indicate operation */
9624 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9626 case 0x1b: /* FMULX */
9627 case 0x1f: /* FRECPS */
9628 case 0x3f: /* FRSQRTS */
9629 case 0x5d: /* FACGE */
9630 case 0x7d: /* FACGT */
9631 case 0x1c: /* FCMEQ */
9632 case 0x5c: /* FCMGE */
9633 case 0x7c: /* FCMGT */
9634 case 0x7a: /* FABD */
9637 unallocated_encoding(s
);
9641 if (!fp_access_check(s
)) {
9645 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9650 case 0x1: /* SQADD, UQADD */
9651 case 0x5: /* SQSUB, UQSUB */
9652 case 0x9: /* SQSHL, UQSHL */
9653 case 0xb: /* SQRSHL, UQRSHL */
9655 case 0x8: /* SSHL, USHL */
9656 case 0xa: /* SRSHL, URSHL */
9657 case 0x6: /* CMGT, CMHI */
9658 case 0x7: /* CMGE, CMHS */
9659 case 0x11: /* CMTST, CMEQ */
9660 case 0x10: /* ADD, SUB (vector) */
9662 unallocated_encoding(s
);
9666 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9667 if (size
!= 1 && size
!= 2) {
9668 unallocated_encoding(s
);
9673 unallocated_encoding(s
);
9677 if (!fp_access_check(s
)) {
9681 tcg_rd
= tcg_temp_new_i64();
9684 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9685 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9687 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9688 tcg_temp_free_i64(tcg_rn
);
9689 tcg_temp_free_i64(tcg_rm
);
9691 /* Do a single operation on the lowest element in the vector.
9692 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9693 * no side effects for all these operations.
9694 * OPTME: special-purpose helpers would avoid doing some
9695 * unnecessary work in the helper for the 8 and 16 bit cases.
9697 NeonGenTwoOpEnvFn
*genenvfn
;
9698 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9699 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9700 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9702 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9703 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9706 case 0x1: /* SQADD, UQADD */
9708 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9709 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9710 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9711 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9713 genenvfn
= fns
[size
][u
];
9716 case 0x5: /* SQSUB, UQSUB */
9718 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9719 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9720 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9721 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9723 genenvfn
= fns
[size
][u
];
9726 case 0x9: /* SQSHL, UQSHL */
9728 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9729 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9730 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9731 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9733 genenvfn
= fns
[size
][u
];
9736 case 0xb: /* SQRSHL, UQRSHL */
9738 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9739 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9740 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9741 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9743 genenvfn
= fns
[size
][u
];
9746 case 0x16: /* SQDMULH, SQRDMULH */
9748 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9749 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9750 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9752 assert(size
== 1 || size
== 2);
9753 genenvfn
= fns
[size
- 1][u
];
9757 g_assert_not_reached();
9760 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9761 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9762 tcg_temp_free_i32(tcg_rd32
);
9763 tcg_temp_free_i32(tcg_rn
);
9764 tcg_temp_free_i32(tcg_rm
);
9767 write_fp_dreg(s
, rd
, tcg_rd
);
9769 tcg_temp_free_i64(tcg_rd
);
9772 /* AdvSIMD scalar three same FP16
9773 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9774 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9775 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9776 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9777 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9778 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9780 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9783 int rd
= extract32(insn
, 0, 5);
9784 int rn
= extract32(insn
, 5, 5);
9785 int opcode
= extract32(insn
, 11, 3);
9786 int rm
= extract32(insn
, 16, 5);
9787 bool u
= extract32(insn
, 29, 1);
9788 bool a
= extract32(insn
, 23, 1);
9789 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9796 case 0x03: /* FMULX */
9797 case 0x04: /* FCMEQ (reg) */
9798 case 0x07: /* FRECPS */
9799 case 0x0f: /* FRSQRTS */
9800 case 0x14: /* FCMGE (reg) */
9801 case 0x15: /* FACGE */
9802 case 0x1a: /* FABD */
9803 case 0x1c: /* FCMGT (reg) */
9804 case 0x1d: /* FACGT */
9807 unallocated_encoding(s
);
9811 if (!dc_isar_feature(aa64_fp16
, s
)) {
9812 unallocated_encoding(s
);
9815 if (!fp_access_check(s
)) {
9819 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9821 tcg_op1
= read_fp_hreg(s
, rn
);
9822 tcg_op2
= read_fp_hreg(s
, rm
);
9823 tcg_res
= tcg_temp_new_i32();
9826 case 0x03: /* FMULX */
9827 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9829 case 0x04: /* FCMEQ (reg) */
9830 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9832 case 0x07: /* FRECPS */
9833 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9835 case 0x0f: /* FRSQRTS */
9836 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9838 case 0x14: /* FCMGE (reg) */
9839 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9841 case 0x15: /* FACGE */
9842 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9844 case 0x1a: /* FABD */
9845 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9846 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9848 case 0x1c: /* FCMGT (reg) */
9849 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9851 case 0x1d: /* FACGT */
9852 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9855 g_assert_not_reached();
9858 write_fp_sreg(s
, rd
, tcg_res
);
9861 tcg_temp_free_i32(tcg_res
);
9862 tcg_temp_free_i32(tcg_op1
);
9863 tcg_temp_free_i32(tcg_op2
);
9864 tcg_temp_free_ptr(fpst
);
9867 /* AdvSIMD scalar three same extra
9868 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9869 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9870 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9871 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9873 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9876 int rd
= extract32(insn
, 0, 5);
9877 int rn
= extract32(insn
, 5, 5);
9878 int opcode
= extract32(insn
, 11, 4);
9879 int rm
= extract32(insn
, 16, 5);
9880 int size
= extract32(insn
, 22, 2);
9881 bool u
= extract32(insn
, 29, 1);
9882 TCGv_i32 ele1
, ele2
, ele3
;
9886 switch (u
* 16 + opcode
) {
9887 case 0x10: /* SQRDMLAH (vector) */
9888 case 0x11: /* SQRDMLSH (vector) */
9889 if (size
!= 1 && size
!= 2) {
9890 unallocated_encoding(s
);
9893 feature
= dc_isar_feature(aa64_rdm
, s
);
9896 unallocated_encoding(s
);
9900 unallocated_encoding(s
);
9903 if (!fp_access_check(s
)) {
9907 /* Do a single operation on the lowest element in the vector.
9908 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9909 * with no side effects for all these operations.
9910 * OPTME: special-purpose helpers would avoid doing some
9911 * unnecessary work in the helper for the 16 bit cases.
9913 ele1
= tcg_temp_new_i32();
9914 ele2
= tcg_temp_new_i32();
9915 ele3
= tcg_temp_new_i32();
9917 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9918 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9919 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9922 case 0x0: /* SQRDMLAH */
9924 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9926 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9929 case 0x1: /* SQRDMLSH */
9931 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9933 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9937 g_assert_not_reached();
9939 tcg_temp_free_i32(ele1
);
9940 tcg_temp_free_i32(ele2
);
9942 res
= tcg_temp_new_i64();
9943 tcg_gen_extu_i32_i64(res
, ele3
);
9944 tcg_temp_free_i32(ele3
);
9946 write_fp_dreg(s
, rd
, res
);
9947 tcg_temp_free_i64(res
);
9950 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9951 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9952 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9954 /* Handle 64->64 opcodes which are shared between the scalar and
9955 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9956 * is valid in either group and also the double-precision fp ops.
9957 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9963 case 0x4: /* CLS, CLZ */
9965 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9967 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9971 /* This opcode is shared with CNT and RBIT but we have earlier
9972 * enforced that size == 3 if and only if this is the NOT insn.
9974 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9976 case 0x7: /* SQABS, SQNEG */
9978 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9980 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9983 case 0xa: /* CMLT */
9984 /* 64 bit integer comparison against zero, result is
9985 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9990 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9991 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9993 case 0x8: /* CMGT, CMGE */
9994 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9996 case 0x9: /* CMEQ, CMLE */
9997 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9999 case 0xb: /* ABS, NEG */
10001 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
10003 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
10006 case 0x2f: /* FABS */
10007 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
10009 case 0x6f: /* FNEG */
10010 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
10012 case 0x7f: /* FSQRT */
10013 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
10015 case 0x1a: /* FCVTNS */
10016 case 0x1b: /* FCVTMS */
10017 case 0x1c: /* FCVTAS */
10018 case 0x3a: /* FCVTPS */
10019 case 0x3b: /* FCVTZS */
10021 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10022 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10023 tcg_temp_free_i32(tcg_shift
);
10026 case 0x5a: /* FCVTNU */
10027 case 0x5b: /* FCVTMU */
10028 case 0x5c: /* FCVTAU */
10029 case 0x7a: /* FCVTPU */
10030 case 0x7b: /* FCVTZU */
10032 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10033 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10034 tcg_temp_free_i32(tcg_shift
);
10037 case 0x18: /* FRINTN */
10038 case 0x19: /* FRINTM */
10039 case 0x38: /* FRINTP */
10040 case 0x39: /* FRINTZ */
10041 case 0x58: /* FRINTA */
10042 case 0x79: /* FRINTI */
10043 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10045 case 0x59: /* FRINTX */
10046 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10048 case 0x1e: /* FRINT32Z */
10049 case 0x5e: /* FRINT32X */
10050 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10052 case 0x1f: /* FRINT64Z */
10053 case 0x5f: /* FRINT64X */
10054 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10057 g_assert_not_reached();
10061 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
10062 bool is_scalar
, bool is_u
, bool is_q
,
10063 int size
, int rn
, int rd
)
10065 bool is_double
= (size
== MO_64
);
10068 if (!fp_access_check(s
)) {
10072 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
10075 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10076 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10077 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10078 NeonGenTwoDoubleOpFn
*genfn
;
10083 case 0x2e: /* FCMLT (zero) */
10086 case 0x2c: /* FCMGT (zero) */
10087 genfn
= gen_helper_neon_cgt_f64
;
10089 case 0x2d: /* FCMEQ (zero) */
10090 genfn
= gen_helper_neon_ceq_f64
;
10092 case 0x6d: /* FCMLE (zero) */
10095 case 0x6c: /* FCMGE (zero) */
10096 genfn
= gen_helper_neon_cge_f64
;
10099 g_assert_not_reached();
10102 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10103 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10105 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10107 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10109 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10111 tcg_temp_free_i64(tcg_res
);
10112 tcg_temp_free_i64(tcg_zero
);
10113 tcg_temp_free_i64(tcg_op
);
10115 clear_vec_high(s
, !is_scalar
, rd
);
10117 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10118 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10119 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10120 NeonGenTwoSingleOpFn
*genfn
;
10122 int pass
, maxpasses
;
10124 if (size
== MO_16
) {
10126 case 0x2e: /* FCMLT (zero) */
10129 case 0x2c: /* FCMGT (zero) */
10130 genfn
= gen_helper_advsimd_cgt_f16
;
10132 case 0x2d: /* FCMEQ (zero) */
10133 genfn
= gen_helper_advsimd_ceq_f16
;
10135 case 0x6d: /* FCMLE (zero) */
10138 case 0x6c: /* FCMGE (zero) */
10139 genfn
= gen_helper_advsimd_cge_f16
;
10142 g_assert_not_reached();
10146 case 0x2e: /* FCMLT (zero) */
10149 case 0x2c: /* FCMGT (zero) */
10150 genfn
= gen_helper_neon_cgt_f32
;
10152 case 0x2d: /* FCMEQ (zero) */
10153 genfn
= gen_helper_neon_ceq_f32
;
10155 case 0x6d: /* FCMLE (zero) */
10158 case 0x6c: /* FCMGE (zero) */
10159 genfn
= gen_helper_neon_cge_f32
;
10162 g_assert_not_reached();
10169 int vector_size
= 8 << is_q
;
10170 maxpasses
= vector_size
>> size
;
10173 for (pass
= 0; pass
< maxpasses
; pass
++) {
10174 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10176 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10178 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10181 write_fp_sreg(s
, rd
, tcg_res
);
10183 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10186 tcg_temp_free_i32(tcg_res
);
10187 tcg_temp_free_i32(tcg_zero
);
10188 tcg_temp_free_i32(tcg_op
);
10190 clear_vec_high(s
, is_q
, rd
);
10194 tcg_temp_free_ptr(fpst
);
10197 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10198 bool is_scalar
, bool is_u
, bool is_q
,
10199 int size
, int rn
, int rd
)
10201 bool is_double
= (size
== 3);
10202 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10205 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10206 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10209 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10210 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10212 case 0x3d: /* FRECPE */
10213 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10215 case 0x3f: /* FRECPX */
10216 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10218 case 0x7d: /* FRSQRTE */
10219 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10222 g_assert_not_reached();
10224 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10226 tcg_temp_free_i64(tcg_res
);
10227 tcg_temp_free_i64(tcg_op
);
10228 clear_vec_high(s
, !is_scalar
, rd
);
10230 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10231 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10232 int pass
, maxpasses
;
10237 maxpasses
= is_q
? 4 : 2;
10240 for (pass
= 0; pass
< maxpasses
; pass
++) {
10241 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10244 case 0x3c: /* URECPE */
10245 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10247 case 0x3d: /* FRECPE */
10248 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10250 case 0x3f: /* FRECPX */
10251 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10253 case 0x7d: /* FRSQRTE */
10254 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10257 g_assert_not_reached();
10261 write_fp_sreg(s
, rd
, tcg_res
);
10263 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10266 tcg_temp_free_i32(tcg_res
);
10267 tcg_temp_free_i32(tcg_op
);
10269 clear_vec_high(s
, is_q
, rd
);
10272 tcg_temp_free_ptr(fpst
);
10275 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10276 int opcode
, bool u
, bool is_q
,
10277 int size
, int rn
, int rd
)
10279 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10280 * in the source becomes a size element in the destination).
10283 TCGv_i32 tcg_res
[2];
10284 int destelt
= is_q
? 2 : 0;
10285 int passes
= scalar
? 1 : 2;
10288 tcg_res
[1] = tcg_const_i32(0);
10291 for (pass
= 0; pass
< passes
; pass
++) {
10292 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10293 NeonGenNarrowFn
*genfn
= NULL
;
10294 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10297 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10299 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10301 tcg_res
[pass
] = tcg_temp_new_i32();
10304 case 0x12: /* XTN, SQXTUN */
10306 static NeonGenNarrowFn
* const xtnfns
[3] = {
10307 gen_helper_neon_narrow_u8
,
10308 gen_helper_neon_narrow_u16
,
10309 tcg_gen_extrl_i64_i32
,
10311 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10312 gen_helper_neon_unarrow_sat8
,
10313 gen_helper_neon_unarrow_sat16
,
10314 gen_helper_neon_unarrow_sat32
,
10317 genenvfn
= sqxtunfns
[size
];
10319 genfn
= xtnfns
[size
];
10323 case 0x14: /* SQXTN, UQXTN */
10325 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10326 { gen_helper_neon_narrow_sat_s8
,
10327 gen_helper_neon_narrow_sat_u8
},
10328 { gen_helper_neon_narrow_sat_s16
,
10329 gen_helper_neon_narrow_sat_u16
},
10330 { gen_helper_neon_narrow_sat_s32
,
10331 gen_helper_neon_narrow_sat_u32
},
10333 genenvfn
= fns
[size
][u
];
10336 case 0x16: /* FCVTN, FCVTN2 */
10337 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10339 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10341 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10342 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10343 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10344 TCGv_i32 ahp
= get_ahp_flag();
10346 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10347 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10348 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10349 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10350 tcg_temp_free_i32(tcg_lo
);
10351 tcg_temp_free_i32(tcg_hi
);
10352 tcg_temp_free_ptr(fpst
);
10353 tcg_temp_free_i32(ahp
);
10356 case 0x56: /* FCVTXN, FCVTXN2 */
10357 /* 64 bit to 32 bit float conversion
10358 * with von Neumann rounding (round to odd)
10361 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10364 g_assert_not_reached();
10368 genfn(tcg_res
[pass
], tcg_op
);
10369 } else if (genenvfn
) {
10370 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10373 tcg_temp_free_i64(tcg_op
);
10376 for (pass
= 0; pass
< 2; pass
++) {
10377 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10378 tcg_temp_free_i32(tcg_res
[pass
]);
10380 clear_vec_high(s
, is_q
, rd
);
10383 /* Remaining saturating accumulating ops */
10384 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10385 bool is_q
, int size
, int rn
, int rd
)
10387 bool is_double
= (size
== 3);
10390 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10391 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10394 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10395 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10396 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10398 if (is_u
) { /* USQADD */
10399 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10400 } else { /* SUQADD */
10401 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10403 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10405 tcg_temp_free_i64(tcg_rd
);
10406 tcg_temp_free_i64(tcg_rn
);
10407 clear_vec_high(s
, !is_scalar
, rd
);
10409 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10410 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10411 int pass
, maxpasses
;
10416 maxpasses
= is_q
? 4 : 2;
10419 for (pass
= 0; pass
< maxpasses
; pass
++) {
10421 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10422 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10424 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10425 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10428 if (is_u
) { /* USQADD */
10431 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10434 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10437 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10440 g_assert_not_reached();
10442 } else { /* SUQADD */
10445 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10448 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10451 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10454 g_assert_not_reached();
10459 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10460 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10461 tcg_temp_free_i64(tcg_zero
);
10463 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10465 tcg_temp_free_i32(tcg_rd
);
10466 tcg_temp_free_i32(tcg_rn
);
10467 clear_vec_high(s
, is_q
, rd
);
10471 /* AdvSIMD scalar two reg misc
10472 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10473 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10474 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10475 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10477 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10479 int rd
= extract32(insn
, 0, 5);
10480 int rn
= extract32(insn
, 5, 5);
10481 int opcode
= extract32(insn
, 12, 5);
10482 int size
= extract32(insn
, 22, 2);
10483 bool u
= extract32(insn
, 29, 1);
10484 bool is_fcvt
= false;
10486 TCGv_i32 tcg_rmode
;
10487 TCGv_ptr tcg_fpstatus
;
10490 case 0x3: /* USQADD / SUQADD*/
10491 if (!fp_access_check(s
)) {
10494 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10496 case 0x7: /* SQABS / SQNEG */
10498 case 0xa: /* CMLT */
10500 unallocated_encoding(s
);
10504 case 0x8: /* CMGT, CMGE */
10505 case 0x9: /* CMEQ, CMLE */
10506 case 0xb: /* ABS, NEG */
10508 unallocated_encoding(s
);
10512 case 0x12: /* SQXTUN */
10514 unallocated_encoding(s
);
10518 case 0x14: /* SQXTN, UQXTN */
10520 unallocated_encoding(s
);
10523 if (!fp_access_check(s
)) {
10526 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10529 case 0x16 ... 0x1d:
10531 /* Floating point: U, size[1] and opcode indicate operation;
10532 * size[0] indicates single or double precision.
10534 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10535 size
= extract32(size
, 0, 1) ? 3 : 2;
10537 case 0x2c: /* FCMGT (zero) */
10538 case 0x2d: /* FCMEQ (zero) */
10539 case 0x2e: /* FCMLT (zero) */
10540 case 0x6c: /* FCMGE (zero) */
10541 case 0x6d: /* FCMLE (zero) */
10542 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10544 case 0x1d: /* SCVTF */
10545 case 0x5d: /* UCVTF */
10547 bool is_signed
= (opcode
== 0x1d);
10548 if (!fp_access_check(s
)) {
10551 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10554 case 0x3d: /* FRECPE */
10555 case 0x3f: /* FRECPX */
10556 case 0x7d: /* FRSQRTE */
10557 if (!fp_access_check(s
)) {
10560 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10562 case 0x1a: /* FCVTNS */
10563 case 0x1b: /* FCVTMS */
10564 case 0x3a: /* FCVTPS */
10565 case 0x3b: /* FCVTZS */
10566 case 0x5a: /* FCVTNU */
10567 case 0x5b: /* FCVTMU */
10568 case 0x7a: /* FCVTPU */
10569 case 0x7b: /* FCVTZU */
10571 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10573 case 0x1c: /* FCVTAS */
10574 case 0x5c: /* FCVTAU */
10575 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10577 rmode
= FPROUNDING_TIEAWAY
;
10579 case 0x56: /* FCVTXN, FCVTXN2 */
10581 unallocated_encoding(s
);
10584 if (!fp_access_check(s
)) {
10587 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10590 unallocated_encoding(s
);
10595 unallocated_encoding(s
);
10599 if (!fp_access_check(s
)) {
10604 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10605 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10606 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10609 tcg_fpstatus
= NULL
;
10613 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10614 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10616 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10617 write_fp_dreg(s
, rd
, tcg_rd
);
10618 tcg_temp_free_i64(tcg_rd
);
10619 tcg_temp_free_i64(tcg_rn
);
10621 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10622 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10624 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10627 case 0x7: /* SQABS, SQNEG */
10629 NeonGenOneOpEnvFn
*genfn
;
10630 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10631 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10632 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10633 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10635 genfn
= fns
[size
][u
];
10636 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10639 case 0x1a: /* FCVTNS */
10640 case 0x1b: /* FCVTMS */
10641 case 0x1c: /* FCVTAS */
10642 case 0x3a: /* FCVTPS */
10643 case 0x3b: /* FCVTZS */
10645 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10646 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10647 tcg_temp_free_i32(tcg_shift
);
10650 case 0x5a: /* FCVTNU */
10651 case 0x5b: /* FCVTMU */
10652 case 0x5c: /* FCVTAU */
10653 case 0x7a: /* FCVTPU */
10654 case 0x7b: /* FCVTZU */
10656 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10657 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10658 tcg_temp_free_i32(tcg_shift
);
10662 g_assert_not_reached();
10665 write_fp_sreg(s
, rd
, tcg_rd
);
10666 tcg_temp_free_i32(tcg_rd
);
10667 tcg_temp_free_i32(tcg_rn
);
10671 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10672 tcg_temp_free_i32(tcg_rmode
);
10673 tcg_temp_free_ptr(tcg_fpstatus
);
10677 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10678 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10679 int immh
, int immb
, int opcode
, int rn
, int rd
)
10681 int size
= 32 - clz32(immh
) - 1;
10682 int immhb
= immh
<< 3 | immb
;
10683 int shift
= 2 * (8 << size
) - immhb
;
10684 GVecGen2iFn
*gvec_fn
;
10686 if (extract32(immh
, 3, 1) && !is_q
) {
10687 unallocated_encoding(s
);
10690 tcg_debug_assert(size
<= 3);
10692 if (!fp_access_check(s
)) {
10697 case 0x02: /* SSRA / USRA (accumulate) */
10698 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10701 case 0x08: /* SRI */
10702 gvec_fn
= gen_gvec_sri
;
10705 case 0x00: /* SSHR / USHR */
10707 if (shift
== 8 << size
) {
10708 /* Shift count the same size as element size produces zero. */
10709 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10710 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10713 gvec_fn
= tcg_gen_gvec_shri
;
10715 /* Shift count the same size as element size produces all sign. */
10716 if (shift
== 8 << size
) {
10719 gvec_fn
= tcg_gen_gvec_sari
;
10723 case 0x04: /* SRSHR / URSHR (rounding) */
10724 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10727 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10728 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10732 g_assert_not_reached();
10735 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10738 /* SHL/SLI - Vector shift left */
10739 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10740 int immh
, int immb
, int opcode
, int rn
, int rd
)
10742 int size
= 32 - clz32(immh
) - 1;
10743 int immhb
= immh
<< 3 | immb
;
10744 int shift
= immhb
- (8 << size
);
10746 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10747 assert(size
>= 0 && size
<= 3);
10749 if (extract32(immh
, 3, 1) && !is_q
) {
10750 unallocated_encoding(s
);
10754 if (!fp_access_check(s
)) {
10759 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10761 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10765 /* USHLL/SHLL - Vector shift left with widening */
10766 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10767 int immh
, int immb
, int opcode
, int rn
, int rd
)
10769 int size
= 32 - clz32(immh
) - 1;
10770 int immhb
= immh
<< 3 | immb
;
10771 int shift
= immhb
- (8 << size
);
10773 int esize
= 8 << size
;
10774 int elements
= dsize
/esize
;
10775 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10776 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10780 unallocated_encoding(s
);
10784 if (!fp_access_check(s
)) {
10788 /* For the LL variants the store is larger than the load,
10789 * so if rd == rn we would overwrite parts of our input.
10790 * So load everything right now and use shifts in the main loop.
10792 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10794 for (i
= 0; i
< elements
; i
++) {
10795 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10796 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10797 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10798 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10802 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10803 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10804 int immh
, int immb
, int opcode
, int rn
, int rd
)
10806 int immhb
= immh
<< 3 | immb
;
10807 int size
= 32 - clz32(immh
) - 1;
10809 int esize
= 8 << size
;
10810 int elements
= dsize
/esize
;
10811 int shift
= (2 * esize
) - immhb
;
10812 bool round
= extract32(opcode
, 0, 1);
10813 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10814 TCGv_i64 tcg_round
;
10817 if (extract32(immh
, 3, 1)) {
10818 unallocated_encoding(s
);
10822 if (!fp_access_check(s
)) {
10826 tcg_rn
= tcg_temp_new_i64();
10827 tcg_rd
= tcg_temp_new_i64();
10828 tcg_final
= tcg_temp_new_i64();
10829 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10832 uint64_t round_const
= 1ULL << (shift
- 1);
10833 tcg_round
= tcg_const_i64(round_const
);
10838 for (i
= 0; i
< elements
; i
++) {
10839 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10840 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10841 false, true, size
+1, shift
);
10843 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10847 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10849 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10852 tcg_temp_free_i64(tcg_round
);
10854 tcg_temp_free_i64(tcg_rn
);
10855 tcg_temp_free_i64(tcg_rd
);
10856 tcg_temp_free_i64(tcg_final
);
10858 clear_vec_high(s
, is_q
, rd
);
10862 /* AdvSIMD shift by immediate
10863 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10864 * +---+---+---+-------------+------+------+--------+---+------+------+
10865 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10866 * +---+---+---+-------------+------+------+--------+---+------+------+
10868 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10870 int rd
= extract32(insn
, 0, 5);
10871 int rn
= extract32(insn
, 5, 5);
10872 int opcode
= extract32(insn
, 11, 5);
10873 int immb
= extract32(insn
, 16, 3);
10874 int immh
= extract32(insn
, 19, 4);
10875 bool is_u
= extract32(insn
, 29, 1);
10876 bool is_q
= extract32(insn
, 30, 1);
10878 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10882 case 0x08: /* SRI */
10884 unallocated_encoding(s
);
10888 case 0x00: /* SSHR / USHR */
10889 case 0x02: /* SSRA / USRA (accumulate) */
10890 case 0x04: /* SRSHR / URSHR (rounding) */
10891 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10892 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10894 case 0x0a: /* SHL / SLI */
10895 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10897 case 0x10: /* SHRN */
10898 case 0x11: /* RSHRN / SQRSHRUN */
10900 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10903 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10906 case 0x12: /* SQSHRN / UQSHRN */
10907 case 0x13: /* SQRSHRN / UQRSHRN */
10908 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10911 case 0x14: /* SSHLL / USHLL */
10912 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10914 case 0x1c: /* SCVTF / UCVTF */
10915 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10918 case 0xc: /* SQSHLU */
10920 unallocated_encoding(s
);
10923 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10925 case 0xe: /* SQSHL, UQSHL */
10926 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10928 case 0x1f: /* FCVTZS/ FCVTZU */
10929 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10932 unallocated_encoding(s
);
10937 /* Generate code to do a "long" addition or subtraction, ie one done in
10938 * TCGv_i64 on vector lanes twice the width specified by size.
10940 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10941 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10943 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10944 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10945 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10946 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10948 NeonGenTwo64OpFn
*genfn
;
10951 genfn
= fns
[size
][is_sub
];
10952 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10955 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10956 int opcode
, int rd
, int rn
, int rm
)
10958 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10959 TCGv_i64 tcg_res
[2];
10962 tcg_res
[0] = tcg_temp_new_i64();
10963 tcg_res
[1] = tcg_temp_new_i64();
10965 /* Does this op do an adding accumulate, a subtracting accumulate,
10966 * or no accumulate at all?
10984 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10985 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10988 /* size == 2 means two 32x32->64 operations; this is worth special
10989 * casing because we can generally handle it inline.
10992 for (pass
= 0; pass
< 2; pass
++) {
10993 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10994 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10995 TCGv_i64 tcg_passres
;
10996 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10998 int elt
= pass
+ is_q
* 2;
11000 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
11001 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
11004 tcg_passres
= tcg_res
[pass
];
11006 tcg_passres
= tcg_temp_new_i64();
11010 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11011 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11013 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11014 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11016 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11017 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11019 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
11020 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
11022 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
11023 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
11024 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
11026 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
11027 tcg_temp_free_i64(tcg_tmp1
);
11028 tcg_temp_free_i64(tcg_tmp2
);
11031 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11032 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11033 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11034 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11036 case 9: /* SQDMLAL, SQDMLAL2 */
11037 case 11: /* SQDMLSL, SQDMLSL2 */
11038 case 13: /* SQDMULL, SQDMULL2 */
11039 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11040 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
11041 tcg_passres
, tcg_passres
);
11044 g_assert_not_reached();
11047 if (opcode
== 9 || opcode
== 11) {
11048 /* saturating accumulate ops */
11050 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
11052 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
11053 tcg_res
[pass
], tcg_passres
);
11054 } else if (accop
> 0) {
11055 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11056 } else if (accop
< 0) {
11057 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11061 tcg_temp_free_i64(tcg_passres
);
11064 tcg_temp_free_i64(tcg_op1
);
11065 tcg_temp_free_i64(tcg_op2
);
11068 /* size 0 or 1, generally helper functions */
11069 for (pass
= 0; pass
< 2; pass
++) {
11070 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11071 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11072 TCGv_i64 tcg_passres
;
11073 int elt
= pass
+ is_q
* 2;
11075 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
11076 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11079 tcg_passres
= tcg_res
[pass
];
11081 tcg_passres
= tcg_temp_new_i64();
11085 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11086 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11088 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11089 static NeonGenWidenFn
* const widenfns
[2][2] = {
11090 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11091 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11093 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11095 widenfn(tcg_op2_64
, tcg_op2
);
11096 widenfn(tcg_passres
, tcg_op1
);
11097 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11098 tcg_passres
, tcg_op2_64
);
11099 tcg_temp_free_i64(tcg_op2_64
);
11102 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11103 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11106 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11108 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11112 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11114 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11118 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11119 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11120 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11123 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11125 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11129 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11131 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11135 case 9: /* SQDMLAL, SQDMLAL2 */
11136 case 11: /* SQDMLSL, SQDMLSL2 */
11137 case 13: /* SQDMULL, SQDMULL2 */
11139 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11140 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11141 tcg_passres
, tcg_passres
);
11144 g_assert_not_reached();
11146 tcg_temp_free_i32(tcg_op1
);
11147 tcg_temp_free_i32(tcg_op2
);
11150 if (opcode
== 9 || opcode
== 11) {
11151 /* saturating accumulate ops */
11153 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11155 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11159 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11160 tcg_res
[pass
], tcg_passres
);
11162 tcg_temp_free_i64(tcg_passres
);
11167 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11168 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11169 tcg_temp_free_i64(tcg_res
[0]);
11170 tcg_temp_free_i64(tcg_res
[1]);
11173 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11174 int opcode
, int rd
, int rn
, int rm
)
11176 TCGv_i64 tcg_res
[2];
11177 int part
= is_q
? 2 : 0;
11180 for (pass
= 0; pass
< 2; pass
++) {
11181 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11182 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11183 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11184 static NeonGenWidenFn
* const widenfns
[3][2] = {
11185 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11186 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11187 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11189 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11191 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11192 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11193 widenfn(tcg_op2_wide
, tcg_op2
);
11194 tcg_temp_free_i32(tcg_op2
);
11195 tcg_res
[pass
] = tcg_temp_new_i64();
11196 gen_neon_addl(size
, (opcode
== 3),
11197 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11198 tcg_temp_free_i64(tcg_op1
);
11199 tcg_temp_free_i64(tcg_op2_wide
);
11202 for (pass
= 0; pass
< 2; pass
++) {
11203 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11204 tcg_temp_free_i64(tcg_res
[pass
]);
11208 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11210 tcg_gen_addi_i64(in
, in
, 1U << 31);
11211 tcg_gen_extrh_i64_i32(res
, in
);
11214 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11215 int opcode
, int rd
, int rn
, int rm
)
11217 TCGv_i32 tcg_res
[2];
11218 int part
= is_q
? 2 : 0;
11221 for (pass
= 0; pass
< 2; pass
++) {
11222 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11223 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11224 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11225 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11226 { gen_helper_neon_narrow_high_u8
,
11227 gen_helper_neon_narrow_round_high_u8
},
11228 { gen_helper_neon_narrow_high_u16
,
11229 gen_helper_neon_narrow_round_high_u16
},
11230 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11232 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11234 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11235 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11237 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11239 tcg_temp_free_i64(tcg_op1
);
11240 tcg_temp_free_i64(tcg_op2
);
11242 tcg_res
[pass
] = tcg_temp_new_i32();
11243 gennarrow(tcg_res
[pass
], tcg_wideres
);
11244 tcg_temp_free_i64(tcg_wideres
);
11247 for (pass
= 0; pass
< 2; pass
++) {
11248 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11249 tcg_temp_free_i32(tcg_res
[pass
]);
11251 clear_vec_high(s
, is_q
, rd
);
11254 /* AdvSIMD three different
11255 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11256 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11257 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11258 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11260 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11262 /* Instructions in this group fall into three basic classes
11263 * (in each case with the operation working on each element in
11264 * the input vectors):
11265 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11267 * (2) wide 64 x 128 -> 128
11268 * (3) narrowing 128 x 128 -> 64
11269 * Here we do initial decode, catch unallocated cases and
11270 * dispatch to separate functions for each class.
11272 int is_q
= extract32(insn
, 30, 1);
11273 int is_u
= extract32(insn
, 29, 1);
11274 int size
= extract32(insn
, 22, 2);
11275 int opcode
= extract32(insn
, 12, 4);
11276 int rm
= extract32(insn
, 16, 5);
11277 int rn
= extract32(insn
, 5, 5);
11278 int rd
= extract32(insn
, 0, 5);
11281 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11282 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11283 /* 64 x 128 -> 128 */
11285 unallocated_encoding(s
);
11288 if (!fp_access_check(s
)) {
11291 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11293 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11294 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11295 /* 128 x 128 -> 64 */
11297 unallocated_encoding(s
);
11300 if (!fp_access_check(s
)) {
11303 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11305 case 14: /* PMULL, PMULL2 */
11307 unallocated_encoding(s
);
11311 case 0: /* PMULL.P8 */
11312 if (!fp_access_check(s
)) {
11315 /* The Q field specifies lo/hi half input for this insn. */
11316 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11317 gen_helper_neon_pmull_h
);
11320 case 3: /* PMULL.P64 */
11321 if (!dc_isar_feature(aa64_pmull
, s
)) {
11322 unallocated_encoding(s
);
11325 if (!fp_access_check(s
)) {
11328 /* The Q field specifies lo/hi half input for this insn. */
11329 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11330 gen_helper_gvec_pmull_q
);
11334 unallocated_encoding(s
);
11338 case 9: /* SQDMLAL, SQDMLAL2 */
11339 case 11: /* SQDMLSL, SQDMLSL2 */
11340 case 13: /* SQDMULL, SQDMULL2 */
11341 if (is_u
|| size
== 0) {
11342 unallocated_encoding(s
);
11346 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11347 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11348 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11349 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11350 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11351 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11352 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11353 /* 64 x 64 -> 128 */
11355 unallocated_encoding(s
);
11358 if (!fp_access_check(s
)) {
11362 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11365 /* opcode 15 not allocated */
11366 unallocated_encoding(s
);
11371 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11372 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11374 int rd
= extract32(insn
, 0, 5);
11375 int rn
= extract32(insn
, 5, 5);
11376 int rm
= extract32(insn
, 16, 5);
11377 int size
= extract32(insn
, 22, 2);
11378 bool is_u
= extract32(insn
, 29, 1);
11379 bool is_q
= extract32(insn
, 30, 1);
11381 if (!fp_access_check(s
)) {
11385 switch (size
+ 4 * is_u
) {
11387 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11390 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11393 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11396 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11399 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11402 case 5: /* BSL bitwise select */
11403 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11405 case 6: /* BIT, bitwise insert if true */
11406 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11408 case 7: /* BIF, bitwise insert if false */
11409 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11413 g_assert_not_reached();
11417 /* Pairwise op subgroup of C3.6.16.
11419 * This is called directly or via the handle_3same_float for float pairwise
11420 * operations where the opcode and size are calculated differently.
11422 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11423 int size
, int rn
, int rm
, int rd
)
11428 /* Floating point operations need fpst */
11429 if (opcode
>= 0x58) {
11430 fpst
= fpstatus_ptr(FPST_FPCR
);
11435 if (!fp_access_check(s
)) {
11439 /* These operations work on the concatenated rm:rn, with each pair of
11440 * adjacent elements being operated on to produce an element in the result.
11443 TCGv_i64 tcg_res
[2];
11445 for (pass
= 0; pass
< 2; pass
++) {
11446 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11447 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11448 int passreg
= (pass
== 0) ? rn
: rm
;
11450 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11451 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11452 tcg_res
[pass
] = tcg_temp_new_i64();
11455 case 0x17: /* ADDP */
11456 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11458 case 0x58: /* FMAXNMP */
11459 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11461 case 0x5a: /* FADDP */
11462 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11464 case 0x5e: /* FMAXP */
11465 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11467 case 0x78: /* FMINNMP */
11468 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11470 case 0x7e: /* FMINP */
11471 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11474 g_assert_not_reached();
11477 tcg_temp_free_i64(tcg_op1
);
11478 tcg_temp_free_i64(tcg_op2
);
11481 for (pass
= 0; pass
< 2; pass
++) {
11482 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11483 tcg_temp_free_i64(tcg_res
[pass
]);
11486 int maxpass
= is_q
? 4 : 2;
11487 TCGv_i32 tcg_res
[4];
11489 for (pass
= 0; pass
< maxpass
; pass
++) {
11490 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11491 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11492 NeonGenTwoOpFn
*genfn
= NULL
;
11493 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11494 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11496 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11497 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11498 tcg_res
[pass
] = tcg_temp_new_i32();
11501 case 0x17: /* ADDP */
11503 static NeonGenTwoOpFn
* const fns
[3] = {
11504 gen_helper_neon_padd_u8
,
11505 gen_helper_neon_padd_u16
,
11511 case 0x14: /* SMAXP, UMAXP */
11513 static NeonGenTwoOpFn
* const fns
[3][2] = {
11514 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11515 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11516 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11518 genfn
= fns
[size
][u
];
11521 case 0x15: /* SMINP, UMINP */
11523 static NeonGenTwoOpFn
* const fns
[3][2] = {
11524 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11525 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11526 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11528 genfn
= fns
[size
][u
];
11531 /* The FP operations are all on single floats (32 bit) */
11532 case 0x58: /* FMAXNMP */
11533 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11535 case 0x5a: /* FADDP */
11536 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11538 case 0x5e: /* FMAXP */
11539 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11541 case 0x78: /* FMINNMP */
11542 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11544 case 0x7e: /* FMINP */
11545 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11548 g_assert_not_reached();
11551 /* FP ops called directly, otherwise call now */
11553 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11556 tcg_temp_free_i32(tcg_op1
);
11557 tcg_temp_free_i32(tcg_op2
);
11560 for (pass
= 0; pass
< maxpass
; pass
++) {
11561 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11562 tcg_temp_free_i32(tcg_res
[pass
]);
11564 clear_vec_high(s
, is_q
, rd
);
11568 tcg_temp_free_ptr(fpst
);
11572 /* Floating point op subgroup of C3.6.16. */
11573 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11575 /* For floating point ops, the U, size[1] and opcode bits
11576 * together indicate the operation. size[0] indicates single
11579 int fpopcode
= extract32(insn
, 11, 5)
11580 | (extract32(insn
, 23, 1) << 5)
11581 | (extract32(insn
, 29, 1) << 6);
11582 int is_q
= extract32(insn
, 30, 1);
11583 int size
= extract32(insn
, 22, 1);
11584 int rm
= extract32(insn
, 16, 5);
11585 int rn
= extract32(insn
, 5, 5);
11586 int rd
= extract32(insn
, 0, 5);
11588 int datasize
= is_q
? 128 : 64;
11589 int esize
= 32 << size
;
11590 int elements
= datasize
/ esize
;
11592 if (size
== 1 && !is_q
) {
11593 unallocated_encoding(s
);
11597 switch (fpopcode
) {
11598 case 0x58: /* FMAXNMP */
11599 case 0x5a: /* FADDP */
11600 case 0x5e: /* FMAXP */
11601 case 0x78: /* FMINNMP */
11602 case 0x7e: /* FMINP */
11603 if (size
&& !is_q
) {
11604 unallocated_encoding(s
);
11607 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11610 case 0x1b: /* FMULX */
11611 case 0x1f: /* FRECPS */
11612 case 0x3f: /* FRSQRTS */
11613 case 0x5d: /* FACGE */
11614 case 0x7d: /* FACGT */
11615 case 0x19: /* FMLA */
11616 case 0x39: /* FMLS */
11617 case 0x18: /* FMAXNM */
11618 case 0x1a: /* FADD */
11619 case 0x1c: /* FCMEQ */
11620 case 0x1e: /* FMAX */
11621 case 0x38: /* FMINNM */
11622 case 0x3a: /* FSUB */
11623 case 0x3e: /* FMIN */
11624 case 0x5b: /* FMUL */
11625 case 0x5c: /* FCMGE */
11626 case 0x5f: /* FDIV */
11627 case 0x7a: /* FABD */
11628 case 0x7c: /* FCMGT */
11629 if (!fp_access_check(s
)) {
11632 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11635 case 0x1d: /* FMLAL */
11636 case 0x3d: /* FMLSL */
11637 case 0x59: /* FMLAL2 */
11638 case 0x79: /* FMLSL2 */
11639 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11640 unallocated_encoding(s
);
11643 if (fp_access_check(s
)) {
11644 int is_s
= extract32(insn
, 23, 1);
11645 int is_2
= extract32(insn
, 29, 1);
11646 int data
= (is_2
<< 1) | is_s
;
11647 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11648 vec_full_reg_offset(s
, rn
),
11649 vec_full_reg_offset(s
, rm
), cpu_env
,
11650 is_q
? 16 : 8, vec_full_reg_size(s
),
11651 data
, gen_helper_gvec_fmlal_a64
);
11656 unallocated_encoding(s
);
11661 /* Integer op subgroup of C3.6.16. */
11662 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11664 int is_q
= extract32(insn
, 30, 1);
11665 int u
= extract32(insn
, 29, 1);
11666 int size
= extract32(insn
, 22, 2);
11667 int opcode
= extract32(insn
, 11, 5);
11668 int rm
= extract32(insn
, 16, 5);
11669 int rn
= extract32(insn
, 5, 5);
11670 int rd
= extract32(insn
, 0, 5);
11675 case 0x13: /* MUL, PMUL */
11676 if (u
&& size
!= 0) {
11677 unallocated_encoding(s
);
11681 case 0x0: /* SHADD, UHADD */
11682 case 0x2: /* SRHADD, URHADD */
11683 case 0x4: /* SHSUB, UHSUB */
11684 case 0xc: /* SMAX, UMAX */
11685 case 0xd: /* SMIN, UMIN */
11686 case 0xe: /* SABD, UABD */
11687 case 0xf: /* SABA, UABA */
11688 case 0x12: /* MLA, MLS */
11690 unallocated_encoding(s
);
11694 case 0x16: /* SQDMULH, SQRDMULH */
11695 if (size
== 0 || size
== 3) {
11696 unallocated_encoding(s
);
11701 if (size
== 3 && !is_q
) {
11702 unallocated_encoding(s
);
11708 if (!fp_access_check(s
)) {
11713 case 0x01: /* SQADD, UQADD */
11715 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11717 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11720 case 0x05: /* SQSUB, UQSUB */
11722 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11724 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11727 case 0x08: /* SSHL, USHL */
11729 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11731 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11734 case 0x0c: /* SMAX, UMAX */
11736 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11738 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11741 case 0x0d: /* SMIN, UMIN */
11743 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11745 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11748 case 0xe: /* SABD, UABD */
11750 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11752 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11755 case 0xf: /* SABA, UABA */
11757 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11759 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11762 case 0x10: /* ADD, SUB */
11764 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11766 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11769 case 0x13: /* MUL, PMUL */
11770 if (!u
) { /* MUL */
11771 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11772 } else { /* PMUL */
11773 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11776 case 0x12: /* MLA, MLS */
11778 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11780 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11783 case 0x16: /* SQDMULH, SQRDMULH */
11785 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11786 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11787 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11789 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11793 if (!u
) { /* CMTST */
11794 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11798 cond
= TCG_COND_EQ
;
11800 case 0x06: /* CMGT, CMHI */
11801 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11803 case 0x07: /* CMGE, CMHS */
11804 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11806 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11807 vec_full_reg_offset(s
, rn
),
11808 vec_full_reg_offset(s
, rm
),
11809 is_q
? 16 : 8, vec_full_reg_size(s
));
11815 for (pass
= 0; pass
< 2; pass
++) {
11816 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11817 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11818 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11820 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11821 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11823 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11825 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11827 tcg_temp_free_i64(tcg_res
);
11828 tcg_temp_free_i64(tcg_op1
);
11829 tcg_temp_free_i64(tcg_op2
);
11832 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11833 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11834 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11835 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11836 NeonGenTwoOpFn
*genfn
= NULL
;
11837 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11839 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11840 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11843 case 0x0: /* SHADD, UHADD */
11845 static NeonGenTwoOpFn
* const fns
[3][2] = {
11846 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11847 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11848 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11850 genfn
= fns
[size
][u
];
11853 case 0x2: /* SRHADD, URHADD */
11855 static NeonGenTwoOpFn
* const fns
[3][2] = {
11856 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11857 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11858 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11860 genfn
= fns
[size
][u
];
11863 case 0x4: /* SHSUB, UHSUB */
11865 static NeonGenTwoOpFn
* const fns
[3][2] = {
11866 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11867 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11868 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11870 genfn
= fns
[size
][u
];
11873 case 0x9: /* SQSHL, UQSHL */
11875 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11876 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11877 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11878 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11880 genenvfn
= fns
[size
][u
];
11883 case 0xa: /* SRSHL, URSHL */
11885 static NeonGenTwoOpFn
* const fns
[3][2] = {
11886 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11887 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11888 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11890 genfn
= fns
[size
][u
];
11893 case 0xb: /* SQRSHL, UQRSHL */
11895 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11896 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11897 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11898 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11900 genenvfn
= fns
[size
][u
];
11904 g_assert_not_reached();
11908 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11910 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11913 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11915 tcg_temp_free_i32(tcg_res
);
11916 tcg_temp_free_i32(tcg_op1
);
11917 tcg_temp_free_i32(tcg_op2
);
11920 clear_vec_high(s
, is_q
, rd
);
11923 /* AdvSIMD three same
11924 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11925 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11926 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11927 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11929 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11931 int opcode
= extract32(insn
, 11, 5);
11934 case 0x3: /* logic ops */
11935 disas_simd_3same_logic(s
, insn
);
11937 case 0x17: /* ADDP */
11938 case 0x14: /* SMAXP, UMAXP */
11939 case 0x15: /* SMINP, UMINP */
11941 /* Pairwise operations */
11942 int is_q
= extract32(insn
, 30, 1);
11943 int u
= extract32(insn
, 29, 1);
11944 int size
= extract32(insn
, 22, 2);
11945 int rm
= extract32(insn
, 16, 5);
11946 int rn
= extract32(insn
, 5, 5);
11947 int rd
= extract32(insn
, 0, 5);
11948 if (opcode
== 0x17) {
11949 if (u
|| (size
== 3 && !is_q
)) {
11950 unallocated_encoding(s
);
11955 unallocated_encoding(s
);
11959 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11962 case 0x18 ... 0x31:
11963 /* floating point ops, sz[1] and U are part of opcode */
11964 disas_simd_3same_float(s
, insn
);
11967 disas_simd_3same_int(s
, insn
);
11973 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11975 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11976 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11977 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11978 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11980 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11981 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11984 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11986 int opcode
, fpopcode
;
11987 int is_q
, u
, a
, rm
, rn
, rd
;
11988 int datasize
, elements
;
11991 bool pairwise
= false;
11993 if (!dc_isar_feature(aa64_fp16
, s
)) {
11994 unallocated_encoding(s
);
11998 if (!fp_access_check(s
)) {
12002 /* For these floating point ops, the U, a and opcode bits
12003 * together indicate the operation.
12005 opcode
= extract32(insn
, 11, 3);
12006 u
= extract32(insn
, 29, 1);
12007 a
= extract32(insn
, 23, 1);
12008 is_q
= extract32(insn
, 30, 1);
12009 rm
= extract32(insn
, 16, 5);
12010 rn
= extract32(insn
, 5, 5);
12011 rd
= extract32(insn
, 0, 5);
12013 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
12014 datasize
= is_q
? 128 : 64;
12015 elements
= datasize
/ 16;
12017 switch (fpopcode
) {
12018 case 0x10: /* FMAXNMP */
12019 case 0x12: /* FADDP */
12020 case 0x16: /* FMAXP */
12021 case 0x18: /* FMINNMP */
12022 case 0x1e: /* FMINP */
12027 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
12030 int maxpass
= is_q
? 8 : 4;
12031 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12032 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12033 TCGv_i32 tcg_res
[8];
12035 for (pass
= 0; pass
< maxpass
; pass
++) {
12036 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
12037 int passelt
= (pass
<< 1) & (maxpass
- 1);
12039 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
12040 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
12041 tcg_res
[pass
] = tcg_temp_new_i32();
12043 switch (fpopcode
) {
12044 case 0x10: /* FMAXNMP */
12045 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12048 case 0x12: /* FADDP */
12049 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12051 case 0x16: /* FMAXP */
12052 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12054 case 0x18: /* FMINNMP */
12055 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12058 case 0x1e: /* FMINP */
12059 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12062 g_assert_not_reached();
12066 for (pass
= 0; pass
< maxpass
; pass
++) {
12067 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12068 tcg_temp_free_i32(tcg_res
[pass
]);
12071 tcg_temp_free_i32(tcg_op1
);
12072 tcg_temp_free_i32(tcg_op2
);
12075 for (pass
= 0; pass
< elements
; pass
++) {
12076 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12077 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12078 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12080 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12081 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12083 switch (fpopcode
) {
12084 case 0x0: /* FMAXNM */
12085 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12087 case 0x1: /* FMLA */
12088 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12089 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12092 case 0x2: /* FADD */
12093 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12095 case 0x3: /* FMULX */
12096 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12098 case 0x4: /* FCMEQ */
12099 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12101 case 0x6: /* FMAX */
12102 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12104 case 0x7: /* FRECPS */
12105 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12107 case 0x8: /* FMINNM */
12108 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12110 case 0x9: /* FMLS */
12111 /* As usual for ARM, separate negation for fused multiply-add */
12112 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12113 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12114 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12117 case 0xa: /* FSUB */
12118 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12120 case 0xe: /* FMIN */
12121 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12123 case 0xf: /* FRSQRTS */
12124 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12126 case 0x13: /* FMUL */
12127 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12129 case 0x14: /* FCMGE */
12130 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12132 case 0x15: /* FACGE */
12133 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12135 case 0x17: /* FDIV */
12136 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12138 case 0x1a: /* FABD */
12139 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12140 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12142 case 0x1c: /* FCMGT */
12143 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12145 case 0x1d: /* FACGT */
12146 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12149 fprintf(stderr
, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64
"\n",
12150 __func__
, insn
, fpopcode
, s
->pc_curr
);
12151 g_assert_not_reached();
12154 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12155 tcg_temp_free_i32(tcg_res
);
12156 tcg_temp_free_i32(tcg_op1
);
12157 tcg_temp_free_i32(tcg_op2
);
12161 tcg_temp_free_ptr(fpst
);
12163 clear_vec_high(s
, is_q
, rd
);
12166 /* AdvSIMD three same extra
12167 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12168 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12169 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12170 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12172 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12174 int rd
= extract32(insn
, 0, 5);
12175 int rn
= extract32(insn
, 5, 5);
12176 int opcode
= extract32(insn
, 11, 4);
12177 int rm
= extract32(insn
, 16, 5);
12178 int size
= extract32(insn
, 22, 2);
12179 bool u
= extract32(insn
, 29, 1);
12180 bool is_q
= extract32(insn
, 30, 1);
12184 switch (u
* 16 + opcode
) {
12185 case 0x10: /* SQRDMLAH (vector) */
12186 case 0x11: /* SQRDMLSH (vector) */
12187 if (size
!= 1 && size
!= 2) {
12188 unallocated_encoding(s
);
12191 feature
= dc_isar_feature(aa64_rdm
, s
);
12193 case 0x02: /* SDOT (vector) */
12194 case 0x12: /* UDOT (vector) */
12195 if (size
!= MO_32
) {
12196 unallocated_encoding(s
);
12199 feature
= dc_isar_feature(aa64_dp
, s
);
12201 case 0x03: /* USDOT */
12202 if (size
!= MO_32
) {
12203 unallocated_encoding(s
);
12206 feature
= dc_isar_feature(aa64_i8mm
, s
);
12208 case 0x04: /* SMMLA */
12209 case 0x14: /* UMMLA */
12210 case 0x05: /* USMMLA */
12211 if (!is_q
|| size
!= MO_32
) {
12212 unallocated_encoding(s
);
12215 feature
= dc_isar_feature(aa64_i8mm
, s
);
12217 case 0x18: /* FCMLA, #0 */
12218 case 0x19: /* FCMLA, #90 */
12219 case 0x1a: /* FCMLA, #180 */
12220 case 0x1b: /* FCMLA, #270 */
12221 case 0x1c: /* FCADD, #90 */
12222 case 0x1e: /* FCADD, #270 */
12224 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12225 || (size
== 3 && !is_q
)) {
12226 unallocated_encoding(s
);
12229 feature
= dc_isar_feature(aa64_fcma
, s
);
12232 unallocated_encoding(s
);
12236 unallocated_encoding(s
);
12239 if (!fp_access_check(s
)) {
12244 case 0x0: /* SQRDMLAH (vector) */
12245 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12248 case 0x1: /* SQRDMLSH (vector) */
12249 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12252 case 0x2: /* SDOT / UDOT */
12253 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
12254 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12257 case 0x3: /* USDOT */
12258 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
12261 case 0x04: /* SMMLA, UMMLA */
12262 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
12263 u
? gen_helper_gvec_ummla_b
12264 : gen_helper_gvec_smmla_b
);
12266 case 0x05: /* USMMLA */
12267 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
12270 case 0x8: /* FCMLA, #0 */
12271 case 0x9: /* FCMLA, #90 */
12272 case 0xa: /* FCMLA, #180 */
12273 case 0xb: /* FCMLA, #270 */
12274 rot
= extract32(opcode
, 0, 2);
12277 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
12278 gen_helper_gvec_fcmlah
);
12281 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12282 gen_helper_gvec_fcmlas
);
12285 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12286 gen_helper_gvec_fcmlad
);
12289 g_assert_not_reached();
12293 case 0xc: /* FCADD, #90 */
12294 case 0xe: /* FCADD, #270 */
12295 rot
= extract32(opcode
, 1, 1);
12298 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12299 gen_helper_gvec_fcaddh
);
12302 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12303 gen_helper_gvec_fcadds
);
12306 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12307 gen_helper_gvec_fcaddd
);
12310 g_assert_not_reached();
12315 g_assert_not_reached();
12319 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12320 int size
, int rn
, int rd
)
12322 /* Handle 2-reg-misc ops which are widening (so each size element
12323 * in the source becomes a 2*size element in the destination.
12324 * The only instruction like this is FCVTL.
12329 /* 32 -> 64 bit fp conversion */
12330 TCGv_i64 tcg_res
[2];
12331 int srcelt
= is_q
? 2 : 0;
12333 for (pass
= 0; pass
< 2; pass
++) {
12334 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12335 tcg_res
[pass
] = tcg_temp_new_i64();
12337 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12338 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12339 tcg_temp_free_i32(tcg_op
);
12341 for (pass
= 0; pass
< 2; pass
++) {
12342 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12343 tcg_temp_free_i64(tcg_res
[pass
]);
12346 /* 16 -> 32 bit fp conversion */
12347 int srcelt
= is_q
? 4 : 0;
12348 TCGv_i32 tcg_res
[4];
12349 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12350 TCGv_i32 ahp
= get_ahp_flag();
12352 for (pass
= 0; pass
< 4; pass
++) {
12353 tcg_res
[pass
] = tcg_temp_new_i32();
12355 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12356 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12359 for (pass
= 0; pass
< 4; pass
++) {
12360 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12361 tcg_temp_free_i32(tcg_res
[pass
]);
12364 tcg_temp_free_ptr(fpst
);
12365 tcg_temp_free_i32(ahp
);
12369 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12370 bool is_q
, int size
, int rn
, int rd
)
12372 int op
= (opcode
<< 1) | u
;
12373 int opsz
= op
+ size
;
12374 int grp_size
= 3 - opsz
;
12375 int dsize
= is_q
? 128 : 64;
12379 unallocated_encoding(s
);
12383 if (!fp_access_check(s
)) {
12388 /* Special case bytes, use bswap op on each group of elements */
12389 int groups
= dsize
/ (8 << grp_size
);
12391 for (i
= 0; i
< groups
; i
++) {
12392 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12394 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12395 switch (grp_size
) {
12397 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
12400 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
12403 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12406 g_assert_not_reached();
12408 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12409 tcg_temp_free_i64(tcg_tmp
);
12411 clear_vec_high(s
, is_q
, rd
);
12413 int revmask
= (1 << grp_size
) - 1;
12414 int esize
= 8 << size
;
12415 int elements
= dsize
/ esize
;
12416 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12417 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12418 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12420 for (i
= 0; i
< elements
; i
++) {
12421 int e_rev
= (i
& 0xf) ^ revmask
;
12422 int off
= e_rev
* esize
;
12423 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12425 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12426 tcg_rn
, off
- 64, esize
);
12428 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12431 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12432 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12434 tcg_temp_free_i64(tcg_rd_hi
);
12435 tcg_temp_free_i64(tcg_rd
);
12436 tcg_temp_free_i64(tcg_rn
);
12440 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12441 bool is_q
, int size
, int rn
, int rd
)
12443 /* Implement the pairwise operations from 2-misc:
12444 * SADDLP, UADDLP, SADALP, UADALP.
12445 * These all add pairs of elements in the input to produce a
12446 * double-width result element in the output (possibly accumulating).
12448 bool accum
= (opcode
== 0x6);
12449 int maxpass
= is_q
? 2 : 1;
12451 TCGv_i64 tcg_res
[2];
12454 /* 32 + 32 -> 64 op */
12455 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12457 for (pass
= 0; pass
< maxpass
; pass
++) {
12458 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12459 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12461 tcg_res
[pass
] = tcg_temp_new_i64();
12463 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12464 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12465 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12467 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12468 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12471 tcg_temp_free_i64(tcg_op1
);
12472 tcg_temp_free_i64(tcg_op2
);
12475 for (pass
= 0; pass
< maxpass
; pass
++) {
12476 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12477 NeonGenOne64OpFn
*genfn
;
12478 static NeonGenOne64OpFn
* const fns
[2][2] = {
12479 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12480 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12483 genfn
= fns
[size
][u
];
12485 tcg_res
[pass
] = tcg_temp_new_i64();
12487 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12488 genfn(tcg_res
[pass
], tcg_op
);
12491 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12493 gen_helper_neon_addl_u16(tcg_res
[pass
],
12494 tcg_res
[pass
], tcg_op
);
12496 gen_helper_neon_addl_u32(tcg_res
[pass
],
12497 tcg_res
[pass
], tcg_op
);
12500 tcg_temp_free_i64(tcg_op
);
12504 tcg_res
[1] = tcg_const_i64(0);
12506 for (pass
= 0; pass
< 2; pass
++) {
12507 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12508 tcg_temp_free_i64(tcg_res
[pass
]);
12512 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12514 /* Implement SHLL and SHLL2 */
12516 int part
= is_q
? 2 : 0;
12517 TCGv_i64 tcg_res
[2];
12519 for (pass
= 0; pass
< 2; pass
++) {
12520 static NeonGenWidenFn
* const widenfns
[3] = {
12521 gen_helper_neon_widen_u8
,
12522 gen_helper_neon_widen_u16
,
12523 tcg_gen_extu_i32_i64
,
12525 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12526 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12528 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12529 tcg_res
[pass
] = tcg_temp_new_i64();
12530 widenfn(tcg_res
[pass
], tcg_op
);
12531 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12533 tcg_temp_free_i32(tcg_op
);
12536 for (pass
= 0; pass
< 2; pass
++) {
12537 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12538 tcg_temp_free_i64(tcg_res
[pass
]);
12542 /* AdvSIMD two reg misc
12543 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12544 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12545 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12546 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12548 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12550 int size
= extract32(insn
, 22, 2);
12551 int opcode
= extract32(insn
, 12, 5);
12552 bool u
= extract32(insn
, 29, 1);
12553 bool is_q
= extract32(insn
, 30, 1);
12554 int rn
= extract32(insn
, 5, 5);
12555 int rd
= extract32(insn
, 0, 5);
12556 bool need_fpstatus
= false;
12557 bool need_rmode
= false;
12559 TCGv_i32 tcg_rmode
;
12560 TCGv_ptr tcg_fpstatus
;
12563 case 0x0: /* REV64, REV32 */
12564 case 0x1: /* REV16 */
12565 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12567 case 0x5: /* CNT, NOT, RBIT */
12568 if (u
&& size
== 0) {
12571 } else if (u
&& size
== 1) {
12574 } else if (!u
&& size
== 0) {
12578 unallocated_encoding(s
);
12580 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12581 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12583 unallocated_encoding(s
);
12586 if (!fp_access_check(s
)) {
12590 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12592 case 0x4: /* CLS, CLZ */
12594 unallocated_encoding(s
);
12598 case 0x2: /* SADDLP, UADDLP */
12599 case 0x6: /* SADALP, UADALP */
12601 unallocated_encoding(s
);
12604 if (!fp_access_check(s
)) {
12607 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12609 case 0x13: /* SHLL, SHLL2 */
12610 if (u
== 0 || size
== 3) {
12611 unallocated_encoding(s
);
12614 if (!fp_access_check(s
)) {
12617 handle_shll(s
, is_q
, size
, rn
, rd
);
12619 case 0xa: /* CMLT */
12621 unallocated_encoding(s
);
12625 case 0x8: /* CMGT, CMGE */
12626 case 0x9: /* CMEQ, CMLE */
12627 case 0xb: /* ABS, NEG */
12628 if (size
== 3 && !is_q
) {
12629 unallocated_encoding(s
);
12633 case 0x3: /* SUQADD, USQADD */
12634 if (size
== 3 && !is_q
) {
12635 unallocated_encoding(s
);
12638 if (!fp_access_check(s
)) {
12641 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12643 case 0x7: /* SQABS, SQNEG */
12644 if (size
== 3 && !is_q
) {
12645 unallocated_encoding(s
);
12650 case 0x16 ... 0x1f:
12652 /* Floating point: U, size[1] and opcode indicate operation;
12653 * size[0] indicates single or double precision.
12655 int is_double
= extract32(size
, 0, 1);
12656 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12657 size
= is_double
? 3 : 2;
12659 case 0x2f: /* FABS */
12660 case 0x6f: /* FNEG */
12661 if (size
== 3 && !is_q
) {
12662 unallocated_encoding(s
);
12666 case 0x1d: /* SCVTF */
12667 case 0x5d: /* UCVTF */
12669 bool is_signed
= (opcode
== 0x1d) ? true : false;
12670 int elements
= is_double
? 2 : is_q
? 4 : 2;
12671 if (is_double
&& !is_q
) {
12672 unallocated_encoding(s
);
12675 if (!fp_access_check(s
)) {
12678 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12681 case 0x2c: /* FCMGT (zero) */
12682 case 0x2d: /* FCMEQ (zero) */
12683 case 0x2e: /* FCMLT (zero) */
12684 case 0x6c: /* FCMGE (zero) */
12685 case 0x6d: /* FCMLE (zero) */
12686 if (size
== 3 && !is_q
) {
12687 unallocated_encoding(s
);
12690 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12692 case 0x7f: /* FSQRT */
12693 if (size
== 3 && !is_q
) {
12694 unallocated_encoding(s
);
12698 case 0x1a: /* FCVTNS */
12699 case 0x1b: /* FCVTMS */
12700 case 0x3a: /* FCVTPS */
12701 case 0x3b: /* FCVTZS */
12702 case 0x5a: /* FCVTNU */
12703 case 0x5b: /* FCVTMU */
12704 case 0x7a: /* FCVTPU */
12705 case 0x7b: /* FCVTZU */
12706 need_fpstatus
= true;
12708 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12709 if (size
== 3 && !is_q
) {
12710 unallocated_encoding(s
);
12714 case 0x5c: /* FCVTAU */
12715 case 0x1c: /* FCVTAS */
12716 need_fpstatus
= true;
12718 rmode
= FPROUNDING_TIEAWAY
;
12719 if (size
== 3 && !is_q
) {
12720 unallocated_encoding(s
);
12724 case 0x3c: /* URECPE */
12726 unallocated_encoding(s
);
12730 case 0x3d: /* FRECPE */
12731 case 0x7d: /* FRSQRTE */
12732 if (size
== 3 && !is_q
) {
12733 unallocated_encoding(s
);
12736 if (!fp_access_check(s
)) {
12739 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12741 case 0x56: /* FCVTXN, FCVTXN2 */
12743 unallocated_encoding(s
);
12747 case 0x16: /* FCVTN, FCVTN2 */
12748 /* handle_2misc_narrow does a 2*size -> size operation, but these
12749 * instructions encode the source size rather than dest size.
12751 if (!fp_access_check(s
)) {
12754 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12756 case 0x17: /* FCVTL, FCVTL2 */
12757 if (!fp_access_check(s
)) {
12760 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12762 case 0x18: /* FRINTN */
12763 case 0x19: /* FRINTM */
12764 case 0x38: /* FRINTP */
12765 case 0x39: /* FRINTZ */
12767 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12769 case 0x59: /* FRINTX */
12770 case 0x79: /* FRINTI */
12771 need_fpstatus
= true;
12772 if (size
== 3 && !is_q
) {
12773 unallocated_encoding(s
);
12777 case 0x58: /* FRINTA */
12779 rmode
= FPROUNDING_TIEAWAY
;
12780 need_fpstatus
= true;
12781 if (size
== 3 && !is_q
) {
12782 unallocated_encoding(s
);
12786 case 0x7c: /* URSQRTE */
12788 unallocated_encoding(s
);
12792 case 0x1e: /* FRINT32Z */
12793 case 0x1f: /* FRINT64Z */
12795 rmode
= FPROUNDING_ZERO
;
12797 case 0x5e: /* FRINT32X */
12798 case 0x5f: /* FRINT64X */
12799 need_fpstatus
= true;
12800 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12801 unallocated_encoding(s
);
12806 unallocated_encoding(s
);
12812 unallocated_encoding(s
);
12816 if (!fp_access_check(s
)) {
12820 if (need_fpstatus
|| need_rmode
) {
12821 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12823 tcg_fpstatus
= NULL
;
12826 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12827 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12834 if (u
&& size
== 0) { /* NOT */
12835 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12839 case 0x8: /* CMGT, CMGE */
12841 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12843 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12846 case 0x9: /* CMEQ, CMLE */
12848 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12850 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12853 case 0xa: /* CMLT */
12854 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12857 if (u
) { /* ABS, NEG */
12858 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12860 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12866 /* All 64-bit element operations can be shared with scalar 2misc */
12869 /* Coverity claims (size == 3 && !is_q) has been eliminated
12870 * from all paths leading to here.
12872 tcg_debug_assert(is_q
);
12873 for (pass
= 0; pass
< 2; pass
++) {
12874 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12875 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12877 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12879 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12880 tcg_rmode
, tcg_fpstatus
);
12882 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12884 tcg_temp_free_i64(tcg_res
);
12885 tcg_temp_free_i64(tcg_op
);
12890 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12891 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12892 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12894 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12897 /* Special cases for 32 bit elements */
12899 case 0x4: /* CLS */
12901 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12903 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12906 case 0x7: /* SQABS, SQNEG */
12908 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12910 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12913 case 0x2f: /* FABS */
12914 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12916 case 0x6f: /* FNEG */
12917 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12919 case 0x7f: /* FSQRT */
12920 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12922 case 0x1a: /* FCVTNS */
12923 case 0x1b: /* FCVTMS */
12924 case 0x1c: /* FCVTAS */
12925 case 0x3a: /* FCVTPS */
12926 case 0x3b: /* FCVTZS */
12928 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12929 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12930 tcg_shift
, tcg_fpstatus
);
12931 tcg_temp_free_i32(tcg_shift
);
12934 case 0x5a: /* FCVTNU */
12935 case 0x5b: /* FCVTMU */
12936 case 0x5c: /* FCVTAU */
12937 case 0x7a: /* FCVTPU */
12938 case 0x7b: /* FCVTZU */
12940 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12941 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12942 tcg_shift
, tcg_fpstatus
);
12943 tcg_temp_free_i32(tcg_shift
);
12946 case 0x18: /* FRINTN */
12947 case 0x19: /* FRINTM */
12948 case 0x38: /* FRINTP */
12949 case 0x39: /* FRINTZ */
12950 case 0x58: /* FRINTA */
12951 case 0x79: /* FRINTI */
12952 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12954 case 0x59: /* FRINTX */
12955 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12957 case 0x7c: /* URSQRTE */
12958 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12960 case 0x1e: /* FRINT32Z */
12961 case 0x5e: /* FRINT32X */
12962 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12964 case 0x1f: /* FRINT64Z */
12965 case 0x5f: /* FRINT64X */
12966 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12969 g_assert_not_reached();
12972 /* Use helpers for 8 and 16 bit elements */
12974 case 0x5: /* CNT, RBIT */
12975 /* For these two insns size is part of the opcode specifier
12976 * (handled earlier); they always operate on byte elements.
12979 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12981 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12984 case 0x7: /* SQABS, SQNEG */
12986 NeonGenOneOpEnvFn
*genfn
;
12987 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12988 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12989 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12991 genfn
= fns
[size
][u
];
12992 genfn(tcg_res
, cpu_env
, tcg_op
);
12995 case 0x4: /* CLS, CLZ */
12998 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
13000 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
13004 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
13006 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
13011 g_assert_not_reached();
13015 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13017 tcg_temp_free_i32(tcg_res
);
13018 tcg_temp_free_i32(tcg_op
);
13021 clear_vec_high(s
, is_q
, rd
);
13024 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13025 tcg_temp_free_i32(tcg_rmode
);
13027 if (need_fpstatus
) {
13028 tcg_temp_free_ptr(tcg_fpstatus
);
13032 /* AdvSIMD [scalar] two register miscellaneous (FP16)
13034 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
13035 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13036 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
13037 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13038 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
13039 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
13041 * This actually covers two groups where scalar access is governed by
13042 * bit 28. A bunch of the instructions (float to integral) only exist
13043 * in the vector form and are un-allocated for the scalar decode. Also
13044 * in the scalar decode Q is always 1.
13046 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
13048 int fpop
, opcode
, a
, u
;
13052 bool only_in_vector
= false;
13055 TCGv_i32 tcg_rmode
= NULL
;
13056 TCGv_ptr tcg_fpstatus
= NULL
;
13057 bool need_rmode
= false;
13058 bool need_fpst
= true;
13061 if (!dc_isar_feature(aa64_fp16
, s
)) {
13062 unallocated_encoding(s
);
13066 rd
= extract32(insn
, 0, 5);
13067 rn
= extract32(insn
, 5, 5);
13069 a
= extract32(insn
, 23, 1);
13070 u
= extract32(insn
, 29, 1);
13071 is_scalar
= extract32(insn
, 28, 1);
13072 is_q
= extract32(insn
, 30, 1);
13074 opcode
= extract32(insn
, 12, 5);
13075 fpop
= deposit32(opcode
, 5, 1, a
);
13076 fpop
= deposit32(fpop
, 6, 1, u
);
13079 case 0x1d: /* SCVTF */
13080 case 0x5d: /* UCVTF */
13087 elements
= (is_q
? 8 : 4);
13090 if (!fp_access_check(s
)) {
13093 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13097 case 0x2c: /* FCMGT (zero) */
13098 case 0x2d: /* FCMEQ (zero) */
13099 case 0x2e: /* FCMLT (zero) */
13100 case 0x6c: /* FCMGE (zero) */
13101 case 0x6d: /* FCMLE (zero) */
13102 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13104 case 0x3d: /* FRECPE */
13105 case 0x3f: /* FRECPX */
13107 case 0x18: /* FRINTN */
13109 only_in_vector
= true;
13110 rmode
= FPROUNDING_TIEEVEN
;
13112 case 0x19: /* FRINTM */
13114 only_in_vector
= true;
13115 rmode
= FPROUNDING_NEGINF
;
13117 case 0x38: /* FRINTP */
13119 only_in_vector
= true;
13120 rmode
= FPROUNDING_POSINF
;
13122 case 0x39: /* FRINTZ */
13124 only_in_vector
= true;
13125 rmode
= FPROUNDING_ZERO
;
13127 case 0x58: /* FRINTA */
13129 only_in_vector
= true;
13130 rmode
= FPROUNDING_TIEAWAY
;
13132 case 0x59: /* FRINTX */
13133 case 0x79: /* FRINTI */
13134 only_in_vector
= true;
13135 /* current rounding mode */
13137 case 0x1a: /* FCVTNS */
13139 rmode
= FPROUNDING_TIEEVEN
;
13141 case 0x1b: /* FCVTMS */
13143 rmode
= FPROUNDING_NEGINF
;
13145 case 0x1c: /* FCVTAS */
13147 rmode
= FPROUNDING_TIEAWAY
;
13149 case 0x3a: /* FCVTPS */
13151 rmode
= FPROUNDING_POSINF
;
13153 case 0x3b: /* FCVTZS */
13155 rmode
= FPROUNDING_ZERO
;
13157 case 0x5a: /* FCVTNU */
13159 rmode
= FPROUNDING_TIEEVEN
;
13161 case 0x5b: /* FCVTMU */
13163 rmode
= FPROUNDING_NEGINF
;
13165 case 0x5c: /* FCVTAU */
13167 rmode
= FPROUNDING_TIEAWAY
;
13169 case 0x7a: /* FCVTPU */
13171 rmode
= FPROUNDING_POSINF
;
13173 case 0x7b: /* FCVTZU */
13175 rmode
= FPROUNDING_ZERO
;
13177 case 0x2f: /* FABS */
13178 case 0x6f: /* FNEG */
13181 case 0x7d: /* FRSQRTE */
13182 case 0x7f: /* FSQRT (vector) */
13185 fprintf(stderr
, "%s: insn 0x%04x fpop 0x%2x\n", __func__
, insn
, fpop
);
13186 g_assert_not_reached();
13190 /* Check additional constraints for the scalar encoding */
13193 unallocated_encoding(s
);
13196 /* FRINTxx is only in the vector form */
13197 if (only_in_vector
) {
13198 unallocated_encoding(s
);
13203 if (!fp_access_check(s
)) {
13207 if (need_rmode
|| need_fpst
) {
13208 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13212 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13213 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13217 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13218 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13221 case 0x1a: /* FCVTNS */
13222 case 0x1b: /* FCVTMS */
13223 case 0x1c: /* FCVTAS */
13224 case 0x3a: /* FCVTPS */
13225 case 0x3b: /* FCVTZS */
13226 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13228 case 0x3d: /* FRECPE */
13229 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13231 case 0x3f: /* FRECPX */
13232 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13234 case 0x5a: /* FCVTNU */
13235 case 0x5b: /* FCVTMU */
13236 case 0x5c: /* FCVTAU */
13237 case 0x7a: /* FCVTPU */
13238 case 0x7b: /* FCVTZU */
13239 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13241 case 0x6f: /* FNEG */
13242 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13244 case 0x7d: /* FRSQRTE */
13245 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13248 g_assert_not_reached();
13251 /* limit any sign extension going on */
13252 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13253 write_fp_sreg(s
, rd
, tcg_res
);
13255 tcg_temp_free_i32(tcg_res
);
13256 tcg_temp_free_i32(tcg_op
);
13258 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13259 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13260 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13262 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13265 case 0x1a: /* FCVTNS */
13266 case 0x1b: /* FCVTMS */
13267 case 0x1c: /* FCVTAS */
13268 case 0x3a: /* FCVTPS */
13269 case 0x3b: /* FCVTZS */
13270 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13272 case 0x3d: /* FRECPE */
13273 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13275 case 0x5a: /* FCVTNU */
13276 case 0x5b: /* FCVTMU */
13277 case 0x5c: /* FCVTAU */
13278 case 0x7a: /* FCVTPU */
13279 case 0x7b: /* FCVTZU */
13280 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13282 case 0x18: /* FRINTN */
13283 case 0x19: /* FRINTM */
13284 case 0x38: /* FRINTP */
13285 case 0x39: /* FRINTZ */
13286 case 0x58: /* FRINTA */
13287 case 0x79: /* FRINTI */
13288 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13290 case 0x59: /* FRINTX */
13291 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13293 case 0x2f: /* FABS */
13294 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13296 case 0x6f: /* FNEG */
13297 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13299 case 0x7d: /* FRSQRTE */
13300 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13302 case 0x7f: /* FSQRT */
13303 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13306 g_assert_not_reached();
13309 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13311 tcg_temp_free_i32(tcg_res
);
13312 tcg_temp_free_i32(tcg_op
);
13315 clear_vec_high(s
, is_q
, rd
);
13319 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13320 tcg_temp_free_i32(tcg_rmode
);
13323 if (tcg_fpstatus
) {
13324 tcg_temp_free_ptr(tcg_fpstatus
);
13328 /* AdvSIMD scalar x indexed element
13329 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13330 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13331 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13332 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13333 * AdvSIMD vector x indexed element
13334 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13335 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13336 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13337 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13339 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13341 /* This encoding has two kinds of instruction:
13342 * normal, where we perform elt x idxelt => elt for each
13343 * element in the vector
13344 * long, where we perform elt x idxelt and generate a result of
13345 * double the width of the input element
13346 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13348 bool is_scalar
= extract32(insn
, 28, 1);
13349 bool is_q
= extract32(insn
, 30, 1);
13350 bool u
= extract32(insn
, 29, 1);
13351 int size
= extract32(insn
, 22, 2);
13352 int l
= extract32(insn
, 21, 1);
13353 int m
= extract32(insn
, 20, 1);
13354 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13355 int rm
= extract32(insn
, 16, 4);
13356 int opcode
= extract32(insn
, 12, 4);
13357 int h
= extract32(insn
, 11, 1);
13358 int rn
= extract32(insn
, 5, 5);
13359 int rd
= extract32(insn
, 0, 5);
13360 bool is_long
= false;
13362 bool is_fp16
= false;
13366 switch (16 * u
+ opcode
) {
13367 case 0x08: /* MUL */
13368 case 0x10: /* MLA */
13369 case 0x14: /* MLS */
13371 unallocated_encoding(s
);
13375 case 0x02: /* SMLAL, SMLAL2 */
13376 case 0x12: /* UMLAL, UMLAL2 */
13377 case 0x06: /* SMLSL, SMLSL2 */
13378 case 0x16: /* UMLSL, UMLSL2 */
13379 case 0x0a: /* SMULL, SMULL2 */
13380 case 0x1a: /* UMULL, UMULL2 */
13382 unallocated_encoding(s
);
13387 case 0x03: /* SQDMLAL, SQDMLAL2 */
13388 case 0x07: /* SQDMLSL, SQDMLSL2 */
13389 case 0x0b: /* SQDMULL, SQDMULL2 */
13392 case 0x0c: /* SQDMULH */
13393 case 0x0d: /* SQRDMULH */
13395 case 0x01: /* FMLA */
13396 case 0x05: /* FMLS */
13397 case 0x09: /* FMUL */
13398 case 0x19: /* FMULX */
13401 case 0x1d: /* SQRDMLAH */
13402 case 0x1f: /* SQRDMLSH */
13403 if (!dc_isar_feature(aa64_rdm
, s
)) {
13404 unallocated_encoding(s
);
13408 case 0x0e: /* SDOT */
13409 case 0x1e: /* UDOT */
13410 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13411 unallocated_encoding(s
);
13415 case 0x0f: /* SUDOT, USDOT */
13416 if (is_scalar
|| (size
& 1) || !dc_isar_feature(aa64_i8mm
, s
)) {
13417 unallocated_encoding(s
);
13422 case 0x11: /* FCMLA #0 */
13423 case 0x13: /* FCMLA #90 */
13424 case 0x15: /* FCMLA #180 */
13425 case 0x17: /* FCMLA #270 */
13426 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13427 unallocated_encoding(s
);
13432 case 0x00: /* FMLAL */
13433 case 0x04: /* FMLSL */
13434 case 0x18: /* FMLAL2 */
13435 case 0x1c: /* FMLSL2 */
13436 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13437 unallocated_encoding(s
);
13441 /* is_fp, but we pass cpu_env not fp_status. */
13444 unallocated_encoding(s
);
13449 case 1: /* normal fp */
13450 /* convert insn encoded size to MemOp size */
13452 case 0: /* half-precision */
13456 case MO_32
: /* single precision */
13457 case MO_64
: /* double precision */
13460 unallocated_encoding(s
);
13465 case 2: /* complex fp */
13466 /* Each indexable element is a complex pair. */
13471 unallocated_encoding(s
);
13479 unallocated_encoding(s
);
13484 default: /* integer */
13488 unallocated_encoding(s
);
13493 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13494 unallocated_encoding(s
);
13498 /* Given MemOp size, adjust register and indexing. */
13501 index
= h
<< 2 | l
<< 1 | m
;
13504 index
= h
<< 1 | l
;
13509 unallocated_encoding(s
);
13516 g_assert_not_reached();
13519 if (!fp_access_check(s
)) {
13524 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13529 switch (16 * u
+ opcode
) {
13530 case 0x0e: /* SDOT */
13531 case 0x1e: /* UDOT */
13532 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13533 u
? gen_helper_gvec_udot_idx_b
13534 : gen_helper_gvec_sdot_idx_b
);
13536 case 0x0f: /* SUDOT, USDOT */
13537 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13538 extract32(insn
, 23, 1)
13539 ? gen_helper_gvec_usdot_idx_b
13540 : gen_helper_gvec_sudot_idx_b
);
13543 case 0x11: /* FCMLA #0 */
13544 case 0x13: /* FCMLA #90 */
13545 case 0x15: /* FCMLA #180 */
13546 case 0x17: /* FCMLA #270 */
13548 int rot
= extract32(insn
, 13, 2);
13549 int data
= (index
<< 2) | rot
;
13550 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
13551 vec_full_reg_offset(s
, rn
),
13552 vec_full_reg_offset(s
, rm
),
13553 vec_full_reg_offset(s
, rd
), fpst
,
13554 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13556 ? gen_helper_gvec_fcmlas_idx
13557 : gen_helper_gvec_fcmlah_idx
);
13558 tcg_temp_free_ptr(fpst
);
13562 case 0x00: /* FMLAL */
13563 case 0x04: /* FMLSL */
13564 case 0x18: /* FMLAL2 */
13565 case 0x1c: /* FMLSL2 */
13567 int is_s
= extract32(opcode
, 2, 1);
13569 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13570 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13571 vec_full_reg_offset(s
, rn
),
13572 vec_full_reg_offset(s
, rm
), cpu_env
,
13573 is_q
? 16 : 8, vec_full_reg_size(s
),
13574 data
, gen_helper_gvec_fmlal_idx_a64
);
13578 case 0x08: /* MUL */
13579 if (!is_long
&& !is_scalar
) {
13580 static gen_helper_gvec_3
* const fns
[3] = {
13581 gen_helper_gvec_mul_idx_h
,
13582 gen_helper_gvec_mul_idx_s
,
13583 gen_helper_gvec_mul_idx_d
,
13585 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13586 vec_full_reg_offset(s
, rn
),
13587 vec_full_reg_offset(s
, rm
),
13588 is_q
? 16 : 8, vec_full_reg_size(s
),
13589 index
, fns
[size
- 1]);
13594 case 0x10: /* MLA */
13595 if (!is_long
&& !is_scalar
) {
13596 static gen_helper_gvec_4
* const fns
[3] = {
13597 gen_helper_gvec_mla_idx_h
,
13598 gen_helper_gvec_mla_idx_s
,
13599 gen_helper_gvec_mla_idx_d
,
13601 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13602 vec_full_reg_offset(s
, rn
),
13603 vec_full_reg_offset(s
, rm
),
13604 vec_full_reg_offset(s
, rd
),
13605 is_q
? 16 : 8, vec_full_reg_size(s
),
13606 index
, fns
[size
- 1]);
13611 case 0x14: /* MLS */
13612 if (!is_long
&& !is_scalar
) {
13613 static gen_helper_gvec_4
* const fns
[3] = {
13614 gen_helper_gvec_mls_idx_h
,
13615 gen_helper_gvec_mls_idx_s
,
13616 gen_helper_gvec_mls_idx_d
,
13618 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13619 vec_full_reg_offset(s
, rn
),
13620 vec_full_reg_offset(s
, rm
),
13621 vec_full_reg_offset(s
, rd
),
13622 is_q
? 16 : 8, vec_full_reg_size(s
),
13623 index
, fns
[size
- 1]);
13630 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13633 assert(is_fp
&& is_q
&& !is_long
);
13635 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13637 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13638 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13639 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13641 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13643 switch (16 * u
+ opcode
) {
13644 case 0x05: /* FMLS */
13645 /* As usual for ARM, separate negation for fused multiply-add */
13646 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13648 case 0x01: /* FMLA */
13649 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13650 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13652 case 0x09: /* FMUL */
13653 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13655 case 0x19: /* FMULX */
13656 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13659 g_assert_not_reached();
13662 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13663 tcg_temp_free_i64(tcg_op
);
13664 tcg_temp_free_i64(tcg_res
);
13667 tcg_temp_free_i64(tcg_idx
);
13668 clear_vec_high(s
, !is_scalar
, rd
);
13669 } else if (!is_long
) {
13670 /* 32 bit floating point, or 16 or 32 bit integer.
13671 * For the 16 bit scalar case we use the usual Neon helpers and
13672 * rely on the fact that 0 op 0 == 0 with no side effects.
13674 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13675 int pass
, maxpasses
;
13680 maxpasses
= is_q
? 4 : 2;
13683 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13685 if (size
== 1 && !is_scalar
) {
13686 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13687 * the index into both halves of the 32 bit tcg_idx and then use
13688 * the usual Neon helpers.
13690 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13693 for (pass
= 0; pass
< maxpasses
; pass
++) {
13694 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13695 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13697 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13699 switch (16 * u
+ opcode
) {
13700 case 0x08: /* MUL */
13701 case 0x10: /* MLA */
13702 case 0x14: /* MLS */
13704 static NeonGenTwoOpFn
* const fns
[2][2] = {
13705 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13706 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13708 NeonGenTwoOpFn
*genfn
;
13709 bool is_sub
= opcode
== 0x4;
13712 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13714 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13716 if (opcode
== 0x8) {
13719 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13720 genfn
= fns
[size
- 1][is_sub
];
13721 genfn(tcg_res
, tcg_op
, tcg_res
);
13724 case 0x05: /* FMLS */
13725 case 0x01: /* FMLA */
13726 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13727 is_scalar
? size
: MO_32
);
13730 if (opcode
== 0x5) {
13731 /* As usual for ARM, separate negation for fused
13733 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13736 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13739 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13744 if (opcode
== 0x5) {
13745 /* As usual for ARM, separate negation for
13746 * fused multiply-add */
13747 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13749 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13753 g_assert_not_reached();
13756 case 0x09: /* FMUL */
13760 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13763 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13768 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13771 g_assert_not_reached();
13774 case 0x19: /* FMULX */
13778 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13781 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13786 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13789 g_assert_not_reached();
13792 case 0x0c: /* SQDMULH */
13794 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13797 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13801 case 0x0d: /* SQRDMULH */
13803 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13806 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13810 case 0x1d: /* SQRDMLAH */
13811 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13812 is_scalar
? size
: MO_32
);
13814 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13815 tcg_op
, tcg_idx
, tcg_res
);
13817 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13818 tcg_op
, tcg_idx
, tcg_res
);
13821 case 0x1f: /* SQRDMLSH */
13822 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13823 is_scalar
? size
: MO_32
);
13825 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13826 tcg_op
, tcg_idx
, tcg_res
);
13828 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13829 tcg_op
, tcg_idx
, tcg_res
);
13833 g_assert_not_reached();
13837 write_fp_sreg(s
, rd
, tcg_res
);
13839 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13842 tcg_temp_free_i32(tcg_op
);
13843 tcg_temp_free_i32(tcg_res
);
13846 tcg_temp_free_i32(tcg_idx
);
13847 clear_vec_high(s
, is_q
, rd
);
13849 /* long ops: 16x16->32 or 32x32->64 */
13850 TCGv_i64 tcg_res
[2];
13852 bool satop
= extract32(opcode
, 0, 1);
13853 MemOp memop
= MO_32
;
13860 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13862 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13864 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13865 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13866 TCGv_i64 tcg_passres
;
13872 passelt
= pass
+ (is_q
* 2);
13875 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13877 tcg_res
[pass
] = tcg_temp_new_i64();
13879 if (opcode
== 0xa || opcode
== 0xb) {
13880 /* Non-accumulating ops */
13881 tcg_passres
= tcg_res
[pass
];
13883 tcg_passres
= tcg_temp_new_i64();
13886 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13887 tcg_temp_free_i64(tcg_op
);
13890 /* saturating, doubling */
13891 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13892 tcg_passres
, tcg_passres
);
13895 if (opcode
== 0xa || opcode
== 0xb) {
13899 /* Accumulating op: handle accumulate step */
13900 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13903 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13904 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13906 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13907 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13909 case 0x7: /* SQDMLSL, SQDMLSL2 */
13910 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13912 case 0x3: /* SQDMLAL, SQDMLAL2 */
13913 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13918 g_assert_not_reached();
13920 tcg_temp_free_i64(tcg_passres
);
13922 tcg_temp_free_i64(tcg_idx
);
13924 clear_vec_high(s
, !is_scalar
, rd
);
13926 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13929 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13932 /* The simplest way to handle the 16x16 indexed ops is to
13933 * duplicate the index into both halves of the 32 bit tcg_idx
13934 * and then use the usual Neon helpers.
13936 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13939 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13940 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13941 TCGv_i64 tcg_passres
;
13944 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13946 read_vec_element_i32(s
, tcg_op
, rn
,
13947 pass
+ (is_q
* 2), MO_32
);
13950 tcg_res
[pass
] = tcg_temp_new_i64();
13952 if (opcode
== 0xa || opcode
== 0xb) {
13953 /* Non-accumulating ops */
13954 tcg_passres
= tcg_res
[pass
];
13956 tcg_passres
= tcg_temp_new_i64();
13959 if (memop
& MO_SIGN
) {
13960 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13962 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13965 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13966 tcg_passres
, tcg_passres
);
13968 tcg_temp_free_i32(tcg_op
);
13970 if (opcode
== 0xa || opcode
== 0xb) {
13974 /* Accumulating op: handle accumulate step */
13975 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13978 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13979 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13982 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13983 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13986 case 0x7: /* SQDMLSL, SQDMLSL2 */
13987 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13989 case 0x3: /* SQDMLAL, SQDMLAL2 */
13990 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13995 g_assert_not_reached();
13997 tcg_temp_free_i64(tcg_passres
);
13999 tcg_temp_free_i32(tcg_idx
);
14002 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
14007 tcg_res
[1] = tcg_const_i64(0);
14010 for (pass
= 0; pass
< 2; pass
++) {
14011 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
14012 tcg_temp_free_i64(tcg_res
[pass
]);
14017 tcg_temp_free_ptr(fpst
);
14022 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14023 * +-----------------+------+-----------+--------+-----+------+------+
14024 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14025 * +-----------------+------+-----------+--------+-----+------+------+
14027 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
14029 int size
= extract32(insn
, 22, 2);
14030 int opcode
= extract32(insn
, 12, 5);
14031 int rn
= extract32(insn
, 5, 5);
14032 int rd
= extract32(insn
, 0, 5);
14034 gen_helper_gvec_2
*genfn2
= NULL
;
14035 gen_helper_gvec_3
*genfn3
= NULL
;
14037 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
14038 unallocated_encoding(s
);
14043 case 0x4: /* AESE */
14045 genfn3
= gen_helper_crypto_aese
;
14047 case 0x6: /* AESMC */
14049 genfn2
= gen_helper_crypto_aesmc
;
14051 case 0x5: /* AESD */
14053 genfn3
= gen_helper_crypto_aese
;
14055 case 0x7: /* AESIMC */
14057 genfn2
= gen_helper_crypto_aesmc
;
14060 unallocated_encoding(s
);
14064 if (!fp_access_check(s
)) {
14068 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
14070 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
14074 /* Crypto three-reg SHA
14075 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
14076 * +-----------------+------+---+------+---+--------+-----+------+------+
14077 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
14078 * +-----------------+------+---+------+---+--------+-----+------+------+
14080 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
14082 int size
= extract32(insn
, 22, 2);
14083 int opcode
= extract32(insn
, 12, 3);
14084 int rm
= extract32(insn
, 16, 5);
14085 int rn
= extract32(insn
, 5, 5);
14086 int rd
= extract32(insn
, 0, 5);
14087 gen_helper_gvec_3
*genfn
;
14091 unallocated_encoding(s
);
14096 case 0: /* SHA1C */
14097 genfn
= gen_helper_crypto_sha1c
;
14098 feature
= dc_isar_feature(aa64_sha1
, s
);
14100 case 1: /* SHA1P */
14101 genfn
= gen_helper_crypto_sha1p
;
14102 feature
= dc_isar_feature(aa64_sha1
, s
);
14104 case 2: /* SHA1M */
14105 genfn
= gen_helper_crypto_sha1m
;
14106 feature
= dc_isar_feature(aa64_sha1
, s
);
14108 case 3: /* SHA1SU0 */
14109 genfn
= gen_helper_crypto_sha1su0
;
14110 feature
= dc_isar_feature(aa64_sha1
, s
);
14112 case 4: /* SHA256H */
14113 genfn
= gen_helper_crypto_sha256h
;
14114 feature
= dc_isar_feature(aa64_sha256
, s
);
14116 case 5: /* SHA256H2 */
14117 genfn
= gen_helper_crypto_sha256h2
;
14118 feature
= dc_isar_feature(aa64_sha256
, s
);
14120 case 6: /* SHA256SU1 */
14121 genfn
= gen_helper_crypto_sha256su1
;
14122 feature
= dc_isar_feature(aa64_sha256
, s
);
14125 unallocated_encoding(s
);
14130 unallocated_encoding(s
);
14134 if (!fp_access_check(s
)) {
14137 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14140 /* Crypto two-reg SHA
14141 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14142 * +-----------------+------+-----------+--------+-----+------+------+
14143 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14144 * +-----------------+------+-----------+--------+-----+------+------+
14146 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14148 int size
= extract32(insn
, 22, 2);
14149 int opcode
= extract32(insn
, 12, 5);
14150 int rn
= extract32(insn
, 5, 5);
14151 int rd
= extract32(insn
, 0, 5);
14152 gen_helper_gvec_2
*genfn
;
14156 unallocated_encoding(s
);
14161 case 0: /* SHA1H */
14162 feature
= dc_isar_feature(aa64_sha1
, s
);
14163 genfn
= gen_helper_crypto_sha1h
;
14165 case 1: /* SHA1SU1 */
14166 feature
= dc_isar_feature(aa64_sha1
, s
);
14167 genfn
= gen_helper_crypto_sha1su1
;
14169 case 2: /* SHA256SU0 */
14170 feature
= dc_isar_feature(aa64_sha256
, s
);
14171 genfn
= gen_helper_crypto_sha256su0
;
14174 unallocated_encoding(s
);
14179 unallocated_encoding(s
);
14183 if (!fp_access_check(s
)) {
14186 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14189 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14191 tcg_gen_rotli_i64(d
, m
, 1);
14192 tcg_gen_xor_i64(d
, d
, n
);
14195 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14197 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14198 tcg_gen_xor_vec(vece
, d
, d
, n
);
14201 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14202 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14204 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14205 static const GVecGen3 op
= {
14206 .fni8
= gen_rax1_i64
,
14207 .fniv
= gen_rax1_vec
,
14208 .opt_opc
= vecop_list
,
14209 .fno
= gen_helper_crypto_rax1
,
14212 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14215 /* Crypto three-reg SHA512
14216 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14217 * +-----------------------+------+---+---+-----+--------+------+------+
14218 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14219 * +-----------------------+------+---+---+-----+--------+------+------+
14221 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14223 int opcode
= extract32(insn
, 10, 2);
14224 int o
= extract32(insn
, 14, 1);
14225 int rm
= extract32(insn
, 16, 5);
14226 int rn
= extract32(insn
, 5, 5);
14227 int rd
= extract32(insn
, 0, 5);
14229 gen_helper_gvec_3
*oolfn
= NULL
;
14230 GVecGen3Fn
*gvecfn
= NULL
;
14234 case 0: /* SHA512H */
14235 feature
= dc_isar_feature(aa64_sha512
, s
);
14236 oolfn
= gen_helper_crypto_sha512h
;
14238 case 1: /* SHA512H2 */
14239 feature
= dc_isar_feature(aa64_sha512
, s
);
14240 oolfn
= gen_helper_crypto_sha512h2
;
14242 case 2: /* SHA512SU1 */
14243 feature
= dc_isar_feature(aa64_sha512
, s
);
14244 oolfn
= gen_helper_crypto_sha512su1
;
14247 feature
= dc_isar_feature(aa64_sha3
, s
);
14248 gvecfn
= gen_gvec_rax1
;
14251 g_assert_not_reached();
14255 case 0: /* SM3PARTW1 */
14256 feature
= dc_isar_feature(aa64_sm3
, s
);
14257 oolfn
= gen_helper_crypto_sm3partw1
;
14259 case 1: /* SM3PARTW2 */
14260 feature
= dc_isar_feature(aa64_sm3
, s
);
14261 oolfn
= gen_helper_crypto_sm3partw2
;
14263 case 2: /* SM4EKEY */
14264 feature
= dc_isar_feature(aa64_sm4
, s
);
14265 oolfn
= gen_helper_crypto_sm4ekey
;
14268 unallocated_encoding(s
);
14274 unallocated_encoding(s
);
14278 if (!fp_access_check(s
)) {
14283 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14285 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14289 /* Crypto two-reg SHA512
14290 * 31 12 11 10 9 5 4 0
14291 * +-----------------------------------------+--------+------+------+
14292 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14293 * +-----------------------------------------+--------+------+------+
14295 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14297 int opcode
= extract32(insn
, 10, 2);
14298 int rn
= extract32(insn
, 5, 5);
14299 int rd
= extract32(insn
, 0, 5);
14303 case 0: /* SHA512SU0 */
14304 feature
= dc_isar_feature(aa64_sha512
, s
);
14307 feature
= dc_isar_feature(aa64_sm4
, s
);
14310 unallocated_encoding(s
);
14315 unallocated_encoding(s
);
14319 if (!fp_access_check(s
)) {
14324 case 0: /* SHA512SU0 */
14325 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14328 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14331 g_assert_not_reached();
14335 /* Crypto four-register
14336 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14337 * +-------------------+-----+------+---+------+------+------+
14338 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14339 * +-------------------+-----+------+---+------+------+------+
14341 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14343 int op0
= extract32(insn
, 21, 2);
14344 int rm
= extract32(insn
, 16, 5);
14345 int ra
= extract32(insn
, 10, 5);
14346 int rn
= extract32(insn
, 5, 5);
14347 int rd
= extract32(insn
, 0, 5);
14353 feature
= dc_isar_feature(aa64_sha3
, s
);
14355 case 2: /* SM3SS1 */
14356 feature
= dc_isar_feature(aa64_sm3
, s
);
14359 unallocated_encoding(s
);
14364 unallocated_encoding(s
);
14368 if (!fp_access_check(s
)) {
14373 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14376 tcg_op1
= tcg_temp_new_i64();
14377 tcg_op2
= tcg_temp_new_i64();
14378 tcg_op3
= tcg_temp_new_i64();
14379 tcg_res
[0] = tcg_temp_new_i64();
14380 tcg_res
[1] = tcg_temp_new_i64();
14382 for (pass
= 0; pass
< 2; pass
++) {
14383 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14384 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14385 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14389 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14392 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14394 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14396 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14397 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14399 tcg_temp_free_i64(tcg_op1
);
14400 tcg_temp_free_i64(tcg_op2
);
14401 tcg_temp_free_i64(tcg_op3
);
14402 tcg_temp_free_i64(tcg_res
[0]);
14403 tcg_temp_free_i64(tcg_res
[1]);
14405 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14407 tcg_op1
= tcg_temp_new_i32();
14408 tcg_op2
= tcg_temp_new_i32();
14409 tcg_op3
= tcg_temp_new_i32();
14410 tcg_res
= tcg_temp_new_i32();
14411 tcg_zero
= tcg_const_i32(0);
14413 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14414 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14415 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14417 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14418 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14419 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14420 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14422 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14423 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14424 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14425 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14427 tcg_temp_free_i32(tcg_op1
);
14428 tcg_temp_free_i32(tcg_op2
);
14429 tcg_temp_free_i32(tcg_op3
);
14430 tcg_temp_free_i32(tcg_res
);
14431 tcg_temp_free_i32(tcg_zero
);
14436 * 31 21 20 16 15 10 9 5 4 0
14437 * +-----------------------+------+--------+------+------+
14438 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14439 * +-----------------------+------+--------+------+------+
14441 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14443 int rm
= extract32(insn
, 16, 5);
14444 int imm6
= extract32(insn
, 10, 6);
14445 int rn
= extract32(insn
, 5, 5);
14446 int rd
= extract32(insn
, 0, 5);
14448 if (!dc_isar_feature(aa64_sha3
, s
)) {
14449 unallocated_encoding(s
);
14453 if (!fp_access_check(s
)) {
14457 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
14458 vec_full_reg_offset(s
, rn
),
14459 vec_full_reg_offset(s
, rm
), imm6
, 16,
14460 vec_full_reg_size(s
));
14463 /* Crypto three-reg imm2
14464 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14465 * +-----------------------+------+-----+------+--------+------+------+
14466 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14467 * +-----------------------+------+-----+------+--------+------+------+
14469 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14471 static gen_helper_gvec_3
* const fns
[4] = {
14472 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14473 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14475 int opcode
= extract32(insn
, 10, 2);
14476 int imm2
= extract32(insn
, 12, 2);
14477 int rm
= extract32(insn
, 16, 5);
14478 int rn
= extract32(insn
, 5, 5);
14479 int rd
= extract32(insn
, 0, 5);
14481 if (!dc_isar_feature(aa64_sm3
, s
)) {
14482 unallocated_encoding(s
);
14486 if (!fp_access_check(s
)) {
14490 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14493 /* C3.6 Data processing - SIMD, inc Crypto
14495 * As the decode gets a little complex we are using a table based
14496 * approach for this part of the decode.
14498 static const AArch64DecodeTable data_proc_simd
[] = {
14499 /* pattern , mask , fn */
14500 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14501 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14502 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14503 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14504 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14505 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14506 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14507 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14508 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14509 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14510 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14511 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14512 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14513 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14514 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14515 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14516 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14517 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14518 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14519 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14520 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14521 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14522 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14523 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14524 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14525 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14526 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14527 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14528 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14529 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14530 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14531 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14532 { 0x00000000, 0x00000000, NULL
}
14535 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14537 /* Note that this is called with all non-FP cases from
14538 * table C3-6 so it must UNDEF for entries not specifically
14539 * allocated to instructions in that table.
14541 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14545 unallocated_encoding(s
);
14549 /* C3.6 Data processing - SIMD and floating point */
14550 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14552 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14553 disas_data_proc_fp(s
, insn
);
14555 /* SIMD, including crypto */
14556 disas_data_proc_simd(s
, insn
);
14562 * @env: The cpu environment
14563 * @s: The DisasContext
14565 * Return true if the page is guarded.
14567 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14569 uint64_t addr
= s
->base
.pc_first
;
14570 #ifdef CONFIG_USER_ONLY
14571 return page_get_flags(addr
) & PAGE_BTI
;
14573 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14574 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14575 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14578 * We test this immediately after reading an insn, which means
14579 * that any normal page must be in the TLB. The only exception
14580 * would be for executing from flash or device memory, which
14581 * does not retain the TLB entry.
14583 * FIXME: Assume false for those, for now. We could use
14584 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14585 * table entry even for that case.
14587 return (tlb_hit(entry
->addr_code
, addr
) &&
14588 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14593 * btype_destination_ok:
14594 * @insn: The instruction at the branch destination
14595 * @bt: SCTLR_ELx.BT
14596 * @btype: PSTATE.BTYPE, and is non-zero
14598 * On a guarded page, there are a limited number of insns
14599 * that may be present at the branch target:
14600 * - branch target identifiers,
14601 * - paciasp, pacibsp,
14604 * Anything else causes a Branch Target Exception.
14606 * Return true if the branch is compatible, false to raise BTITRAP.
14608 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14610 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14612 switch (extract32(insn
, 5, 7)) {
14613 case 0b011001: /* PACIASP */
14614 case 0b011011: /* PACIBSP */
14616 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14617 * with btype == 3. Otherwise all btype are ok.
14619 return !bt
|| btype
!= 3;
14620 case 0b100000: /* BTI */
14621 /* Not compatible with any btype. */
14623 case 0b100010: /* BTI c */
14624 /* Not compatible with btype == 3 */
14626 case 0b100100: /* BTI j */
14627 /* Not compatible with btype == 2 */
14629 case 0b100110: /* BTI jc */
14630 /* Compatible with any btype. */
14634 switch (insn
& 0xffe0001fu
) {
14635 case 0xd4200000u
: /* BRK */
14636 case 0xd4400000u
: /* HLT */
14637 /* Give priority to the breakpoint exception. */
14644 /* C3.1 A64 instruction index by encoding */
14645 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14649 s
->pc_curr
= s
->base
.pc_next
;
14650 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14652 s
->base
.pc_next
+= 4;
14654 s
->fp_access_checked
= false;
14655 s
->sve_access_checked
= false;
14657 if (dc_isar_feature(aa64_bti
, s
)) {
14658 if (s
->base
.num_insns
== 1) {
14660 * At the first insn of the TB, compute s->guarded_page.
14661 * We delayed computing this until successfully reading
14662 * the first insn of the TB, above. This (mostly) ensures
14663 * that the softmmu tlb entry has been populated, and the
14664 * page table GP bit is available.
14666 * Note that we need to compute this even if btype == 0,
14667 * because this value is used for BR instructions later
14668 * where ENV is not available.
14670 s
->guarded_page
= is_guarded_page(env
, s
);
14672 /* First insn can have btype set to non-zero. */
14673 tcg_debug_assert(s
->btype
>= 0);
14676 * Note that the Branch Target Exception has fairly high
14677 * priority -- below debugging exceptions but above most
14678 * everything else. This allows us to handle this now
14679 * instead of waiting until the insn is otherwise decoded.
14683 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14684 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14685 syn_btitrap(s
->btype
),
14686 default_exception_el(s
));
14690 /* Not the first insn: btype must be 0. */
14691 tcg_debug_assert(s
->btype
== 0);
14695 switch (extract32(insn
, 25, 4)) {
14696 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14697 unallocated_encoding(s
);
14700 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14701 unallocated_encoding(s
);
14704 case 0x8: case 0x9: /* Data processing - immediate */
14705 disas_data_proc_imm(s
, insn
);
14707 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14708 disas_b_exc_sys(s
, insn
);
14713 case 0xe: /* Loads and stores */
14714 disas_ldst(s
, insn
);
14717 case 0xd: /* Data processing - register */
14718 disas_data_proc_reg(s
, insn
);
14721 case 0xf: /* Data processing - SIMD and floating point */
14722 disas_data_proc_simd_fp(s
, insn
);
14725 assert(FALSE
); /* all 15 cases should be handled above */
14729 /* if we allocated any temporaries, free them here */
14733 * After execution of most insns, btype is reset to 0.
14734 * Note that we set btype == -1 when the insn sets btype.
14736 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14741 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14744 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14745 CPUARMState
*env
= cpu
->env_ptr
;
14746 ARMCPU
*arm_cpu
= env_archcpu(env
);
14747 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14748 int bound
, core_mmu_idx
;
14750 dc
->isar
= &arm_cpu
->isar
;
14754 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14755 * there is no secure EL1, so we route exceptions to EL3.
14757 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14758 !arm_el_is_aa64(env
, 3);
14761 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14762 dc
->condexec_mask
= 0;
14763 dc
->condexec_cond
= 0;
14764 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14765 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14766 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14767 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14768 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14769 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14770 #if !defined(CONFIG_USER_ONLY)
14771 dc
->user
= (dc
->current_el
== 0);
14773 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14774 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14775 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14776 dc
->sve_len
= (EX_TBFLAG_A64(tb_flags
, ZCR_LEN
) + 1) * 16;
14777 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14778 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14779 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14780 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14781 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14782 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14783 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14785 dc
->vec_stride
= 0;
14786 dc
->cp_regs
= arm_cpu
->cp_regs
;
14787 dc
->features
= env
->features
;
14788 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14790 #ifdef CONFIG_USER_ONLY
14791 /* In sve_probe_page, we assume TBI is enabled. */
14792 tcg_debug_assert(dc
->tbid
& 1);
14795 /* Single step state. The code-generation logic here is:
14797 * generate code with no special handling for single-stepping (except
14798 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14799 * this happens anyway because those changes are all system register or
14801 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14802 * emit code for one insn
14803 * emit code to clear PSTATE.SS
14804 * emit code to generate software step exception for completed step
14805 * end TB (as usual for having generated an exception)
14806 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14807 * emit code to generate a software step exception
14810 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14811 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14812 dc
->is_ldex
= false;
14813 dc
->debug_target_el
= EX_TBFLAG_ANY(tb_flags
, DEBUG_TARGET_EL
);
14815 /* Bound the number of insns to execute to those left on the page. */
14816 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14818 /* If architectural single step active, limit to 1. */
14819 if (dc
->ss_active
) {
14822 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14824 init_tmp_a64_array(dc
);
14827 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14831 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14833 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14835 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14836 dc
->insn_start
= tcg_last_op();
14839 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14840 const CPUBreakpoint
*bp
)
14842 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14844 if (bp
->flags
& BP_CPU
) {
14845 gen_a64_set_pc_im(dc
->base
.pc_next
);
14846 gen_helper_check_breakpoints(cpu_env
);
14847 /* End the TB early; it likely won't be executed */
14848 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14850 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14851 /* The address covered by the breakpoint must be
14852 included in [tb->pc, tb->pc + tb->size) in order
14853 to for it to be properly cleared -- thus we
14854 increment the PC here so that the logic setting
14855 tb->size below does the right thing. */
14856 dc
->base
.pc_next
+= 4;
14857 dc
->base
.is_jmp
= DISAS_NORETURN
;
14863 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14865 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14866 CPUARMState
*env
= cpu
->env_ptr
;
14868 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14869 /* Singlestep state is Active-pending.
14870 * If we're in this state at the start of a TB then either
14871 * a) we just took an exception to an EL which is being debugged
14872 * and this is the first insn in the exception handler
14873 * b) debug exceptions were masked and we just unmasked them
14874 * without changing EL (eg by clearing PSTATE.D)
14875 * In either case we're going to take a swstep exception in the
14876 * "did not step an insn" case, and so the syndrome ISV and EX
14877 * bits should be zero.
14879 assert(dc
->base
.num_insns
== 1);
14880 gen_swstep_exception(dc
, 0, 0);
14881 dc
->base
.is_jmp
= DISAS_NORETURN
;
14883 disas_a64_insn(env
, dc
);
14886 translator_loop_temp_check(&dc
->base
);
14889 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14891 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14893 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14894 /* Note that this means single stepping WFI doesn't halt the CPU.
14895 * For conditional branch insns this is harmless unreachable code as
14896 * gen_goto_tb() has already handled emitting the debug exception
14897 * (and thus a tb-jump is not possible when singlestepping).
14899 switch (dc
->base
.is_jmp
) {
14901 gen_a64_set_pc_im(dc
->base
.pc_next
);
14905 if (dc
->base
.singlestep_enabled
) {
14906 gen_exception_internal(EXCP_DEBUG
);
14908 gen_step_complete_exception(dc
);
14911 case DISAS_NORETURN
:
14915 switch (dc
->base
.is_jmp
) {
14917 case DISAS_TOO_MANY
:
14918 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14921 case DISAS_UPDATE_EXIT
:
14922 gen_a64_set_pc_im(dc
->base
.pc_next
);
14925 tcg_gen_exit_tb(NULL
, 0);
14927 case DISAS_UPDATE_NOCHAIN
:
14928 gen_a64_set_pc_im(dc
->base
.pc_next
);
14931 tcg_gen_lookup_and_goto_ptr();
14933 case DISAS_NORETURN
:
14937 gen_a64_set_pc_im(dc
->base
.pc_next
);
14938 gen_helper_wfe(cpu_env
);
14941 gen_a64_set_pc_im(dc
->base
.pc_next
);
14942 gen_helper_yield(cpu_env
);
14946 /* This is a special case because we don't want to just halt the CPU
14947 * if trying to debug across a WFI.
14949 TCGv_i32 tmp
= tcg_const_i32(4);
14951 gen_a64_set_pc_im(dc
->base
.pc_next
);
14952 gen_helper_wfi(cpu_env
, tmp
);
14953 tcg_temp_free_i32(tmp
);
14954 /* The helper doesn't necessarily throw an exception, but we
14955 * must go back to the main loop to check for interrupts anyway.
14957 tcg_gen_exit_tb(NULL
, 0);
14964 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14967 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14969 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14970 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14973 const TranslatorOps aarch64_translator_ops
= {
14974 .init_disas_context
= aarch64_tr_init_disas_context
,
14975 .tb_start
= aarch64_tr_tb_start
,
14976 .insn_start
= aarch64_tr_insn_start
,
14977 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14978 .translate_insn
= aarch64_tr_translate_insn
,
14979 .tb_stop
= aarch64_tr_tb_stop
,
14980 .disas_log
= aarch64_tr_disas_log
,