4 * Copyright Red Hat, Inc. 2013-2014
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #ifndef VIRTIO_GPU_HW_H
39 #define VIRTIO_GPU_HW_H
41 #include "standard-headers/linux/types.h"
43 #define VIRTIO_GPU_FEATURE_VIRGL 0
45 enum virtio_gpu_ctrl_type
{
46 VIRTIO_GPU_UNDEFINED
= 0,
49 VIRTIO_GPU_CMD_GET_DISPLAY_INFO
= 0x0100,
50 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D
,
51 VIRTIO_GPU_CMD_RESOURCE_UNREF
,
52 VIRTIO_GPU_CMD_SET_SCANOUT
,
53 VIRTIO_GPU_CMD_RESOURCE_FLUSH
,
54 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D
,
55 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING
,
56 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING
,
57 VIRTIO_GPU_CMD_GET_CAPSET_INFO
,
58 VIRTIO_GPU_CMD_GET_CAPSET
,
61 VIRTIO_GPU_CMD_CTX_CREATE
= 0x0200,
62 VIRTIO_GPU_CMD_CTX_DESTROY
,
63 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE
,
64 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE
,
65 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D
,
66 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D
,
67 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D
,
68 VIRTIO_GPU_CMD_SUBMIT_3D
,
71 VIRTIO_GPU_CMD_UPDATE_CURSOR
= 0x0300,
72 VIRTIO_GPU_CMD_MOVE_CURSOR
,
74 /* success responses */
75 VIRTIO_GPU_RESP_OK_NODATA
= 0x1100,
76 VIRTIO_GPU_RESP_OK_DISPLAY_INFO
,
77 VIRTIO_GPU_RESP_OK_CAPSET_INFO
,
78 VIRTIO_GPU_RESP_OK_CAPSET
,
81 VIRTIO_GPU_RESP_ERR_UNSPEC
= 0x1200,
82 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY
,
83 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID
,
84 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID
,
85 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID
,
86 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER
,
89 #define VIRTIO_GPU_FLAG_FENCE (1 << 0)
91 struct virtio_gpu_ctrl_hdr
{
99 /* data passed in the cursor vq */
101 struct virtio_gpu_cursor_pos
{
108 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
109 struct virtio_gpu_update_cursor
{
110 struct virtio_gpu_ctrl_hdr hdr
;
111 struct virtio_gpu_cursor_pos pos
; /* update & move */
112 uint32_t resource_id
; /* update only */
113 uint32_t hot_x
; /* update only */
114 uint32_t hot_y
; /* update only */
118 /* data passed in the control vq, 2d related */
120 struct virtio_gpu_rect
{
127 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
128 struct virtio_gpu_resource_unref
{
129 struct virtio_gpu_ctrl_hdr hdr
;
130 uint32_t resource_id
;
134 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
135 struct virtio_gpu_resource_create_2d
{
136 struct virtio_gpu_ctrl_hdr hdr
;
137 uint32_t resource_id
;
143 /* VIRTIO_GPU_CMD_SET_SCANOUT */
144 struct virtio_gpu_set_scanout
{
145 struct virtio_gpu_ctrl_hdr hdr
;
146 struct virtio_gpu_rect r
;
148 uint32_t resource_id
;
151 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
152 struct virtio_gpu_resource_flush
{
153 struct virtio_gpu_ctrl_hdr hdr
;
154 struct virtio_gpu_rect r
;
155 uint32_t resource_id
;
159 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
160 struct virtio_gpu_transfer_to_host_2d
{
161 struct virtio_gpu_ctrl_hdr hdr
;
162 struct virtio_gpu_rect r
;
164 uint32_t resource_id
;
168 struct virtio_gpu_mem_entry
{
174 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
175 struct virtio_gpu_resource_attach_backing
{
176 struct virtio_gpu_ctrl_hdr hdr
;
177 uint32_t resource_id
;
181 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
182 struct virtio_gpu_resource_detach_backing
{
183 struct virtio_gpu_ctrl_hdr hdr
;
184 uint32_t resource_id
;
188 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
189 #define VIRTIO_GPU_MAX_SCANOUTS 16
190 struct virtio_gpu_resp_display_info
{
191 struct virtio_gpu_ctrl_hdr hdr
;
192 struct virtio_gpu_display_one
{
193 struct virtio_gpu_rect r
;
196 } pmodes
[VIRTIO_GPU_MAX_SCANOUTS
];
199 /* data passed in the control vq, 3d related */
201 struct virtio_gpu_box
{
206 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
207 struct virtio_gpu_transfer_host_3d
{
208 struct virtio_gpu_ctrl_hdr hdr
;
209 struct virtio_gpu_box box
;
211 uint32_t resource_id
;
214 uint32_t layer_stride
;
217 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
218 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
219 struct virtio_gpu_resource_create_3d
{
220 struct virtio_gpu_ctrl_hdr hdr
;
221 uint32_t resource_id
;
235 /* VIRTIO_GPU_CMD_CTX_CREATE */
236 struct virtio_gpu_ctx_create
{
237 struct virtio_gpu_ctrl_hdr hdr
;
243 /* VIRTIO_GPU_CMD_CTX_DESTROY */
244 struct virtio_gpu_ctx_destroy
{
245 struct virtio_gpu_ctrl_hdr hdr
;
248 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
249 struct virtio_gpu_ctx_resource
{
250 struct virtio_gpu_ctrl_hdr hdr
;
251 uint32_t resource_id
;
255 /* VIRTIO_GPU_CMD_SUBMIT_3D */
256 struct virtio_gpu_cmd_submit
{
257 struct virtio_gpu_ctrl_hdr hdr
;
262 #define VIRTIO_GPU_CAPSET_VIRGL 1
264 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
265 struct virtio_gpu_get_capset_info
{
266 struct virtio_gpu_ctrl_hdr hdr
;
267 uint32_t capset_index
;
271 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
272 struct virtio_gpu_resp_capset_info
{
273 struct virtio_gpu_ctrl_hdr hdr
;
275 uint32_t capset_max_version
;
276 uint32_t capset_max_size
;
280 /* VIRTIO_GPU_CMD_GET_CAPSET */
281 struct virtio_gpu_get_capset
{
282 struct virtio_gpu_ctrl_hdr hdr
;
284 uint32_t capset_version
;
287 /* VIRTIO_GPU_RESP_OK_CAPSET */
288 struct virtio_gpu_resp_capset
{
289 struct virtio_gpu_ctrl_hdr hdr
;
290 uint8_t capset_data
[];
293 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
295 struct virtio_gpu_config
{
296 uint32_t events_read
;
297 uint32_t events_clear
;
298 uint32_t num_scanouts
;
299 uint32_t num_capsets
;
302 /* simple formats for fbcon/X use */
303 enum virtio_gpu_formats
{
304 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM
= 1,
305 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM
= 2,
306 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM
= 3,
307 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM
= 4,
309 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM
= 67,
310 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM
= 68,
312 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM
= 121,
313 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM
= 134,